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Place rsp.Step inside cached interpreter. Gains about 3 more fps

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iris
2026-05-29 10:24:57 +02:00
parent bb97dcc23f
commit 2147195774
7 changed files with 4 additions and 166 deletions
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src/backend/core/RSP.cpp
-102
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@@ -31,39 +31,6 @@ void RSP::Reset() {
steps = 0;
}
/*
FORCE_INLINE void logRSP(const RSP& rsp, const u32 instr) {
debug("{:04X} {:08X} ", rsp.oldPC, instr);
for (auto gpr : rsp.gpr) {
debug("{:08X} ", gpr);
}
for (auto vpr : rsp.vpr) {
for (int i = 0; i < 8; i++) {
debug("{:04X}", vpr.element[i]);
}
debug(" ");
}
for (int i = 0; i < 8; i++) {
debug("{:04X}", rsp.acc.h.element[i]);
}
debug(" ");
for (int i = 0; i < 8; i++) {
debug("{:04X}", rsp.acc.m.element[i]);
}
debug(" ");
for (int i = 0; i < 8; i++) {
debug("{:04X}", rsp.acc.l.element[i]);
}
debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
}
*/
auto RSP::Read(const u32 addr) -> u32 {
switch (addr) {
case 0x04040000:
@@ -177,9 +144,6 @@ void RSP::DMA<false>() {
auto &dst = spDMASPAddr.bank ? imem : dmem;
u32 mem_address = spDMASPAddr.address & 0xFF8;
if (spDMASPAddr.bank) {
cachedState.EvictCachedBlock(mem_address);
}
u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
@@ -235,70 +199,4 @@ void RSP::Write(const u32 addr, const u32 val) {
panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
}
}
void RSP::CacheBlock(u16 addr) {
auto blockAddr = addr;
CachedLine line;
u32 i;
bool fetchDelaySlot = false;
for (i = 0; i < MAX_INSTR_PER_BLOCK; i++) {
Instruction instr = ircolib::ReadAccess<u32>(imem, addr & IMEM_DSIZE);
addr += 4;
line.code[i] = instr;
if (fetchDelaySlot) {
i++;
break;
}
if (InstrEndsBlock(instr)) {
if (InstrHasDelaySlot(instr) && !fetchDelaySlot) {
fetchDelaySlot = true;
continue;
}
if (i == 0)
i = 1;
break;
}
}
line.cycles = i;
line.len = i;
cachedState.blocks[CACHE_GET_BLOCK(blockAddr)]->lines[CACHE_GET_LINE(blockAddr)] = new CachedLine(line);
return ExecuteCached();
}
void RSP::ExecuteCached() {
u16 addr = pc;
auto &blocks = cachedState.blocks;
if (!blocks[CACHE_GET_BLOCK(addr)]) {
blocks[CACHE_GET_BLOCK(addr)] = new CachedBlock<cachedState.MAX_LINES / 4>();
return CacheBlock(addr);
}
const auto line = blocks[CACHE_GET_BLOCK(addr)]->lines[CACHE_GET_LINE(addr)];
if (line) {
for (u32 i = 0; i < line->len; i++) {
prevDelaySlot = delaySlot;
delaySlot = false;
oldPC = pc & 0xFFC;
pc = nextPC & 0xFFC;
nextPC += 4;
Instruction instr = line->code[i];
Exec(instr);
}
return;
}
return CacheBlock(addr);
}
} // namespace n64