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This commit is contained in:
Simone
@@ -1,6 +1,18 @@
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#include <IR.hpp>
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#include <IR.hpp>
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namespace n64 {
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namespace n64 {
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Entry::Entry(Opcode op, Operand dst, Operand op1, Operand op2)
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: op(op), dst(dst), op1(op1), op2(op2) {}
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Entry::Entry(Opcode op, Operand op1, Operand op2)
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: op(op), op1(op1), op2(op2) {}
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Entry::Entry(Opcode op, Operand op1, std::optional<BranchCond> bc, Operand op2)
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: op(op), op1(op1), branchCond(bc), op2(op2) {}
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Entry::Entry(Opcode op, Operand dst, Operand op1, Operand op2, Shift s)
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: op(op), dst(dst), op1(op1), op2(op2), shift(s) {}
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void IR::push(const Entry& e) {
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void IR::push(const Entry& e) {
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code.push_back(e);
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code.push_back(e);
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}
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}
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@@ -5,15 +5,28 @@
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namespace n64 {
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namespace n64 {
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struct Entry {
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struct Entry {
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enum : u8 {
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enum : u16 {
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LINK = 0x10,
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LINK = 0x100,
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LIKELY = 0x20,
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LIKELY = 0x200,
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REGISTER = 0x40
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REGISTER = 0x400,
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SET_LLBIT = 0x800
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};
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enum Shift {
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LEFT, RIGHT
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};
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};
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enum Opcode : u16 {
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enum Opcode : u16 {
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MOV, ADD, SUB, MUL, DIV, AND, NOR, XOR, OR, SRL, SLL, SRA,
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MOV, ADD, SUB, UMUL, SMUL, DIV, AND, NOR, XOR, OR, SRL, SLL, SRA,
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LOAD, STORE, BRANCH, JUMP
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LOADS8, LOADS8_SHIFT, STORE8, STORE8_SHIFT,
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LOADS16, LOADS16_SHIFT, STORE16, STORE16_SHIFT,
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LOADS32, LOADS32_SHIFT, STORE32, STORE32_SHIFT,
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LOADS64, LOADS64_SHIFT, STORE64, STORE64_SHIFT,
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LOADU8, LOADU8_SHIFT,
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LOADU16, LOADU16_SHIFT,
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LOADU32, LOADU32_SHIFT,
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LOADU64, LOADU64_SHIFT,
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BRANCH, JUMP,
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} op;
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} op;
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struct Operand {
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struct Operand {
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@@ -21,27 +34,26 @@ struct Entry {
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NONE, REG_F64, REG_F32, IMM_F64, IMM_F32,
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NONE, REG_F64, REG_F32, IMM_F64, IMM_F32,
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REG_S64, REG_S32, REG_U64, REG_U32, REG_U5, IMM_S16,
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REG_S64, REG_S32, REG_U64, REG_U32, REG_U5, IMM_S16,
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IMM_S32, IMM_S64, IMM_U16, IMM_U32, IMM_U64, IMM_U5,
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IMM_S32, IMM_S64, IMM_U16, IMM_U32, IMM_U64, IMM_U5,
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MEM_U8, MEM_U16, MEM_U32, MEM_U64
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} type;
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} type;
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std::optional<u64> index_or_imm;
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Operand(Type t, std::optional<u64> i = std::nullopt)
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std::optional<u64> index_or_imm = std::nullopt;
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: type(t), index_or_imm(i) {}
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} dst = Operand::NONE, op1, op2;
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Operand(Type t, std::optional <u64> imm = std::nullopt)
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: type(t), index_or_imm(imm) {}
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} dst = Operand::NONE, op1 = Operand::NONE, op2 = Operand::NONE;
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enum BranchCond {
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enum BranchCond {
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EQ, NE, LT, GT, LE, GE
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EQ, NE, LT, GT, LE, GE
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};
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};
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std::optional<BranchCond> branchCond = std::nullopt;
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std::optional<BranchCond> branchCond = std::nullopt;
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std::optional<Shift> shift = std::nullopt;
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Entry(Opcode op, Operand dst, Operand op1, Operand op2)
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Entry(Opcode op, Operand dst, Operand op1, Operand op2);
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: op(op), dst(dst), op1(op1), op2(op2) {}
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Entry(Opcode op, Operand op1, Operand op2);
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Entry(Opcode op, Operand op1, std::optional<BranchCond> bc, Operand op2);
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Entry(Opcode op, Operand op1, Operand op2)
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Entry(Opcode op, Operand dst, Operand op1, Operand op2, Shift s);
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: op(op), op1(op1), op2(op2) {}
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Entry(Opcode op, Operand op1, std::optional<BranchCond> bc, Operand op2)
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: op(op), op1(op1), branchCond(bc), op2(op2) {}
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};
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};
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struct IR {
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struct IR {
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@@ -176,502 +176,250 @@ void JIT::daddiu(u32 instr) {
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}
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}
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void JIT::div(u32 instr) {
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void JIT::div(u32 instr) {
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auto op1 = Entry::Operand{ Entry::Operand::REG_S32, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::REG_S32, u8(RT(instr)) };
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Entry e(Entry::DIV, op1, op2);
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ir.push(e);
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}
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}
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void JIT::divu(u32 instr) {
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void JIT::divu(u32 instr) {
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movsxd(rax, GPR(dword, RS(instr))); // dividend
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auto op1 = Entry::Operand{ Entry::Operand::REG_U32, u8(RS(instr)) };
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movsxd(rcx, GPR(dword, RT(instr))); // divisor
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auto op2 = Entry::Operand{ Entry::Operand::REG_U32, u8(RT(instr)) };
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cmp(rcx, 0);
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Entry e(Entry::DIV, op1, op2);
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je("divu_divisor==0");
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ir.push(e);
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CodeGenerator::div(rcx);
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mov(qword[rdi + offsetof(Registers, lo)], eax);
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mov(qword[rdi + offsetof(Registers, hi)], edx);
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jmp("divu_exit");
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L("divu_divisor==0");
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mov(qword[rdi + offsetof(Registers, hi)], rax);
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mov(qword[rdi + offsetof(Registers, lo)], -1);
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L("divu_exit");
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}
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}
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void JIT::ddiv(u32 instr) {
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void JIT::ddiv(u32 instr) {
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mov(rax, GPR(qword, RS(instr)));
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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mov(rcx, GPR(qword, RT(instr)));
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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mov(r8, 0x8000000000000000);
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Entry e(Entry::DIV, op1, op2);
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mov(r9, rax);
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ir.push(e);
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CodeGenerator::xor_(r9, r8);
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mov(r8, 0xFFFFFFFFFFFFFFFF);
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mov(r10, rcx);
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CodeGenerator::xor_(r10, r8);
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CodeGenerator::xor_(r9, r10);
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cmp(rcx, 0);
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je("ddiv_else_if");
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cmp(r9, 1);
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jne("ddiv_else");
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mov(qword[rdi + offsetof(Registers, lo)], rax);
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mov(qword[rdi + offsetof(Registers, hi)], 0);
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jmp("ddiv_exit");
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L("ddiv_else_if");
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mov(qword[rdi + offsetof(Registers, hi)], rax);
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cmp(rax, 0);
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jge("ddiv_dividend>=0");
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mov(qword[rdi + offsetof(Registers, lo)], 1);
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L("ddiv_dividend>=0");
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mov(qword[rdi + offsetof(Registers, lo)], -1);
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L("ddiv_else");
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CodeGenerator::div(rcx);
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mov(qword[rdi + offsetof(Registers, lo)], rax);
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mov(qword[rdi + offsetof(Registers, hi)], rdx);
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L("ddiv_exit");
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}
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}
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void JIT::ddivu(u32 instr) {
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void JIT::ddivu(u32 instr) {
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mov(rax, GPR(qword, RS(instr)));
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auto op1 = Entry::Operand{ Entry::Operand::REG_U64, u8(RS(instr)) };
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mov(rcx, GPR(qword, RT(instr)));
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auto op2 = Entry::Operand{ Entry::Operand::REG_U64, u8(RT(instr)) };
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cmp(rcx, 0);
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Entry e(Entry::DIV, op1, op2);
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je("ddivu_divisor==0");
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ir.push(e);
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CodeGenerator::div(rcx);
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mov(qword[rdi + offsetof(Registers, lo)], rax);
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mov(qword[rdi + offsetof(Registers, hi)], rdx);
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jmp("ddivu_exit");
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L("ddivu_divisor==0");
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mov(qword[rdi + offsetof(Registers, lo)], -1);
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mov(qword[rdi + offsetof(Registers, hi)], rax);
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L("ddivu_exit");
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}
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}
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void JIT::lui(u32 instr) {
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void JIT::lui(u32 instr) {
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u64 val = s64(s16(instr));
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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val <<= 16;
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auto op1 = Entry::Operand{ Entry::Operand::IMM_S16, u64(s16(instr)) << 16 };
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mov(GPR(qword, RT(instr)), val);
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Entry e(Entry::LOADS64, dst, op1);
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ir.push(e);
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}
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}
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void JIT::lb(u32 instr) {
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void JIT::lb(u32 instr) {
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mov(rdx, GPR(qword, RS(instr)));
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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CodeGenerator::add(rdx, s64(s16(instr)));
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U8, s16(instr) };
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mov(rsi, LOAD);
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr))};
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push(rcx);
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Entry e(Entry::LOADS8, dst, op1, op2);
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lea(rcx, dword[rbp-4]);
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ir.push(e);
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emitCall(MapVAddr);
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pop(rcx);
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cmp(rax, 0);
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je("lb_exception");
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mov(rsi, dword[rbp-4]);
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push(rcx);
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emitMemberCall(&Mem::Read<u8>, &mem);
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pop(rcx);
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mov(GPR(qword, RT(instr)), rax.cvt8());
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L("lb_exception");
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mov(rsi, rdx);
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emitCall(HandleTLBException);
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push(rsi);
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mov(rdi, REG(byte, cop0.tlbError));
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mov(rsi, LOAD);
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emitCall(GetTLBExceptionCode);
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pop(rsi);
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mov(rsi, rax);
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mov(rdx, 0);
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mov(rcx, 1);
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emitCall(FireException);
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}
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}
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void JIT::lh(u32 instr) {
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void JIT::lh(u32 instr) {
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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if ((address & 0b1) > 0) {
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U16, s16(instr) };
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HandleTLBException(regs, address);
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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Entry e(Entry::LOADS16, dst, op1, op2);
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return;
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ir.push(e);
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}
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u32 paddr = 0;
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if(!MapVAddr(regs, LOAD, address, paddr)) {
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HandleTLBException(regs, address);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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} else {
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regs.gpr[RT(instr)] = (s16)mem.Read<u16>(regs, paddr);
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}
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}
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}
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void JIT::lw(u32 instr) {
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void JIT::lw(u32 instr) {
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s16 offset = instr;
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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u64 address = regs.gpr[RS(instr)] + offset;
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
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if (check_address_error(0b11, address)) {
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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HandleTLBException(regs, address);
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Entry e(Entry::LOADS32, dst, op1, op2);
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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ir.push(e);
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return;
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}
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u32 physical = 0;
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if (!MapVAddr(regs, LOAD, address, physical)) {
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HandleTLBException(regs, address);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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} else {
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regs.gpr[RT(instr)] = (s32)mem.Read<u32>(regs, physical);
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}
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}
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}
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void JIT::ll(u32 instr) {
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void JIT::ll(u32 instr) {
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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u32 physical;
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
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if (!MapVAddr(regs, LOAD, address, physical)) {
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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HandleTLBException(regs, address);
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auto opc = Entry::Opcode(u16(Entry::LOADS64) | Entry::SET_LLBIT);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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Entry e(opc, dst, op1, op2);
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} else {
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ir.push(e);
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if ((address & 0b11) > 0) {
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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return;
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} else {
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regs.gpr[RT(instr)] = (s32)mem.Read<u32>(regs, physical);
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}
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}
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regs.cop0.llbit = true;
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regs.cop0.LLAddr = physical >> 4;
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}
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}
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void JIT::lwl(u32 instr) {
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void JIT::lwl(u32 instr) {
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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u32 paddr = 0;
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
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if(!MapVAddr(regs, LOAD, address, paddr)) {
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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HandleTLBException(regs, address);
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Entry e(Entry::LOADS32_SHIFT, dst, op1, op2, Entry::LEFT);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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ir.push(e);
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} else {
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u32 shift = 8 * ((address ^ 0) & 3);
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u32 mask = 0xFFFFFFFF << shift;
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u32 data = mem.Read<u32>(regs, paddr & ~3);
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s32 result = s32((regs.gpr[RT(instr)] & ~mask) | (data << shift));
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regs.gpr[RT(instr)] = result;
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}
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}
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}
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void JIT::lwr(u32 instr) {
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void JIT::lwr(u32 instr) {
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u64 address = regs.gpr[RS(instr)] + (s16)instr;
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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u32 paddr = 0;
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
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if(!MapVAddr(regs, LOAD, address, paddr)) {
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auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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HandleTLBException(regs, address);
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Entry e(Entry::LOADS32_SHIFT, dst, op1, op2, Entry::RIGHT);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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ir.push(e);
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} else {
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u32 shift = 8 * ((address ^ 3) & 3);
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u32 mask = 0xFFFFFFFF >> shift;
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u32 data = mem.Read<u32>(regs, paddr & ~3);
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s32 result = s32((regs.gpr[RT(instr)] & ~mask) | (data >> shift));
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regs.gpr[RT(instr)] = result;
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}
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}
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}
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void JIT::ld(u32 instr) {
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void JIT::ld(u32 instr) {
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s64 address = regs.gpr[RS(instr)] + (s16)instr;
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auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
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if (check_address_error(0b111, address)) {
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auto op1 = Entry::Operand{ Entry::Operand::MEM_U64, s16(instr) };
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HandleTLBException(regs, address);
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
|
Entry e(Entry::LOADS64, dst, op1, op2);
|
||||||
return;
|
ir.push(e);
|
||||||
}
|
|
||||||
|
|
||||||
u32 paddr = 0;
|
|
||||||
if(!MapVAddr(regs, LOAD, address, paddr)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
s64 value = mem.Read<u64>(regs, paddr);
|
|
||||||
regs.gpr[RT(instr)] = value;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::lld(u32 instr) {
|
void JIT::lld(u32 instr) {
|
||||||
if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
FireException(regs, ExceptionCode::ReservedInstruction, 0, regs.oldPC);
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
return;
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
}
|
auto opc = Entry::Opcode(u16(Entry::Opcode::LOADS64) | Entry::SET_LLBIT);
|
||||||
|
Entry e(opc, dst, op1, op2);
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
ir.push(e);
|
||||||
u32 paddr;
|
|
||||||
if (!MapVAddr(regs, LOAD, address, paddr)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
if ((address & 0b111) > 0) {
|
|
||||||
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
regs.gpr[RT(instr)] = mem.Read<u64>(regs, paddr);
|
|
||||||
regs.cop0.llbit = true;
|
|
||||||
regs.cop0.LLAddr = paddr >> 4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::ldl(u32 instr) {
|
void JIT::ldl(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr = 0;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
if (!MapVAddr(regs, LOAD, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::LOADS64_SHIFT, dst, op1, op2, Entry::LEFT);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
s32 shift = 8 * ((address ^ 0) & 7);
|
|
||||||
u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
|
|
||||||
u64 data = mem.Read<u64>(regs, paddr & ~7);
|
|
||||||
s64 result = (s64) ((regs.gpr[RT(instr)] & ~mask) | (data << shift));
|
|
||||||
regs.gpr[RT(instr)] = result;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::ldr(u32 instr) {
|
void JIT::ldr(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
if (!MapVAddr(regs, LOAD, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::LOADS64_SHIFT, dst, op1, op2, Entry::RIGHT);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
s32 shift = 8 * ((address ^ 7) & 7);
|
|
||||||
u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
|
|
||||||
u64 data = mem.Read<u64>(regs, paddr & ~7);
|
|
||||||
s64 result = (s64) ((regs.gpr[RT(instr)] & ~mask) | (data >> shift));
|
|
||||||
regs.gpr[RT(instr)] = result;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::lbu(u32 instr) {
|
void JIT::lbu(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U8, s16(instr) };
|
||||||
if (!MapVAddr(regs, LOAD, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::LOADU8, dst, op1, op2);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
u8 value = mem.Read<u8>(regs, paddr);
|
|
||||||
regs.gpr[RT(instr)] = value;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::lhu(u32 instr) {
|
void JIT::lhu(u32 instr) {
|
||||||
s64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
if ((address & 0b1) > 0) {
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U16, s16(instr) };
|
||||||
HandleTLBException(regs, address);
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
|
Entry e(Entry::LOADU16, dst, op1, op2);
|
||||||
return;
|
ir.push(e);
|
||||||
}
|
|
||||||
u32 paddr;
|
|
||||||
if (!MapVAddr(regs, LOAD, address, paddr)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
u16 value = mem.Read<u16>(regs, paddr);
|
|
||||||
regs.gpr[RT(instr)] = value;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::lwu(u32 instr) {
|
void JIT::lwu(u32 instr) {
|
||||||
s64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
if ((address & 0b11) > 0) {
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
HandleTLBException(regs, address);
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
|
Entry e(Entry::LOADU16, dst, op1, op2);
|
||||||
return;
|
ir.push(e);
|
||||||
}
|
|
||||||
|
|
||||||
u32 paddr;
|
|
||||||
if (!MapVAddr(regs, LOAD, address, paddr)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
u32 value = mem.Read<u32>(regs, paddr);
|
|
||||||
regs.gpr[RT(instr)] = value;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sb(u32 instr) {
|
void JIT::sb(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U8, s16(instr) };
|
||||||
if (!MapVAddr(regs, STORE, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::STORE8, dst, op1, op2);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
mem.Write<u8>(regs, paddr, regs.gpr[RT(instr)]);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sc(u32 instr) {
|
void JIT::sc(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
if ((address & 0b11) > 0) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
|
auto opc = Entry::Opcode(u16(Entry::STORE32) | Entry::SET_LLBIT);
|
||||||
return;
|
Entry e(opc, dst, op1, op2);
|
||||||
}
|
ir.push(e);
|
||||||
|
|
||||||
if(regs.cop0.llbit) {
|
|
||||||
regs.cop0.llbit = false;
|
|
||||||
u32 paddr = 0;
|
|
||||||
if(!MapVAddr(regs, STORE, address, paddr)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
mem.Write<u32>(regs, paddr, regs.gpr[RT(instr)]);
|
|
||||||
regs.gpr[RT(instr)] = 1;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
regs.gpr[RT(instr)] = 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::scd(u32 instr) {
|
void JIT::scd(u32 instr) {
|
||||||
if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
FireException(regs, ExceptionCode::ReservedInstruction, 0, regs.oldPC);
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
return;
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
}
|
auto opc = Entry::Opcode(u16(Entry::STORE64) | Entry::SET_LLBIT);
|
||||||
|
Entry e(opc, dst, op1, op2);
|
||||||
s64 address = regs.gpr[RS(instr)] + (s16)instr;
|
ir.push(e);
|
||||||
if ((address & 0b111) > 0) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if(regs.cop0.llbit) {
|
|
||||||
regs.cop0.llbit = false;
|
|
||||||
u32 paddr = 0;
|
|
||||||
if(!MapVAddr(regs, STORE, address, paddr)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
mem.Write<u32>(regs, paddr, regs.gpr[RT(instr)]);
|
|
||||||
regs.gpr[RT(instr)] = 1;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
regs.gpr[RT(instr)] = 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sh(u32 instr) {
|
void JIT::sh(u32 instr) {
|
||||||
s64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U16, s16(instr) };
|
||||||
u32 physical;
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
if(!MapVAddr(regs, STORE, address, physical)) {
|
Entry e(Entry::STORE16, dst, op1, op2);
|
||||||
HandleTLBException(regs, address);
|
ir.push(e);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
mem.Write<u16>(regs, physical, regs.gpr[RT(instr)]);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sw(u32 instr) {
|
void JIT::sw(u32 instr) {
|
||||||
s16 offset = instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u64 address = regs.gpr[RS(instr)] + offset;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
if (check_address_error(0b11, address)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::STORE32, dst, op1, op2);
|
||||||
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
|
ir.push(e);
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 physical;
|
|
||||||
if(!MapVAddr(regs, STORE, address, physical)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
mem.Write<u32>(regs, physical, regs.gpr[RT(instr)]);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sd(u32 instr) {
|
void JIT::sd(u32 instr) {
|
||||||
s64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
if (check_address_error(0b111, address)) {
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U64, s16(instr) };
|
||||||
HandleTLBException(regs, address);
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
|
Entry e(Entry::STORE64, dst, op1, op2);
|
||||||
return;
|
ir.push(e);
|
||||||
}
|
|
||||||
|
|
||||||
u32 physical;
|
|
||||||
if(!MapVAddr(regs, STORE, address, physical)) {
|
|
||||||
HandleTLBException(regs, address);
|
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
||||||
} else {
|
|
||||||
mem.Write(regs, physical, regs.gpr[RT(instr)]);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sdl(u32 instr) {
|
void JIT::sdl(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U64, s16(instr) };
|
||||||
if (!MapVAddr(regs, STORE, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::STORE64, dst, op1, op2, Entry::LEFT);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
s32 shift = 8 * ((address ^ 0) & 7);
|
|
||||||
u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
|
|
||||||
u64 data = mem.Read<u64>(regs, paddr & ~7);
|
|
||||||
u64 rt = regs.gpr[RT(instr)];
|
|
||||||
mem.Write(regs, paddr & ~7, (data & ~mask) | (rt >> shift));
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sdr(u32 instr) {
|
void JIT::sdr(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U64, s16(instr) };
|
||||||
if (!MapVAddr(regs, STORE, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::STORE64, dst, op1, op2, Entry::RIGHT);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
s32 shift = 8 * ((address ^ 7) & 7);
|
|
||||||
u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
|
|
||||||
u64 data = mem.Read<u64>(regs, paddr & ~7);
|
|
||||||
u64 rt = regs.gpr[RT(instr)];
|
|
||||||
mem.Write(regs, paddr & ~7, (data & ~mask) | (rt << shift));
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::swl(u32 instr) {
|
void JIT::swl(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
if (!MapVAddr(regs, STORE, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::STORE32, dst, op1, op2, Entry::LEFT);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
u32 shift = 8 * ((address ^ 0) & 3);
|
|
||||||
u32 mask = 0xFFFFFFFF >> shift;
|
|
||||||
u32 data = mem.Read<u32>(regs, paddr & ~3);
|
|
||||||
u32 rt = regs.gpr[RT(instr)];
|
|
||||||
mem.Write<u32>(regs, paddr & ~3, (data & ~mask) | (rt >> shift));
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::swr(u32 instr) {
|
void JIT::swr(u32 instr) {
|
||||||
u64 address = regs.gpr[RS(instr)] + (s16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
u32 paddr;
|
auto op1 = Entry::Operand{ Entry::Operand::MEM_U32, s16(instr) };
|
||||||
if (!MapVAddr(regs, STORE, address, paddr)) {
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
HandleTLBException(regs, address);
|
Entry e(Entry::STORE32, dst, op1, op2, Entry::RIGHT);
|
||||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
ir.push(e);
|
||||||
} else {
|
|
||||||
u32 shift = 8 * ((address ^ 3) & 3);
|
|
||||||
u32 mask = 0xFFFFFFFF << shift;
|
|
||||||
u32 data = mem.Read<u32>(regs, paddr & ~3);
|
|
||||||
u32 rt = regs.gpr[RT(instr)];
|
|
||||||
mem.Write<u32>(regs, paddr & ~3, (data & ~mask) | (rt << shift));
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::ori(u32 instr) {
|
void JIT::ori(u32 instr) {
|
||||||
s64 imm = (u16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rax, GPR(qword, RS(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::IMM_U16, u16(instr) };
|
||||||
CodeGenerator::or_(rax, imm);
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
mov(GPR(qword, RT(instr)), rax);
|
Entry e(Entry::OR, dst, op1, op2);
|
||||||
|
ir.push(e);
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::or_(u32 instr) {
|
void JIT::or_(u32 instr) {
|
||||||
if (RD(instr) != 0) [[likely]] {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RD(instr)) };
|
||||||
mov(rax, GPR(qword, RS(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rcx, GPR(qword, RT(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
CodeGenerator::or_(rax, rcx);
|
Entry e(Entry::OR, dst, op1, op2);
|
||||||
mov(GPR(qword, RD(instr)), rax);
|
ir.push(e);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::nor(u32 instr) {
|
void JIT::nor(u32 instr) {
|
||||||
if (RD(instr) != 0) [[likely]] {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RD(instr)) };
|
||||||
mov(rax, GPR(qword, RS(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rcx, GPR(qword, RT(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
CodeGenerator::or_(rax, rcx);
|
Entry e(Entry::NOR, dst, op1, op2);
|
||||||
not_(rax);
|
ir.push(e);
|
||||||
mov(GPR(qword, RD(instr)), rax);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::j(u32 instr) {
|
void JIT::j(u32 instr) {
|
||||||
@@ -733,37 +481,35 @@ void JIT::sltu(u32 instr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void JIT::xori(u32 instr) {
|
void JIT::xori(u32 instr) {
|
||||||
s64 imm = (u16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rax, imm);
|
auto op1 = Entry::Operand{ Entry::Operand::IMM_U16, u16(instr)};
|
||||||
mov(rcx, GPR(qword, RS(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
CodeGenerator::xor_(rcx, rax);
|
Entry e(Entry::XOR, dst, op1, op2);
|
||||||
mov(GPR(qword, RT(instr)), rcx);
|
ir.push(e);
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::xor_(u32 instr) {
|
void JIT::xor_(u32 instr) {
|
||||||
if (RD(instr) != 0) [[likely]] {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RD(instr)) };
|
||||||
mov(rax, GPR(qword, RT(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rcx, GPR(qword, RS(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
CodeGenerator::xor_(rax, rcx);
|
Entry e(Entry::XOR, dst, op1, op2);
|
||||||
mov(GPR(qword, RD(instr)), rax);
|
ir.push(e);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::andi(u32 instr) {
|
void JIT::andi(u32 instr) {
|
||||||
s64 imm = (u16)instr;
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rax, (u16)instr);
|
auto op1 = Entry::Operand{ Entry::Operand::IMM_U16, u16(instr) };
|
||||||
mov(rcx, GPR(qword, RS(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
CodeGenerator::and_(rcx, rax);
|
Entry e(Entry::AND, dst, op1, op2);
|
||||||
mov(GPR(qword, RT(instr)), rcx);
|
ir.push(e);
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::and_(u32 instr) {
|
void JIT::and_(u32 instr) {
|
||||||
if (RD(instr) != 0) [[likely]] {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RD(instr)) };
|
||||||
mov(rax, GPR(qword, RT(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
mov(rcx, GPR(qword, RS(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
CodeGenerator::and_(rax, rcx);
|
Entry e(Entry::AND, dst, op1, op2);
|
||||||
mov(GPR(qword, RD(instr)), rax);
|
ir.push(e);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sll(u32 instr) {
|
void JIT::sll(u32 instr) {
|
||||||
@@ -966,12 +712,11 @@ void JIT::jr(u32 instr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void JIT::dsub(u32 instr) {
|
void JIT::dsub(u32 instr) {
|
||||||
if (RD(instr) != 0) [[likely]] {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RD(instr)) };
|
||||||
mov(rax, GPR(qword, RT(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
mov(rcx, GPR(qword, RS(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
CodeGenerator::sub(rcx, rax);
|
Entry e(Entry::SUB, dst, op1, op2);
|
||||||
mov(GPR(qword, RD(instr)), rcx);
|
ir.push(e);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::dsubu(u32 instr) {
|
void JIT::dsubu(u32 instr) {
|
||||||
@@ -979,13 +724,11 @@ void JIT::dsubu(u32 instr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void JIT::sub(u32 instr) {
|
void JIT::sub(u32 instr) {
|
||||||
if (RD(instr) != 0) [[likely]] {
|
auto dst = Entry::Operand{ Entry::Operand::REG_S64, u8(RD(instr)) };
|
||||||
mov(eax, GPR(qword, RT(instr)));
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S32, u8(RS(instr)) };
|
||||||
mov(ecx, GPR(qword, RS(instr)));
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S32, u8(RT(instr)) };
|
||||||
CodeGenerator::sub(ecx, eax);
|
Entry e(Entry::SUB, dst, op1, op2);
|
||||||
movsxd(rax, ecx);
|
ir.push(e);
|
||||||
mov(GPR(qword, RD(instr)), rax);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::subu(u32 instr) {
|
void JIT::subu(u32 instr) {
|
||||||
@@ -993,35 +736,31 @@ void JIT::subu(u32 instr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void JIT::dmultu(u32 instr) {
|
void JIT::dmultu(u32 instr) {
|
||||||
u64 rt = regs.gpr[RT(instr)];
|
auto op1 = Entry::Operand{ Entry::Operand::REG_U64, u8(RS(instr)) };
|
||||||
u64 rs = regs.gpr[RS(instr)];
|
auto op2 = Entry::Operand{ Entry::Operand::REG_U64, u8(RT(instr)) };
|
||||||
u128 result = (u128)rt * (u128)rs;
|
Entry e(Entry::UMUL, op1, op2);
|
||||||
regs.lo = (s64)(result & 0xFFFFFFFFFFFFFFFF);
|
ir.push(e);
|
||||||
regs.hi = (s64)(result >> 64);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::dmult(u32 instr) {
|
void JIT::dmult(u32 instr) {
|
||||||
s64 rt = regs.gpr[RT(instr)];
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||||
s64 rs = regs.gpr[RS(instr)];
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||||
s128 result = (s128)rt * (s128)rs;
|
Entry e(Entry::SMUL, op1, op2);
|
||||||
regs.lo = result & 0xFFFFFFFFFFFFFFFF;
|
ir.push(e);
|
||||||
regs.hi = result >> 64;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::multu(u32 instr) {
|
void JIT::multu(u32 instr) {
|
||||||
u32 rt = regs.gpr[RT(instr)];
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S32, u8(RS(instr)) };
|
||||||
u32 rs = regs.gpr[RS(instr)];
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S32, u8(RT(instr)) };
|
||||||
u64 result = (u64)rt * (u64)rs;
|
Entry e(Entry::UMUL, op1, op2);
|
||||||
regs.lo = (s64)((s32)result);
|
ir.push(e);
|
||||||
regs.hi = (s64)((s32)(result >> 32));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::mult(u32 instr) {
|
void JIT::mult(u32 instr) {
|
||||||
s32 rt = regs.gpr[RT(instr)];
|
auto op1 = Entry::Operand{ Entry::Operand::REG_S32, u8(RS(instr)) };
|
||||||
s32 rs = regs.gpr[RS(instr)];
|
auto op2 = Entry::Operand{ Entry::Operand::REG_S32, u8(RT(instr)) };
|
||||||
s64 result = (s64)rt * (s64)rs;
|
Entry e(Entry::SMUL, op1, op2);
|
||||||
regs.lo = (s64)((s32)result);
|
ir.push(e);
|
||||||
regs.hi = (s64)((s32)(result >> 32));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void JIT::mflo(u32 instr) {
|
void JIT::mflo(u32 instr) {
|
||||||
|
|||||||
Reference in New Issue
Block a user