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Huge refactor: Make Core a singleton

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This commit is contained in:
irisz64
2025-07-29 11:08:05 +02:00
parent e0e887ce90
commit 3061334004
56 changed files with 426 additions and 594 deletions
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59
src/backend/core/interpreter/instructions.cpp
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@@ -1,4 +1,4 @@
#include <core/Interpreter.hpp>
#include <Core.hpp>
#define check_signed_overflow(op1, op2, res) (((~((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
#define check_signed_underflow(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
@@ -194,7 +194,7 @@ void Interpreter::lb(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
regs.Write(RT(instr), (s8)mem.Read<u8>(regs, paddr));
regs.Write(RT(instr), (s8)mem.Read<u8>(paddr));
}
}
@@ -211,7 +211,7 @@ void Interpreter::lh(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
regs.Write(RT(instr), (s16)mem.Read<u16>(regs, paddr));
regs.Write(RT(instr), (s16)mem.Read<u16>(paddr));
}
}
@@ -229,7 +229,7 @@ void Interpreter::lw(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
regs.Write(RT(instr), (s32)mem.Read<u32>(regs, physical));
regs.Write(RT(instr), (s32)mem.Read<u32>(physical));
}
}
@@ -240,7 +240,7 @@ void Interpreter::ll(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
const s32 result = mem.Read<u32>(regs, physical);
const s32 result = mem.Read<u32>(physical);
if (check_address_error(0b11, address)) {
regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
return;
@@ -262,7 +262,7 @@ void Interpreter::lwl(const u32 instr) {
} else {
const u32 shift = 8 * ((address ^ 0) & 3);
const u32 mask = 0xFFFFFFFF << shift;
const u32 data = mem.Read<u32>(regs, paddr & ~3);
const u32 data = mem.Read<u32>(paddr & ~3);
const s32 result = s32((regs.Read<s64>(RT(instr)) & ~mask) | (data << shift));
regs.Write(RT(instr), result);
}
@@ -277,7 +277,7 @@ void Interpreter::lwr(const u32 instr) {
} else {
const u32 shift = 8 * ((address ^ 3) & 3);
const u32 mask = 0xFFFFFFFF >> shift;
const u32 data = mem.Read<u32>(regs, paddr & ~3);
const u32 data = mem.Read<u32>(paddr & ~3);
const s32 result = s32((regs.Read<s64>(RT(instr)) & ~mask) | (data >> shift));
regs.Write(RT(instr), result);
}
@@ -296,7 +296,7 @@ void Interpreter::ld(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
const s64 value = mem.Read<u64>(regs, paddr);
const s64 value = mem.Read<u64>(paddr);
regs.Write(RT(instr), value);
}
}
@@ -316,7 +316,7 @@ void Interpreter::lld(const u32 instr) {
if (check_address_error(0b111, address)) {
regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
} else {
regs.Write(RT(instr), mem.Read<u64>(regs, paddr));
regs.Write(RT(instr), mem.Read<u64>(paddr));
regs.cop0.llbit = true;
regs.cop0.LLAddr = paddr >> 4;
}
@@ -332,7 +332,7 @@ void Interpreter::ldl(const u32 instr) {
} else {
const s32 shift = 8 * ((address ^ 0) & 7);
const u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
const u64 data = mem.Read<u64>(regs, paddr & ~7);
const u64 data = mem.Read<u64>(paddr & ~7);
const s64 result = (s64)((regs.Read<s64>(RT(instr)) & ~mask) | (data << shift));
regs.Write(RT(instr), result);
}
@@ -347,7 +347,7 @@ void Interpreter::ldr(const u32 instr) {
} else {
const s32 shift = 8 * ((address ^ 7) & 7);
const u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
const u64 data = mem.Read<u64>(regs, paddr & ~7);
const u64 data = mem.Read<u64>(paddr & ~7);
const s64 result = (s64)((regs.Read<s64>(RT(instr)) & ~mask) | (data >> shift));
regs.Write(RT(instr), result);
}
@@ -360,7 +360,7 @@ void Interpreter::lbu(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
const u8 value = mem.Read<u8>(regs, paddr);
const u8 value = mem.Read<u8>(paddr);
regs.Write(RT(instr), value);
}
}
@@ -377,7 +377,7 @@ void Interpreter::lhu(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
const u16 value = mem.Read<u16>(regs, paddr);
const u16 value = mem.Read<u16>(paddr);
regs.Write(RT(instr), value);
}
}
@@ -395,7 +395,7 @@ void Interpreter::lwu(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
} else {
const u32 value = mem.Read<u32>(regs, paddr);
const u32 value = mem.Read<u32>(paddr);
regs.Write(RT(instr), value);
}
}
@@ -407,7 +407,7 @@ void Interpreter::sb(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
mem.Write<u8>(regs, paddr, regs.Read<s64>(RT(instr)));
mem.Write<u8>(paddr, regs.Read<s64>(RT(instr)));
}
}
@@ -430,7 +430,7 @@ void Interpreter::sc(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
mem.Write<u32>(regs, paddr, regs.Read<s64>(RT(instr)));
mem.Write<u32>(paddr, regs.Read<s64>(RT(instr)));
regs.Write(RT(instr), 1);
}
} else {
@@ -462,7 +462,7 @@ void Interpreter::scd(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
mem.Write<u32>(regs, paddr, regs.Read<s64>(RT(instr)));
mem.Write<u32>(paddr, regs.Read<s64>(RT(instr)));
regs.Write(RT(instr), 1);
}
} else {
@@ -478,7 +478,7 @@ void Interpreter::sh(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
mem.Write<u16>(regs, physical, regs.Read<s64>(RT(instr)));
mem.Write<u16>(physical, regs.Read<s64>(RT(instr)));
}
}
@@ -496,7 +496,7 @@ void Interpreter::sw(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
mem.Write<u32>(regs, physical, regs.Read<s64>(RT(instr)));
mem.Write<u32>(physical, regs.Read<s64>(RT(instr)));
}
}
@@ -513,7 +513,7 @@ void Interpreter::sd(const u32 instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
mem.Write(regs, physical, regs.Read<s64>(RT(instr)));
mem.Write(physical, regs.Read<s64>(RT(instr)));
}
}
@@ -526,9 +526,9 @@ void Interpreter::sdl(const u32 instr) {
} else {
const s32 shift = 8 * ((address ^ 0) & 7);
const u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
const u64 data = mem.Read<u64>(regs, paddr & ~7);
const u64 data = mem.Read<u64>(paddr & ~7);
const u64 rt = regs.Read<s64>(RT(instr));
mem.Write(regs, paddr & ~7, (data & ~mask) | (rt >> shift));
mem.Write(paddr & ~7, (data & ~mask) | (rt >> shift));
}
}
@@ -541,9 +541,9 @@ void Interpreter::sdr(const u32 instr) {
} else {
const s32 shift = 8 * ((address ^ 7) & 7);
const u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
const u64 data = mem.Read<u64>(regs, paddr & ~7);
const u64 data = mem.Read<u64>(paddr & ~7);
const u64 rt = regs.Read<s64>(RT(instr));
mem.Write(regs, paddr & ~7, (data & ~mask) | (rt << shift));
mem.Write(paddr & ~7, (data & ~mask) | (rt << shift));
}
}
@@ -556,9 +556,9 @@ void Interpreter::swl(const u32 instr) {
} else {
const u32 shift = 8 * ((address ^ 0) & 3);
const u32 mask = 0xFFFFFFFF >> shift;
const u32 data = mem.Read<u32>(regs, paddr & ~3);
const u32 data = mem.Read<u32>(paddr & ~3);
const u32 rt = regs.Read<s64>(RT(instr));
mem.Write<u32>(regs, paddr & ~3, (data & ~mask) | (rt >> shift));
mem.Write<u32>(paddr & ~3, (data & ~mask) | (rt >> shift));
}
}
@@ -571,9 +571,9 @@ void Interpreter::swr(const u32 instr) {
} else {
const u32 shift = 8 * ((address ^ 3) & 3);
const u32 mask = 0xFFFFFFFF << shift;
const u32 data = mem.Read<u32>(regs, paddr & ~3);
const u32 data = mem.Read<u32>(paddr & ~3);
const u32 rt = regs.Read<s64>(RT(instr));
mem.Write<u32>(regs, paddr & ~3, (data & ~mask) | (rt << shift));
mem.Write<u32>(paddr & ~3, (data & ~mask) | (rt << shift));
}
}
@@ -824,8 +824,9 @@ void Interpreter::mtlo(const u32 instr) { regs.lo = regs.Read<s64>(RS(instr)); }
void Interpreter::mthi(const u32 instr) { regs.hi = regs.Read<s64>(RS(instr)); }
void Interpreter::trap(const bool cond) const {
Cop0& cop0 = Core::GetInstance().cpu->GetRegs().cop0;
if (cond) {
regs.cop0.FireException(ExceptionCode::Trap, 0, regs.oldPC);
cop0.FireException(ExceptionCode::Trap, 0, regs.oldPC);
}
}