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fix buncha things, can't be assed to list

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This commit is contained in:
CocoSimone
2023-02-10 16:16:16 +01:00
parent 5d35fb229f
commit 30c6931f09
12 changed files with 332 additions and 374 deletions
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36
src/backend/core/Mem.hpp
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@@ -28,30 +28,18 @@ struct Mem {
return mmio.rdp.rdram.data();
}
template <bool tlb = true>
u8 Read8(Registers&, u64, s64);
template <bool tlb = true>
u16 Read16(Registers&, u64, s64);
template <bool tlb = true>
u32 Read32(Registers&, u64, s64);
template <bool tlb = true>
u64 Read64(Registers&, u64, s64);
template <bool tlb = true>
void Write8(Registers&, JIT::Dynarec&, u64, u32, s64);
template <bool tlb = true>
void Write16(Registers&, JIT::Dynarec&, u64, u32, s64);
template <bool tlb = true>
void Write32(Registers&, JIT::Dynarec&, u64, u32, s64);
template <bool tlb = true>
void Write64(Registers&, JIT::Dynarec&, u64, u64, s64);
template <bool tlb = true>
void Write8(Registers&, u64, u32, s64);
template <bool tlb = true>
void Write16(Registers&, u64, u32, s64);
template <bool tlb = true>
void Write32(Registers&, u64, u32, s64);
template <bool tlb = true>
void Write64(Registers&, u64, u64, s64);
u8 Read8(Registers&, u32);
u16 Read16(Registers&, u32);
u32 Read32(Registers&, u32);
u64 Read64(Registers&, u32);
void Write8(Registers&, JIT::Dynarec&, u32, u32);
void Write16(Registers&, JIT::Dynarec&, u32, u32);
void Write32(Registers&, JIT::Dynarec&, u32, u32);
void Write64(Registers&, JIT::Dynarec&, u32, u64);
void Write8(Registers&, u32, u32);
void Write16(Registers&, u32, u32);
void Write32(Registers&, u32, u32);
void Write64(Registers&, u32, u64);
MMIO mmio;
u8 pifRam[PIF_RAM_SIZE]{};