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fix some warnings and use the damn FORCE_INLINE macro otherwise what's it there for

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SimoneN64
2023-06-05 20:54:34 +02:00
parent 776634a293
commit 32c66fdf5f
25 changed files with 139 additions and 133 deletions
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67
src/backend/core/mmio/PI.cpp
View File

@@ -14,7 +14,6 @@ void PI::Reset() {
cartAddr = 0;
rdLen = 0;
wrLen = 0;
memset(stub, 0, 8);
}
auto PI::Read(MI& mi, u32 addr) const -> u32 {
@@ -46,14 +45,14 @@ auto PI::Read(MI& mi, u32 addr) const -> u32 {
FORCE_INLINE u8 PIGetDomain(u32 address) {
switch (address) {
case 0x6000000 ... 0x7FFFFFF:
case REGION_CART_1_2:
case CART_REGION_1_1:
case CART_REGION_1_2:
return 1;
case REGION_CART_2_1:
case REGION_CART_2_2:
case CART_REGION_2_1:
case CART_REGION_2_2:
return 2;
default:
logfatal("Unknown PI domain for address %08X!\n", address);
Util::panic("Unknown PI domain for address {:08X}!", address);
}
}
@@ -63,20 +62,20 @@ FORCE_INLINE u32 PIAccessTiming(PI& pi, u8 domain, u32 length) {
uint32_t pulse_width = 0;
uint32_t release = 0;
uint32_t page_size = 0;
uint32_t pages = 0;
uint32_t pages;
switch (domain) {
case 1:
latency = pi.pi_bsd_dom1_lat + 1;
pulse_width = pi.pi_bsd_dom1_pwd + 1;
release = pi.pi_bsd_dom1_rls + 1;
page_size = pow(2, (pi.pi_bsd_dom1_pgs + 2));
page_size = std::pow(2, (pi.pi_bsd_dom1_pgs + 2));
break;
case 2:
latency = pi.pi_bsd_dom2_lat + 1;
pulse_width = pi.pi_bsd_dom2_pwd + 1;
release = pi.pi_bsd_dom2_rls + 1;
page_size = pow(2, (pi.pi_bsd_dom2_pgs + 2));
page_size = std::pow(2, (pi.pi_bsd_dom2_pgs + 2));
break;
default:
Util::panic("Unknown PI domain: %d\n", domain);
@@ -90,26 +89,6 @@ FORCE_INLINE u32 PIAccessTiming(PI& pi, u8 domain, u32 length) {
return cycles * 1.5; // Converting RCP clock speed to CPU clock speed
}
template <bool toCart>
FORCE_INLINE void DMA(Mem& mem, Registers& regs) {
MI& mi = mem.mmio.mi;
PI& pi = mem.mmio.pi;
u32 len = toCart ? pi.rdLen : pi.wrLen;
u32 cart_addr = pi.cartAddr & 0xFFFFFFFE;
u32 dram_addr = pi.dramAddr & 0x007FFFFE;
for(int i = 0; i < len; i++) {
if constexpr (toCart) {
mem.rom.cart[BYTE_ADDRESS(cart_addr + i) & mem.rom.mask] = mem.mmio.rdp.rdram[BYTE_ADDRESS(dram_addr + i) & RDRAM_DSIZE];
} else {
mem.mmio.rdp.rdram[BYTE_ADDRESS(dram_addr + i) & RDRAM_DSIZE] = mem.rom.cart[BYTE_ADDRESS(cart_addr + i) & mem.rom.mask];
}
}
pi.dramAddr = dram_addr + len;
pi.cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, pi.dramAddr, pi.cartAddr);
}
void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
MI& mi = mem.mmio.mi;
switch(addr) {
@@ -123,7 +102,14 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
len -= dram_addr & 0x7;
}
rdLen = len;
scheduler.enqueueRelative(Event{, DMA<true>});
for(int i = 0; i < len; i++) {
mem.rom.cart[BYTE_ADDRESS(cart_addr + i) & mem.rom.mask] = mem.mmio.rdp.rdram[BYTE_ADDRESS(dram_addr + i) & RDRAM_DSIZE];
}
dramAddr = dram_addr + len;
cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
} break;
case 0x0460000C: {
u32 len = (val & 0x00FFFFFF) + 1;
@@ -133,16 +119,27 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
len -= (dram_addr & 0x7);
}
wrLen = len;
scheduler.enqueueRelative(Event{, DMA<false>});
for(int i = 0; i < len; i++) {
mem.mmio.rdp.rdram[BYTE_ADDRESS(dram_addr + i) & RDRAM_DSIZE] = mem.rom.cart[BYTE_ADDRESS(cart_addr + i) & mem.rom.mask];
}
dramAddr = dram_addr + len;
cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cartAddr, dramAddr);
} break;
case 0x04600010:
if(val & 2) {
InterruptLower(mi, regs, Interrupt::PI);
} break;
case 0x04600014: case 0x04600018: case 0x0460001C: case 0x04600020:
case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030:
stub[(addr & 0xff) - 5] = val & 0xff;
break;
case 0x04600014: pi_bsd_dom1_lat = val & 0xff; break;
case 0x04600018: pi_bsd_dom1_pwd = val & 0xff; break;
case 0x0460001C: pi_bsd_dom1_pgs = val & 0xff; break;
case 0x04600020: pi_bsd_dom1_rls = val & 0xff; break;
case 0x04600024: pi_bsd_dom2_lat = val & 0xff; break;
case 0x04600028: pi_bsd_dom2_pwd = val & 0xff; break;
case 0x0460002C: pi_bsd_dom2_pgs = val & 0xff; break;
case 0x04600030: pi_bsd_dom2_rls = val & 0xff; break;
default:
Util::panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
}

4
src/backend/core/mmio/PIF.cpp
View File

@@ -34,7 +34,7 @@ void PIF::LoadMempak(fs::path path) {
fclose(f);
}
inline size_t getSaveSize(SaveType saveType) {
FORCE_INLINE size_t getSaveSize(SaveType saveType) {
switch (saveType) {
case SAVE_NONE:
return 0;
@@ -110,7 +110,7 @@ void PIF::CICChallenge() {
}
}
inline u8 data_crc(const u8* data) {
FORCE_INLINE u8 data_crc(const u8* data) {
u8 crc = 0;
for (int i = 0; i <= 32; i++) {
for (int j = 7; j >= 0; j--) {

2
src/backend/core/mmio/PIF.hpp
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@@ -127,7 +127,7 @@ struct PIF {
ram[addr & PIF_RAM_DSIZE] = val;
}
inline AccessoryType getAccessoryType() const {
FORCE_INLINE AccessoryType getAccessoryType() const {
if (channel >= 4 || joybusDevices[channel].type != JOYBUS_CONTROLLER) {
return ACCESSORY_NONE;
} else {