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Squashed 'external/capstone/' changes from 5430745e..b102f1b8

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b102f1b8 Update Actions (#2593)
86293136 Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594)
27da950c Clarify between machine used vs. Capstone module affected. (#2586)
186f7aa0 Fix linking issue on Windows. (#2587)
e160cbc5 Fix complex atomic instructions handling (#2584)
9907b22d Update v6 to have Debian Packages (#2579)
efbbc3bb cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally (#2581)
be6be784 x86: update read/write registers for transfer instructions (#2578)
812e654c Update BPF arch (#2568)
2c4b05f6 Clean up the cstest documentation and build instructions. (#2580)
4dc14ba1 Fix 2572 (#2574)
b25aa841 PPC regressions (#2575)
0a29bf80 Small arm64 compat header fixes (#2563)
b42e0903 Make thumb, v8 and m-class positional cstool arguments. (#2557)
89aee400 Add arm64 and sysz compatibility layer to Python bindings (#2559)
a4281337 Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 (#2558)
ef74d449 Arm regressions (#2556)
93a104c0 PPC LLVM 18 (#2540)
e46838ed Merge branch 'v6' into next
cf3600e7 Update Changelog Version to 6.0.0-Alpha2 (#2553)
b295cf57 Prepare for update (#2552)
fc59da4d fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551)
7d01d7e7 Auto-Sync reproducability + ARM update (#2532)
6ad2608d Python package building rework (#2538)
e3bc578d Move debian package generation to a dispatch only workflow (#2543)
abbf32b4 fix coverity (#2546)
1ecfb5b0 xtensa: update to espressif/llvm-project (#2533)
379e2a41 Rename build arguments: (#2534)
d7be5f9f Change CI to create Debian Package to Release (#2521)
f6f96796 tricore: fixes #2474 (#2523)
09f35961 This time actually fix big endian issue. (#2530)
306d5716 Fix endianess issue during assignment. (#2528)
2cfca35e Add CC and VAS compatibility macros (#2525)
32519c01 Fix stringop-truncation warning some compilers raise. (#2522)
5026c2c4 Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64
cecb5ede Fix #2509. (#2510)
f97e2705 xtensa: Fix Branch Target (#2516)
1d13a12f AArch64: Replace vararg add_cs_detail by multiple concrete functions
8b618528 Update libcyaml dependency in cstest to 1.4.2 (#2508)
ea081286 Tricore EA calculation (#2504)
7db9a080 Fix cstest build with Ninja (#2506)
76242699 Only trigger on released action. (#2497)
981d648b Add hard asserts to all SStream functions and memset MCInst. (#2501)
d667a627 Update labeler with Xtensa and v6 files. (#2500)
52b54ee3 Fixing UB santizer, `LITBASE` and assert errors. (#2499)
97db712c Remove irrelevant changes. (#2496)
5bd05e34 Remove irrelevant changes. (#2495)
616488c7 Update changelog for V6.0.0-Alpha1 (#2493) (#2494)
c5955b92 Update changelog for V6.0.0-Alpha1 (#2493)
a424e709 Be ready for V6-Alpha1 (#2492)
235ba8e0 SystemZ fixes (#2488)
5dffa75b Fix LDR not assigning immediate as memory offset. (#2487)
21f7bc85 Xtensa Support (#2380)
29d87734 Several small fixups (#2489)
a34901e9 Update sponsors and remove empty file. (#2485)
3120932d Fix Coverity CID 509730: overflow before widen (#2486)
1014864d Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482)
0c90fe13 Replace `assert` with `CS_ASSERT` in modules (#2478)
823bfd53 AArch64 issues (#2473)

git-subtree-dir: external/capstone
git-subtree-split: b102f1b89e0455c072a751d287ab64378c14205f
This commit is contained in:
Simone
2025-01-07 15:08:55 +00:00
parent 352a52804d
commit 3621a6c080
1521 changed files with 323443 additions and 365407 deletions
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219
arch/PowerPC/PPCDisassembler.c
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@@ -104,6 +104,14 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
return decodeRegisterClass(Inst, RegNo, FRegs);
}
static DecodeStatus DecodeFpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
if (RegNo > 30 || (RegNo & 1))
return MCDisassembler_Fail;
return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
}
static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
@@ -257,29 +265,39 @@ static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
N)(MCInst * Inst, uint64_t Imm, \
int64_t Address, const void *Decoder) \
{ \
if (!isUIntN(N, Imm)) \
return MCDisassembler_Fail; \
MCOperand_CreateImm0(Inst, (Imm)); \
return MCDisassembler_Success; \
}
DEFINE_decodeUImmOperand(5) DEFINE_decodeUImmOperand(16)
DEFINE_decodeUImmOperand(6) DEFINE_decodeUImmOperand(10)
DEFINE_decodeUImmOperand(8) DEFINE_decodeUImmOperand(7)
DEFINE_decodeUImmOperand(12)
DEFINE_decodeUImmOperand(1);
DEFINE_decodeUImmOperand(2);
DEFINE_decodeUImmOperand(3);
DEFINE_decodeUImmOperand(4);
DEFINE_decodeUImmOperand(5);
DEFINE_decodeUImmOperand(6);
DEFINE_decodeUImmOperand(7);
DEFINE_decodeUImmOperand(8);
DEFINE_decodeUImmOperand(10);
DEFINE_decodeUImmOperand(12);
DEFINE_decodeUImmOperand(16);
#define DEFINE_decodeSImmOperand(N) \
static DecodeStatus CONCAT(decodeSImmOperand, \
N)(MCInst * Inst, uint64_t Imm, \
int64_t Address, const void *Decoder) \
{ \
MCOperand_CreateImm0(Inst, (SignExtend64(Imm, N))); \
if (!isUIntN(N, Imm)) \
return MCDisassembler_Fail; \
MCOperand_CreateImm0(Inst, (SignExtend64((Imm), N))); \
return MCDisassembler_Success; \
}
DEFINE_decodeSImmOperand(16)
DEFINE_decodeSImmOperand(5)
DEFINE_decodeSImmOperand(34)
DEFINE_decodeSImmOperand(16);
DEFINE_decodeSImmOperand(5);
DEFINE_decodeSImmOperand(34);
static DecodeStatus
decodeImmZeroOperand(MCInst *Inst, uint64_t Imm, int64_t Address,
const void *Decoder)
static DecodeStatus decodeImmZeroOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
if (Imm != 0)
return MCDisassembler_Fail;
@@ -297,158 +315,65 @@ static DecodeStatus decodeVSRpEvenOperands(MCInst *Inst, uint64_t RegNo,
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memri field (imm, reg), which has the low 16-bits as the
// displacement and the next 5 bits as the register #.
uint64_t Base = Imm >> 16;
uint64_t Disp = Imm & 0xFFFF;
switch (MCInst_getOpcode(Inst)) {
default:
break;
case PPC_LBZU:
case PPC_LHAU:
case PPC_LHZU:
case PPC_LWZU:
case PPC_LFSU:
case PPC_LFDU:
// Add the tied output operand.
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
break;
case PPC_STBU:
case PPC_STHU:
case PPC_STWU:
case PPC_STFSU:
case PPC_STFDU:
MCInst_insert0(Inst, 0,
MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
break;
}
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memrix field (imm, reg), which has the low 14-bits as the
// displacement and the next 5 bits as the register #.
uint64_t Base = Imm >> 14;
uint64_t Disp = Imm & 0x3FFF;
if (MCInst_getOpcode(Inst) == PPC_LDU)
// Add the tied output operand.
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
else if (MCInst_getOpcode(Inst) == PPC_STDU)
MCInst_insert0(Inst, 0,
MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 2, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIHashOperands(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the memrix field for a hash store or hash check operation.
// The field is composed of a register and an immediate value that is 6 bits
// and covers the range -8 to -512. The immediate is always negative and 2s
// complement which is why we sign extend a 7 bit value.
const uint64_t Base = Imm >> 6;
const int64_t Disp = SignExtend64((Imm & 0x3F) + 64, 7) * 8;
MCOperand_CreateImm0(Inst, (Disp));
MCOperand_CreateReg0(Inst, (RRegs[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
// displacement with 16-byte aligned, and the next 5 bits as the register #.
uint64_t Base = Imm >> 12;
uint64_t Disp = Imm & 0xFFF;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 4, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRI34PCRelOperands(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as
// the displacement, and the next 5 bits as an immediate 0.
uint64_t Base = Imm >> 34;
uint64_t Disp = Imm & 0x3FFFFFFFFUL;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
return decodeImmZeroOperand(Inst, Base, Address, Decoder);
}
static DecodeStatus decodeMemRI34Operands(MCInst *Inst, uint64_t Imm,
static DecodeStatus decodeDispSPE8Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memri34 field (imm, reg), which has the low 34-bits as the
// displacement, and the next 5 bits as the register #.
uint64_t Base = Imm >> 34;
uint64_t Disp = Imm & 0x3FFFFFFFFUL;
// Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the spe8disp field (imm, reg), which has the low 5-bits as the
// displacement with 8-byte aligned, and the next 5 bits as the register #.
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
MCOperand_CreateImm0(Inst, (Disp << 3));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
static DecodeStatus decodeDispSPE4Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the spe4disp field (imm, reg), which has the low 5-bits as the
// displacement with 4-byte aligned, and the next 5 bits as the register #.
// Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
MCOperand_CreateImm0(Inst, (Disp << 2));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
static DecodeStatus decodeDispSPE2Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the spe2disp field (imm, reg), which has the low 5-bits as the
// displacement with 2-byte aligned, and the next 5 bits as the register #.
// Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
MCOperand_CreateImm0(Inst, (Disp << 1));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeDispRIXOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// The rix displacement is an immediate shifted by 2
MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 2), 16)));
return MCDisassembler_Success;
}
static DecodeStatus decodeDispRIX16Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// The rix16 displacement has 12-bits which are shifted by 4.
MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 4), 16)));
return MCDisassembler_Success;
}
static DecodeStatus decodeDispRIHashOperand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the disp field for a hash store or hash check operation.
// The field is composed of an immediate value that is 6 bits
// and covers the range -8 to -512. The immediate is always negative and 2s
// complement which is why we sign extend a 7 bit value.
const int64_t Disp = SignExtend64(((Imm & 0x3F) + 64), 7) * 8;
MCOperand_CreateImm0(Inst, (Disp));
return MCDisassembler_Success;
}
@@ -486,7 +411,7 @@ DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
uint32_t BaseInst = readBytes32(MI, Bytes + 4);
uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
DecodeStatus result =
decodeInstruction_4(DecoderTable64, MI, Inst, Address);
decodeInstruction_4(DecoderTable64, MI, Inst, Address, NULL);
if (result != MCDisassembler_Fail) {
*Size = 8;
return result;
@@ -505,22 +430,22 @@ DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureQPX)) {
DecodeStatus result = decodeInstruction_4(DecoderTableQPX32, MI,
Inst, Address);
Inst, Address, NULL);
if (result != MCDisassembler_Fail)
return result;
} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureSPE)) {
DecodeStatus result = decodeInstruction_4(DecoderTableSPE32, MI,
Inst, Address);
Inst, Address, NULL);
if (result != MCDisassembler_Fail)
return result;
} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeaturePS)) {
DecodeStatus result = decodeInstruction_4(DecoderTablePS32, MI,
Inst, Address);
Inst, Address, NULL);
if (result != MCDisassembler_Fail)
return result;
}
return decodeInstruction_4(DecoderTable32, MI, Inst, Address);
return decodeInstruction_4(DecoderTable32, MI, Inst, Address, NULL);
}
DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes,