Figure out why the program counter never stops increasing after a certain point

src/backend/core/Interpreter.cpp

@@ -52,6 +52,18 @@ bool Interpreter::MaybeAdvance() {
         return false;
     }
 
+    regs.push_to_stack_trace(regs.pc);
+    if ((u32)regs.pc == 0x4) {
+        auto &regs = Core::GetRegs();
+        std::sort(regs.stack_trace.begin(), regs.stack_trace.end());
+
+        std::println("Stack trace:");
+        for (int i = 0; i < regs.stack_trace.size(); i++) {
+            std::println("    [{:016X}]", regs.stack_trace[i]);
+        }
+        exit(1);
+    }
+
     regs.oldPC = regs.pc;
     regs.pc = regs.nextPC;
     regs.nextPC += 4;
@@ -101,23 +113,22 @@ u32 DivideAddr(u32 addr, u32 &offset) {
     return addr / MAX_LINES_PER_BLOCK;
 }
 
-CachedLine *CachedState::GetLine(u64 addr) {
+std::shared_ptr<CachedLine> CachedState::GetLine(u64 addr) {
     u32 offset;
     u32 page = DivideAddr(addr, offset);
-    if (blocks[page] && blocks[page]->valid)
-        return &blocks[page]->lines[offset];
+    if (blocks[page])
+        return blocks[page]->lines[offset];
 
     return nullptr;
 }
 
-void CachedState::InsertLine(u64 addr, const CachedLine &line) {
+void CachedState::InsertLine(u64 addr, std::shared_ptr<CachedLine> line) {
     u32 offset;
     u32 page = DivideAddr(addr, offset);
 
     if (!blocks[page])
         blocks[page] = std::make_unique<CachedBlock>();
 
-    blocks[page]->valid = true;
     blocks[page]->lines[offset] = line;
 }
 
@@ -125,8 +136,8 @@ void CachedState::EvictLine(u64 addr) {
     u32 offset;
     u32 page = DivideAddr(addr, offset);
 
-    if (blocks[page] && blocks[page]->valid)
-        blocks[page]->valid = false;
+    if (blocks[page])
+        blocks[page] = nullptr;
 }
 
 u32 Interpreter::ExecuteCached() {
@@ -141,13 +152,12 @@ u32 Interpreter::ExecuteCached() {
 
             Instruction instr = line->code[i];
             DecodeExecute(instr);
-            if (IsBranchLikely(instr) && !regs.delaySlot) {
-                line->len -= 1; // Branch likely with false condition, it wasn't taken so don't execute the delay slot
-                                // and remove it from the cache
-                if (line->len <= 0)
-                    line->len = 1;
+
+            Core::GetInstance().StepRSP(1);
+
+            // Branch likely with false condition, it wasn't taken so don't execute the delay slot
+            if (IsBranchLikely(instr) && !regs.delaySlot)
                 break;
-            }
         }
 
         if (line->cycles == 0)
@@ -182,7 +192,7 @@ u32 Interpreter::ExecuteCached() {
         }
     }
 
-    cachedState.InsertLine(block_addr, {code, i, i});
+    cachedState.InsertLine(block_addr, std::make_shared<CachedLine>(code, i, i));
 
     return ExecuteCached();
 }