it's a start...

src/backend/core/RSP.cpp

@@ -1,5 +1,6 @@
 #include <Core.hpp>
 #include <log.hpp>
+#include <jit/helpers.hpp>
 
 namespace n64 {
 RSP::RSP() { Reset(); }
@@ -230,4 +231,70 @@ void RSP::Write(const u32 addr, const u32 val) {
         panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
     }
 }
+
+void RSP::CacheBlock(u16 addr) {
+    auto blockAddr = addr;
+
+    CachedLine line;
+    u32 i;
+    bool fetchDelaySlot = false;
+
+    for (i = 0; i < MAX_INSTR_PER_BLOCK; i++) {
+        Instruction instr = ircolib::ReadAccess<u32>(imem, addr & IMEM_DSIZE);
+
+        addr += 4;
+        line.code[i] = instr;
+
+        if (fetchDelaySlot) {
+            i++;
+            break;
+        }
+
+        if (InstrEndsBlock(instr)) {
+            if (InstrHasDelaySlot(instr) && !fetchDelaySlot) {
+                fetchDelaySlot = true;
+                continue;
+            }
+
+            if (i == 0)
+                i = 1;
+
+            break;
+        }
+    }
+
+    line.cycles = i;
+    line.len = i;
+    cachedState.blocks[CACHE_GET_BLOCK(blockAddr)]->lines[CACHE_GET_LINE(blockAddr)] = new CachedLine(line);
+
+    return ExecuteCached();
+}
+
+void RSP::ExecuteCached() {
+    u16 addr = pc;
+    auto &blocks = cachedState.blocks;
+    if (!blocks[CACHE_GET_BLOCK(addr)]) {
+        blocks[CACHE_GET_BLOCK(addr)] = new CachedBlock<cachedState.MAX_LINES / 4>();
+        return CacheBlock(addr);
+    }
+
+    const auto line = blocks[CACHE_GET_BLOCK(addr)]->lines[CACHE_GET_LINE(addr)];
+    if (line) {
+        for (u32 i = 0; i < line->len; i++) {
+            prevDelaySlot = delaySlot;
+            delaySlot = false;
+
+            oldPC = pc & 0xFFC;
+            pc = nextPC & 0xFFC;
+            nextPC += 4;
+
+            Instruction instr = line->code[i];
+            Exec(instr);
+        }
+
+        return;
+    }
+
+    return CacheBlock(addr);
+}
 } // namespace n64