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Move "Step" out of Interpreter.hpp

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SimoneN64
2023-07-25 09:15:32 +02:00
parent 698032f0a1
commit 44c3a6f155
2 changed files with 30 additions and 28 deletions
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29
src/backend/core/Interpreter.cpp
View File

@@ -5,4 +5,33 @@ void Interpreter::Reset() {
regs.Reset(); regs.Reset();
mem.Reset(); mem.Reset();
} }
int Interpreter::Step() {
CheckCompareInterrupt();
regs.prevDelaySlot = regs.delaySlot;
regs.delaySlot = false;
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, regs.pc, paddr)) {
HandleTLBException(regs, regs.pc);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, false);
return 0;
}
u32 instruction = mem.Read32(regs, paddr);
if(ShouldServiceInterrupt()) {
FireException(regs, ExceptionCode::Interrupt, 0, false);
return 0;
}
regs.oldPC = regs.pc;
regs.pc = regs.nextPC;
regs.nextPC += 4;
Exec(instruction);
return 1;
}
} }

29
src/backend/core/Interpreter.hpp
View File

@@ -8,34 +8,7 @@ struct Core;
struct Interpreter : BaseCPU { struct Interpreter : BaseCPU {
Interpreter() = default; Interpreter() = default;
~Interpreter() override = default; ~Interpreter() override = default;
FORCE_INLINE int Step() override { int Step() override;
CheckCompareInterrupt();
regs.prevDelaySlot = regs.delaySlot;
regs.delaySlot = false;
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, regs.pc, paddr)) {
HandleTLBException(regs, regs.pc);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, false);
return 0;
}
u32 instruction = mem.Read32(regs, paddr);
if(ShouldServiceInterrupt()) {
FireException(regs, ExceptionCode::Interrupt, 0, false);
return 0;
}
regs.oldPC = regs.pc;
regs.pc = regs.nextPC;
regs.nextPC += 4;
Exec(instruction);
return 1;
}
void Reset() override; void Reset() override;
Registers regs; Registers regs;
Mem mem; Mem mem;