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src/backend/core/Interpreter.cpp

@@ -93,14 +93,6 @@ u32 Interpreter::Step() {
 
     DecodeExecute(instr);
 
-    if (!mem.mmio.rsp.spStatus.halt) {
-        rspSyncCount++;
-        if (rspSyncCount >= 3)
-            Scheduler::GetInstance().EnqueueRelative(0, RSP_STEP);
-    }
-
-    Scheduler::GetInstance().HandleEvents();
-
     return 1;
 }
 
@@ -132,8 +124,10 @@ void CachedState::EvictLine(u64 addr) {
     u32 offset;
     u32 page = DivideAddr(addr, offset);
 
-    if (blocks[page])
-        blocks[page] = nullptr;
+    if (blocks[page]) {
+        blocks[page]->lines[offset].reset();
+        blocks[page].reset();
+    }
 }
 
 u32 Interpreter::ExecuteCached() {
@@ -149,7 +143,6 @@ u32 Interpreter::ExecuteCached() {
             Instruction instr = line->code[i];
             DecodeExecute(instr);
 
-            Scheduler::GetInstance().HandleEvents();
             // Branch likely with false condition, it wasn't taken so don't execute the delay slot
             if (IsBranchLikely(instr) && !regs.delaySlot)
                 break;
@@ -187,15 +180,6 @@ u32 Interpreter::ExecuteCached() {
         }
     }
 
-    if (!mem.mmio.rsp.spStatus.halt) {
-        for (int j = 1; j <= (int)std::floor((double)i / 3); j++) {
-            Scheduler::GetInstance().EnqueueRelative(j * 3, RSP_STEP);
-        }
-    } else {
-        regs.steps = 0;
-        mem.mmio.rsp.steps = 0;
-    }
-
     cachedState.InsertLine(blockAddr, std::make_shared<CachedLine>(code, i, i));
 
     return ExecuteCached();