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No more segfault in JIT. Keeps executing the same blocks over and over though...

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CocoSimone
2023-01-04 16:50:33 +01:00
parent 5da1e2a443
commit 64630ea06b
43 changed files with 823 additions and 849 deletions
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8
src/backend/core/rsp/instructions.cpp
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@@ -45,7 +45,7 @@ inline auto GetCop0Reg(RSP& rsp, RDP& rdp, u8 index) -> u32{
case 13: return rdp.dpc.status.cmdBusy;
case 14: return rdp.dpc.status.pipeBusy;
case 15: return rdp.dpc.status.tmemBusy;
default: util::panic("Unhandled RSP COP0 register read at index {}\n", index);
default: Util::panic("Unhandled RSP COP0 register read at index {}\n", index);
}
}
@@ -70,13 +70,13 @@ inline void SetCop0Reg(Registers& regs, Mem& mem, u8 index, u32 val) {
if(val == 0) {
ReleaseSemaphore(rsp);
} else {
util::panic("Write with non-zero value to RSP_COP0_RESERVED ({})\n", val);
Util::panic("Write with non-zero value to RSP_COP0_RESERVED ({})\n", val);
}
break;
case 8: rdp.WriteStart(val); break;
case 9: rdp.WriteEnd(mi, regs, rsp, val); break;
case 11: rdp.WriteStatus(mi, regs, rsp, val); break;
default: util::panic("Unhandled RSP COP0 register write at index {}\n", index);
default: Util::panic("Unhandled RSP COP0 register write at index {}\n", index);
}
}
@@ -735,7 +735,7 @@ void RSP::vmov(u32 instr) {
se = (e & 0b111) | (vs & 0b000);
break;
default:
util::panic("VMOV: This should be unreachable!\n");
Util::panic("VMOV: This should be unreachable!\n");
}
u8 de = vs & 7;