asdjkfhaskdjdf
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@@ -52,18 +52,6 @@ bool Interpreter::MaybeAdvance() {
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return false;
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}
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regs.push_to_stack_trace(regs.pc);
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if ((u32)regs.pc == 0x4) {
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auto ®s = Core::GetRegs();
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std::sort(regs.stack_trace.begin(), regs.stack_trace.end());
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std::println("Stack trace:");
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for (int i = 0; i < regs.stack_trace.size(); i++) {
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std::println(" [{:016X}]", regs.stack_trace[i]);
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}
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exit(1);
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}
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regs.oldPC = regs.pc;
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regs.pc = regs.nextPC;
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regs.nextPC += 4;
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@@ -105,6 +93,14 @@ u32 Interpreter::Step() {
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DecodeExecute(instr);
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if (!mem.mmio.rsp.spStatus.halt) {
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rspSyncCount++;
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if (rspSyncCount >= 3)
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Scheduler::GetInstance().EnqueueRelative(0, RSP_STEP);
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}
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Scheduler::GetInstance().HandleEvents();
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return 1;
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}
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@@ -142,7 +138,7 @@ void CachedState::EvictLine(u64 addr) {
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u32 Interpreter::ExecuteCached() {
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auto addr = regs.pc;
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auto block_addr = addr;
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auto blockAddr = addr;
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auto line = cachedState.GetLine(addr);
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if (line) {
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@@ -153,8 +149,7 @@ u32 Interpreter::ExecuteCached() {
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Instruction instr = line->code[i];
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DecodeExecute(instr);
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Core::GetInstance().StepRSP(1);
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Scheduler::GetInstance().HandleEvents();
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// Branch likely with false condition, it wasn't taken so don't execute the delay slot
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if (IsBranchLikely(instr) && !regs.delaySlot)
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break;
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@@ -192,7 +187,16 @@ u32 Interpreter::ExecuteCached() {
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}
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}
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cachedState.InsertLine(block_addr, std::make_shared<CachedLine>(code, i, i));
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if (!mem.mmio.rsp.spStatus.halt) {
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for (int j = 1; j <= (int)std::floor((double)i / 3); j++) {
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Scheduler::GetInstance().EnqueueRelative(j * 3, RSP_STEP);
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}
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} else {
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regs.steps = 0;
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mem.mmio.rsp.steps = 0;
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}
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cachedState.InsertLine(blockAddr, std::make_shared<CachedLine>(code, i, i));
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return ExecuteCached();
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}
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