prep cache impl

.clangd

@@ -0,0 +1,4 @@
+CompileFlags:
+  CompilationDatabase: build/
+Completion:
+  HeaderInsertion: Never

src/backend/Core.cpp

@@ -62,9 +62,7 @@ void Core::LoadROM(const std::string &rom_) {
     romLoaded = true;
 }
 
-u32 Core::StepCPU() {
+u32 Core::StepCPU() { return cpu->Step() + regs.PopStalledCycles(); }
-  return cpu->Step() + regs.PopStalledCycles();
-}
 
 void Core::StepRSP(const u32 cpuCycles) {
     MMIO &mmio = mem->mmio;

src/backend/core/BaseCPU.hpp

@@ -4,6 +4,27 @@
 #include <Disassembler.hpp>
 
 namespace n64 {
+struct alignas(32) InstructionCache {
+    bool valid;
+    u32 data[8];
+    u32 ptag;
+
+  private:
+    int GetLineIndex(u64 vaddr) { return (vaddr >> 5) & 0x1FF; }
+    u32 GetLineStart(u64 paddr) { return paddr & ~0x1F; }
+};
+
+struct alignas(32) DataCache {
+    bool valid, dirty;
+    u8 data[16];
+    u32 ptag;
+    int index;
+
+  private:
+    int GetLineIndex(u64 vaddr) { return (vaddr >> 4) & 0x1FF; }
+    u32 GetLineStart(u64 paddr) { return paddr & ~0xF; }
+};
+
 struct BaseCPU {
     virtual ~BaseCPU() = default;
     virtual u32 Step() = 0;