prep cache impl

.clangd

@@ -0,0 +1,4 @@
+CompileFlags:
+  CompilationDatabase: build/
+Completion:
+  HeaderInsertion: Never

src/backend/Core.cpp

@@ -9,13 +9,13 @@ Core::Core() {
     if (selectedCpu == "interpreter") {
         cpuType = Interpreted;
         cpu = std::make_unique<Interpreter>(*mem, regs);
-  } else if(selectedCpu == "jit") {
-    #ifndef __aarch64__
+    } else if (selectedCpu == "jit") {
+#ifndef __aarch64__
         cpuType = DynamicRecompiler;
         cpu = std::make_unique<JIT>(*mem, regs);
-    #else
+#else
         panic("JIT currently unsupported on aarch64");
-    #endif
+#endif
     } else {
         panic("Unimplemented CPU type");
     }
@@ -31,7 +31,7 @@ void Core::Reset() {
     regs.Reset();
     mem->Reset();
     cpu->Reset();
-  if(romLoaded)
+    if (romLoaded)
         mem->mmio.si.pif.Execute();
 }
 
@@ -62,9 +62,7 @@ void Core::LoadROM(const std::string &rom_) {
     romLoaded = true;
 }
 
-u32 Core::StepCPU() {
-  return cpu->Step() + regs.PopStalledCycles();
-}
+u32 Core::StepCPU() { return cpu->Step() + regs.PopStalledCycles(); }
 
 void Core::StepRSP(const u32 cpuCycles) {
     MMIO &mmio = mem->mmio;
@@ -101,11 +99,11 @@ void Core::Run(const float volumeL, const float volumeR) {
                 mmio.mi.InterruptRaise(MI::Interrupt::VI);
             }
 
-      while(cycles < mem->mmio.vi.cyclesPerHalfline) {
+            while (cycles < mem->mmio.vi.cyclesPerHalfline) {
                 const u32 taken = StepCPU();
                 cycles += taken;
 
-        if((broken = breakpoints.contains(regs.nextPC)))
+                if ((broken = breakpoints.contains(regs.nextPC)))
                     break;
 
                 StepRSP(taken);
@@ -113,13 +111,13 @@ void Core::Run(const float volumeL, const float volumeR) {
                 Scheduler::GetInstance().Tick(taken);
             }
 
-      if(broken)
+            if (broken)
                 break;
 
             cycles -= mmio.vi.cyclesPerHalfline;
         }
 
-    if(broken)
+        if (broken)
             break;
 
         if ((mmio.vi.current & 0x3FE) == mmio.vi.intr) {
@@ -130,7 +128,7 @@ void Core::Run(const float volumeL, const float volumeR) {
         Scheduler::GetInstance().Tick(frameCycles);
     }
 
-  if(broken)
+    if (broken)
         pause = true;
 }
 } // namespace n64

src/backend/core/BaseCPU.hpp

@@ -4,6 +4,27 @@
 #include <Disassembler.hpp>
 
 namespace n64 {
+struct alignas(32) InstructionCache {
+    bool valid;
+    u32 data[8];
+    u32 ptag;
+
+  private:
+    int GetLineIndex(u64 vaddr) { return (vaddr >> 5) & 0x1FF; }
+    u32 GetLineStart(u64 paddr) { return paddr & ~0x1F; }
+};
+
+struct alignas(32) DataCache {
+    bool valid, dirty;
+    u8 data[16];
+    u32 ptag;
+    int index;
+
+  private:
+    int GetLineIndex(u64 vaddr) { return (vaddr >> 4) & 0x1FF; }
+    u32 GetLineStart(u64 paddr) { return paddr & ~0xF; }
+};
+
 struct BaseCPU {
     virtual ~BaseCPU() = default;
     virtual u32 Step() = 0;