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[Apple Arm] Disable JIT stuff under ARM64 for now

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This commit is contained in:
SimoneN64
2025-02-09 20:53:17 +01:00
parent b819299308
commit 7d27351609
4 changed files with 18 additions and 0 deletions
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2
src/backend/core/JIT.cpp
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@@ -2,6 +2,7 @@
#include <jit/helpers.hpp>
namespace n64 {
#ifndef __aarch64__
JIT::JIT(ParallelRDP &parallel) : regs(this), mem(regs, parallel, this) {
blockCache.resize(kUpperSize);
if (cs_open(CS_ARCH_MIPS, static_cast<cs_mode>(CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN), &disassemblerMips) !=
@@ -183,4 +184,5 @@ std::vector<u8> JIT::Serialize() {
}
void JIT::Deserialize(const std::vector<u8> &data) { memcpy(&regs, data.data(), sizeof(Registers)); }
#endif
} // namespace n64

4
src/backend/core/JIT.hpp
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@@ -18,6 +18,9 @@ static constexpr u32 kCodeCacheSize = 32_mb;
static constexpr u32 kCodeCacheAllocSize = kCodeCacheSize + 4_kb;
#define REG(acc, x) code.acc[code.rbp + (reinterpret_cast<uintptr_t>(&regs.x) - (uintptr_t)this)]
#ifdef __aarch64__
struct JIT : BaseCPU {};
#else
struct JIT : BaseCPU {
explicit JIT(ParallelRDP &);
~JIT() override = default;
@@ -222,4 +225,5 @@ private:
void xor_(u32);
void xori(u32);
};
#endif
} // namespace n64

8
src/backend/core/Mem.cpp
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@@ -357,12 +357,14 @@ void Mem::WriteInterpreter<u8>(Registers &regs, u32 paddr, u32 val) {
}
}
#ifndef __aarch64__
template <>
void Mem::WriteJIT<u8>(Registers &regs, const u32 paddr, const u32 val) {
WriteInterpreter<u8>(regs, paddr, val);
if (jit)
jit->InvalidateBlock(paddr);
}
#endif
template <>
void Mem::Write<u8>(Registers &regs, const u32 paddr, const u32 val) {
@@ -410,12 +412,14 @@ void Mem::WriteInterpreter<u16>(Registers &regs, u32 paddr, u32 val) {
}
}
#ifndef __aarch64__
template <>
void Mem::WriteJIT<u16>(Registers &regs, const u32 paddr, const u32 val) {
WriteInterpreter<u16>(regs, paddr, val);
if (jit)
jit->InvalidateBlock(paddr);
}
#endif
template <>
void Mem::Write<u16>(Registers &regs, const u32 paddr, const u32 val) {
@@ -460,23 +464,27 @@ void Mem::WriteInterpreter<u32>(Registers &regs, const u32 paddr, const u32 val)
}
}
#ifndef __aarch64__
template <>
void Mem::WriteJIT<u32>(Registers &regs, const u32 paddr, const u32 val) {
WriteInterpreter<u32>(regs, paddr, val);
if (jit)
jit->InvalidateBlock(paddr);
}
#endif
template <>
void Mem::Write<u32>(Registers &regs, const u32 paddr, const u32 val) {
WriteInterpreter<u32>(regs, paddr, val);
}
#ifndef __aarch64__
void Mem::WriteJIT(const Registers &regs, const u32 paddr, const u64 val) {
WriteInterpreter(regs, paddr, val);
if (jit)
jit->InvalidateBlock(paddr);
}
#endif
void Mem::Write(const Registers &regs, const u32 paddr, const u64 val) { WriteInterpreter(regs, paddr, val); }

4
src/backend/core/registers/Registers.cpp
View File

@@ -75,6 +75,7 @@ s8 Registers::Read<s8>(size_t idx) {
return static_cast<s8>(Read<u8>(idx));
}
#ifndef __aarch64__
template <>
void Registers::Read<u64>(size_t idx, Xbyak::Reg reg) {
jit->code.mov(reg.cvt64(), jit->GPR<u64>(idx));
@@ -114,6 +115,7 @@ template <>
void Registers::Read<s8>(size_t idx, Xbyak::Reg reg) {
jit->code.mov(reg.cvt8(), jit->GPR<s8>(idx));
}
#endif
template <>
void Registers::Write<bool>(size_t idx, bool v) {
@@ -195,6 +197,7 @@ void Registers::Write<s8>(size_t idx, s8 v) {
gpr[idx] = v;
}
#ifndef __aarch64__
template <>
void Registers::Write<bool>(size_t idx, Xbyak::Reg v) {
if (idx == 0)
@@ -310,4 +313,5 @@ template <>
void Registers::Write<s64>(size_t idx, Xbyak::Reg v) {
Write<u64>(idx, v);
}
#endif
} // namespace n64