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get rid of fmt dependency since we are on C++23

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irisz64
2025-07-22 11:30:37 +02:00
parent 9b169825ee
commit 8549d5a21c
173 changed files with 452 additions and 83654 deletions
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10
src/backend/core/Disassembler.cpp
View File

@@ -8,7 +8,7 @@ Disassembler::DisassemblyResult Disassembler::DisassembleSimple(const u32 addres
if (count <= 0)
return {};
DisassemblyResult result{true, fmt::format("0x{:016X}:\t{}\t{}", insn[0].address, insn[0].mnemonic, insn[0].op_str)};
DisassemblyResult result{true, std::format("0x{:016X}:\t{}\t{}", insn[0].address, insn[0].mnemonic, insn[0].op_str)};
cs_free(insn, count);
@@ -27,18 +27,18 @@ Disassembler::DisassemblyResult Disassembler::DisassembleDetailed(const u32 addr
result.address = insn[0].address;
result.mnemonic = insn[0].mnemonic;
result.full += fmt::format("0x{:016X}", result.address) + ":\t";
result.full += std::format("0x{:016X}", result.address) + ":\t";
result.full += result.mnemonic + "\t";
const cs_detail *details = insn[0].detail;
auto formatOperand = [&](const cs_mips_op &operand) {
switch (operand.type) {
case MIPS_OP_IMM:
return fmt::format("#{:X}", operand.is_unsigned ? operand.uimm : operand.imm);
return std::format("#{:X}", operand.is_unsigned ? operand.uimm : operand.imm);
case MIPS_OP_MEM:
return fmt::format("{}(0x{:X})", cs_reg_name(handle, operand.mem.base), operand.mem.disp);
return std::format("{}(0x{:X})", cs_reg_name(handle, operand.mem.base), operand.mem.disp);
case MIPS_OP_REG:
return fmt::format("{}", cs_reg_name(handle, operand.reg));
return std::format("{}", cs_reg_name(handle, operand.reg));
default:
return std::string{""};
}

4
src/backend/core/Disassembler.hpp
View File

@@ -31,11 +31,11 @@ private:
explicit Disassembler(const bool rsp) : rsp(rsp) {
if (cs_open(CS_ARCH_MIPS, static_cast<cs_mode>((rsp ? CS_MODE_32 : CS_MODE_64) | CS_MODE_BIG_ENDIAN), &handle) !=
CS_ERR_OK) {
Util::panic("Could not initialize {} disassembler!", rsp ? "RSP" : "CPU");
panic("Could not initialize {} disassembler!", rsp ? "RSP" : "CPU");
}
if (cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON) != CS_ERR_OK) {
Util::warn("Could not enable disassembler's details!");
warn("Could not enable disassembler's details!");
details = false;
}
}

28
src/backend/core/JIT.cpp
View File

@@ -7,11 +7,11 @@ JIT::JIT(ParallelRDP &parallel) : regs(this), mem(regs, parallel, this) {
blockCache.resize(kUpperSize);
if (cs_open(CS_ARCH_MIPS, static_cast<cs_mode>(CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN), &disassemblerMips) !=
CS_ERR_OK) {
Util::panic("Failed to initialize MIPS disassembler");
panic("Failed to initialize MIPS disassembler");
}
if (cs_open(CS_ARCH_X86, static_cast<cs_mode>(CS_MODE_64 | CS_MODE_LITTLE_ENDIAN), &disassemblerX86) != CS_ERR_OK) {
Util::panic("Failed to initialize x86 disassembler");
panic("Failed to initialize x86 disassembler");
}
}
@@ -46,14 +46,14 @@ u32 JIT::FetchInstruction() {
regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, blockPC);
return 1;*/
Util::panic("[JIT]: Unhandled exception ADL due to unaligned PC virtual value! (0x{:016X})", blockPC);
panic("[JIT]: Unhandled exception ADL due to unaligned PC virtual value! (0x{:016X})", blockPC);
}
if (!regs.cop0.MapVAddr(Cop0::LOAD, blockPC, paddr)) {
/*regs.cop0.HandleTLBException(blockPC);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, blockPC);
return 1;*/
Util::panic(
panic(
"[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address! (virtual: 0x{:016X})",
static_cast<int>(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD)), static_cast<u64>(blockPC));
}
@@ -71,7 +71,7 @@ int JIT::Step() {
/*regs.cop0.HandleTLBException(blockPC);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, blockPC);
return 1;*/
Util::panic("[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address! (virtual: 0x{:016X})",
panic("[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address! (virtual: 0x{:016X})",
static_cast<int>(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD)), static_cast<u64>(blockPC));
}
@@ -80,14 +80,14 @@ int JIT::Step() {
if (!blockCache[upperIndex].empty()) {
if (blockCache[upperIndex][lowerIndex]) {
// Util::trace("[JIT]: Executing already compiled block @ 0x{:016X}", blockPC);
// trace("[JIT]: Executing already compiled block @ 0x{:016X}", blockPC);
return blockCache[upperIndex][lowerIndex]();
}
} else {
blockCache[upperIndex].resize(kLowerSize);
}
Util::trace("[JIT]: Compiling block @ 0x{:016X}:", blockPC);
trace("[JIT]: Compiling block @ 0x{:016X}:", blockPC);
const auto blockInfo = code.getCurr();
const auto block = code.getCurr<BlockFn>();
blockCache[upperIndex][lowerIndex] = block;
@@ -104,7 +104,7 @@ int JIT::Step() {
code.mov(code.rbp, reinterpret_cast<uintptr_t>(this)); // Load context pointer
//cs_insn *insn;
Util::trace("\tMIPS code (guest PC = 0x{:016X}):", blockPC);
trace("\tMIPS code (guest PC = 0x{:016X}):", blockPC);
while (!instrEndsBlock) {
// CheckCompareInterrupt();
@@ -122,10 +122,10 @@ int JIT::Step() {
auto count = cs_disasm(disassemblerMips, reinterpret_cast<const u8 *>(&bswapped), 4, blockPC, 0, &insn);
if (count > 0) {
Util::trace("\t\t0x{:016X}:\t{}\t\t{}\n", insn->address, insn->mnemonic, insn->op_str);
trace("\t\t0x{:016X}:\t{}\t\t{}\n", insn->address, insn->mnemonic, insn->op_str);
cs_free(insn, count);
} else {
Util::trace("\t\tCould not disassemble 0x{:08X} due to error {}\n", instruction, (int)cs_errno(disassemblerMips));
trace("\t\tCould not disassemble 0x{:08X} due to error {}\n", instruction, (int)cs_errno(disassemblerMips));
}
if(ShouldServiceInterrupt()) {
@@ -140,7 +140,7 @@ int JIT::Step() {
const u32 delay_instruction = FetchInstruction();
instrEndsBlock = InstrEndsBlock(delay_instruction);
if(instrEndsBlock)
Util::panic("Branch in delay slot - YOU SHOULD KILL YOURSELF, NOW!!!");
panic("Branch in delay slot - YOU SHOULD KILL YOURSELF, NOW!!!");
blockOldPC = blockPC;
blockPC = blockNextPC;
@@ -167,18 +167,18 @@ int JIT::Step() {
//static auto blockInfoSize = 0;
//blockInfoSize = code.getSize() - blockInfoSize;
//Util::trace("\tX86 code (block address = 0x{:016X}):", (uintptr_t)block);
//trace("\tX86 code (block address = 0x{:016X}):", (uintptr_t)block);
//auto count = cs_disasm(disassemblerX86, blockInfo, blockInfoSize, (uintptr_t)block, 0, &insn);
//if (count > 0) {
// for (size_t j = 0; j < count; j++) {
// Util::trace("\t\t0x{:016X}:\t{}\t\t{}\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
// trace("\t\t0x{:016X}:\t{}\t\t{}\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
// }
//
// cs_free(insn, count);
//}
// const auto dump = code.getCode();
// Util::WriteFileBinary(dump, code.getSize(), "jit.dump");
// Util::panic("");
// panic("");
return block();
}

26
src/backend/core/JIT.hpp
View File

@@ -67,7 +67,7 @@ private:
return code.qword[code.rbp + (reinterpret_cast<uintptr_t>(&regs.gpr[index]) - reinterpret_cast<uintptr_t>(this))];
}
Util::panic("[JIT]: Invalid register addressing");
panic("[JIT]: Invalid register addressing");
// never actually hit, but just to silence the warning "not all control paths return a value"
return Xbyak::Address{0};
}
@@ -229,17 +229,17 @@ private:
void mthi(u32);
void mtlo(u32);
void nor(u32);
void sb(u32) { Util::panic("[JIT] Implement sb!"); }
void sc(u32) { Util::panic("[JIT] Implement sc!"); }
void scd(u32) { Util::panic("[JIT] Implement scd!"); }
void sd(u32) { Util::panic("[JIT] Implement sd!"); }
void sdc1(u32) { Util::panic("[JIT] Implement sdc1!"); }
void sdl(u32) { Util::panic("[JIT] Implement sdl!"); }
void sdr(u32) { Util::panic("[JIT] Implement sdr!"); }
void sh(u32) { Util::panic("[JIT] Implement sh!"); }
void sb(u32) { panic("[JIT] Implement sb!"); }
void sc(u32) { panic("[JIT] Implement sc!"); }
void scd(u32) { panic("[JIT] Implement scd!"); }
void sd(u32) { panic("[JIT] Implement sd!"); }
void sdc1(u32) { panic("[JIT] Implement sdc1!"); }
void sdl(u32) { panic("[JIT] Implement sdl!"); }
void sdr(u32) { panic("[JIT] Implement sdr!"); }
void sh(u32) { panic("[JIT] Implement sh!"); }
void sw(u32);
void swl(u32) { Util::panic("[JIT] Implement swl!"); }
void swr(u32) { Util::panic("[JIT] Implement swr!"); }
void swl(u32) { panic("[JIT] Implement swl!"); }
void swr(u32) { panic("[JIT] Implement swr!"); }
void slti(u32);
void sltiu(u32);
void slt(u32);
@@ -248,12 +248,12 @@ private:
void sllv(u32);
void sub(u32);
void subu(u32);
void swc1(u32) { Util::panic("[JIT] Implement swc1!"); }
void swc1(u32) { panic("[JIT] Implement swc1!"); }
void sra(u32);
void srav(u32);
void srl(u32);
void srlv(u32);
void trap(bool) { Util::panic("[JIT] Implement trap!"); }
void trap(bool) { panic("[JIT] Implement trap!"); }
void or_(u32);
void ori(u32);
void xor_(u32);

4
src/backend/core/MMIO.cpp
View File

@@ -32,7 +32,7 @@ u32 MMIO::Read(u32 addr) {
case SI_REGION:
return si.Read(addr);
default:
Util::panic("Unhandled mmio read at addr {:08X}", addr);
panic("Unhandled mmio read at addr {:08X}", addr);
}
}
@@ -63,7 +63,7 @@ void MMIO::Write(const u32 addr, const u32 val) {
si.Write(addr, val);
break;
default:
Util::panic("Unhandled mmio write at addr {:08X} with val {:08X}", addr, val);
panic("Unhandled mmio write at addr {:08X} with val {:08X}", addr, val);
}
}

72
src/backend/core/Mem.cpp
View File

@@ -18,7 +18,7 @@ void Mem::Reset() {
std::error_code error;
saveData.sync(error);
if (error) {
Util::panic("Could not sync save data");
panic("Could not sync save data");
}
saveData.unmap();
}
@@ -35,7 +35,7 @@ void Mem::LoadSRAM(SaveType save_type, fs::path path) {
if (saveData.is_mapped()) {
saveData.sync(error);
if (error) {
Util::panic("Could not sync {}", sramPath);
panic("Could not sync {}", sramPath);
}
saveData.unmap();
}
@@ -47,12 +47,12 @@ void Mem::LoadSRAM(SaveType save_type, fs::path path) {
}
if (sramVec.size() != SRAM_SIZE) {
Util::panic("Corrupt SRAM!");
panic("Corrupt SRAM!");
}
saveData = mio::make_mmap_sink(sramPath, 0, mio::map_entire_file, error);
if (error) {
Util::panic("Could not mmap {}", sramPath);
panic("Could not mmap {}", sramPath);
}
}
}
@@ -78,7 +78,7 @@ FORCE_INLINE void SetROMCIC(u32 checksum, ROM &rom) {
rom.cicType = CIC_NUS_6106_7106;
break;
default:
Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum);
warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum);
rom.cicType = UNKNOWN_CIC_TYPE;
break;
}
@@ -88,7 +88,7 @@ std::vector<u8> Mem::OpenArchive(const std::string &path, size_t &sizeAdjusted)
const auto stream = ar_open_file(fs::path(path).string().c_str());
if (!stream) {
Util::panic("Could not open archive! Are you sure it's an archive?");
panic("Could not open archive! Are you sure it's an archive?");
}
ar_archive *archive = ar_open_zip_archive(stream, false);
@@ -102,7 +102,7 @@ std::vector<u8> Mem::OpenArchive(const std::string &path, size_t &sizeAdjusted)
if (!archive) {
ar_close(stream);
Util::panic("Could not open archive! Are you sure it's a supported archive? (7z, zip, rar and tar are supported)");
panic("Could not open archive! Are you sure it's a supported archive? (7z, zip, rar and tar are supported)");
}
std::vector<u8> buf{};
@@ -123,7 +123,7 @@ std::vector<u8> Mem::OpenArchive(const std::string &path, size_t &sizeAdjusted)
ar_close_archive(archive);
ar_close(stream);
Util::panic("Could not find any rom image in the archive!");
panic("Could not find any rom image in the archive!");
}
ar_close_archive(archive);
@@ -201,7 +201,7 @@ u8 Mem::Read(Registers &regs, const u32 paddr) {
case 0x04100000 ... 0x041FFFFF:
case 0x04600000 ... 0x048FFFFF:
case 0x04300000 ... 0x044FFFFF:
Util::panic("MMIO Read<u8>!\n");
panic("MMIO Read<u8>!\n");
case AI_REGION:
{
const u32 w = mmio.ai.Read(paddr & ~3);
@@ -218,7 +218,7 @@ u8 Mem::Read(Registers &regs, const u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF: // unused
return 0;
default:
Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
return 0;
}
}
@@ -249,7 +249,7 @@ u16 Mem::Read(Registers &regs, const u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF:
return 0;
default:
Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
return 0;
}
}
@@ -280,7 +280,7 @@ u32 Mem::Read(Registers &regs, const u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF:
return 0;
default:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
return 0;
}
}
@@ -311,7 +311,7 @@ u64 Mem::Read(Registers &regs, const u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF:
return 0;
default:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
return 0;
}
}
@@ -333,11 +333,11 @@ void Mem::WriteInterpreter<u8>(Registers &regs, u32 paddr, u32 val) {
}
break;
case REGION_CART:
Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
mmio.pi.BusWrite<u8, false>(paddr, val);
break;
case MMIO_REGION:
Util::panic("MMIO Write<u8>!");
panic("MMIO Write<u8>!");
case PIF_RAM_REGION:
val = val << (8 * (3 - (paddr & 3)));
paddr = (paddr - PIF_RAM_REGION_START) & ~3;
@@ -352,7 +352,7 @@ void Mem::WriteInterpreter<u8>(Registers &regs, u32 paddr, u32 val) {
case 0x80000000 ... 0xFFFFFFFF:
break;
default:
Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
}
}
@@ -388,11 +388,11 @@ void Mem::WriteInterpreter<u16>(Registers &regs, u32 paddr, u32 val) {
}
break;
case REGION_CART:
Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
mmio.pi.BusWrite<u16, false>(paddr, val);
break;
case MMIO_REGION:
Util::panic("MMIO Write<u16>!");
panic("MMIO Write<u16>!");
case PIF_RAM_REGION:
val = val << (16 * !(paddr & 2));
paddr &= ~3;
@@ -407,7 +407,7 @@ void Mem::WriteInterpreter<u16>(Registers &regs, u32 paddr, u32 val) {
case 0x80000000 ... 0xFFFFFFFF:
break;
default:
Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
}
}
@@ -441,7 +441,7 @@ void Mem::WriteInterpreter<u32>(Registers &regs, const u32 paddr, const u32 val)
}
break;
case REGION_CART:
Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
mmio.pi.BusWrite<u32, false>(paddr, val);
break;
case MMIO_REGION:
@@ -459,7 +459,7 @@ void Mem::WriteInterpreter<u32>(Registers &regs, const u32 paddr, const u32 val)
case 0x80000000 ... 0xFFFFFFFF:
break;
default:
Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
}
}
@@ -503,11 +503,11 @@ void Mem::WriteInterpreter(const Registers &regs, const u32 paddr, u64 val) {
}
break;
case REGION_CART:
Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
mmio.pi.BusWrite<false>(paddr, val);
break;
case MMIO_REGION:
Util::panic("MMIO Write!");
panic("MMIO Write!");
case PIF_RAM_REGION:
Util::WriteAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START, bswap(val));
si.pif.ProcessCommands(*this);
@@ -520,7 +520,7 @@ void Mem::WriteInterpreter(const Registers &regs, const u32 paddr, u64 val) {
case 0x80000000 ... 0xFFFFFFFF:
break;
default:
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
}
}
@@ -532,14 +532,14 @@ u32 Mem::BackupRead<u32>(const u32 addr) {
return 0;
case SAVE_EEPROM_4k:
case SAVE_EEPROM_16k:
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
return 0;
case SAVE_FLASH_1m:
return flash.Read<u32>(addr);
case SAVE_SRAM_256k:
return 0xFFFFFFFF;
default:
Util::panic("Backup read word with unknown save type");
panic("Backup read word with unknown save type");
}
}
@@ -550,7 +550,7 @@ u8 Mem::BackupRead<u8>(const u32 addr) {
return 0;
case SAVE_EEPROM_4k:
case SAVE_EEPROM_16k:
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
return 0;
case SAVE_FLASH_1m:
return flash.Read<u8>(addr);
@@ -559,10 +559,10 @@ u8 Mem::BackupRead<u8>(const u32 addr) {
assert(addr < saveData.size());
return saveData[addr];
} else {
Util::panic("Invalid backup Read<u8> if save data is not initialized");
panic("Invalid backup Read<u8> if save data is not initialized");
}
default:
Util::panic("Backup read word with unknown save type");
panic("Backup read word with unknown save type");
}
}
@@ -570,18 +570,18 @@ template <>
void Mem::BackupWrite<u32>(const u32 addr, const u32 val) {
switch (saveType) {
case SAVE_NONE:
Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
warn("Accessing cartridge with save type SAVE_NONE in write word");
break;
case SAVE_EEPROM_4k:
case SAVE_EEPROM_16k:
Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
panic("Accessing cartridge with save type SAVE_EEPROM in write word");
case SAVE_FLASH_1m:
flash.Write<u32>(addr, val);
break;
case SAVE_SRAM_256k:
break;
default:
Util::panic("Backup read word with unknown save type");
panic("Backup read word with unknown save type");
}
}
@@ -589,11 +589,11 @@ template <>
void Mem::BackupWrite<u8>(const u32 addr, const u8 val) {
switch (saveType) {
case SAVE_NONE:
Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
warn("Accessing cartridge with save type SAVE_NONE in write word");
break;
case SAVE_EEPROM_4k:
case SAVE_EEPROM_16k:
Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
panic("Accessing cartridge with save type SAVE_EEPROM in write word");
case SAVE_FLASH_1m:
flash.Write<u8>(addr, val);
break;
@@ -602,11 +602,11 @@ void Mem::BackupWrite<u8>(const u32 addr, const u8 val) {
assert(addr < saveData.size());
saveData[addr] = val;
} else {
Util::panic("Invalid backup Write<u8> if save data is not initialized");
panic("Invalid backup Write<u8> if save data is not initialized");
}
break;
default:
Util::panic("Backup read word with unknown save type");
panic("Backup read word with unknown save type");
}
}

76
src/backend/core/RDP.cpp
View File

@@ -102,7 +102,7 @@ auto RDP::Read(const u32 addr) const -> u32 {
case 0x0410001C:
return dpc.tmem;
default:
Util::panic("Unhandled DP Command Registers read (addr: {:08X})", addr);
panic("Unhandled DP Command Registers read (addr: {:08X})", addr);
}
return 0;
@@ -120,7 +120,7 @@ void RDP::Write(const u32 addr, const u32 val) {
WriteStatus(val);
break;
default:
Util::panic("Unhandled DP Command Registers write (addr: {:08X}, val: {:08X})", addr, val);
panic("Unhandled DP Command Registers write (addr: {:08X}, val: {:08X})", addr, val);
}
}
@@ -150,41 +150,41 @@ void RDP::WriteStatus(const u32 val) {
/*
FORCE_INLINE void logCommand(u8 cmd) {
switch(cmd) {
case 0x08: Util::debug("Fill triangle"); break;
case 0x09: Util::debug("Fill, zbuf triangle"); break;
case 0x0a: Util::debug("Texture triangle"); break;
case 0x0b: Util::debug("Texture, zbuf triangle"); break;
case 0x0c: Util::debug("Shade triangle"); break;
case 0x0d: Util::debug("Shade, zbuf triangle"); break;
case 0x0e: Util::debug("Shade, texture triangle"); break;
case 0x0f: Util::debug("Shade, texture, zbuf triangle"); break;
case 0x24: Util::debug("Texture rectangle"); break;
case 0x25: Util::debug("Texture rectangle flip"); break;
case 0x26: Util::debug("Sync load"); break;
case 0x27: Util::debug("Sync pipe"); break;
case 0x28: Util::debug("Sync tile"); break;
case 0x29: Util::debug("Sync full"); break;
case 0x2a: Util::debug("Set key gb"); break;
case 0x2b: Util::debug("Set key r"); break;
case 0x2c: Util::debug("Set convert"); break;
case 0x2d: Util::debug("Set scissor"); break;
case 0x2e: Util::debug("Set prim depth"); break;
case 0x2f: Util::debug("Set other modes"); break;
case 0x30: Util::debug("Load TLUT"); break;
case 0x32: Util::debug("Set tile size"); break;
case 0x33: Util::debug("Load block"); break;
case 0x34: Util::debug("Load tile"); break;
case 0x35: Util::debug("Set tile"); break;
case 0x36: Util::debug("Fill rectangle"); break;
case 0x37: Util::debug("Set fill color"); break;
case 0x38: Util::debug("Set fog color"); break;
case 0x39: Util::debug("Set blend color"); break;
case 0x3a: Util::debug("Set prim color"); break;
case 0x3b: Util::debug("Set env color"); break;
case 0x3c: Util::debug("Set combine"); break;
case 0x3d: Util::debug("Set texture image"); break;
case 0x3e: Util::debug("Set mask image"); break;
case 0x3f: Util::debug("Set color image"); break;
case 0x08: debug("Fill triangle"); break;
case 0x09: debug("Fill, zbuf triangle"); break;
case 0x0a: debug("Texture triangle"); break;
case 0x0b: debug("Texture, zbuf triangle"); break;
case 0x0c: debug("Shade triangle"); break;
case 0x0d: debug("Shade, zbuf triangle"); break;
case 0x0e: debug("Shade, texture triangle"); break;
case 0x0f: debug("Shade, texture, zbuf triangle"); break;
case 0x24: debug("Texture rectangle"); break;
case 0x25: debug("Texture rectangle flip"); break;
case 0x26: debug("Sync load"); break;
case 0x27: debug("Sync pipe"); break;
case 0x28: debug("Sync tile"); break;
case 0x29: debug("Sync full"); break;
case 0x2a: debug("Set key gb"); break;
case 0x2b: debug("Set key r"); break;
case 0x2c: debug("Set convert"); break;
case 0x2d: debug("Set scissor"); break;
case 0x2e: debug("Set prim depth"); break;
case 0x2f: debug("Set other modes"); break;
case 0x30: debug("Load TLUT"); break;
case 0x32: debug("Set tile size"); break;
case 0x33: debug("Load block"); break;
case 0x34: debug("Load tile"); break;
case 0x35: debug("Set tile"); break;
case 0x36: debug("Fill rectangle"); break;
case 0x37: debug("Set fill color"); break;
case 0x38: debug("Set fog color"); break;
case 0x39: debug("Set blend color"); break;
case 0x3a: debug("Set prim color"); break;
case 0x3b: debug("Set env color"); break;
case 0x3c: debug("Set combine"); break;
case 0x3d: debug("Set texture image"); break;
case 0x3e: debug("Set mask image"); break;
case 0x3f: debug("Set color image"); break;
}
}
*/
@@ -208,7 +208,7 @@ void RDP::RunCommand() {
return;
if (len + remaining_cmds * 4 > 0xFFFFF) {
Util::panic("Too many RDP commands");
panic("Too many RDP commands");
return;
}

34
src/backend/core/RSP.cpp
View File

@@ -34,34 +34,34 @@ void RSP::Reset() {
/*
FORCE_INLINE void logRSP(const RSP& rsp, const u32 instr) {
Util::debug("{:04X} {:08X} ", rsp.oldPC, instr);
debug("{:04X} {:08X} ", rsp.oldPC, instr);
for (auto gpr : rsp.gpr) {
Util::debug("{:08X} ", gpr);
debug("{:08X} ", gpr);
}
for (auto vpr : rsp.vpr) {
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", vpr.element[i]);
debug("{:04X}", vpr.element[i]);
}
Util::debug(" ");
debug(" ");
}
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", rsp.acc.h.element[i]);
debug("{:04X}", rsp.acc.h.element[i]);
}
Util::debug(" ");
debug(" ");
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", rsp.acc.m.element[i]);
debug("{:04X}", rsp.acc.m.element[i]);
}
Util::debug(" ");
debug(" ");
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", rsp.acc.l.element[i]);
debug("{:04X}", rsp.acc.l.element[i]);
}
Util::debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
Util::debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
}
*/
@@ -85,7 +85,7 @@ auto RSP::Read(const u32 addr) -> u32 {
case 0x04080000:
return pc & 0xFFC;
default:
Util::panic("Unimplemented SP register read {:08X}", addr);
panic("Unimplemented SP register read {:08X}", addr);
}
}
@@ -127,7 +127,7 @@ void RSP::DMA<true>() {
u32 mem_address = spDMASPAddr.address & 0xFF8;
u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
Util::trace("SP DMA from RSP to RDRAM (size: {} B, {:08X} to {:08X})", length, mem_address, dram_address);
trace("SP DMA from RSP to RDRAM (size: {} B, {:08X} to {:08X})", length, mem_address, dram_address);
for (u32 i = 0; i < spDMALen.count + 1; i++) {
for (u32 j = 0; j < length; j++) {
@@ -141,7 +141,7 @@ void RSP::DMA<true>() {
mem_address += length;
mem_address &= 0xFF8;
}
Util::trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
lastSuccessfulSPAddr.address = mem_address;
lastSuccessfulSPAddr.bank = spDMASPAddr.bank;
@@ -159,7 +159,7 @@ void RSP::DMA<false>() {
u32 mem_address = spDMASPAddr.address & 0xFF8;
u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
Util::trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
for (u32 i = 0; i < spDMALen.count + 1; i++) {
for (u32 j = 0; j < length; j++) {
@@ -173,7 +173,7 @@ void RSP::DMA<false>() {
mem_address += length;
mem_address &= 0xFF8;
}
Util::trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
lastSuccessfulSPAddr.address = mem_address;
lastSuccessfulSPAddr.bank = spDMASPAddr.bank;
@@ -209,7 +209,7 @@ void RSP::Write(const u32 addr, const u32 val) {
}
break;
default:
Util::panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
}
}
} // namespace n64

4
src/backend/core/interpreter/cop0instructions.cpp
View File

@@ -27,7 +27,7 @@ void Cop0::eret() {
void Cop0::tlbr() {
if (index.i >= 32) {
Util::panic("TLBR with TLB index {}", index.i);
panic("TLBR with TLB index {}", index.i);
}
const TLBEntry entry = tlb[index.i];
@@ -48,7 +48,7 @@ void Cop0::tlbw(const int index_) {
page_mask.mask = top | (top >> 1);
if (index_ >= 32) {
Util::panic("TLBWI with TLB index {}", index_);
panic("TLBWI with TLB index {}", index_);
}
tlb[index_].entryHi.raw = entryHi.raw;

4
src/backend/core/interpreter/cop1instructions.cpp
View File

@@ -539,7 +539,7 @@ void Cop1::cfc1(const u32 instr) {
val = fcr31.read();
break;
default:
Util::panic("Undefined CFC1 with rd != 0 or 31");
panic("Undefined CFC1 with rd != 0 or 31");
}
regs.Write(RT(instr), val);
}
@@ -587,7 +587,7 @@ void Cop1::ctc1(const u32 instr) {
}
break;
default:
Util::panic("Undefined CTC1 with rd != 0 or 31");
panic("Undefined CTC1 with rd != 0 or 31");
}
}

8
src/backend/core/interpreter/decode.cpp
View File

@@ -164,7 +164,7 @@ void Interpreter::special(const u32 instr) {
dsra32(instr);
break;
default:
Util::panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr,
panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr,
static_cast<u64>(regs.oldPC));
}
}
@@ -215,7 +215,7 @@ void Interpreter::regimm(const u32 instr) {
bllink(instr, regs.Read<s64>(RS(instr)) >= 0);
break;
default:
Util::panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr,
panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr,
static_cast<u64>(regs.oldPC));
}
}
@@ -330,7 +330,7 @@ void Interpreter::Exec(const u32 instr) {
bl(instr, regs.cop1.fcr31.compare);
break;
default:
Util::panic("Undefined BC COP1 {:02X}", mask_branch);
panic("Undefined BC COP1 {:02X}", mask_branch);
}
break;
}
@@ -445,7 +445,7 @@ void Interpreter::Exec(const u32 instr) {
sd(instr);
break;
default:
Util::panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, static_cast<u64>(regs.oldPC));
panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, static_cast<u64>(regs.oldPC));
}
}
} // namespace n64

10
src/backend/core/jit/decode.cpp
View File

@@ -163,7 +163,7 @@ void JIT::special(const u32 instr) {
dsra32(instr);
break;
default:
Util::panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr,
panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr,
static_cast<u64>(regs.oldPC));
}
}
@@ -214,7 +214,7 @@ void JIT::regimm(const u32 instr) {
bgezall(instr);
break;
default:
Util::panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr,
panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr,
static_cast<u64>(regs.oldPC));
}
}
@@ -270,7 +270,7 @@ void JIT::Emit(const u32 instr) {
lui(instr);
break;
case COP0:
Util::panic("[JIT]: Unimplemented Cop0 decode");
panic("[JIT]: Unimplemented Cop0 decode");
break;
case COP1:
{
@@ -299,7 +299,7 @@ void JIT::Emit(const u32 instr) {
blfc1(instr);
break;
default:
Util::panic("Undefined BC COP1 {:02X}", mask_branch);
panic("Undefined BC COP1 {:02X}", mask_branch);
}
break;
}
@@ -413,7 +413,7 @@ void JIT::Emit(const u32 instr) {
sd(instr);
break;
default:
Util::panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, static_cast<u64>(regs.oldPC));
panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, static_cast<u64>(regs.oldPC));
}
}
} // namespace n64

150
src/backend/core/jit/instructions.cpp
View File

@@ -20,7 +20,7 @@ void JIT::add(const u32 instr) {
const u32 result = rs + rt;
if (check_signed_overflow(rs, rt, result)) {
// regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
Util::panic("[JIT]: Unhandled Overflow exception in ADD!");
panic("[JIT]: Unhandled Overflow exception in ADD!");
}
regs.Write<s32>(RD(instr), result);
@@ -89,7 +89,7 @@ void JIT::addi(u32 instr) {
auto rs = regs.Read<u32>(RS(instr));
u32 result = rs + imm;
if (check_signed_overflow(rs, imm, result)) {
Util::panic("[JIT]: Unhandled Overflow exception in ADDI!");
panic("[JIT]: Unhandled Overflow exception in ADDI!");
}
regs.Write<s32>(RT(instr), static_cast<s32>(result));
@@ -292,7 +292,7 @@ void JIT::bgez(const u32 instr) {
}
void JIT::bltzl(const u32 instr) {
Util::panic("Implement branch likely < 0");
panic("Implement branch likely < 0");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
if (regs.IsRegConstant(RS(instr))) {
@@ -306,7 +306,7 @@ void JIT::bltzl(const u32 instr) {
}
void JIT::bgezl(const u32 instr) {
Util::panic("Implement branch likely >= 0");
panic("Implement branch likely >= 0");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
if (regs.IsRegConstant(RS(instr))) {
@@ -348,7 +348,7 @@ void JIT::bgezal(const u32 instr) {
}
void JIT::bltzall(const u32 instr) {
Util::panic("Implement branch likely and link < 0");
panic("Implement branch likely and link < 0");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
regs.Write<s64>(31, blockNextPC);
@@ -363,7 +363,7 @@ void JIT::bltzall(const u32 instr) {
}
void JIT::bgezall(const u32 instr) {
Util::panic("Implement branch likely and link >= 0");
panic("Implement branch likely and link >= 0");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
regs.Write<s64>(31, blockNextPC);
@@ -406,7 +406,7 @@ void JIT::beq(const u32 instr) {
}
void JIT::beql(const u32 instr) {
Util::panic("Implement branch likely ==");
panic("Implement branch likely ==");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
if (regs.IsRegConstant(RS(instr)) && regs.IsRegConstant(RT(instr))) {
@@ -463,7 +463,7 @@ void JIT::bne(const u32 instr) {
}
void JIT::bnel(const u32 instr) {
Util::panic("Implement branch likely !=");
panic("Implement branch likely !=");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
if (regs.IsRegConstant(RS(instr)) && regs.IsRegConstant(RT(instr))) {
@@ -505,7 +505,7 @@ void JIT::blez(const u32 instr) {
}
void JIT::blezl(const u32 instr) {
Util::panic("Implement branch likely <= 0");
panic("Implement branch likely <= 0");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
if (regs.IsRegConstant(RS(instr))) {
@@ -532,7 +532,7 @@ void JIT::bgtz(const u32 instr) {
}
void JIT::bgtzl(const u32 instr) {
Util::panic("Implement branch likely > 0");
panic("Implement branch likely > 0");
const s16 imm = instr;
const s64 offset = u64((s64)imm) << 2;
if (regs.IsRegConstant(RS(instr))) {
@@ -552,7 +552,7 @@ void JIT::dadd(u32 instr) {
u64 result = rt + rs;
if (check_signed_overflow(rs, rt, result)) {
// regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
Util::panic("[JIT]: Unhandled Overflow exception in DADD!");
panic("[JIT]: Unhandled Overflow exception in DADD!");
}
regs.Write(RD(instr), result);
return;
@@ -592,7 +592,7 @@ void JIT::daddi(u32 instr) {
u64 result = imm + rs;
if (check_signed_overflow(rs, imm, result)) {
// regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
Util::panic("[JIT]: Unhandled Overflow exception in DADDI!");
panic("[JIT]: Unhandled Overflow exception in DADDI!");
}
regs.Write(RT(instr), result);
return;
@@ -632,7 +632,7 @@ void JIT::ddiv(u32 instr) {
regs.SetLOConstant();
regs.SetHIConstant();
} else {
Util::panic("[JIT]: Implement non constant DDIV!");
panic("[JIT]: Implement non constant DDIV!");
}
}
@@ -653,7 +653,7 @@ void JIT::ddivu(u32 instr) {
regs.SetLOConstant();
regs.SetHIConstant();
} else {
Util::panic("[JIT]: Implement non constant DDIVU!");
panic("[JIT]: Implement non constant DDIVU!");
}
}
@@ -679,7 +679,7 @@ void JIT::div(u32 instr) {
regs.SetLOConstant();
regs.SetHIConstant();
} else {
Util::panic("[JIT]: Implement non constant DIV!");
panic("[JIT]: Implement non constant DIV!");
}
}
@@ -700,7 +700,7 @@ void JIT::divu(u32 instr) {
regs.SetLOConstant();
regs.SetHIConstant();
} else {
Util::panic("[JIT]: Implement non constant DIVU!");
panic("[JIT]: Implement non constant DIVU!");
}
}
@@ -714,7 +714,7 @@ void JIT::dmult(u32 instr) {
regs.SetHIConstant();
regs.SetLOConstant();
} else {
Util::panic("[JIT]: Implement non constant DMULT!");
panic("[JIT]: Implement non constant DMULT!");
}
}
@@ -728,7 +728,7 @@ void JIT::dmultu(u32 instr) {
regs.SetHIConstant();
regs.SetLOConstant();
} else {
Util::panic("[JIT]: Implement non constant DMULT!");
panic("[JIT]: Implement non constant DMULT!");
}
}
@@ -738,7 +738,7 @@ void JIT::dsll(u32 instr) {
auto result = regs.Read<s64>(RT(instr)) << sa;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSLL!");
panic("[JIT]: Implement non constant DSLL!");
}
}
@@ -748,7 +748,7 @@ void JIT::dsllv(u32 instr) {
auto result = regs.Read<s64>(RT(instr)) << sa;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSLLV!");
panic("[JIT]: Implement non constant DSLLV!");
}
}
@@ -758,7 +758,7 @@ void JIT::dsll32(u32 instr) {
auto result = regs.Read<s64>(RT(instr)) << (sa + 32);
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSLL32!");
panic("[JIT]: Implement non constant DSLL32!");
}
}
@@ -769,7 +769,7 @@ void JIT::dsra(u32 instr) {
s64 result = rt >> sa;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSRA!");
panic("[JIT]: Implement non constant DSRA!");
}
}
@@ -781,7 +781,7 @@ void JIT::dsrav(u32 instr) {
s64 result = rt >> sa;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSRAV!");
panic("[JIT]: Implement non constant DSRAV!");
}
}
@@ -792,7 +792,7 @@ void JIT::dsra32(u32 instr) {
s64 result = rt >> (sa + 32);
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSRA32!");
panic("[JIT]: Implement non constant DSRA32!");
}
}
@@ -803,7 +803,7 @@ void JIT::dsrl(u32 instr) {
u64 result = rt >> sa;
regs.Write(RD(instr), s64(result));
} else {
Util::panic("[JIT]: Implement non constant DSRL!");
panic("[JIT]: Implement non constant DSRL!");
}
}
@@ -814,7 +814,7 @@ void JIT::dsrlv(u32 instr) {
u64 result = rt >> amount;
regs.Write(RD(instr), s64(result));
} else {
Util::panic("[JIT]: Implement non constant DSRLV!");
panic("[JIT]: Implement non constant DSRLV!");
}
}
@@ -825,7 +825,7 @@ void JIT::dsrl32(u32 instr) {
u64 result = rt >> (sa + 32);
regs.Write(RD(instr), s64(result));
} else {
Util::panic("[JIT]: Implement non constant DSRL32!");
panic("[JIT]: Implement non constant DSRL32!");
}
}
@@ -836,12 +836,12 @@ void JIT::dsub(u32 instr) {
s64 result = rs - rt;
if (check_signed_underflow(rs, rt, result)) {
// regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
Util::panic("[JIT]: Unhandled Overflow exception in DSUB!");
panic("[JIT]: Unhandled Overflow exception in DSUB!");
} else {
regs.Write(RD(instr), result);
}
} else {
Util::panic("[JIT]: Implement non constant DSUB!");
panic("[JIT]: Implement non constant DSUB!");
}
}
@@ -852,7 +852,7 @@ void JIT::dsubu(u32 instr) {
s64 result = rs - rt;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant DSUBU!");
panic("[JIT]: Implement non constant DSUBU!");
}
}
@@ -890,7 +890,7 @@ void JIT::lbu(u32 instr) {
if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LBU!");
panic("[JIT]: Unhandled TLBL exception in LBU!");
} else {
code.mov(code.ARG2,
code.ptr[code.rbp + (reinterpret_cast<uintptr_t>(&regs) - reinterpret_cast<uintptr_t>(this))]);
@@ -899,7 +899,7 @@ void JIT::lbu(u32 instr) {
regs.Write<u8>(RT(instr), code.rax);
}
} else {
Util::panic("[JIT]: Implement non constant LBU!");
panic("[JIT]: Implement non constant LBU!");
}
}
@@ -909,7 +909,7 @@ void JIT::lb(u32 instr) {
if (u32 paddr = 0; !regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LB (pc: 0x{:016X})!", blockPC);
panic("[JIT]: Unhandled TLBL exception in LB (pc: 0x{:016X})!", blockPC);
} else {
code.mov(code.ARG2,
code.ptr[code.rbp + (reinterpret_cast<uintptr_t>(&regs) - reinterpret_cast<uintptr_t>(this))]);
@@ -918,7 +918,7 @@ void JIT::lb(u32 instr) {
regs.Write<s8>(RT(instr), code.rax);
}
} else {
Util::panic("[JIT]: Implement non constant LB!");
panic("[JIT]: Implement non constant LB!");
}
}
@@ -929,14 +929,14 @@ void JIT::ld(u32 instr) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
// return;
Util::panic("[JIT]: Unhandled ADEL exception in LD!");
panic("[JIT]: Unhandled ADEL exception in LD!");
}
u32 paddr = 0;
if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LD!");
panic("[JIT]: Unhandled TLBL exception in LD!");
} else {
code.mov(code.ARG2,
code.ptr[code.rbp + (reinterpret_cast<uintptr_t>(&regs) - reinterpret_cast<uintptr_t>(this))]);
@@ -945,7 +945,7 @@ void JIT::ld(u32 instr) {
regs.Write<u64>(RT(instr), code.rax);
}
} else {
Util::panic("[JIT]: Implement non constant LD!");
panic("[JIT]: Implement non constant LD!");
}
}
@@ -956,14 +956,14 @@ void JIT::ldc1(u32 instr) {
if (u32 physical; !regs.cop0.MapVAddr(Cop0::LOAD, addr, physical)) {
// regs.cop0.HandleTLBException(addr);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LD1!");
panic("[JIT]: Unhandled TLBL exception in LD1!");
} else {
const u64 data = mem.Read<u64>(regs, physical);
regs.cop1.FGR_T<u64>(regs.cop0.status, FT(instr)) = data;
regs.cop1.fgrIsConstant[FT(instr)] = true;
}
} else {
Util::panic("[JIT]: Implement non constant LD1!");
panic("[JIT]: Implement non constant LD1!");
}
}
@@ -974,9 +974,9 @@ void JIT::ldl(u32 instr) {
if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LDL!");
panic("[JIT]: Unhandled TLBL exception in LDL!");
} else {
Util::panic("[JIT]: Implement constant LDL!");
panic("[JIT]: Implement constant LDL!");
const s32 shift = 8 * ((address ^ 0) & 7);
const u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
const u64 data = mem.Read<u64>(regs, paddr & ~7);
@@ -984,7 +984,7 @@ void JIT::ldl(u32 instr) {
regs.Write(RT(instr), result);
}
} else {
Util::panic("[JIT]: Implement non constant LDL!");
panic("[JIT]: Implement non constant LDL!");
}
}
@@ -995,7 +995,7 @@ void JIT::ldr(u32 instr) {
if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LDR!");
panic("[JIT]: Unhandled TLBL exception in LDR!");
} else {
const s32 shift = 8 * ((address ^ 7) & 7);
const u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
@@ -1004,7 +1004,7 @@ void JIT::ldr(u32 instr) {
regs.Write(RT(instr), result);
}
} else {
Util::panic("[JIT]: Implement non constant LDR!");
panic("[JIT]: Implement non constant LDR!");
}
}
@@ -1015,7 +1015,7 @@ void JIT::lh(u32 instr) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
// return;
Util::panic("[JIT]: Unhandled ADEL exception in LH!");
panic("[JIT]: Unhandled ADEL exception in LH!");
return;
}
@@ -1023,7 +1023,7 @@ void JIT::lh(u32 instr) {
if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LH!");
panic("[JIT]: Unhandled TLBL exception in LH!");
return;
}
@@ -1034,7 +1034,7 @@ void JIT::lh(u32 instr) {
return;
}
Util::panic("[JIT]: Implement non constant LH!");
panic("[JIT]: Implement non constant LH!");
}
void JIT::lhu(u32 instr) {
@@ -1071,9 +1071,9 @@ void JIT::lhu(u32 instr) {
regs.Write<u16>(RT(instr), code.rax);
}
void JIT::ll(u32) { Util::panic("[JIT]: Implement constant LL!"); }
void JIT::ll(u32) { panic("[JIT]: Implement constant LL!"); }
void JIT::lld(u32) { Util::panic("[JIT]: Implement constant LLD!"); }
void JIT::lld(u32) { panic("[JIT]: Implement constant LLD!"); }
void JIT::lw(u32 instr) {
const s16 offset = instr;
@@ -1084,14 +1084,14 @@ void JIT::lw(u32 instr) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
// return;
Util::panic("[JIT]: Unhandled ADEL exception in LW!");
panic("[JIT]: Unhandled ADEL exception in LW!");
return;
}
if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBL exception in LW!");
panic("[JIT]: Unhandled TLBL exception in LW!");
return;
}
@@ -1116,13 +1116,13 @@ void JIT::lw(u32 instr) {
regs.Write<s32>(RT(instr), code.rax);
}
void JIT::lwc1(u32) { Util::panic("[JIT]: Implement constant LWC1!"); }
void JIT::lwc1(u32) { panic("[JIT]: Implement constant LWC1!"); }
void JIT::lwl(u32) { Util::panic("[JIT]: Implement constant LWL!"); }
void JIT::lwl(u32) { panic("[JIT]: Implement constant LWL!"); }
void JIT::lwu(u32) { Util::panic("[JIT]: Implement constant LWU!"); }
void JIT::lwu(u32) { panic("[JIT]: Implement constant LWU!"); }
void JIT::lwr(u32) { Util::panic("[JIT]: Implement constant LWR!"); }
void JIT::lwr(u32) { panic("[JIT]: Implement constant LWR!"); }
void JIT::mfhi(u32 instr) {
if (regs.GetHIConstant()) {
@@ -1152,7 +1152,7 @@ void JIT::mult(u32 instr) {
regs.hi = (s64)((s32)(result >> 32));
regs.SetHIConstant();
} else {
Util::panic("[JIT]: Implement non constant MULT!");
panic("[JIT]: Implement non constant MULT!");
}
}
@@ -1166,7 +1166,7 @@ void JIT::multu(u32 instr) {
regs.hi = (s64)((s32)(result >> 32));
regs.SetHIConstant();
} else {
Util::panic("[JIT]: Implement non constant MULTU!");
panic("[JIT]: Implement non constant MULTU!");
}
}
@@ -1196,7 +1196,7 @@ void JIT::nor(u32 instr) {
if (regs.IsRegConstant(RS(instr), RT(instr))) {
regs.Write(RD(instr), ~(regs.Read<s64>(RS(instr)) | regs.Read<s64>(RT(instr))));
} else {
Util::panic("[JIT]: Implement non constant NOR!");
panic("[JIT]: Implement non constant NOR!");
}
}
@@ -1207,7 +1207,7 @@ void JIT::slti(u32 instr) {
return;
}
Util::panic("[JIT]: Implement non constant SLTI!");
panic("[JIT]: Implement non constant SLTI!");
}
void JIT::sltiu(u32 instr) {
@@ -1215,7 +1215,7 @@ void JIT::sltiu(u32 instr) {
s16 imm = instr;
regs.Write(RT(instr), regs.Read<u64>(RS(instr)) < imm);
} else {
Util::panic("[JIT]: Implement non constant SLTIU!");
panic("[JIT]: Implement non constant SLTIU!");
}
}
@@ -1254,7 +1254,7 @@ void JIT::sltu(u32 instr) {
if (regs.IsRegConstant(RS(instr), RT(instr))) {
regs.Write(RD(instr), regs.Read<u64>(RS(instr)) < regs.Read<u64>(RT(instr)));
} else {
Util::panic("[JIT]: Implement non constant SLT!");
panic("[JIT]: Implement non constant SLT!");
}
}
@@ -1277,7 +1277,7 @@ void JIT::sllv(u32 instr) {
s32 result = rt << sa;
regs.Write(RD(instr), (s64)result);
} else {
Util::panic("[JIT]: Implement non constant SLLV!");
panic("[JIT]: Implement non constant SLLV!");
}
}
@@ -1292,7 +1292,7 @@ void JIT::sub(u32 instr) {
regs.Write(RD(instr), result);
}
} else {
Util::panic("[JIT]: Implement non constant SUB!");
panic("[JIT]: Implement non constant SUB!");
}
}
@@ -1303,7 +1303,7 @@ void JIT::subu(u32 instr) {
u32 result = rs - rt;
regs.Write(RD(instr), (s64)((s32)result));
} else {
Util::panic("[JIT]: Implement non constant SUBU!");
panic("[JIT]: Implement non constant SUBU!");
}
}
@@ -1314,7 +1314,7 @@ void JIT::sra(u32 instr) {
s32 result = rt >> sa;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant SRA!");
panic("[JIT]: Implement non constant SRA!");
}
}
@@ -1326,7 +1326,7 @@ void JIT::srav(u32 instr) {
s32 result = rt >> sa;
regs.Write(RD(instr), result);
} else {
Util::panic("[JIT]: Implement non constant SRAV!");
panic("[JIT]: Implement non constant SRAV!");
}
}
@@ -1337,7 +1337,7 @@ void JIT::srl(u32 instr) {
u32 result = rt >> sa;
regs.Write(RD(instr), (s32)result);
} else {
Util::panic("[JIT]: Implement non constant SRL!");
panic("[JIT]: Implement non constant SRL!");
}
}
@@ -1349,14 +1349,14 @@ void JIT::sw(const u32 instr) {
if (check_address_error(0b11, address)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(ExceptionCode::AddressErrorStore, 0, regs.oldPC);
Util::panic("[JIT]: Unhandled ADES exception in SW!");
panic("[JIT]: Unhandled ADES exception in SW!");
return;
}
if (!regs.cop0.MapVAddr(Cop0::STORE, address, physical)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBS exception in SW!");
panic("[JIT]: Unhandled TLBS exception in SW!");
} else {
code.lea(code.ARG2,
code.ptr[code.rbp + (reinterpret_cast<uintptr_t>(&regs) - reinterpret_cast<uintptr_t>(this))]);
@@ -1374,14 +1374,14 @@ void JIT::sw(const u32 instr) {
if (check_address_error(0b11, address)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(ExceptionCode::AddressErrorStore, 0, regs.oldPC);
Util::panic("[JIT]: Unhandled ADES exception in SW!");
panic("[JIT]: Unhandled ADES exception in SW!");
return;
}
if (!regs.cop0.MapVAddr(Cop0::STORE, address, physical)) {
// regs.cop0.HandleTLBException(address);
// regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
Util::panic("[JIT]: Unhandled TLBS exception in SW!");
panic("[JIT]: Unhandled TLBS exception in SW!");
} else {
code.mov(code.ARG2,
code.ptr[code.rbp + (reinterpret_cast<uintptr_t>(&regs) - reinterpret_cast<uintptr_t>(this))]);
@@ -1433,7 +1433,7 @@ void JIT::srlv(u32 instr) {
s32 result = rt >> sa;
regs.Write(RD(instr), (s64)result);
} else {
Util::panic("[JIT]: Implement non constant SRLV!");
panic("[JIT]: Implement non constant SRLV!");
}
}
@@ -1441,7 +1441,7 @@ void JIT::or_(u32 instr) {
if (regs.IsRegConstant(RS(instr), RT(instr))) {
regs.Write(RD(instr), regs.Read<s64>(RS(instr)) | regs.Read<s64>(RT(instr)));
} else {
Util::panic("[JIT]: Implement non constant OR!");
panic("[JIT]: Implement non constant OR!");
}
}
@@ -1463,7 +1463,7 @@ void JIT::xori(u32 instr) {
s64 imm = (u16)instr;
regs.Write(RT(instr), regs.Read<s64>(RS(instr)) ^ imm);
} else {
Util::panic("[JIT]: Implement non constant XORI!");
panic("[JIT]: Implement non constant XORI!");
}
}
@@ -1471,7 +1471,7 @@ void JIT::xor_(u32 instr) {
if (regs.IsRegConstant(RS(instr), RT(instr))) {
regs.Write(RD(instr), regs.Read<s64>(RT(instr)) ^ regs.Read<s64>(RS(instr)));
} else {
Util::panic("[JIT]: Implement non constant XOR!");
panic("[JIT]: Implement non constant XOR!");
}
}
} // namespace n64

40
src/backend/core/mem/Flash.cpp
View File

@@ -26,7 +26,7 @@ void Flash::Load(SaveType saveType, const std::string &path) {
if (saveData.is_mapped()) {
saveData.sync(error);
if (error) {
Util::panic("Could not sync {}", flashPath);
panic("Could not sync {}", flashPath);
}
saveData.unmap();
}
@@ -40,18 +40,18 @@ void Flash::Load(SaveType saveType, const std::string &path) {
}
if (flashVec.size() != FLASH_SIZE) {
Util::panic("Corrupt SRAM!");
panic("Corrupt SRAM!");
}
saveData = mio::make_mmap_sink(flashPath, 0, mio::map_entire_file, error);
if (error) {
Util::panic("Could not make mmap {}", flashPath);
panic("Could not make mmap {}", flashPath);
}
}
}
void Flash::CommandExecute() const {
Util::trace("Flash::CommandExecute");
trace("Flash::CommandExecute");
switch (state) {
case FlashState::Idle:
break;
@@ -61,7 +61,7 @@ void Flash::CommandExecute() const {
saveData[eraseOffs + i] = 0xFF;
}
} else {
Util::panic("Accessing flash when not mapped!");
panic("Accessing flash when not mapped!");
}
break;
case FlashState::Write:
@@ -70,11 +70,11 @@ void Flash::CommandExecute() const {
saveData[writeOffs + i] = writeBuf[i];
}
} else {
Util::panic("Accessing flash when not mapped!");
panic("Accessing flash when not mapped!");
}
break;
case FlashState::Read:
Util::panic("Execute command when flash in read state");
panic("Execute command when flash in read state");
break;
case FlashState::Status:
break;
@@ -164,10 +164,10 @@ void Flash::Write<u32>(u32 index, u32 val) {
CommandRead();
break;
default:
Util::warn("Invalid flash command: {:02X}", cmd);
warn("Invalid flash command: {:02X}", cmd);
}
} else {
Util::warn("Flash Write of {:08X} @ {:08X}", val, index);
warn("Flash Write of {:08X} @ {:08X}", val, index);
}
}
@@ -175,19 +175,19 @@ template <>
void Flash::Write<u8>(u32 index, u8 val) {
switch (state) {
case FlashState::Idle:
Util::panic("Invalid FlashState::Idle with Write<u8>");
panic("Invalid FlashState::Idle with Write<u8>");
case FlashState::Status:
Util::panic("Invalid FlashState::Status with Write<u8>");
panic("Invalid FlashState::Status with Write<u8>");
case FlashState::Erase:
Util::panic("Invalid FlashState::Erase with Write<u8>");
panic("Invalid FlashState::Erase with Write<u8>");
case FlashState::Read:
Util::panic("Invalid FlashState::Read with Write<u8>");
panic("Invalid FlashState::Read with Write<u8>");
case FlashState::Write:
assert(index <= 0x7F && "Out of range flash Write8");
writeBuf[index] = val;
break;
default:
Util::warn("Invalid flash state on Write<u8>: {:02X}", static_cast<u8>(state));
warn("Invalid flash state on Write<u8>: {:02X}", static_cast<u8>(state));
}
}
@@ -195,27 +195,27 @@ template <>
u8 Flash::Read<u8>(const u32 index) const {
switch (state) {
case FlashState::Idle:
Util::panic("Flash read byte while in state FLASH_STATE_IDLE");
panic("Flash read byte while in state FLASH_STATE_IDLE");
case FlashState::Write:
Util::panic("Flash read byte while in state FLASH_STATE_WRITE");
panic("Flash read byte while in state FLASH_STATE_WRITE");
case FlashState::Read:
if (saveData.is_mapped()) {
const u8 value = saveData[index];
Util::trace("Flash read byte in state read: index {:08X} = {:02X}", index, value);
trace("Flash read byte in state read: index {:08X} = {:02X}", index, value);
return value;
}
Util::panic("Accessing flash when not mapped!");
panic("Accessing flash when not mapped!");
case FlashState::Status:
{
const u32 offset = (7 - (index % 8)) * 8;
const u8 value = (status >> offset) & 0xFF;
Util::trace("Flash read byte in state status: index {:08X} = {:02X}", index, value);
trace("Flash read byte in state status: index {:08X} = {:02X}", index, value);
return value;
}
default:
Util::panic("Flash read byte while in unknown state");
panic("Flash read byte while in unknown state");
return 0;
}
}

2
src/backend/core/mmio/AI.cpp
View File

@@ -76,7 +76,7 @@ void AI::Write(const u32 addr, const u32 val) {
dac.precision = bitrate + 1;
break;
default:
Util::panic("Unhandled AI write at addr {:08X} with val {:08X}", addr, val);
panic("Unhandled AI write at addr {:08X} with val {:08X}", addr, val);
}
}

6
src/backend/core/mmio/Audio.cpp
View File

@@ -11,7 +11,7 @@ namespace n64 {
AudioDevice::AudioDevice() {
audioStreamMutex = SDL_CreateMutex();
if (!audioStreamMutex) {
Util::panic("Unable to initialize audio mutex: {}", SDL_GetError());
panic("Unable to initialize audio mutex: {}", SDL_GetError());
}
SDL_InitSubSystem(SDL_INIT_AUDIO);
@@ -19,7 +19,7 @@ AudioDevice::AudioDevice() {
audioStream = SDL_OpenAudioDeviceStream(SDL_AUDIO_DEVICE_DEFAULT_PLAYBACK, &request, nullptr, nullptr);
if (!audioStream) {
Util::panic("Unable to create audio stream: {}", SDL_GetError());
panic("Unable to create audio stream: {}", SDL_GetError());
}
}
@@ -50,7 +50,7 @@ void AudioDevice::AdjustSampleRate(int sampleRate) {
audioStream = SDL_OpenAudioDeviceStream(SDL_AUDIO_DEVICE_DEFAULT_PLAYBACK, &request, nullptr, nullptr);
if (!audioStream) {
Util::panic("Unable to create audio stream: {}", SDL_GetError());
panic("Unable to create audio stream: {}", SDL_GetError());
}
UnlockMutex();
}

4
src/backend/core/mmio/MI.cpp
View File

@@ -24,7 +24,7 @@ auto MI::Read(u32 paddr) const -> u32 {
case 0xC:
return miIntrMask.raw & 0x3F;
default:
Util::panic("Unhandled MI[{:08X}] read", paddr);
panic("Unhandled MI[{:08X}] read", paddr);
}
}
@@ -81,7 +81,7 @@ void MI::Write(u32 paddr, u32 val) {
UpdateInterrupt();
break;
default:
Util::panic_trace("Unhandled MI write @ 0x{:08X} with value 0x{:08X}", paddr, val);
panic("Unhandled MI write @ 0x{:08X} with value 0x{:08X}", paddr, val);
}
}
} // namespace n64

118
src/backend/core/mmio/PI.cpp
View File

@@ -48,15 +48,15 @@ template <>
auto PI::BusRead<u8, true>(u32 addr) -> u8 {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_64DD_REG:
Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_64DD_ROM:
Util::warn("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
warn("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
"returning FF because it is not emulated",
addr);
return 0xFF;
@@ -67,14 +67,14 @@ auto PI::BusRead<u8, true>(u32 addr) -> u8 {
// round to nearest 4 byte boundary, keeping old LSB
const u32 index = BYTE_ADDRESS(addr) - SREGION_PI_ROM;
if (index >= mem.rom.cart.size()) {
Util::warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM! ({}/0x{:016X})", addr,
warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM! ({}/0x{:016X})", addr,
index, index, mem.rom.cart.size(), mem.rom.cart.size());
return 0xFF;
}
return mem.rom.cart[index];
}
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -86,15 +86,15 @@ auto PI::BusRead<u8, false>(u32 addr) -> u8 {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_64DD_REG:
Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_64DD_ROM:
Util::warn("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
warn("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
"returning FF because it is not emulated",
addr);
return 0xFF;
@@ -106,14 +106,14 @@ auto PI::BusRead<u8, false>(u32 addr) -> u8 {
// round to nearest 4 byte boundary, keeping old LSB
const u32 index = BYTE_ADDRESS(addr) - SREGION_PI_ROM;
if (index >= mem.rom.cart.size()) {
Util::warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM! ({}/0x{:016X})", addr,
warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM! ({}/0x{:016X})", addr,
index, index, mem.rom.cart.size(), mem.rom.cart.size());
return 0xFF;
}
return mem.rom.cart[index];
}
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -121,25 +121,25 @@ template <>
void PI::BusWrite<u8, true>(u32 addr, u32 val) {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
panic("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
case REGION_PI_64DD_REG:
if (addr == 0x05000020) {
fprintf(stderr, "%c", val);
} else {
Util::warn("Writing byte 0x{:02X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!",
warn("Writing byte 0x{:02X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!",
val, addr);
}
break;
case REGION_PI_64DD_ROM:
Util::panic("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
panic("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
case REGION_PI_SRAM:
mem.BackupWrite<u8>(addr - SREGION_PI_SRAM, val);
break;
case REGION_PI_ROM:
Util::warn("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
warn("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
break;
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -162,30 +162,30 @@ auto PI::BusRead<u16, false>(u32 addr) -> u16 {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_64DD_REG:
Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_64DD_ROM:
Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
"returning FF because it is not emulated",
addr);
case REGION_PI_SRAM:
Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_SRAM", addr);
panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_SRAM", addr);
case REGION_PI_ROM:
{
addr = (addr + 2) & ~3;
const u32 index = HALF_ADDRESS(addr) - SREGION_PI_ROM;
if (index > mem.rom.cart.size() - 1) {
Util::panic("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
panic("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
}
return Util::ReadAccess<u16>(mem.rom.cart, index);
}
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -202,19 +202,19 @@ void PI::BusWrite<u16, false>(u32 addr, u32 val) {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
case REGION_PI_64DD_REG:
Util::panic("Writing half 0x{:04X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!",
panic("Writing half 0x{:04X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!",
val, addr);
case REGION_PI_64DD_ROM:
Util::panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
case REGION_PI_SRAM:
Util::panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_SRAM", val, addr);
panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_SRAM", val, addr);
case REGION_PI_ROM:
Util::warn("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
warn("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
break;
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -231,17 +231,17 @@ auto PI::BusRead<u32, false>(u32 addr) -> u32 {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, "
"returning FF because it is not emulated",
addr);
return 0xFF;
case REGION_PI_64DD_REG:
Util::warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, "
"returning FF because it is not emulated",
addr);
return 0xFF;
case REGION_PI_64DD_ROM:
Util::warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, "
"returning FF because it is not emulated",
addr);
return 0xFF;
@@ -255,18 +255,18 @@ auto PI::BusRead<u32, false>(u32 addr) -> u32 {
case REGION_CART_ISVIEWER_BUFFER:
return bswap(Util::ReadAccess<u32>(mem.isviewer, addr - SREGION_CART_ISVIEWER_BUFFER));
case CART_ISVIEWER_FLUSH:
Util::panic("Read from ISViewer flush!");
panic("Read from ISViewer flush!");
default:
break;
}
Util::warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
return 0;
}
return Util::ReadAccess<u32>(mem.rom.cart, index);
}
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -282,20 +282,20 @@ void PI::BusWrite<u32, false>(u32 addr, u32 val) {
if (!WriteLatch(val)) [[unlikely]] {
return;
}
Util::warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
return;
case REGION_PI_64DD_REG:
if (!WriteLatch(val)) [[unlikely]] {
return;
}
Util::warn("Writing word 0x{:08X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!",
warn("Writing word 0x{:08X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!",
val, addr);
return;
case REGION_PI_64DD_ROM:
if (!WriteLatch(val)) [[unlikely]] {
return;
}
Util::warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
return;
case REGION_PI_SRAM:
if (!WriteLatch(val)) [[unlikely]] {
@@ -313,23 +313,23 @@ void PI::BusWrite<u32, false>(u32 addr, u32 val) {
if (val < CART_ISVIEWER_SIZE) {
std::string message(val + 1, 0);
std::copy_n(mem.isviewer.begin(), val, message.begin());
Util::print<Util::Always>("{}", message);
always("{}", message);
} else {
Util::panic("ISViewer buffer size is emulated at {} bytes, but received a flush command for {} bytes!",
panic("ISViewer buffer size is emulated at {} bytes, but received a flush command for {} bytes!",
CART_ISVIEWER_SIZE, val);
}
break;
}
default:
if (!WriteLatch(val)) [[unlikely]] {
Util::warn("Couldn't latch PI bus, ignoring write to REGION_PI_ROM");
warn("Couldn't latch PI bus, ignoring write to REGION_PI_ROM");
return;
}
Util::warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
}
return;
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -346,23 +346,23 @@ auto PI::BusRead<u64, false>(u32 addr) -> u64 {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", addr);
panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", addr);
case REGION_PI_64DD_REG:
Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG", addr);
panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG", addr);
case REGION_PI_64DD_ROM:
Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", addr);
panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", addr);
case REGION_PI_SRAM:
Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_SRAM", addr);
panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_SRAM", addr);
case REGION_PI_ROM:
{
const u32 index = addr - SREGION_PI_ROM;
if (index > mem.rom.cart.size() - 7) { // -7 because we're reading an entire dword
Util::panic("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
panic("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
}
return Util::ReadAccess<u64>(mem.rom.cart, index);
}
default:
Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
}
}
@@ -379,18 +379,18 @@ void PI::BusWrite<false>(u32 addr, u64 val) {
switch (addr) {
case REGION_PI_UNKNOWN:
Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
case REGION_PI_64DD_REG:
Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_REG", val, addr);
panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_REG", val, addr);
case REGION_PI_64DD_ROM:
Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
case REGION_PI_SRAM:
Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_SRAM", val, addr);
panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_SRAM", val, addr);
case REGION_PI_ROM:
Util::warn("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
warn("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
break;
default:
Util::panic("Should never end up here! Access to address %08X which did not match any PI bus regions!", addr);
panic("Should never end up here! Access to address %08X which did not match any PI bus regions!", addr);
}
}
@@ -435,7 +435,7 @@ auto PI::Read(u32 addr) const -> u32 {
case 0x04600030:
return piBsdDom2Rls;
default:
Util::panic("Unhandled PI[{:08X}] read", addr);
panic("Unhandled PI[{:08X}] read", addr);
}
}
@@ -449,7 +449,7 @@ u8 PI::GetDomain(const u32 address) {
case REGION_PI_SRAM:
return 2;
default:
Util::panic("Unknown PI domain for address {:08X}!", address);
panic("Unknown PI domain for address {:08X}!", address);
}
}
@@ -474,7 +474,7 @@ u32 PI::AccessTiming(const u8 domain, const u32 length) const {
page_size = std::pow(2, (piBsdDom2Pgs + 2));
break;
default:
Util::panic("Unknown PI domain: {}\n", domain);
panic("Unknown PI domain: {}\n", domain);
}
const uint32_t pages = ceil((double)length / page_size);
@@ -489,7 +489,7 @@ u32 PI::AccessTiming(const u8 domain, const u32 length) const {
template <>
void PI::DMA<false>() {
const s32 len = rdLen + 1;
Util::trace("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
trace("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
if (mem.saveType == SAVE_FLASH_1m && cartAddr >= SREGION_PI_SRAM && cartAddr < 0x08010000) {
cartAddr = SREGION_PI_SRAM | ((cartAddr & 0xFFFFF) << 1);
@@ -512,7 +512,7 @@ void PI::DMA<false>() {
template <>
void PI::DMA<true>() {
const s32 len = wrLen + 1;
Util::trace("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cartAddr, dramAddr);
trace("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cartAddr, dramAddr);
if (mem.saveType == SAVE_FLASH_1m && cartAddr >= SREGION_PI_SRAM && cartAddr < 0x08010000) {
cartAddr = SREGION_PI_SRAM | ((cartAddr & 0xFFFFF) << 1);
@@ -582,7 +582,7 @@ void PI::Write(u32 addr, u32 val) {
piBsdDom2Rls = val & 0xff;
break;
default:
Util::panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
}
}
} // namespace n64

34
src/backend/core/mmio/PIF.cpp
View File

@@ -18,14 +18,14 @@ void PIF::Reset() {
if (mempak.is_mapped()) {
mempak.sync(error);
if (error) {
Util::panic("Could not sync {}", mempakPath);
panic("Could not sync {}", mempakPath);
}
mempak.unmap();
}
if (eeprom.is_mapped()) {
eeprom.sync(error);
if (error) {
Util::panic("Could not sync {}", eepromPath);
panic("Could not sync {}", eepromPath);
}
eeprom.unmap();
}
@@ -45,7 +45,7 @@ void PIF::MaybeLoadMempak() {
if (mempak.is_mapped()) {
mempak.sync(error);
if (error) {
Util::panic("Could not sync {}", mempakPath);
panic("Could not sync {}", mempakPath);
}
mempak.unmap();
}
@@ -57,12 +57,12 @@ void PIF::MaybeLoadMempak() {
}
if (mempakVec.size() != MEMPAK_SIZE) {
Util::panic("Corrupt mempak!");
panic("Corrupt mempak!");
}
mempak = mio::make_mmap_sink(mempakPath, 0, mio::map_entire_file, error);
if (error) {
Util::panic("Could not open {}", mempakPath);
panic("Could not open {}", mempakPath);
}
mempakOpen = true;
}
@@ -81,7 +81,7 @@ FORCE_INLINE size_t GetSaveSize(SaveType saveType) {
case SAVE_FLASH_1m:
return 131072;
default:
Util::panic("Unknown save type!");
panic("Unknown save type!");
}
}
@@ -96,7 +96,7 @@ void PIF::LoadEeprom(const SaveType saveType, const std::string &path) {
if (eeprom.is_mapped()) {
eeprom.sync(error);
if (error) {
Util::panic("Could not sync {}", eepromPath);
panic("Could not sync {}", eepromPath);
}
eeprom.unmap();
}
@@ -112,12 +112,12 @@ void PIF::LoadEeprom(const SaveType saveType, const std::string &path) {
}
if (eepromVec.size() != eepromSize) {
Util::panic("Corrupt eeprom!");
panic("Corrupt eeprom!");
}
eeprom = mio::make_mmap_sink(eepromPath, 0, mio::map_entire_file, error);
if (error) {
Util::panic("Could not open {}", eepromPath);
panic("Could not open {}", eepromPath);
}
}
}
@@ -235,13 +235,13 @@ void PIF::ProcessCommands(const Mem &mem) {
}
break;
default:
Util::panic("Invalid read RTC block {}", cmd[CMD_START]);
panic("Invalid read RTC block {}", cmd[CMD_START]);
}
break;
case 8:
break;
default:
Util::panic("Invalid PIF command: {:X}", cmd[2]);
panic("Invalid PIF command: {:X}", cmd[2]);
}
i += cmdlen + reslen;
@@ -321,12 +321,12 @@ void PIF::EepromRead(const u8 *cmd, u8 *res, const Mem &mem) const {
if (channel == 4) {
const u8 offset = cmd[3];
if ((offset * 8) >= GetSaveSize(mem.saveType)) {
Util::panic("Out of range EEPROM read! offset: {:02X}", offset);
panic("Out of range EEPROM read! offset: {:02X}", offset);
}
std::copy_n(eeprom.begin() + offset * 8, 8, res);
} else {
Util::panic("EEPROM read on bad channel {}", channel);
panic("EEPROM read on bad channel {}", channel);
}
}
@@ -335,14 +335,14 @@ void PIF::EepromWrite(const u8 *cmd, u8 *res, const Mem &mem) {
if (channel == 4) {
const u8 offset = cmd[3];
if ((offset * 8) >= GetSaveSize(mem.saveType)) {
Util::panic("Out of range EEPROM write! offset: {:02X}", offset);
panic("Out of range EEPROM write! offset: {:02X}", offset);
}
std::copy_n(cmd + 4, 8, eeprom.begin() + offset * 8);
res[0] = 0; // Error byte, I guess it always succeeds?
} else {
Util::panic("EEPROM write on bad channel {}", channel);
panic("EEPROM write on bad channel {}", channel);
}
}
@@ -351,7 +351,7 @@ void PIF::HLE(const bool pal, const CICType cicType) const {
switch (cicType) {
case UNKNOWN_CIC_TYPE:
Util::warn("Unknown CIC type!");
warn("Unknown CIC type!");
break;
case CIC_NUS_6101:
regs.Write<u64>(0, 0x0000000000000000);
@@ -617,7 +617,7 @@ void PIF::Execute() const {
mem.Write<u32>(regs, PIF_RAM_REGION_START + 0x24, cicSeeds[cicType]);
switch (cicType) {
case UNKNOWN_CIC_TYPE:
Util::warn("Unknown CIC type!");
warn("Unknown CIC type!");
break;
case CIC_NUS_6101 ... CIC_NUS_6103_7103:
mem.Write<u32>(regs, 0x318, RDRAM_SIZE);

2
src/backend/core/mmio/PIF/Device.cpp
View File

@@ -72,7 +72,7 @@ void PIF::ControllerID(u8 *res) const {
break;
}
} else {
Util::panic("Device ID on unknown channel {}", channel);
panic("Device ID on unknown channel {}", channel);
}
}

50
src/backend/core/mmio/PIF/MupenMovie.cpp
View File

@@ -32,7 +32,7 @@ bool MupenMovie::Load(const fs::path &path) {
filename = path.stem().string();
loadedTasMovie = Util::ReadFileBinary(path.string());
if (!IsLoaded()) {
Util::error("Error loading movie!");
error("Error loading movie!");
return false;
}
@@ -40,27 +40,27 @@ bool MupenMovie::Load(const fs::path &path) {
if (loadedTasMovieHeader.signature[0] != 0x4D || loadedTasMovieHeader.signature[1] != 0x36 ||
loadedTasMovieHeader.signature[2] != 0x34 || loadedTasMovieHeader.signature[3] != 0x1A) {
Util::error("Failed to load movie: incorrect signature. Are you sure this is a valid movie?");
error("Failed to load movie: incorrect signature. Are you sure this is a valid movie?");
return false;
}
if (loadedTasMovieHeader.version != 3) {
Util::error("This movie is version {}: only version 3 is supported.", loadedTasMovieHeader.version);
error("This movie is version {}: only version 3 is supported.", loadedTasMovieHeader.version);
return false;
}
if (loadedTasMovieHeader.startType != 2) {
Util::error("Movie start type is {} - only movies with a start type of 2 are supported (start at power on)",
error("Movie start type is {} - only movies with a start type of 2 are supported (start at power on)",
loadedTasMovieHeader.startType);
return false;
}
Util::info("Loaded movie '{}' ", loadedTasMovieHeader.movie_description);
Util::info("by {}", loadedTasMovieHeader.author_name);
Util::info("{} controller(s) connected", loadedTasMovieHeader.numControllers);
info("Loaded movie '{}' ", loadedTasMovieHeader.movie_description);
info("by {}", loadedTasMovieHeader.author_name);
info("{} controller(s) connected", loadedTasMovieHeader.numControllers);
if (loadedTasMovieHeader.numControllers != 1) {
Util::error("Currently, only movies with 1 controller connected are supported.");
error("Currently, only movies with 1 controller connected are supported.");
return false;
}
@@ -70,7 +70,7 @@ bool MupenMovie::Load(const fs::path &path) {
MupenMovie::MupenMovie(const fs::path &path) {
if (!Load(path)) {
Util::panic("");
panic("");
}
}
@@ -82,22 +82,22 @@ void MupenMovie::Reset() {
}
FORCE_INLINE void LogController(const n64::Controller &controller) {
Util::debug("c_right: {}", controller.cRight);
Util::debug("c_left: {}", controller.cLeft);
Util::debug("c_down: {}", controller.cDown);
Util::debug("c_up: {}", controller.cUp);
Util::debug("r: {}", controller.r);
Util::debug("l: {}", controller.l);
Util::debug("dp_right: {}", controller.dpRight);
Util::debug("dp_left: {}", controller.dpLeft);
Util::debug("dp_down: {}", controller.dpDown);
Util::debug("dp_up: {}", controller.dpUp);
Util::debug("z: {}", controller.z);
Util::debug("b: {}", controller.b);
Util::debug("a: {}", controller.a);
Util::debug("start: {}", controller.start);
Util::debug("joy_x: {}", controller.joyX);
Util::debug("joy_y: {}", controller.joyY);
debug("c_right: {}", controller.cRight);
debug("c_left: {}", controller.cLeft);
debug("c_down: {}", controller.cDown);
debug("c_up: {}", controller.cUp);
debug("r: {}", controller.r);
debug("l: {}", controller.l);
debug("dp_right: {}", controller.dpRight);
debug("dp_left: {}", controller.dpLeft);
debug("dp_down: {}", controller.dpDown);
debug("dp_up: {}", controller.dpUp);
debug("z: {}", controller.z);
debug("b: {}", controller.b);
debug("a: {}", controller.a);
debug("start: {}", controller.start);
debug("joy_x: {}", controller.joyX);
debug("joy_y: {}", controller.joyY);
}
n64::Controller MupenMovie::NextInputs() {

4
src/backend/core/mmio/RI.cpp
View File

@@ -22,7 +22,7 @@ auto RI::Read(u32 addr) const -> u32 {
case 0x04700010:
return refresh;
default:
Util::panic("Unhandled RI[{:08X}] read", addr);
panic("Unhandled RI[{:08X}] read", addr);
}
}
@@ -41,7 +41,7 @@ void RI::Write(u32 addr, u32 val) {
refresh = val;
break;
default:
Util::panic("Unhandled RI[{:08X}] write with val {:08X}", addr, val);
panic("Unhandled RI[{:08X}] write with val {:08X}", addr, val);
}
}
} // namespace n64

8
src/backend/core/mmio/SI.cpp
View File

@@ -32,7 +32,7 @@ auto SI::Read(u32 addr) const -> u32 {
return val;
}
default:
Util::panic("Unhandled SI[{:08X}] read", addr);
panic("Unhandled SI[{:08X}] read", addr);
}
}
@@ -43,7 +43,7 @@ void SI::DMA<true>() {
for (int i = 0; i < 64; i++) {
mem.mmio.rdp.WriteRDRAM<u8>(dramAddr + i, pif.Read(pifAddr + i));
}
Util::trace("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})", pifAddr, dramAddr);
trace("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})", pifAddr, dramAddr);
}
// rdram -> pif
@@ -52,7 +52,7 @@ void SI::DMA<false>() {
for (int i = 0; i < 64; i++) {
pif.Write(pifAddr + i, mem.mmio.rdp.ReadRDRAM<u8>(dramAddr + i));
}
Util::trace("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})", dramAddr, pifAddr);
trace("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})", dramAddr, pifAddr);
}
void SI::DMA() {
@@ -85,7 +85,7 @@ void SI::Write(u32 addr, u32 val) {
mem.mmio.mi.InterruptLower(MI::Interrupt::SI);
break;
default:
Util::panic("Unhandled SI[{:08X}] write ({:08X})", addr, val);
panic("Unhandled SI[{:08X}] write ({:08X})", addr, val);
}
}
} // namespace n64

4
src/backend/core/mmio/VI.cpp
View File

@@ -55,7 +55,7 @@ u32 VI::Read(const u32 paddr) const {
case 0x04400034:
return yscale.raw;
default:
Util::panic("Unimplemented VI[%08X] read", paddr);
panic("Unimplemented VI[%08X] read", paddr);
}
}
@@ -113,7 +113,7 @@ void VI::Write(const u32 paddr, const u32 val) {
yscale.raw = val;
break;
default:
Util::panic("Unimplemented VI[%08X] write (%08X)", paddr, val);
panic("Unimplemented VI[%08X] write (%08X)", paddr, val);
}
}
} // namespace n64

44
src/backend/core/registers/Cop0.cpp
View File

@@ -104,7 +104,7 @@ u32 Cop0::GetReg32(const u8 addr) {
case 31:
return openbus;
default:
Util::panic("Unsupported word read from COP0 register {}", addr);
panic("Unsupported word read from COP0 register {}", addr);
}
}
@@ -141,7 +141,7 @@ u64 Cop0::GetReg64(const u8 addr) const {
case 31:
return openbus;
default:
Util::panic("Unsupported dword read from COP0 register {}", addr);
panic("Unsupported dword read from COP0 register {}", addr);
}
}
@@ -237,7 +237,7 @@ void Cop0::SetReg32(const u8 addr, const u32 value) {
case 31:
break;
default:
Util::panic("Unsupported word write from COP0 register {}", addr);
panic("Unsupported word write from COP0 register {}", addr);
}
}
@@ -282,7 +282,7 @@ void Cop0::SetReg64(const u8 addr, const u64 value) {
ErrorEPC = (s64)value;
break;
default:
Util::panic("Unsupported dword write to COP0 register {}", addr);
panic("Unsupported dword write to COP0 register {}", addr);
}
}
@@ -386,7 +386,7 @@ void Cop0::FireException(const ExceptionCode code, const int cop, s64 pc) const
regs.cop0.cause.exceptionCode = static_cast<u8>(code);
if (regs.cop0.status.bev) {
Util::panic("BEV bit set!");
panic("BEV bit set!");
} else {
switch (code) {
case ExceptionCode::Interrupt:
@@ -416,7 +416,7 @@ void Cop0::FireException(const ExceptionCode code, const int cop, s64 pc) const
}
break;
default:
Util::panic("Unhandled exception! {}", static_cast<u8>(code));
panic("Unhandled exception! {}", static_cast<u8>(code));
}
}
@@ -437,7 +437,7 @@ void Cop0::HandleTLBException(const u64 vaddr) const {
ExceptionCode Cop0::GetTLBExceptionCode(const TLBError error, const TLBAccessType accessType) {
switch (error) {
case NONE:
Util::panic("Getting TLB exception with error NONE");
panic("Getting TLB exception with error NONE");
case INVALID:
case MISS:
return accessType == LOAD ? ExceptionCode::TLBLoad : ExceptionCode::TLBStore;
@@ -446,7 +446,7 @@ ExceptionCode Cop0::GetTLBExceptionCode(const TLBError error, const TLBAccessTyp
case DISALLOWED_ADDRESS:
return accessType == LOAD ? ExceptionCode::AddressErrorLoad : ExceptionCode::AddressErrorStore;
default:
Util::panic("Getting TLB exception for unknown error code! ({})", static_cast<u8>(error));
panic("Getting TLB exception for unknown error code! ({})", static_cast<u8>(error));
return {};
}
}
@@ -485,12 +485,12 @@ void Cop0::decode(const u32 instr) {
eret();
break;
default:
Util::panic("Unimplemented COP0 function {} {} ({:08X}) ({:016X})", mask_cop2 >> 3, mask_cop2 & 7, instr,
panic("Unimplemented COP0 function {} {} ({:08X}) ({:016X})", mask_cop2 >> 3, mask_cop2 & 7, instr,
regs.oldPC);
}
break;
default:
Util::panic("Unimplemented COP0 instruction {} {}", mask_cop >> 4, mask_cop & 7);
panic("Unimplemented COP0 instruction {} {}", mask_cop >> 4, mask_cop & 7);
}
}
@@ -505,9 +505,9 @@ bool Cop0::MapVAddr(const TLBAccessType accessType, const u64 vaddr, u32 &paddr)
}
if (regs.cop0.supervisorMode) {
Util::panic("Supervisor mode memory access, 64 bit mode");
panic("Supervisor mode memory access, 64 bit mode");
} else {
Util::panic("Unknown mode! This should never happen!");
panic("Unknown mode! This should never happen!");
}
} else {
if (regs.cop0.kernelMode) [[likely]] {
@@ -519,9 +519,9 @@ bool Cop0::MapVAddr(const TLBAccessType accessType, const u64 vaddr, u32 &paddr)
}
if (regs.cop0.supervisorMode) {
Util::panic("Supervisor mode memory access, 32 bit mode");
panic("Supervisor mode memory access, 32 bit mode");
} else {
Util::panic("Unknown mode! This should never happen!");
panic("Unknown mode! This should never happen!");
}
}
}
@@ -545,9 +545,9 @@ bool Cop0::MapVAddr32(const TLBAccessType accessType, const u64 vaddr, u32 &padd
paddr = vaddr & 0x1FFFFFFF;
return true;
case 6:
Util::panic("Unimplemented virtual mapping in KSSEG! ({:08X})", vaddr);
panic("Unimplemented virtual mapping in KSSEG! ({:08X})", vaddr);
default:
Util::panic("Should never end up in default case in map_vaddr! ({:08X})", vaddr);
panic("Should never end up in default case in map_vaddr! ({:08X})", vaddr);
}
return false;
@@ -571,10 +571,10 @@ bool Cop0::MapVAddr64(const TLBAccessType accessType, const u64 vaddr, u32 &padd
case VREGION_XKPHYS:
{
if (!regs.cop0.kernelMode) {
Util::panic("Access to XKPHYS address 0x{:016X} when outside kernel mode!", vaddr);
panic("Access to XKPHYS address 0x{:016X} when outside kernel mode!", vaddr);
}
if (const u8 high_two_bits = (vaddr >> 62) & 0b11; high_two_bits != 0b10) {
Util::panic("Access to XKPHYS address 0x{:016X} with high two bits != 0b10!", vaddr);
panic("Access to XKPHYS address 0x{:016X} with high two bits != 0b10!", vaddr);
}
const u8 subsegment = (vaddr >> 59) & 0b11;
bool cached = subsegment != 2; // do something with this eventually
@@ -592,16 +592,16 @@ bool Cop0::MapVAddr64(const TLBAccessType accessType, const u64 vaddr, u32 &padd
// Identical to kseg0 in 32 bit mode.
// Unmapped translation. Subtract the base address of the space to get the physical address.
paddr = vaddr - START_VREGION_KSEG0; // Implies cutting off the high 32 bits
Util::trace("CKSEG0: Translated 0x{:016X} to 0x{:08X}", vaddr, paddr);
trace("CKSEG0: Translated 0x{:016X} to 0x{:08X}", vaddr, paddr);
return true;
case VREGION_CKSEG1:
// Identical to kseg1 in 32 bit mode.
// Unmapped translation. Subtract the base address of the space to get the physical address.
paddr = vaddr - START_VREGION_KSEG1; // Implies cutting off the high 32 bits
Util::trace("KSEG1: Translated 0x{:016X} to 0x{:08X}", vaddr, paddr);
trace("KSEG1: Translated 0x{:016X} to 0x{:08X}", vaddr, paddr);
return true;
case VREGION_CKSSEG:
Util::panic("Resolving virtual address 0x{:016X} (VREGION_CKSSEG) in 64 bit mode", vaddr);
panic("Resolving virtual address 0x{:016X} (VREGION_CKSSEG) in 64 bit mode", vaddr);
case VREGION_CKSEG3:
return ProbeTLB(accessType, vaddr, paddr);
case VREGION_XBAD1:
@@ -610,7 +610,7 @@ bool Cop0::MapVAddr64(const TLBAccessType accessType, const u64 vaddr, u32 &padd
regs.cop0.tlbError = DISALLOWED_ADDRESS;
return false;
default:
Util::panic("Resolving virtual address 0x{:016X} in 64 bit mode", vaddr);
panic("Resolving virtual address 0x{:016X} in 64 bit mode", vaddr);
}
return false;

2
src/backend/core/registers/Cop1.cpp
View File

@@ -289,7 +289,7 @@ void Cop1::decode(const u32 instr) {
}
break;
default:
Util::panic("Unimplemented COP1 instruction {} {}", mask_sub >> 3, mask_sub & 7);
panic("Unimplemented COP1 instruction {} {}", mask_sub >> 3, mask_sub & 7);
}
}
} // namespace n64

16
src/backend/core/registers/Registers.cpp
View File

@@ -245,7 +245,7 @@ void Registers::Write<bool>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movsx(v.cvt64(), v.cvt8());
jit->code.mov(jit->GPR<u64>(idx), v);
@@ -259,7 +259,7 @@ void Registers::Write<s8>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movsx(v.cvt64(), v.cvt8());
jit->code.mov(jit->GPR<u64>(idx), v);
@@ -273,7 +273,7 @@ void Registers::Write<u8>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movzx(v.cvt64(), v.cvt8());
jit->code.mov(jit->GPR<u64>(idx), v.cvt64());
@@ -287,7 +287,7 @@ void Registers::Write<s16>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movsx(v.cvt64(), v.cvt16());
jit->code.mov(jit->GPR<u64>(idx), v.cvt64());
@@ -301,7 +301,7 @@ void Registers::Write<u16>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movzx(v.cvt64(), v.cvt16());
jit->code.mov(jit->GPR<u64>(idx), v.cvt64());
@@ -315,7 +315,7 @@ void Registers::Write<s32>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movsxd(v.cvt64(), v.cvt32());
jit->code.mov(jit->GPR<u64>(idx), v.cvt64());
@@ -329,7 +329,7 @@ void Registers::Write<u32>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.movzx(v.cvt64(), v.cvt32());
jit->code.mov(jit->GPR<u64>(idx), v.cvt64());
@@ -343,7 +343,7 @@ void Registers::Write<u64>(size_t idx, Xbyak::Reg v) {
regIsConstant &= ~(1 << idx);
if (!jit)
Util::panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
panic("Did you try to call Registers::Write(size_t, *Xbyak::Reg*) from the interpreter?");
jit->code.mov(jit->GPR<u64>(idx), v.cvt64());
}

18
src/backend/core/rsp/decode.cpp
View File

@@ -67,7 +67,7 @@ FORCE_INLINE void special(MI &mi, RSP &rsp, const u32 instr) {
rsp.sltu(instr);
break;
default:
Util::panic("Unhandled RSP special instruction ({:06b})", mask);
panic("Unhandled RSP special instruction ({:06b})", mask);
}
}
@@ -86,7 +86,7 @@ FORCE_INLINE void regimm(RSP &rsp, const u32 instr) {
rsp.blink(instr, rsp.gpr[RS(instr)] >= 0);
break;
default:
Util::panic("Unhandled RSP regimm instruction ({:05b})", mask);
panic("Unhandled RSP regimm instruction ({:05b})", mask);
}
}
@@ -128,7 +128,7 @@ FORCE_INLINE void lwc2(RSP &rsp, const u32 instr) {
rsp.ltv(instr);
break;
default:
Util::panic("Unhandled RSP LWC2 {:05b}", mask);
panic("Unhandled RSP LWC2 {:05b}", mask);
}
}
@@ -171,7 +171,7 @@ FORCE_INLINE void swc2(RSP &rsp, const u32 instr) {
rsp.stv(instr);
break;
default:
Util::panic("Unhandled RSP SWC2 {:05b}", mask);
panic("Unhandled RSP SWC2 {:05b}", mask);
}
}
@@ -196,7 +196,7 @@ FORCE_INLINE void cop2(RSP &rsp, const u32 instr) {
rsp.ctc2(instr);
break;
default:
Util::panic("Unhandled RSP COP2 sub ({:05b})", mask_sub);
panic("Unhandled RSP COP2 sub ({:05b})", mask_sub);
}
}
break;
@@ -341,7 +341,7 @@ FORCE_INLINE void cop2(RSP &rsp, const u32 instr) {
case 0x3F:
break;
default:
Util::panic("Unhandled RSP COP2 ({:06b})", mask);
panic("Unhandled RSP COP2 ({:06b})", mask);
}
}
@@ -359,10 +359,10 @@ FORCE_INLINE void cop0(Mem &mem, const u32 instr) {
rsp.mtc0(instr);
break;
default:
Util::panic("Unhandled RSP COP0 ({:05b})", mask);
panic("Unhandled RSP COP0 ({:05b})", mask);
}
} else {
Util::panic("RSP COP0 unknown {:08X}", instr);
panic("RSP COP0 unknown {:08X}", instr);
}
}
@@ -455,7 +455,7 @@ void RSP::Exec(const u32 instr) {
break;
default:
mem.DumpIMEM();
Util::panic("Unhandled RSP instruction ({:06b}, {:04X})", mask, oldPC);
panic("Unhandled RSP instruction ({:06b}, {:04X})", mask, oldPC);
}
}
} // namespace n64

8
src/backend/core/rsp/instructions.cpp
View File

@@ -59,7 +59,7 @@ FORCE_INLINE auto GetCop0Reg(RSP &rsp, const RDP &rdp, const u8 index) -> u32 {
case 15:
return rdp.dpc.status.tmemBusy;
default:
Util::panic("Unhandled RSP COP0 register read at index {}", index);
panic("Unhandled RSP COP0 register read at index {}", index);
return 0;
}
}
@@ -90,7 +90,7 @@ FORCE_INLINE void SetCop0Reg(Mem &mem, const u8 index, const u32 val) {
if (val == 0) {
ReleaseSemaphore(rsp);
} else {
Util::panic("Write with non-zero value to RSP_COP0_RESERVED ({})", val);
panic("Write with non-zero value to RSP_COP0_RESERVED ({})", val);
}
break;
case 8:
@@ -103,7 +103,7 @@ FORCE_INLINE void SetCop0Reg(Mem &mem, const u8 index, const u32 val) {
rdp.WriteStatus(val);
break;
default:
Util::panic("Unhandled RSP COP0 register write at index {}", index);
panic("Unhandled RSP COP0 register write at index {}", index);
}
}
@@ -933,7 +933,7 @@ void RSP::vmov(const u32 instr) {
se = (e & 0b111) | (vs & 0b000);
break;
default:
Util::panic("VMOV: This should be unreachable!");
panic("VMOV: This should be unreachable!");
}
const u8 de = vs & 7;