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get rid of fmt dependency since we are on C++23

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irisz64
2025-07-22 11:30:37 +02:00
parent 9b169825ee
commit 8549d5a21c
173 changed files with 452 additions and 83654 deletions
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34
src/backend/core/RSP.cpp
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@@ -34,34 +34,34 @@ void RSP::Reset() {
/*
FORCE_INLINE void logRSP(const RSP& rsp, const u32 instr) {
Util::debug("{:04X} {:08X} ", rsp.oldPC, instr);
debug("{:04X} {:08X} ", rsp.oldPC, instr);
for (auto gpr : rsp.gpr) {
Util::debug("{:08X} ", gpr);
debug("{:08X} ", gpr);
}
for (auto vpr : rsp.vpr) {
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", vpr.element[i]);
debug("{:04X}", vpr.element[i]);
}
Util::debug(" ");
debug(" ");
}
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", rsp.acc.h.element[i]);
debug("{:04X}", rsp.acc.h.element[i]);
}
Util::debug(" ");
debug(" ");
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", rsp.acc.m.element[i]);
debug("{:04X}", rsp.acc.m.element[i]);
}
Util::debug(" ");
debug(" ");
for (int i = 0; i < 8; i++) {
Util::debug("{:04X}", rsp.acc.l.element[i]);
debug("{:04X}", rsp.acc.l.element[i]);
}
Util::debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
Util::debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
}
*/
@@ -85,7 +85,7 @@ auto RSP::Read(const u32 addr) -> u32 {
case 0x04080000:
return pc & 0xFFC;
default:
Util::panic("Unimplemented SP register read {:08X}", addr);
panic("Unimplemented SP register read {:08X}", addr);
}
}
@@ -127,7 +127,7 @@ void RSP::DMA<true>() {
u32 mem_address = spDMASPAddr.address & 0xFF8;
u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
Util::trace("SP DMA from RSP to RDRAM (size: {} B, {:08X} to {:08X})", length, mem_address, dram_address);
trace("SP DMA from RSP to RDRAM (size: {} B, {:08X} to {:08X})", length, mem_address, dram_address);
for (u32 i = 0; i < spDMALen.count + 1; i++) {
for (u32 j = 0; j < length; j++) {
@@ -141,7 +141,7 @@ void RSP::DMA<true>() {
mem_address += length;
mem_address &= 0xFF8;
}
Util::trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
lastSuccessfulSPAddr.address = mem_address;
lastSuccessfulSPAddr.bank = spDMASPAddr.bank;
@@ -159,7 +159,7 @@ void RSP::DMA<false>() {
u32 mem_address = spDMASPAddr.address & 0xFF8;
u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
Util::trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
for (u32 i = 0; i < spDMALen.count + 1; i++) {
for (u32 j = 0; j < length; j++) {
@@ -173,7 +173,7 @@ void RSP::DMA<false>() {
mem_address += length;
mem_address &= 0xFF8;
}
Util::trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
lastSuccessfulSPAddr.address = mem_address;
lastSuccessfulSPAddr.bank = spDMASPAddr.bank;
@@ -209,7 +209,7 @@ void RSP::Write(const u32 addr, const u32 val) {
}
break;
default:
Util::panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
}
}
} // namespace n64