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fix some warnings

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This commit is contained in:
SimoneN64
2023-06-12 10:12:55 +02:00
parent 3bb4f5e31e
commit 91575fe4df
22 changed files with 124 additions and 136 deletions
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2
src/backend/Core.hpp
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@@ -14,7 +14,7 @@ struct Core {
void LoadROM(const std::string&); void LoadROM(const std::string&);
void Run(float volumeL, float volumeR); void Run(float volumeL, float volumeR);
void TogglePause() { pause = !pause; } void TogglePause() { pause = !pause; }
VI& GetVI() { return cpu.mem.mmio.vi; } [[nodiscard]] VI& GetVI() const { return cpu->mem.mmio.vi; }
u32 breakpoint = 0; u32 breakpoint = 0;

2
src/backend/core/Audio.cpp
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@@ -17,7 +17,7 @@ SDL_AudioDeviceID audioDev{};
#define LockAudioMutex() SDL_LockMutex(audioStreamMutex) #define LockAudioMutex() SDL_LockMutex(audioStreamMutex)
#define UnlockAudioMutex() SDL_UnlockMutex(audioStreamMutex) #define UnlockAudioMutex() SDL_UnlockMutex(audioStreamMutex)
void audioCallback(void* userdata, Uint8* stream, int length) { void audioCallback(void*, Uint8* stream, int length) {
int gotten = 0; int gotten = 0;
LockAudioMutex(); LockAudioMutex();
int available = SDL_AudioStreamAvailable(audioStream); int available = SDL_AudioStreamAvailable(audioStream);

1
src/backend/core/Mem.cpp
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@@ -1,5 +1,4 @@
#include <Mem.hpp> #include <Mem.hpp>
#include <fstream>
#include <core/registers/Registers.hpp> #include <core/registers/Registers.hpp>
#include <core/registers/Cop0.hpp> #include <core/registers/Cop0.hpp>
#include <core/Interpreter.hpp> #include <core/Interpreter.hpp>

2
src/backend/core/Mem.hpp
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@@ -46,7 +46,7 @@ struct Flash {
Flash() = default; Flash() = default;
~Flash() = default; ~Flash() = default;
void Reset(); void Reset();
void Load(SaveType, std::string); void Load(SaveType, const std::string&);
FlashState state{}; FlashState state{};
u64 status{}; u64 status{};
size_t eraseOffs{}; size_t eraseOffs{};

3
src/backend/core/RDP.cpp
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@@ -72,7 +72,7 @@ void RDP::WriteStatus(MI& mi, Registers& regs, RSP& rsp, u32 val) {
RunCommand(mi, regs, rsp); RunCommand(mi, regs, rsp);
} }
} }
/*
FORCE_INLINE void logCommand(u8 cmd) { FORCE_INLINE void logCommand(u8 cmd) {
switch(cmd) { switch(cmd) {
case 0x08: Util::debug("Fill triangle"); break; case 0x08: Util::debug("Fill triangle"); break;
@@ -112,6 +112,7 @@ FORCE_INLINE void logCommand(u8 cmd) {
case 0x3f: Util::debug("Set color image"); break; case 0x3f: Util::debug("Set color image"); break;
} }
} }
*/
void RDP::RunCommand(MI& mi, Registers& regs, RSP& rsp) { void RDP::RunCommand(MI& mi, Registers& regs, RSP& rsp) {
if (dpc.status.freeze) { if (dpc.status.freeze) {

2
src/backend/core/RDP.hpp
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@@ -51,7 +51,7 @@ struct DPC {
}; };
struct RDP { struct RDP {
DPC dpc; DPC dpc{};
u32 cmd_buf[0xFFFFF]{}; u32 cmd_buf[0xFFFFF]{};
RDP(); RDP();

6
src/backend/core/RSP.hpp
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@@ -127,12 +127,12 @@ struct RSP {
auto Read(u32 addr) -> u32; auto Read(u32 addr) -> u32;
void Write(Mem& mem, Registers& regs, u32 addr, u32 value); void Write(Mem& mem, Registers& regs, u32 addr, u32 value);
void Exec(Registers& regs, Mem& mem, u32 instr); void Exec(Registers& regs, Mem& mem, u32 instr);
SPStatus spStatus; SPStatus spStatus{};
u16 oldPC{}, pc{}, nextPC{}; u16 oldPC{}, pc{}, nextPC{};
SPDMASPAddr spDMASPAddr{}; SPDMASPAddr spDMASPAddr{};
SPDMADRAMAddr spDMADRAMAddr{}; SPDMADRAMAddr spDMADRAMAddr{};
SPDMASPAddr lastSuccessfulSPAddr; SPDMASPAddr lastSuccessfulSPAddr{};
SPDMADRAMAddr lastSuccessfulDRAMAddr; SPDMADRAMAddr lastSuccessfulDRAMAddr{};
SPDMALen spDMALen{}; SPDMALen spDMALen{};
u8 dmem[DMEM_SIZE]{}, imem[IMEM_SIZE]{}; u8 dmem[DMEM_SIZE]{}, imem[IMEM_SIZE]{};
VPR vpr[32]{}; VPR vpr[32]{};

2
src/backend/core/mem/Flash.cpp
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@@ -12,7 +12,7 @@ void Flash::Reset() {
} }
} }
void Flash::Load(SaveType saveType, std::string path) { void Flash::Load(SaveType saveType, const std::string& path) {
if(saveType == SAVE_FLASH_1m) { if(saveType == SAVE_FLASH_1m) {
flashPath = fs::path(path).replace_extension(".flash").string(); flashPath = fs::path(path).replace_extension(".flash").string();
std::error_code error; std::error_code error;

2
src/backend/core/mmio/AI.cpp
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@@ -6,7 +6,7 @@
namespace n64 { namespace n64 {
void AI::Reset() { void AI::Reset() {
dmaEnable = 0; dmaEnable = false;
dacRate = 0; dacRate = 0;
bitrate = 0; bitrate = 0;
dmaCount = 0; dmaCount = 0;

132
src/backend/core/mmio/PIF.cpp
View File

@@ -26,7 +26,7 @@ void PIF::Reset() {
} }
} }
void PIF::LoadMempak(std::string path) { void PIF::LoadMempak(const std::string& path) {
mempakPath = fs::path(path).replace_extension(".mempak").string(); mempakPath = fs::path(path).replace_extension(".mempak").string();
std::error_code error; std::error_code error;
if (mempak.is_mapped()) { if (mempak.is_mapped()) {
@@ -72,7 +72,7 @@ FORCE_INLINE size_t getSaveSize(SaveType saveType) {
} }
} }
void PIF::LoadEeprom(SaveType saveType, std::string path) { void PIF::LoadEeprom(SaveType saveType, const std::string& path) {
if(saveType == SAVE_EEPROM_16k || saveType == SAVE_EEPROM_4k) { if(saveType == SAVE_EEPROM_16k || saveType == SAVE_EEPROM_4k) {
eepromPath = fs::path(path).replace_extension(".eeprom").string(); eepromPath = fs::path(path).replace_extension(".eeprom").string();
std::error_code error; std::error_code error;
@@ -443,20 +443,20 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
case CIC_NUS_6101: case CIC_NUS_6101:
regs.gpr[0] = 0x0000000000000000; regs.gpr[0] = 0x0000000000000000;
regs.gpr[1] = 0x0000000000000000; regs.gpr[1] = 0x0000000000000000;
regs.gpr[2] = 0xFFFFFFFFDF6445CC; regs.gpr[2] = 0xFFFFFFFFDF6445CCll;
regs.gpr[3] = 0xFFFFFFFFDF6445CC; regs.gpr[3] = 0xFFFFFFFFDF6445CCll;
regs.gpr[4] = 0x00000000000045CC; regs.gpr[4] = 0x00000000000045CC;
regs.gpr[5] = 0x0000000073EE317A; regs.gpr[5] = 0x0000000073EE317A;
regs.gpr[6] = 0xFFFFFFFFA4001F0C; regs.gpr[6] = 0xFFFFFFFFA4001F0Cll;
regs.gpr[7] = 0xFFFFFFFFA4001F08; regs.gpr[7] = 0xFFFFFFFFA4001F08ll;
regs.gpr[8] = 0x00000000000000C0; regs.gpr[8] = 0x00000000000000C0;
regs.gpr[9] = 0x0000000000000000; regs.gpr[9] = 0x0000000000000000;
regs.gpr[10] = 0x0000000000000040; regs.gpr[10] = 0x0000000000000040;
regs.gpr[11] = 0xFFFFFFFFA4000040; regs.gpr[11] = 0xFFFFFFFFA4000040ll;
regs.gpr[12] = 0xFFFFFFFFC7601FAC; regs.gpr[12] = 0xFFFFFFFFC7601FACll;
regs.gpr[13] = 0xFFFFFFFFC7601FAC; regs.gpr[13] = 0xFFFFFFFFC7601FACll;
regs.gpr[14] = 0xFFFFFFFFB48E2ED6; regs.gpr[14] = 0xFFFFFFFFB48E2ED6ll;
regs.gpr[15] = 0xFFFFFFFFBA1A7D4B; regs.gpr[15] = 0xFFFFFFFFBA1A7D4Bll;
regs.gpr[16] = 0x0000000000000000; regs.gpr[16] = 0x0000000000000000;
regs.gpr[17] = 0x0000000000000000; regs.gpr[17] = 0x0000000000000000;
regs.gpr[18] = 0x0000000000000000; regs.gpr[18] = 0x0000000000000000;
@@ -465,16 +465,16 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[21] = 0x0000000000000000; regs.gpr[21] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000001; regs.gpr[23] = 0x0000000000000001;
regs.gpr[24] = 0x0000000000000002; regs.gpr[24] = 0x0000000000000002;
regs.gpr[25] = 0xFFFFFFFF905F4718; regs.gpr[25] = 0xFFFFFFFF905F4718ll;
regs.gpr[26] = 0x0000000000000000; regs.gpr[26] = 0x0000000000000000;
regs.gpr[27] = 0x0000000000000000; regs.gpr[27] = 0x0000000000000000;
regs.gpr[28] = 0x0000000000000000; regs.gpr[28] = 0x0000000000000000;
regs.gpr[29] = 0xFFFFFFFFA4001FF0; regs.gpr[29] = 0xFFFFFFFFA4001FF0ll;
regs.gpr[30] = 0x0000000000000000; regs.gpr[30] = 0x0000000000000000;
regs.gpr[31] = 0xFFFFFFFFA4001550; regs.gpr[31] = 0xFFFFFFFFA4001550ll;
regs.lo = 0xFFFFFFFFBA1A7D4B; regs.lo = 0xFFFFFFFFBA1A7D4Bll;
regs.hi = 0xFFFFFFFF997EC317; regs.hi = 0xFFFFFFFF997EC317ll;
break; break;
case CIC_NUS_7102: case CIC_NUS_7102:
regs.gpr[0] = 0x0000000000000000; regs.gpr[0] = 0x0000000000000000;
@@ -483,16 +483,16 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[3] = 0x000000001E324416; regs.gpr[3] = 0x000000001E324416;
regs.gpr[4] = 0x0000000000004416; regs.gpr[4] = 0x0000000000004416;
regs.gpr[5] = 0x000000000EC5D9AF; regs.gpr[5] = 0x000000000EC5D9AF;
regs.gpr[6] = 0xFFFFFFFFA4001F0C; regs.gpr[6] = 0xFFFFFFFFA4001F0Cll;
regs.gpr[7] = 0xFFFFFFFFA4001F08; regs.gpr[7] = 0xFFFFFFFFA4001F08ll;
regs.gpr[8] = 0x00000000000000C0; regs.gpr[8] = 0x00000000000000C0;
regs.gpr[9] = 0x0000000000000000; regs.gpr[9] = 0x0000000000000000;
regs.gpr[10] = 0x0000000000000040; regs.gpr[10] = 0x0000000000000040;
regs.gpr[11] = 0xFFFFFFFFA4000040; regs.gpr[11] = 0xFFFFFFFFA4000040ll;
regs.gpr[12] = 0x00000000495D3D7B; regs.gpr[12] = 0x00000000495D3D7B;
regs.gpr[13] = 0xFFFFFFFF8B3DFA1E; regs.gpr[13] = 0xFFFFFFFF8B3DFA1Ell;
regs.gpr[14] = 0x000000004798E4D4; regs.gpr[14] = 0x000000004798E4D4;
regs.gpr[15] = 0xFFFFFFFFF1D30682; regs.gpr[15] = 0xFFFFFFFFF1D30682ll;
regs.gpr[16] = 0x0000000000000000; regs.gpr[16] = 0x0000000000000000;
regs.gpr[17] = 0x0000000000000000; regs.gpr[17] = 0x0000000000000000;
regs.gpr[18] = 0x0000000000000000; regs.gpr[18] = 0x0000000000000000;
@@ -506,11 +506,11 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[26] = 0x0000000000000000; regs.gpr[26] = 0x0000000000000000;
regs.gpr[27] = 0x0000000000000000; regs.gpr[27] = 0x0000000000000000;
regs.gpr[28] = 0x0000000000000000; regs.gpr[28] = 0x0000000000000000;
regs.gpr[29] = 0xFFFFFFFFA4001FF0; regs.gpr[29] = 0xFFFFFFFFA4001FF0ll;
regs.gpr[30] = 0x0000000000000000; regs.gpr[30] = 0x0000000000000000;
regs.gpr[31] = 0xFFFFFFFFA4001554; regs.gpr[31] = 0xFFFFFFFFA4001554ll;
regs.lo = 0xFFFFFFFFF1D30682; regs.lo = 0xFFFFFFFFF1D30682ll;
regs.hi = 0x0000000010054A98; regs.hi = 0x0000000010054A98;
break; break;
case CIC_NUS_6102_7101: case CIC_NUS_6102_7101:
@@ -519,14 +519,14 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[2] = 0x000000000EBDA536; regs.gpr[2] = 0x000000000EBDA536;
regs.gpr[3] = 0x000000000EBDA536; regs.gpr[3] = 0x000000000EBDA536;
regs.gpr[4] = 0x000000000000A536; regs.gpr[4] = 0x000000000000A536;
regs.gpr[5] = 0xFFFFFFFFC0F1D859; regs.gpr[5] = 0xFFFFFFFFC0F1D859ll;
regs.gpr[6] = 0xFFFFFFFFA4001F0C; regs.gpr[6] = 0xFFFFFFFFA4001F0Cll;
regs.gpr[7] = 0xFFFFFFFFA4001F08; regs.gpr[7] = 0xFFFFFFFFA4001F08ll;
regs.gpr[8] = 0x00000000000000C0; regs.gpr[8] = 0x00000000000000C0;
regs.gpr[9] = 0x0000000000000000; regs.gpr[9] = 0x0000000000000000;
regs.gpr[10] = 0x0000000000000040; regs.gpr[10] = 0x0000000000000040;
regs.gpr[11] = 0xFFFFFFFFA4000040; regs.gpr[11] = 0xFFFFFFFFA4000040ll;
regs.gpr[12] = 0xFFFFFFFFED10D0B3; regs.gpr[12] = 0xFFFFFFFFED10D0B3ll;
regs.gpr[13] = 0x000000001402A4CC; regs.gpr[13] = 0x000000001402A4CC;
regs.gpr[14] = 0x000000002DE108EA; regs.gpr[14] = 0x000000002DE108EA;
regs.gpr[15] = 0x000000003103E121; regs.gpr[15] = 0x000000003103E121;
@@ -538,13 +538,13 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[21] = 0x0000000000000000; regs.gpr[21] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000000; regs.gpr[23] = 0x0000000000000000;
regs.gpr[24] = 0x0000000000000000; regs.gpr[24] = 0x0000000000000000;
regs.gpr[25] = 0xFFFFFFFF9DEBB54F; regs.gpr[25] = 0xFFFFFFFF9DEBB54Fll;
regs.gpr[26] = 0x0000000000000000; regs.gpr[26] = 0x0000000000000000;
regs.gpr[27] = 0x0000000000000000; regs.gpr[27] = 0x0000000000000000;
regs.gpr[28] = 0x0000000000000000; regs.gpr[28] = 0x0000000000000000;
regs.gpr[29] = 0xFFFFFFFFA4001FF0; regs.gpr[29] = 0xFFFFFFFFA4001FF0ll;
regs.gpr[30] = 0x0000000000000000; regs.gpr[30] = 0x0000000000000000;
regs.gpr[31] = 0xFFFFFFFFA4001550; regs.gpr[31] = 0xFFFFFFFFA4001550ll;
regs.hi = 0x000000003FC18657; regs.hi = 0x000000003FC18657;
regs.lo = 0x000000003103E121; regs.lo = 0x000000003103E121;
@@ -552,7 +552,7 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
if (pal) { if (pal) {
regs.gpr[20] = 0x0000000000000000; regs.gpr[20] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000006; regs.gpr[23] = 0x0000000000000006;
regs.gpr[31] = 0xFFFFFFFFA4001554; regs.gpr[31] = 0xFFFFFFFFA4001554ll;
} }
break; break;
case CIC_NUS_6103_7103: case CIC_NUS_6103_7103:
@@ -561,15 +561,15 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[2] = 0x0000000049A5EE96; regs.gpr[2] = 0x0000000049A5EE96;
regs.gpr[3] = 0x0000000049A5EE96; regs.gpr[3] = 0x0000000049A5EE96;
regs.gpr[4] = 0x000000000000EE96; regs.gpr[4] = 0x000000000000EE96;
regs.gpr[5] = 0xFFFFFFFFD4646273; regs.gpr[5] = 0xFFFFFFFFD4646273ll;
regs.gpr[6] = 0xFFFFFFFFA4001F0C; regs.gpr[6] = 0xFFFFFFFFA4001F0Cll;
regs.gpr[7] = 0xFFFFFFFFA4001F08; regs.gpr[7] = 0xFFFFFFFFA4001F08ll;
regs.gpr[8] = 0x00000000000000C0; regs.gpr[8] = 0x00000000000000C0;
regs.gpr[9] = 0x0000000000000000; regs.gpr[9] = 0x0000000000000000;
regs.gpr[10] = 0x0000000000000040; regs.gpr[10] = 0x0000000000000040;
regs.gpr[11] = 0xFFFFFFFFA4000040; regs.gpr[11] = 0xFFFFFFFFA4000040ll;
regs.gpr[12] = 0xFFFFFFFFCE9DFBF7; regs.gpr[12] = 0xFFFFFFFFCE9DFBF7ll;
regs.gpr[13] = 0xFFFFFFFFCE9DFBF7; regs.gpr[13] = 0xFFFFFFFFCE9DFBF7ll;
regs.gpr[14] = 0x000000001AF99984; regs.gpr[14] = 0x000000001AF99984;
regs.gpr[15] = 0x0000000018B63D28; regs.gpr[15] = 0x0000000018B63D28;
regs.gpr[16] = 0x0000000000000000; regs.gpr[16] = 0x0000000000000000;
@@ -580,13 +580,13 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[21] = 0x0000000000000000; regs.gpr[21] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000000; regs.gpr[23] = 0x0000000000000000;
regs.gpr[24] = 0x0000000000000000; regs.gpr[24] = 0x0000000000000000;
regs.gpr[25] = 0xFFFFFFFF825B21C9; regs.gpr[25] = 0xFFFFFFFF825B21C9ll;
regs.gpr[26] = 0x0000000000000000; regs.gpr[26] = 0x0000000000000000;
regs.gpr[27] = 0x0000000000000000; regs.gpr[27] = 0x0000000000000000;
regs.gpr[28] = 0x0000000000000000; regs.gpr[28] = 0x0000000000000000;
regs.gpr[29] = 0xFFFFFFFFA4001FF0; regs.gpr[29] = 0xFFFFFFFFA4001FF0ll;
regs.gpr[30] = 0x0000000000000000; regs.gpr[30] = 0x0000000000000000;
regs.gpr[31] = 0xFFFFFFFFA4001550; regs.gpr[31] = 0xFFFFFFFFA4001550ll;
regs.lo = 0x0000000018B63D28; regs.lo = 0x0000000018B63D28;
regs.hi = 0x00000000625C2BBE; regs.hi = 0x00000000625C2BBE;
@@ -594,23 +594,23 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
if (pal) { if (pal) {
regs.gpr[20] = 0x0000000000000000; regs.gpr[20] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000006; regs.gpr[23] = 0x0000000000000006;
regs.gpr[31] = 0xFFFFFFFFA4001554; regs.gpr[31] = 0xFFFFFFFFA4001554ll;
} }
break; break;
case CIC_NUS_6105_7105: case CIC_NUS_6105_7105:
regs.gpr[0] = 0x0000000000000000; regs.gpr[0] = 0x0000000000000000;
regs.gpr[1] = 0x0000000000000000; regs.gpr[1] = 0x0000000000000000;
regs.gpr[2] = 0xFFFFFFFFF58B0FBF; regs.gpr[2] = 0xFFFFFFFFF58B0FBFll;
regs.gpr[3] = 0xFFFFFFFFF58B0FBF; regs.gpr[3] = 0xFFFFFFFFF58B0FBFll;
regs.gpr[4] = 0x0000000000000FBF; regs.gpr[4] = 0x0000000000000FBF;
regs.gpr[5] = 0xFFFFFFFFDECAAAD1; regs.gpr[5] = 0xFFFFFFFFDECAAAD1ll;
regs.gpr[6] = 0xFFFFFFFFA4001F0C; regs.gpr[6] = 0xFFFFFFFFA4001F0Cll;
regs.gpr[7] = 0xFFFFFFFFA4001F08; regs.gpr[7] = 0xFFFFFFFFA4001F08ll;
regs.gpr[8] = 0x00000000000000C0; regs.gpr[8] = 0x00000000000000C0;
regs.gpr[9] = 0x0000000000000000; regs.gpr[9] = 0x0000000000000000;
regs.gpr[10] = 0x0000000000000040; regs.gpr[10] = 0x0000000000000040;
regs.gpr[11] = 0xFFFFFFFFA4000040; regs.gpr[11] = 0xFFFFFFFFA4000040ll;
regs.gpr[12] = 0xFFFFFFFF9651F81E; regs.gpr[12] = 0xFFFFFFFF9651F81Ell;
regs.gpr[13] = 0x000000002D42AAC5; regs.gpr[13] = 0x000000002D42AAC5;
regs.gpr[14] = 0x00000000489B52CF; regs.gpr[14] = 0x00000000489B52CF;
regs.gpr[15] = 0x0000000056584D60; regs.gpr[15] = 0x0000000056584D60;
@@ -622,13 +622,13 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[21] = 0x0000000000000000; regs.gpr[21] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000000; regs.gpr[23] = 0x0000000000000000;
regs.gpr[24] = 0x0000000000000002; regs.gpr[24] = 0x0000000000000002;
regs.gpr[25] = 0xFFFFFFFFCDCE565F; regs.gpr[25] = 0xFFFFFFFFCDCE565Fll;
regs.gpr[26] = 0x0000000000000000; regs.gpr[26] = 0x0000000000000000;
regs.gpr[27] = 0x0000000000000000; regs.gpr[27] = 0x0000000000000000;
regs.gpr[28] = 0x0000000000000000; regs.gpr[28] = 0x0000000000000000;
regs.gpr[29] = 0xFFFFFFFFA4001FF0; regs.gpr[29] = 0xFFFFFFFFA4001FF0ll;
regs.gpr[30] = 0x0000000000000000; regs.gpr[30] = 0x0000000000000000;
regs.gpr[31] = 0xFFFFFFFFA4001550; regs.gpr[31] = 0xFFFFFFFFA4001550ll;
regs.lo = 0x0000000056584D60; regs.lo = 0x0000000056584D60;
regs.hi = 0x000000004BE35D1F; regs.hi = 0x000000004BE35D1F;
@@ -636,7 +636,7 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
if (pal) { if (pal) {
regs.gpr[20] = 0x0000000000000000; regs.gpr[20] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000006; regs.gpr[23] = 0x0000000000000006;
regs.gpr[31] = 0xFFFFFFFFA4001554; regs.gpr[31] = 0xFFFFFFFFA4001554ll;
} }
mem.Write32(regs, IMEM_REGION_START + 0x00, 0x3C0DBFC0); mem.Write32(regs, IMEM_REGION_START + 0x00, 0x3C0DBFC0);
@@ -651,18 +651,18 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
case CIC_NUS_6106_7106: case CIC_NUS_6106_7106:
regs.gpr[0] = 0x0000000000000000; regs.gpr[0] = 0x0000000000000000;
regs.gpr[1] = 0x0000000000000000; regs.gpr[1] = 0x0000000000000000;
regs.gpr[2] = 0xFFFFFFFFA95930A4; regs.gpr[2] = 0xFFFFFFFFA95930A4ll;
regs.gpr[3] = 0xFFFFFFFFA95930A4; regs.gpr[3] = 0xFFFFFFFFA95930A4ll;
regs.gpr[4] = 0x00000000000030A4; regs.gpr[4] = 0x00000000000030A4;
regs.gpr[5] = 0xFFFFFFFFB04DC903; regs.gpr[5] = 0xFFFFFFFFB04DC903ll;
regs.gpr[6] = 0xFFFFFFFFA4001F0C; regs.gpr[6] = 0xFFFFFFFFA4001F0Cll;
regs.gpr[7] = 0xFFFFFFFFA4001F08; regs.gpr[7] = 0xFFFFFFFFA4001F08ll;
regs.gpr[8] = 0x00000000000000C0; regs.gpr[8] = 0x00000000000000C0;
regs.gpr[9] = 0x0000000000000000; regs.gpr[9] = 0x0000000000000000;
regs.gpr[10] = 0x0000000000000040; regs.gpr[10] = 0x0000000000000040;
regs.gpr[11] = 0xFFFFFFFFA4000040; regs.gpr[11] = 0xFFFFFFFFA4000040ll;
regs.gpr[12] = 0xFFFFFFFFBCB59510; regs.gpr[12] = 0xFFFFFFFFBCB59510ll;
regs.gpr[13] = 0xFFFFFFFFBCB59510; regs.gpr[13] = 0xFFFFFFFFBCB59510ll;
regs.gpr[14] = 0x000000000CF85C13; regs.gpr[14] = 0x000000000CF85C13;
regs.gpr[15] = 0x000000007A3C07F4; regs.gpr[15] = 0x000000007A3C07F4;
regs.gpr[16] = 0x0000000000000000; regs.gpr[16] = 0x0000000000000000;
@@ -677,16 +677,16 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.gpr[26] = 0x0000000000000000; regs.gpr[26] = 0x0000000000000000;
regs.gpr[27] = 0x0000000000000000; regs.gpr[27] = 0x0000000000000000;
regs.gpr[28] = 0x0000000000000000; regs.gpr[28] = 0x0000000000000000;
regs.gpr[29] = 0xFFFFFFFFA4001FF0; regs.gpr[29] = 0xFFFFFFFFA4001FF0ll;
regs.gpr[30] = 0x0000000000000000; regs.gpr[30] = 0x0000000000000000;
regs.gpr[31] = 0xFFFFFFFFA4001550; regs.gpr[31] = 0xFFFFFFFFA4001550ll;
regs.lo = 0x000000007A3C07F4; regs.lo = 0x000000007A3C07F4;
regs.hi = 0x0000000023953898; regs.hi = 0x0000000023953898;
if (pal) { if (pal) {
regs.gpr[20] = 0x0000000000000000; regs.gpr[20] = 0x0000000000000000;
regs.gpr[23] = 0x0000000000000006; regs.gpr[23] = 0x0000000000000006;
regs.gpr[31] = 0xFFFFFFFFA4001554; regs.gpr[31] = 0xFFFFFFFFA4001554ll;
} }
break; break;
} }
@@ -695,7 +695,7 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
regs.cop0.Reset(); regs.cop0.Reset();
mem.Write32(regs, 0x04300004, 0x01010101); mem.Write32(regs, 0x04300004, 0x01010101);
memcpy(mem.mmio.rsp.dmem, mem.rom.cart, 0x1000); memcpy(mem.mmio.rsp.dmem, mem.rom.cart, 0x1000);
regs.SetPC32(0xA4000040); regs.SetPC32(s32(0xA4000040));
} }
void PIF::ExecutePIF(Mem& mem, Registers& regs) { void PIF::ExecutePIF(Mem& mem, Registers& regs) {

8
src/backend/core/mmio/PIF.hpp
View File

@@ -93,13 +93,13 @@ struct PIF {
PIF() = default; PIF() = default;
~PIF() = default; ~PIF() = default;
void Reset(); void Reset();
void LoadMempak(std::string); void LoadMempak(const std::string&);
void LoadEeprom(SaveType, std::string); void LoadEeprom(SaveType, const std::string&);
void ProcessCommands(Mem&); void ProcessCommands(Mem&);
void InitDevices(SaveType); void InitDevices(SaveType);
void CICChallenge(); void CICChallenge();
void ExecutePIF(Mem& mem, Registers& regs); static void ExecutePIF(Mem& mem, Registers& regs);
void DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType); static void DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType);
void UpdateController(); void UpdateController();
bool ReadButtons(u8*) const; bool ReadButtons(u8*) const;
void ControllerID(u8*) const; void ControllerID(u8*) const;

3
src/backend/core/mmio/SI.hpp
View File

@@ -32,6 +32,7 @@ struct SI {
PIF pif; PIF pif;
}; };
static void DMA(Mem& mem, Registers& regs); // just to silence warning, it is used.
[[maybe_unused]] static void DMA(Mem& mem, Registers& regs);
#define SI_DMA_DELAY (65536 * 2) #define SI_DMA_DELAY (65536 * 2)
} }

10
src/backend/core/mmio/VI.hpp
View File

@@ -85,13 +85,13 @@ struct VI {
VIStatus status{}; VIStatus status{};
VIBurst burst{}; VIBurst burst{};
u32 vburst{}; u32 vburst{};
u32 origin, width, current; u32 origin{}, width{}, current{};
u32 vsync, hsync, intr; u32 vsync{}, hsync{}, intr{};
AxisStart hstart{}, vstart{}; AxisStart hstart{}, vstart{};
bool isPal = false; bool isPal = false;
int swaps{}; int swaps{};
int numHalflines; int numHalflines{};
int numFields; int numFields{};
int cyclesPerHalfline; int cyclesPerHalfline{};
}; };
} // backend } // backend

14
src/backend/core/registers/Cop0.cpp
View File

@@ -16,8 +16,8 @@ void Cop0::Reset() {
status.fr = 1; status.fr = 1;
PRId = 0x00000B22; PRId = 0x00000B22;
Config = 0x7006E463; Config = 0x7006E463;
EPC = 0xFFFFFFFFFFFFFFFF; EPC = 0xFFFFFFFFFFFFFFFFll;
ErrorEPC = 0xFFFFFFFFFFFFFFFF; ErrorEPC = 0xFFFFFFFFFFFFFFFFll;
wired = 0; wired = 0;
index = 63; index = 63;
badVaddr = 0xFFFFFFFFFFFFFFFF; badVaddr = 0xFFFFFFFFFFFFFFFF;
@@ -58,7 +58,7 @@ u32 Cop0::GetReg32(u8 addr) {
} }
} }
u64 Cop0::GetReg64(u8 addr) { u64 Cop0::GetReg64(u8 addr) const {
switch(addr) { switch(addr) {
case COP0_REG_ENTRYLO0: return entryLo0.raw; case COP0_REG_ENTRYLO0: return entryLo0.raw;
case COP0_REG_ENTRYLO1: return entryLo1.raw; case COP0_REG_ENTRYLO1: return entryLo1.raw;
@@ -280,15 +280,15 @@ void FireException(Registers& regs, ExceptionCode code, int cop, bool useOldPC)
case ExceptionCode::ReservedInstruction: case ExceptionCode::CoprocessorUnusable: case ExceptionCode::ReservedInstruction: case ExceptionCode::CoprocessorUnusable:
case ExceptionCode::Overflow: case ExceptionCode::Trap: case ExceptionCode::Overflow: case ExceptionCode::Trap:
case ExceptionCode::FloatingPointError: case ExceptionCode::Watch: case ExceptionCode::FloatingPointError: case ExceptionCode::Watch:
regs.SetPC32(0x80000180); regs.SetPC32(s32(0x80000180));
break; break;
case ExceptionCode::TLBLoad: case ExceptionCode::TLBStore: case ExceptionCode::TLBLoad: case ExceptionCode::TLBStore:
if(old_exl || regs.cop0.tlbError == INVALID) { if(old_exl || regs.cop0.tlbError == INVALID) {
regs.SetPC32(0x80000180); regs.SetPC32(s32(0x80000180));
} else if(Is64BitAddressing(regs.cop0, regs.cop0.badVaddr)) { } else if(Is64BitAddressing(regs.cop0, regs.cop0.badVaddr)) {
regs.SetPC32(0x80000080); regs.SetPC32(s32(0x80000080));
} else { } else {
regs.SetPC32(0x80000000); regs.SetPC32(s32(0x80000000));
} }
break; break;
default: Util::panic("Unhandled exception! {}", static_cast<u8>(code)); default: Util::panic("Unhandled exception! {}", static_cast<u8>(code));

22
src/backend/core/registers/Cop0.hpp
View File

@@ -203,34 +203,34 @@ struct Cop0 {
Cop0(); Cop0();
u32 GetReg32(u8); u32 GetReg32(u8);
u64 GetReg64(u8); u64 GetReg64(u8) const;
void SetReg32(u8, u32); void SetReg32(u8, u32);
void SetReg64(u8, u64); void SetReg64(u8, u64);
void Reset(); void Reset();
bool kernel_mode; bool kernel_mode{};
bool supervisor_mode; bool supervisor_mode{};
bool user_mode; bool user_mode{};
bool is_64bit_addressing; bool is_64bit_addressing{};
bool llbit; bool llbit{};
PageMask pageMask{}; PageMask pageMask{};
EntryHi entryHi{}; EntryHi entryHi{};
EntryLo entryLo0{}, entryLo1{}; EntryLo entryLo0{}, entryLo1{};
u32 index; u32 index{};
Cop0Context context{}; Cop0Context context{};
u32 wired, r7{}; u32 wired{}, r7{};
u64 badVaddr{}, count{}; u64 badVaddr{}, count{};
u32 compare{}; u32 compare{};
Cop0Status status{}; Cop0Status status{};
Cop0Cause cause{}; Cop0Cause cause{};
s64 EPC; s64 EPC{};
u32 PRId, Config, LLAddr{}, WatchLo{}, WatchHi{}; u32 PRId{}, Config{}, LLAddr{}, WatchLo{}, WatchHi{};
Cop0XContext xcontext{}; Cop0XContext xcontext{};
u32 r21{}, r22{}, r23{}, r24{}, r25{}, ParityError{}, CacheError{}, TagLo{}, TagHi{}; u32 r21{}, r22{}, r23{}, r24{}, r25{}, ParityError{}, CacheError{}, TagLo{}, TagHi{};
s64 ErrorEPC; s64 ErrorEPC{};
u32 r31{}; u32 r31{};
TLBEntry tlb[32]{}; TLBEntry tlb[32]{};
TLBError tlbError = NONE; TLBError tlbError = NONE;

5
src/backend/core/registers/Cop1.cpp
View File

@@ -150,10 +150,7 @@ void Cop1::decode(Registers& regs, Interpreter& cpu, u32 instr) {
case 0x06: movl(regs, instr); break; case 0x06: movl(regs, instr); break;
case 0x20: cvtsl(regs, instr); break; case 0x20: cvtsl(regs, instr); break;
case 0x21: cvtdl(regs, instr); break; case 0x21: cvtdl(regs, instr); break;
case 0x24: case 0x24: case 0x25:
FireException(regs, ExceptionCode::ReservedInstruction, 1, true);
break;
case 0x25:
FireException(regs, ExceptionCode::ReservedInstruction, 1, true); FireException(regs, ExceptionCode::ReservedInstruction, 1, true);
break; break;
default: Util::panic("Unimplemented COP1 function L[{} {}] ({:08X}) ({:016X})", mask_fun >> 3, mask_fun & 7, instr, (u64)regs.oldPC); default: Util::panic("Unimplemented COP1 function L[{} {}] ({:08X}) ({:016X})", mask_fun >> 3, mask_fun & 7, instr, (u64)regs.oldPC);

8
src/backend/core/registers/Registers.hpp
View File

@@ -7,12 +7,12 @@ struct Registers {
void Reset(); void Reset();
void SetPC64(s64); void SetPC64(s64);
void SetPC32(s32); void SetPC32(s32);
s64 gpr[32]; s64 gpr[32]{};
Cop0 cop0; Cop0 cop0;
Cop1 cop1; Cop1 cop1;
s64 oldPC, pc, nextPC; s64 oldPC{}, pc{}, nextPC{};
s64 hi, lo; s64 hi{}, lo{};
bool prevDelaySlot, delaySlot; bool prevDelaySlot{}, delaySlot{};
int steps = 0; int steps = 0;
}; };
} }

15
src/backend/core/rsp/decode.cpp
View File

@@ -136,16 +136,10 @@ FORCE_INLINE void cop2(RSP& rsp, u32 instr) {
case 0x13: rsp.vabs(instr); break; case 0x13: rsp.vabs(instr); break;
case 0x14: rsp.vaddc(instr); break; case 0x14: rsp.vaddc(instr); break;
case 0x15: rsp.vsubc(instr); break; case 0x15: rsp.vsubc(instr); break;
case 0x16: rsp.vzero(instr); break; case 0x16 ... 0x1C: case 0x1E: case 0x1F: case 0x2E: case 0x2F:
case 0x17: rsp.vzero(instr); break; rsp.vzero(instr);
case 0x18: rsp.vzero(instr); break; break;
case 0x19: rsp.vzero(instr); break;
case 0x1A: rsp.vzero(instr); break;
case 0x1B: rsp.vzero(instr); break;
case 0x1C: rsp.vzero(instr); break;
case 0x1D: rsp.vsar(instr); break; case 0x1D: rsp.vsar(instr); break;
case 0x1E: rsp.vzero(instr); break;
case 0x1F: rsp.vzero(instr); break;
case 0x20: rsp.vlt(instr); break; case 0x20: rsp.vlt(instr); break;
case 0x21: rsp.veq(instr); break; case 0x21: rsp.veq(instr); break;
case 0x22: rsp.vne(instr); break; case 0x22: rsp.vne(instr); break;
@@ -160,8 +154,6 @@ FORCE_INLINE void cop2(RSP& rsp, u32 instr) {
case 0x2B: rsp.vnor(instr); break; case 0x2B: rsp.vnor(instr); break;
case 0x2C: rsp.vxor(instr); break; case 0x2C: rsp.vxor(instr); break;
case 0x2D: rsp.vnxor(instr); break; case 0x2D: rsp.vnxor(instr); break;
case 0x2E: rsp.vzero(instr); break;
case 0x2F: rsp.vzero(instr); break;
case 0x31: rsp.vrcpl(instr); break; case 0x31: rsp.vrcpl(instr); break;
case 0x35: rsp.vrsql(instr); break; case 0x35: rsp.vrsql(instr); break;
case 0x32: case 0x36: case 0x32: case 0x36:
@@ -196,7 +188,6 @@ FORCE_INLINE void cop0(Registers& regs, Mem& mem, u32 instr) {
void RSP::Exec(Registers &regs, Mem& mem, u32 instr) { void RSP::Exec(Registers &regs, Mem& mem, u32 instr) {
u8 mask = (instr >> 26) & 0x3F; u8 mask = (instr >> 26) & 0x3F;
MMIO& mmio = mem.mmio; MMIO& mmio = mem.mmio;
RDP& rdp = mmio.rdp;
MI& mi = mmio.mi; MI& mi = mmio.mi;
//Util::print("RSP {:02X}", mask); //Util::print("RSP {:02X}", mask);
switch(mask) { switch(mask) {

4
src/backend/core/rsp/instructions.cpp
View File

@@ -98,7 +98,7 @@ FORCE_INLINE VPR Broadcast(const VPR& vt, int l0, int l1, int l2, int l3, int l4
FORCE_INLINE VPR GetVTE(const VPR& vt, u8 e) { FORCE_INLINE VPR GetVTE(const VPR& vt, u8 e) {
VPR vte{}; VPR vte{};
e &= 0xf; e &= 0xf;
switch(e) { switch(e & 0xf) {
case 0 ... 1: return vt; case 0 ... 1: return vt;
case 2: vte.single = _mm_shufflehi_epi16(_mm_shufflelo_epi16(vt.single, 0xF5), 0xF5); break; case 2: vte.single = _mm_shufflehi_epi16(_mm_shufflelo_epi16(vt.single, 0xF5), 0xF5); break;
case 3: vte.single = _mm_shufflehi_epi16(_mm_shufflelo_epi16(vt.single, 0xA0), 0xA0); break; case 3: vte.single = _mm_shufflehi_epi16(_mm_shufflelo_epi16(vt.single, 0xA0), 0xA0); break;
@@ -487,7 +487,7 @@ void RSP::lfv(u32 instr) {
int end = std::min(start + 8, 16); int end = std::min(start + 8, 16);
// TODO: should be possible to do with one loop // TODO: should be possible to do with one loop
VPR tmp; VPR tmp{};
for (u32 offset = 0; offset < 4; offset++) { for (u32 offset = 0; offset < 4; offset++) {
tmp.element[ELEMENT_INDEX(offset + 0)] = ReadByte(address + (base + offset * 4 + 0 & 15)) << 7; tmp.element[ELEMENT_INDEX(offset + 0)] = ReadByte(address + (base + offset * 4 + 0 & 15)) << 7;
tmp.element[ELEMENT_INDEX(offset + 4)] = ReadByte(address + (base + offset * 4 + 8 & 15)) << 7; tmp.element[ELEMENT_INDEX(offset + 4)] = ReadByte(address + (base + offset * 4 + 8 & 15)) << 7;

7
src/frontend/imgui/Settings.cpp
View File

@@ -1,7 +1,6 @@
#include <Settings.hpp> #include <Settings.hpp>
#include <fstream> #include <fstream>
#include <filesystem> #include <filesystem>
#include <nfd.h>
#include <Widgets.hpp> #include <Widgets.hpp>
#include <Core.hpp> #include <Core.hpp>
@@ -12,17 +11,17 @@ namespace fs = std::filesystem;
auto name##Entry = settings[param1][param2]; \ auto name##Entry = settings[param1][param2]; \
if(!name##Entry.empty()) { \ if(!name##Entry.empty()) { \
auto value = name##Entry.get<type>(); \ auto value = name##Entry.get<type>(); \
name = value; \ (name) = value; \
} else { \ } else { \
settingsFile.clear(); \ settingsFile.clear(); \
settings[param1][param2] = defaultVal; \ settings[param1][param2] = defaultVal; \
settingsFile << settings; \ settingsFile << settings; \
name = defaultVal; \ (name) = defaultVal; \
} \ } \
} while(0) } while(0)
Settings::Settings(n64::Core& core) { Settings::Settings() {
auto fileExists = fs::exists("resources/settings.json"); auto fileExists = fs::exists("resources/settings.json");
std::fstream settingsFile; std::fstream settingsFile;
if(fileExists) { if(fileExists) {

8
src/frontend/imgui/Settings.hpp
View File

@@ -6,12 +6,12 @@ namespace n64 { struct Core; }
using namespace nlohmann; using namespace nlohmann;
struct Settings { struct Settings {
Settings(n64::Core&); Settings();
~Settings(); ~Settings();
FORCE_INLINE float GetVolumeL() const { return volumeL; }; [[nodiscard]] FORCE_INLINE float GetVolumeL() const { return volumeL; };
FORCE_INLINE float GetVolumeR() const { return volumeR; }; [[nodiscard]] FORCE_INLINE float GetVolumeR() const { return volumeR; };
FORCE_INLINE bool GetLockChannels() const { return lockChannels; } [[nodiscard]] FORCE_INLINE bool GetLockChannels() const { return lockChannels; }
void RenderWidget(bool& show); void RenderWidget(bool& show);
private: private:

2
src/frontend/imgui/Window.cpp
View File

@@ -9,7 +9,7 @@
VkInstance instance{}; VkInstance instance{};
namespace fs = std::filesystem; namespace fs = std::filesystem;
Window::Window(n64::Core& core) : settings(core) { Window::Window(n64::Core& core) : settings() {
InitSDL(); InitSDL();
InitParallelRDP(core.cpu.mem.GetRDRAM(), window); InitParallelRDP(core.cpu.mem.GetRDRAM(), window);
InitImgui(); InitImgui();