Small changes

src/backend/Scheduler.cpp

@@ -5,17 +5,17 @@
 Scheduler scheduler;
 
 Scheduler::Scheduler() {
-  events.push({UINT64_MAX, [](n64::Mem&, n64::Registers&){
+  enqueueAbsolute({UINT64_MAX, [](n64::Mem&, n64::Registers&){
     Util::panic("How the fuck did we get here?!\n");
   }});
 }
 
 void Scheduler::enqueueRelative(const Event& event) {
-  events.push({event.time + ticks, event.handler});
+  enqueueAbsolute({event.time + ticks, event.handler});
 }
 
-void Scheduler::enqueueAbsolute(const Event& event) {
+void Scheduler::enqueueAbsolute(const Event& e) {
-  events.push({event.time, event.handler});
+  events.push(e);
 }
 
 void Scheduler::tick(u64 t, n64::Mem& mem, n64::Registers& regs) {

src/backend/Scheduler.hpp

@@ -1,6 +1,7 @@
 #pragma once
 #include <common.hpp>
 #include <queue>
+#include <array>
 
 namespace n64 {
 struct Mem;
@@ -8,11 +9,19 @@ struct Registers;
 }
 
 struct Event {
-  u64 time = UINT64_MAX;
+  u64 time = 0;
   void(*handler)(n64::Mem&, n64::Registers&) = nullptr;
 
   friend bool operator<(const Event& rhs, const Event& lhs) {
-    return lhs.time < rhs.time;
+    return rhs.time < lhs.time;
+  }
+
+  friend bool operator>(const Event& rhs, const Event& lhs) {
+    return rhs.time > lhs.time;
+  }
+
+  friend bool operator>=(const Event& rhs, const Event& lhs) {
+    return rhs.time >= lhs.time;
   }
 };
 
@@ -21,8 +30,9 @@ struct Scheduler {
   void enqueueRelative(const Event&);
   void enqueueAbsolute(const Event&);
   void tick(u64, n64::Mem&, n64::Registers&);
-  std::priority_queue<Event> events;
+  std::priority_queue<Event, std::vector<Event>, std::greater<>> events;
   u64 ticks = 0;
+  u8 index = 0;
 };
 
 extern Scheduler scheduler;

src/backend/core/mmio/SI.cpp

@@ -60,13 +60,14 @@ void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
       status.dmaBusy = true;
       toDram = true;
       scheduler.enqueueRelative({SI_DMA_DELAY, DMA});
+      Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})\n", pifAddr, dramAddr);
     } break;
     case 0x04800010: {
       pifAddr = val & 0x1FFFFFFF;
       status.dmaBusy = true;
       toDram = false;
       scheduler.enqueueRelative({SI_DMA_DELAY, DMA});
-      Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", dramAddr, val & 0x1FFFFFFF);
+      Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", dramAddr, pifAddr);
     } break;
     case 0x04800018:
       InterruptLower(mem.mmio.mi, regs, Interrupt::SI);