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Make Scheduler a singleton

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irisz64
2025-07-28 13:44:13 +02:00
parent 9dec9c03b4
commit ad9814bb3c
6 changed files with 14 additions and 12 deletions
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8
src/backend/core/mmio/PI.cpp
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@@ -31,7 +31,7 @@ bool PI::WriteLatch(u32 value) {
} else {
ioBusy = true;
latch = value;
scheduler.EnqueueRelative(100, PI_BUS_WRITE_COMPLETE);
Scheduler::GetInstance().EnqueueRelative(100, PI_BUS_WRITE_COMPLETE);
return true;
}
}
@@ -39,7 +39,7 @@ bool PI::WriteLatch(u32 value) {
bool PI::ReadLatch() {
if (ioBusy) [[unlikely]] {
ioBusy = false;
regs.CpuStall(scheduler.Remove(PI_BUS_WRITE_COMPLETE));
regs.CpuStall(Scheduler::GetInstance().Remove(PI_BUS_WRITE_COMPLETE));
return false;
}
return true;
@@ -506,7 +506,7 @@ void PI::DMA<false>() {
cartAddr += 1;
dmaBusy = true;
scheduler.EnqueueRelative(AccessTiming(GetDomain(cartAddr), rdLen), PI_DMA_COMPLETE);
Scheduler::GetInstance().EnqueueRelative(AccessTiming(GetDomain(cartAddr), rdLen), PI_DMA_COMPLETE);
}
// cart -> rdram
@@ -529,7 +529,7 @@ void PI::DMA<true>() {
cartAddr += 1;
dmaBusy = true;
scheduler.EnqueueRelative(AccessTiming(GetDomain(cartAddr), len), PI_DMA_COMPLETE);
Scheduler::GetInstance().EnqueueRelative(AccessTiming(GetDomain(cartAddr), len), PI_DMA_COMPLETE);
}
void PI::Write(u32 addr, u32 val) {