Finally clangformat

.clang-format

@@ -0,0 +1,52 @@
+---
+Language: Cpp
+BasedOnStyle: LLVM
+AlignConsecutiveAssignments: false
+AlignConsecutiveDeclarations: false
+AlignOperands: false
+AlignTrailingComments: false
+AlwaysBreakTemplateDeclarations: Yes
+BreakBeforeBraces: Custom
+BraceWrapping:
+  AfterCaseLabel: false
+  AfterClass: false
+  AfterControlStatement: false
+  AfterEnum: false
+  AfterFunction: false
+  AfterNamespace: false
+  AfterStruct: false
+  AfterUnion: false
+  AfterExternBlock: false
+  BeforeCatch: true
+  BeforeElse: false
+  BeforeLambdaBody: false
+  BeforeWhile: true
+  SplitEmptyFunction: false
+  SplitEmptyRecord: false
+  SplitEmptyNamespace: false
+BreakConstructorInitializers: AfterColon
+BreakConstructorInitializersBeforeComma: false
+ColumnLimit: 120
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+ContinuationIndentWidth: 2
+IncludeCategories:
+  - Regex: '^<.*'
+    Priority: 1
+  - Regex: '^".*'
+    Priority: 2
+  - Regex: '.*'
+    Priority: 3
+IncludeIsMainRegex: '([-_](test|unittest))?$'
+IndentCaseBlocks: true
+InsertNewlineAtEOF: true
+MacroBlockBegin: ''
+MacroBlockEnd: ''
+MaxEmptyLinesToKeep: 2
+NamespaceIndentation: Inner
+SpaceInEmptyParentheses: false
+SpacesInAngles: false
+SpacesInConditionalStatement: false
+SpacesInCStyleCastParentheses: false
+SpacesInParentheses: false
+TabWidth: 2
+...

src/backend/core/BaseCPU.hpp

@@ -1,6 +1,6 @@
 #pragma once
-#include <Registers.hpp>
 #include <Mem.hpp>
+#include <Registers.hpp>
 
 namespace n64 {
 struct BaseCPU {
@@ -10,8 +10,8 @@ struct BaseCPU {
   virtual bool ShouldServiceInterrupt() = 0;
   virtual void CheckCompareInterrupt() = 0;
   virtual std::vector<u8> Serialize() = 0;
-  virtual void Deserialize(const std::vector<u8>&) = 0;
+  virtual void Deserialize(const std::vector<u8> &) = 0;
-  virtual Mem& GetMem() = 0;
+  virtual Mem &GetMem() = 0;
-  virtual Registers& GetRegs() = 0;
+  virtual Registers &GetRegs() = 0;
 };
-}
+} // namespace n64

src/backend/core/CpuDefinitions.hpp

@@ -1,5 +1,6 @@
 #pragma once
 #include <common.hpp>
+
 namespace n64 {
 constexpr u8 SPECIAL = 0b000000;
 constexpr u8 REGIMM = 0b000001;
@@ -126,4 +127,4 @@ constexpr u8 BLTZAL     = 0b10000;
 constexpr u8 BGEZAL = 0b10001;
 constexpr u8 BLTZALL = 0b10010;
 constexpr u8 BGEZALL = 0b10011;
-}
+} // namespace n64

src/backend/core/Interpreter.cpp

@@ -1,7 +1,7 @@
 #include <Core.hpp>
 
 namespace n64 {
-Interpreter::Interpreter(ParallelRDP& parallel) : mem(regs, parallel) { }
+Interpreter::Interpreter(ParallelRDP &parallel) : mem(regs, parallel) {}
 
 bool Interpreter::ShouldServiceInterrupt() {
   bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0;
@@ -9,14 +9,13 @@ bool Interpreter::ShouldServiceInterrupt() {
   bool currently_handling_exception = regs.cop0.status.exl == 1;
   bool currently_handling_error = regs.cop0.status.erl == 1;
 
-  return interrupts_pending && interrupts_enabled &&
+  return interrupts_pending && interrupts_enabled && !currently_handling_exception && !currently_handling_error;
-         !currently_handling_exception && !currently_handling_error;
 }
 
 void Interpreter::CheckCompareInterrupt() {
   regs.cop0.count++;
   regs.cop0.count &= 0x1FFFFFFFF;
-  if(regs.cop0.count == (u64)regs.cop0.compare << 1) {
+  if (regs.cop0.count == (u64)regs.cop0.compare << 1) {
     regs.cop0.cause.ip7 = 1;
     mem.mmio.mi.UpdateInterrupt();
   }
@@ -28,14 +27,14 @@ int Interpreter::Step() {
   regs.prevDelaySlot = regs.delaySlot;
   regs.delaySlot = false;
 
-  if(check_address_error(0b11, u64(regs.pc))) [[unlikely]] {
+  if (check_address_error(0b11, u64(regs.pc))) [[unlikely]] {
     regs.cop0.HandleTLBException(regs.pc);
     regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.pc);
     return 1;
   }
 
   u32 paddr = 0;
-  if(!regs.cop0.MapVAddr(Cop0::LOAD, regs.pc, paddr)) {
+  if (!regs.cop0.MapVAddr(Cop0::LOAD, regs.pc, paddr)) {
     regs.cop0.HandleTLBException(regs.pc);
     regs.cop0.FireException(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.pc);
     return 1;
@@ -43,7 +42,7 @@ int Interpreter::Step() {
 
   u32 instruction = mem.Read<u32>(regs, paddr);
 
-  if(ShouldServiceInterrupt()) {
+  if (ShouldServiceInterrupt()) {
     regs.cop0.FireException(ExceptionCode::Interrupt, 0, regs.pc);
     return 1;
   }
@@ -67,7 +66,5 @@ std::vector<u8> Interpreter::Serialize() {
   return res;
 }
 
-void Interpreter::Deserialize(const std::vector<u8> &data) {
+void Interpreter::Deserialize(const std::vector<u8> &data) { memcpy(&regs, data.data(), sizeof(Registers)); }
-  memcpy(&regs, data.data(), sizeof(Registers));
+} // namespace n64
-}
-}

src/backend/core/Interpreter.hpp

@@ -1,37 +1,37 @@
 #pragma once
+#include <BaseCPU.hpp>
 #include <Mem.hpp>
 #include <vector>
-#include <BaseCPU.hpp>
 
 namespace n64 {
 struct Core;
+
 struct Interpreter : BaseCPU {
-  explicit Interpreter(ParallelRDP&);
+  explicit Interpreter(ParallelRDP &);
   ~Interpreter() override = default;
   int Step() override;
+
   void Reset() override {
     regs.Reset();
     mem.Reset();
     cop2Latch = {};
   }
 
-  Mem& GetMem() override {
+  Mem &GetMem() override { return mem; }
-    return mem;
+
-  }
+  Registers &GetRegs() override { return regs; }
 
-  Registers& GetRegs() override {
-    return regs;
-  }
 private:
   Registers regs;
   Mem mem;
   u64 cop2Latch{};
   friend struct Cop1;
-#define check_address_error(mask, vaddr) (((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
+#define check_address_error(mask, vaddr)                                                                               \
+  (((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
   bool ShouldServiceInterrupt() override;
   void CheckCompareInterrupt() override;
   std::vector<u8> Serialize() override;
-  void Deserialize(const std::vector<u8>&) override;
+  void Deserialize(const std::vector<u8> &) override;
 
   void cop2Decode(u32);
   void special(u32);
@@ -130,4 +130,4 @@ private:
   void ctc2(u32);
   void cfc2(u32);
 };
-}
+} // namespace n64

src/backend/core/JIT.cpp

@@ -2,10 +2,7 @@
 #include <jit/helpers.hpp>
 
 namespace n64 {
-JIT::JIT(ParallelRDP& parallel) : mem(regs, parallel) {
+JIT::JIT(ParallelRDP &parallel) : mem(regs, parallel) {}
-  regs.gpr[0] = 0;
-  regs.gprIsConstant[0] = true;
-}
 
 bool JIT::ShouldServiceInterrupt() {
   bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0;
@@ -13,14 +10,13 @@ bool JIT::ShouldServiceInterrupt() {
   bool currently_handling_exception = regs.cop0.status.exl == 1;
   bool currently_handling_error = regs.cop0.status.erl == 1;
 
-  return interrupts_pending && interrupts_enabled &&
+  return interrupts_pending && interrupts_enabled && !currently_handling_exception && !currently_handling_error;
-         !currently_handling_exception && !currently_handling_error;
 }
 
 void JIT::CheckCompareInterrupt() {
   regs.cop0.count++;
   regs.cop0.count &= 0x1FFFFFFFF;
-  if(regs.cop0.count == (u64)regs.cop0.compare << 1) {
+  if (regs.cop0.count == (u64)regs.cop0.compare << 1) {
     regs.cop0.cause.ip7 = 1;
     mem.mmio.mi.UpdateInterrupt();
   }
@@ -31,10 +27,10 @@ int JIT::Step() {
   s64 pc = regs.pc;
 
   do {
-    //CheckCompareInterrupt();
+    // CheckCompareInterrupt();
 
-    //regs.prevDelaySlot = regs.delaySlot;
+    // regs.prevDelaySlot = regs.delaySlot;
-    //regs.delaySlot = false;
+    // regs.delaySlot = false;
 
     /*if (check_address_error(0b11, u64(pc))) [[unlikely]] {
       regs.cop0.HandleTLBException(pc);
@@ -47,7 +43,8 @@ int JIT::Step() {
       /*regs.cop0.HandleTLBException(pc);
       regs.cop0.FireException(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, pc);
       return 1;*/
-      Util::panic("[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address!", static_cast<int>(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD)));
+      Util::panic("[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address!",
+                  static_cast<int>(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD)));
     }
 
     instruction = mem.Read<u32>(regs, paddr);
@@ -59,8 +56,9 @@ int JIT::Step() {
 
     pc += 4;
 
-    //Exec(instruction);
+    // Exec(instruction);
-  } while (!InstrEndsBlock(instruction));
+  }
+  while (!InstrEndsBlock(instruction));
 
   return 1;
 }
@@ -75,7 +73,5 @@ std::vector<u8> JIT::Serialize() {
   return res;
 }
 
-void JIT::Deserialize(const std::vector<u8> &data) {
+void JIT::Deserialize(const std::vector<u8> &data) { memcpy(&regs, data.data(), sizeof(Registers)); }
-  memcpy(&regs, data.data(), sizeof(Registers));
+} // namespace n64
-}
-}

src/backend/core/JIT.hpp

@@ -1,36 +1,36 @@
 #pragma once
+#include <BaseCPU.hpp>
 #include <Mem.hpp>
 #include <vector>
-#include <BaseCPU.hpp>
 
 namespace n64 {
 struct Core;
+
 struct JIT : BaseCPU {
-  explicit JIT(ParallelRDP&);
+  explicit JIT(ParallelRDP &);
   ~JIT() override = default;
   int Step() override;
+
   void Reset() override {
     regs.Reset();
     mem.Reset();
   }
 
-  Mem& GetMem() override {
+  Mem &GetMem() override { return mem; }
-    return mem;
+
-  }
+  Registers &GetRegs() override { return regs; }
 
-  Registers& GetRegs() override {
-    return regs;
-  }
 private:
   Registers regs;
   Mem mem;
   u64 cop2Latch{};
   friend struct Cop1;
-#define check_address_error(mask, vaddr) (((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
+#define check_address_error(mask, vaddr)                                                                               \
+  (((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
   bool ShouldServiceInterrupt() override;
   void CheckCompareInterrupt() override;
   std::vector<u8> Serialize() override;
-  void Deserialize(const std::vector<u8>&) override;
+  void Deserialize(const std::vector<u8> &) override;
 
   void Emit(u32);
   void cop2Decode(u32);
@@ -129,4 +129,4 @@ private:
   void ctc2(u32);
   void cfc2(u32);
 };
-}
+} // namespace n64

src/backend/core/MMIO.cpp

@@ -15,14 +15,22 @@ void MMIO::Reset() {
 
 u32 MMIO::Read(u32 addr) {
   switch (addr) {
-    case RSP_REGION: return rsp.Read(addr);
+  case RSP_REGION:
-    case RDP_REGION: return rdp.Read(addr);
+    return rsp.Read(addr);
-    case MI_REGION: return mi.Read(addr);
+  case RDP_REGION:
-    case VI_REGION: return vi.Read(addr);
+    return rdp.Read(addr);
-    case AI_REGION: return ai.Read(addr);
+  case MI_REGION:
-    case PI_REGION: return pi.Read(addr);
+    return mi.Read(addr);
-    case RI_REGION: return ri.Read(addr);
+  case VI_REGION:
-    case SI_REGION: return si.Read(addr);
+    return vi.Read(addr);
+  case AI_REGION:
+    return ai.Read(addr);
+  case PI_REGION:
+    return pi.Read(addr);
+  case RI_REGION:
+    return ri.Read(addr);
+  case SI_REGION:
+    return si.Read(addr);
   default:
     Util::panic("Unhandled mmio read at addr {:08X}", addr);
   }
@@ -30,14 +38,30 @@ u32 MMIO::Read(u32 addr) {
 
 void MMIO::Write(u32 addr, u32 val) {
   switch (addr) {
-    case RSP_REGION: rsp.Write(addr, val); break;
+  case RSP_REGION:
-    case RDP_REGION: rdp.Write(addr, val); break;
+    rsp.Write(addr, val);
-    case MI_REGION: mi.Write(addr, val); break;
+    break;
-    case VI_REGION: vi.Write(addr, val); break;
+  case RDP_REGION:
-    case AI_REGION: ai.Write(addr, val); break;
+    rdp.Write(addr, val);
-    case PI_REGION: pi.Write(addr, val); break;
+    break;
-    case RI_REGION: ri.Write(addr, val); break;
+  case MI_REGION:
-    case SI_REGION: si.Write(addr, val); break;
+    mi.Write(addr, val);
+    break;
+  case VI_REGION:
+    vi.Write(addr, val);
+    break;
+  case AI_REGION:
+    ai.Write(addr, val);
+    break;
+  case PI_REGION:
+    pi.Write(addr, val);
+    break;
+  case RI_REGION:
+    ri.Write(addr, val);
+    break;
+  case SI_REGION:
+    si.Write(addr, val);
+    break;
   default:
     Util::panic("Unhandled mmio write at addr {:08X} with val {:08X}", addr, val);
   }
@@ -47,20 +71,9 @@ std::vector<u8> MMIO::Serialize() {
   std::vector<u8> res{};
 
   auto sPIF = si.pif.Serialize();
-  constexpr u32 rdpSize = sizeof(DPC) +
+  constexpr u32 rdpSize = sizeof(DPC) + 0xFFFFF + RDRAM_SIZE;
-                          0xFFFFF +
+  res.resize(rdpSize + sizeof(RSP) + sizeof(MI) + sizeof(VI) + sizeof(SI) + sizeof(PI) + sizeof(RI) + sizeof(AI) +
-                          RDRAM_SIZE;
+             sizeof(u32) * 2 + sizeof(SIStatus));
-  res.resize(
-    rdpSize +
-    sizeof(RSP) +
-    sizeof(MI) +
-    sizeof(VI) +
-    sizeof(SI) +
-    sizeof(PI) +
-    sizeof(RI) +
-    sizeof(AI) +
-    sizeof(u32)*2 +
-    sizeof(SIStatus));
 
   u32 index = 0;
   memcpy(res.data(), &rsp, sizeof(RSP));
@@ -118,4 +131,4 @@ void MMIO::Deserialize(const std::vector<u8> &data) {
   index += sizeof(u32);
   memcpy(&si.status, data.data() + index, sizeof(SIStatus));
 }
-}
+} // namespace n64

src/backend/core/Mem.cpp

@@ -1,14 +1,14 @@
-#include <Mem.hpp>
-#include <core/registers/Registers.hpp>
-#include <core/registers/Cop0.hpp>
-#include <core/Interpreter.hpp>
-#include <backend/RomHelpers.hpp>
 #include <File.hpp>
-#include <unarr.h>
+#include <Mem.hpp>
+#include <backend/RomHelpers.hpp>
 #include <cassert>
+#include <core/Interpreter.hpp>
+#include <core/registers/Cop0.hpp>
+#include <core/registers/Registers.hpp>
+#include <unarr.h>
 
 namespace n64 {
-Mem::Mem(Registers& regs, ParallelRDP& parallel) : flash(saveData), mmio(*this, regs, parallel) {
+Mem::Mem(Registers &regs, ParallelRDP &parallel) : flash(saveData), mmio(*this, regs, parallel) {
   rom.cart.resize(CART_SIZE);
   std::fill(rom.cart.begin(), rom.cart.end(), 0);
 }
@@ -19,27 +19,31 @@ void Mem::Reset() {
   if (saveData.is_mapped()) {
     std::error_code error;
     saveData.sync(error);
-    if (error) { Util::panic("Could not sync save data"); }
+    if (error) {
+      Util::panic("Could not sync save data");
+    }
     saveData.unmap();
   }
   mmio.Reset();
 }
 
 void Mem::LoadSRAM(SaveType save_type, fs::path path) {
-  if(save_type == SAVE_SRAM_256k) {
+  if (save_type == SAVE_SRAM_256k) {
     std::error_code error;
     if (!savePath.empty()) {
       path = savePath / path.filename();
     }
     sramPath = path.replace_extension(".sram").string();
-    if(saveData.is_mapped()) {
+    if (saveData.is_mapped()) {
       saveData.sync(error);
-      if(error) { Util::panic("Could not sync {}", sramPath); }
+      if (error) {
+        Util::panic("Could not sync {}", sramPath);
+      }
       saveData.unmap();
     }
 
     auto sramVec = Util::ReadFileBinary(sramPath);
-    if(sramVec.empty()) {
+    if (sramVec.empty()) {
       Util::WriteFileBinary(std::array<u8, SRAM_SIZE>{}, sramPath);
       sramVec = Util::ReadFileBinary(sramPath);
     }
@@ -48,20 +52,33 @@ void Mem::LoadSRAM(SaveType save_type, fs::path path) {
       Util::panic("Corrupt SRAM!");
     }
 
-    saveData = mio::make_mmap_sink(
+    saveData = mio::make_mmap_sink(sramPath, 0, mio::map_entire_file, error);
-      sramPath, 0, mio::map_entire_file, error);
+    if (error) {
-    if (error) { Util::panic("Could not mmap {}", sramPath); }
+      Util::panic("Could not mmap {}", sramPath);
+    }
   }
 }
 
-FORCE_INLINE void SetROMCIC(u32 checksum, ROM& rom) {
+FORCE_INLINE void SetROMCIC(u32 checksum, ROM &rom) {
   switch (checksum) {
-    case 0xEC8B1325: rom.cicType = CIC_NUS_7102; break; // 7102
+  case 0xEC8B1325:
-    case 0x1DEB51A9: rom.cicType = CIC_NUS_6101; break; // 6101
+    rom.cicType = CIC_NUS_7102;
-    case 0xC08E5BD6: rom.cicType = CIC_NUS_6102_7101; break;
+    break; // 7102
-    case 0x03B8376A: rom.cicType = CIC_NUS_6103_7103; break;
+  case 0x1DEB51A9:
-    case 0xCF7F41DC: rom.cicType = CIC_NUS_6105_7105; break;
+    rom.cicType = CIC_NUS_6101;
-    case 0xD1059C6A: rom.cicType = CIC_NUS_6106_7106; break;
+    break; // 6101
+  case 0xC08E5BD6:
+    rom.cicType = CIC_NUS_6102_7101;
+    break;
+  case 0x03B8376A:
+    rom.cicType = CIC_NUS_6103_7103;
+    break;
+  case 0xCF7F41DC:
+    rom.cicType = CIC_NUS_6105_7105;
+    break;
+  case 0xD1059C6A:
+    rom.cicType = CIC_NUS_6106_7106;
+    break;
   default:
     Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum);
     rom.cicType = UNKNOWN_CIC_TYPE;
@@ -69,35 +86,36 @@ FORCE_INLINE void SetROMCIC(u32 checksum, ROM& rom) {
   }
 }
 
-std::vector<u8> Mem::OpenArchive(const std::string &path, size_t& sizeAdjusted) {
+std::vector<u8> Mem::OpenArchive(const std::string &path, size_t &sizeAdjusted) {
   auto stream = ar_open_file(fs::path(path).u8string().c_str());
 
-  if(!stream) {
+  if (!stream) {
     Util::panic("Could not open archive! Are you sure it's an archive?");
   }
 
-  ar_archive* archive = ar_open_zip_archive(stream, false);
+  ar_archive *archive = ar_open_zip_archive(stream, false);
 
-  if(!archive) archive = ar_open_rar_archive(stream);
+  if (!archive)
-  if(!archive) archive = ar_open_7z_archive(stream);
+    archive = ar_open_rar_archive(stream);
-  if(!archive) archive = ar_open_tar_archive(stream);
+  if (!archive)
+    archive = ar_open_7z_archive(stream);
+  if (!archive)
+    archive = ar_open_tar_archive(stream);
 
-  if(!archive) {
+  if (!archive) {
     ar_close(stream);
     Util::panic("Could not open archive! Are you sure it's a supported archive? (7z, zip, rar and tar are supported)");
   }
 
   std::vector<u8> buf{};
 
-  std::vector<std::string> rom_exts{".n64",".z64",".v64",".N64",".Z64",".V64"};
+  std::vector<std::string> rom_exts{".n64", ".z64", ".v64", ".N64", ".Z64", ".V64"};
 
-  while(ar_parse_entry(archive)) {
+  while (ar_parse_entry(archive)) {
     auto filename = ar_entry_get_name(archive);
     auto extension = fs::path(filename).extension();
 
-    if(std::any_of(rom_exts.begin(), rom_exts.end(), [&](auto x) {
+    if (std::any_of(rom_exts.begin(), rom_exts.end(), [&](auto x) { return extension == x; })) {
-      return extension == x;
-    })) {
       auto size = ar_entry_get_size(archive);
       sizeAdjusted = Util::NextPow2(size);
       buf.resize(sizeAdjusted);
@@ -115,13 +133,13 @@ std::vector<u8> Mem::OpenArchive(const std::string &path, size_t& sizeAdjusted)
   return buf;
 }
 
-std::vector<u8> Mem::OpenROM(const std::string& filename, size_t& sizeAdjusted) {
+std::vector<u8> Mem::OpenROM(const std::string &filename, size_t &sizeAdjusted) {
   auto buf = Util::ReadFileBinary(filename);
   sizeAdjusted = Util::NextPow2(buf.size());
   return buf;
 }
 
-void Mem::LoadROM(bool isArchive, const std::string& filename) {
+void Mem::LoadROM(bool isArchive, const std::string &filename) {
   size_t sizeAdjusted;
   u32 endianness;
   {
@@ -132,7 +150,7 @@ void Mem::LoadROM(bool isArchive, const std::string& filename) {
       buf = OpenROM(filename, sizeAdjusted);
     }
 
-    endianness = be32toh(*reinterpret_cast<u32*>(buf.data()));
+    endianness = be32toh(*reinterpret_cast<u32 *>(buf.data()));
     Util::SwapN64Rom<true>(buf, endianness);
 
     std::copy(buf.begin(), buf.end(), rom.cart.begin());
@@ -162,19 +180,21 @@ void Mem::LoadROM(bool isArchive, const std::string& filename) {
 
   u32 checksum = Util::crc32(0, &rom.cart[0x40], 0x9c0);
   SetROMCIC(checksum, rom);
-  endianness = be32toh(*reinterpret_cast<u32*>(rom.cart.data()));
+  endianness = be32toh(*reinterpret_cast<u32 *>(rom.cart.data()));
   Util::SwapN64Rom(rom.cart, endianness);
   rom.pal = IsROMPAL();
 }
 
-template<> u8 Mem::Read(n64::Registers &regs, u32 paddr) {
+template <>
-  SI& si = mmio.si;
+u8 Mem::Read(n64::Registers &regs, u32 paddr) {
+  SI &si = mmio.si;
 
   switch (paddr) {
   case RDRAM_REGION:
     return mmio.rdp.ReadRDRAM<u8>(paddr);
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
-      auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+    {
+      auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       return src[BYTE_ADDRESS(paddr & 0xfff)];
     }
   case REGION_CART:
@@ -184,7 +204,8 @@ template<> u8 Mem::Read(n64::Registers &regs, u32 paddr) {
   case 0x04600000 ... 0x048FFFFF:
   case 0x04300000 ... 0x044FFFFF:
     Util::panic("MMIO Read<u8>!\n");
-    case AI_REGION: {
+  case AI_REGION:
+    {
       u32 w = mmio.ai.Read(paddr & ~3);
       int offs = 3 - (paddr & 3);
       return (w >> (offs * 8)) & 0xff;
@@ -199,18 +220,20 @@ template<> u8 Mem::Read(n64::Registers &regs, u32 paddr) {
   case 0x1FC00800 ... 0xFFFFFFFF: // unused
     return 0;
   default:
-      Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
+    Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
   }
 }
 
-template<> u16 Mem::Read(n64::Registers &regs, u32 paddr) {
+template <>
-  SI& si = mmio.si;
+u16 Mem::Read(n64::Registers &regs, u32 paddr) {
+  SI &si = mmio.si;
 
   switch (paddr) {
   case RDRAM_REGION:
     return mmio.rdp.ReadRDRAM<u16>(paddr);
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
-      auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+    {
+      auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       return Util::ReadAccess<u16>(src, HALF_ADDRESS(paddr & 0xfff));
     }
   case MMIO_REGION:
@@ -227,18 +250,20 @@ template<> u16 Mem::Read(n64::Registers &regs, u32 paddr) {
   case 0x1FC00800 ... 0xFFFFFFFF:
     return 0;
   default:
-      Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
+    Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
   }
 }
 
-template<> u32 Mem::Read(n64::Registers &regs, u32 paddr) {
+template <>
-  SI& si = mmio.si;
+u32 Mem::Read(n64::Registers &regs, u32 paddr) {
+  SI &si = mmio.si;
 
-  switch(paddr) {
+  switch (paddr) {
   case RDRAM_REGION:
     return mmio.rdp.ReadRDRAM<u32>(paddr);
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
-      auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+    {
+      auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       return Util::ReadAccess<u32>(src, paddr & 0xfff);
     }
   case MMIO_REGION:
@@ -249,21 +274,26 @@ template<> u32 Mem::Read(n64::Registers &regs, u32 paddr) {
     return Util::ReadAccess<u32>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
   case PIF_RAM_REGION:
     return be32toh(Util::ReadAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START));
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+  case 0x00800000 ... 0x03FFFFFF:
-    case 0x04900000 ... 0x04FFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
+  case 0x04200000 ... 0x042FFFFF:
+  case 0x04900000 ... 0x04FFFFFF:
+  case 0x1FC00800 ... 0xFFFFFFFF:
+    return 0;
   default:
-      Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
+    Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
   }
 }
 
-template<> u64 Mem::Read(n64::Registers &regs, u32 paddr) {
+template <>
-  SI& si = mmio.si;
+u64 Mem::Read(n64::Registers &regs, u32 paddr) {
+  SI &si = mmio.si;
 
   switch (paddr) {
   case RDRAM_REGION:
     return mmio.rdp.ReadRDRAM<u64>(paddr);
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
-      auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+    {
+      auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       return Util::ReadAccess<u64>(src, paddr & 0xfff);
     }
   case MMIO_REGION:
@@ -280,23 +310,26 @@ template<> u64 Mem::Read(n64::Registers &regs, u32 paddr) {
   case 0x1FC00800 ... 0xFFFFFFFF:
     return 0;
   default:
-      Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
+    Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
   }
 }
 
-template<> void Mem::Write<u8>(Registers& regs, u32 paddr, u32 val) {
+template <>
-  SI& si = mmio.si;
+void Mem::Write<u8>(Registers &regs, u32 paddr, u32 val) {
+  SI &si = mmio.si;
 
   switch (paddr) {
   case RDRAM_REGION:
     mmio.rdp.WriteRDRAM<u8>(paddr, val);
     break;
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
+    {
       val = val << (8 * (3 - (paddr & 3)));
-      auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+      auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       paddr = (paddr & 0xFFF) & ~3;
       Util::WriteAccess<u32>(dest, paddr, val);
-    } break;
+    }
+    break;
   case REGION_CART:
     Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
     mmio.pi.BusWrite<u8, false>(paddr, val);
@@ -318,23 +351,26 @@ template<> void Mem::Write<u8>(Registers& regs, u32 paddr, u32 val) {
     break;
   default:
     Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
-                  (u64) regs.pc);
+                (u64)regs.pc);
   }
 }
 
-template<> void Mem::Write<u16>(Registers& regs, u32 paddr, u32 val) {
+template <>
-  SI& si = mmio.si;
+void Mem::Write<u16>(Registers &regs, u32 paddr, u32 val) {
+  SI &si = mmio.si;
 
   switch (paddr) {
   case RDRAM_REGION:
     mmio.rdp.WriteRDRAM<u16>(paddr, val);
     break;
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
+    {
       val = val << (16 * !(paddr & 2));
-      auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+      auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       paddr = (paddr & 0xFFF) & ~3;
       Util::WriteAccess<u32>(dest, paddr, val);
-    } break;
+    }
+    break;
   case REGION_CART:
     Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
     mmio.pi.BusWrite<u16, false>(paddr, val);
@@ -356,21 +392,24 @@ template<> void Mem::Write<u16>(Registers& regs, u32 paddr, u32 val) {
     break;
   default:
     Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
-                  (u64) regs.pc);
+                (u64)regs.pc);
   }
 }
 
-template<> void Mem::Write<u32>(Registers& regs, u32 paddr, u32 val) {
+template <>
-  SI& si = mmio.si;
+void Mem::Write<u32>(Registers &regs, u32 paddr, u32 val) {
+  SI &si = mmio.si;
 
-  switch(paddr) {
+  switch (paddr) {
   case RDRAM_REGION:
     mmio.rdp.WriteRDRAM<u32>(paddr, val);
     break;
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
-      auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+    {
+      auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
-    } break;
+    }
+    break;
   case REGION_CART:
     Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
     mmio.pi.BusWrite<u32, false>(paddr, val);
@@ -387,23 +426,28 @@ template<> void Mem::Write<u32>(Registers& regs, u32 paddr, u32 val) {
   case 0x04900000 ... 0x04FFFFFF:
   case PIF_ROM_REGION:
   case 0x1FC00800 ... 0x7FFFFFFF:
-    case 0x80000000 ... 0xFFFFFFFF: break;
+  case 0x80000000 ... 0xFFFFFFFF:
-    default: Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val, (u64)regs.pc);
+    break;
+  default:
+    Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
+                (u64)regs.pc);
   }
 }
 
-void Mem::Write(Registers& regs, u32 paddr, u64 val) {
+void Mem::Write(Registers &regs, u32 paddr, u64 val) {
-  SI& si = mmio.si;
+  SI &si = mmio.si;
 
   switch (paddr) {
   case RDRAM_REGION:
     mmio.rdp.WriteRDRAM<u64>(paddr, val);
     break;
-    case RSP_MEM_REGION: {
+  case RSP_MEM_REGION:
-      auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
+    {
+      auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
       val >>= 32;
       Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
-    } break;
+    }
+    break;
   case REGION_CART:
     Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
     mmio.pi.BusWrite<false>(paddr, val);
@@ -419,17 +463,21 @@ void Mem::Write(Registers& regs, u32 paddr, u64 val) {
   case 0x04900000 ... 0x04FFFFFF:
   case 0x1FC00000 ... 0x1FC007BF:
   case 0x1FC00800 ... 0x7FFFFFFF:
-    case 0x80000000 ... 0xFFFFFFFF: break;
+  case 0x80000000 ... 0xFFFFFFFF:
+    break;
   default:
     Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
-                  (u64) regs.pc);
+                (u64)regs.pc);
   }
 }
 
-template <> u32 Mem::BackupRead<u32>(u32 addr) {
+template <>
-  switch(saveType) {
+u32 Mem::BackupRead<u32>(u32 addr) {
-    case SAVE_NONE: return 0;
+  switch (saveType) {
-    case SAVE_EEPROM_4k: case SAVE_EEPROM_16k:
+  case SAVE_NONE:
+    return 0;
+  case SAVE_EEPROM_4k:
+  case SAVE_EEPROM_16k:
     Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
     return 0;
   case SAVE_FLASH_1m:
@@ -441,10 +489,13 @@ template <> u32 Mem::BackupRead<u32>(u32 addr) {
   }
 }
 
-template <> u8 Mem::BackupRead<u8>(u32 addr) {
+template <>
+u8 Mem::BackupRead<u8>(u32 addr) {
   switch (saveType) {
-  case SAVE_NONE: return 0;
+  case SAVE_NONE:
-  case SAVE_EEPROM_4k: case SAVE_EEPROM_16k:
+    return 0;
+  case SAVE_EEPROM_4k:
+  case SAVE_EEPROM_16k:
     Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
     return 0;
   case SAVE_FLASH_1m:
@@ -453,8 +504,7 @@ template <> u8 Mem::BackupRead<u8>(u32 addr) {
     if (saveData.is_mapped()) {
       assert(addr < saveData.size());
       return saveData[addr];
-    }
+    } else {
-    else {
       Util::panic("Invalid backup Read<u8> if save data is not initialized");
     }
   default:
@@ -462,12 +512,14 @@ template <> u8 Mem::BackupRead<u8>(u32 addr) {
   }
 }
 
-template <> void Mem::BackupWrite<u32>(u32 addr, u32 val) {
+template <>
-  switch(saveType) {
+void Mem::BackupWrite<u32>(u32 addr, u32 val) {
+  switch (saveType) {
   case SAVE_NONE:
     Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
     break;
-    case SAVE_EEPROM_4k: case SAVE_EEPROM_16k:
+  case SAVE_EEPROM_4k:
+  case SAVE_EEPROM_16k:
     Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
   case SAVE_FLASH_1m:
     flash.Write<u32>(addr, val);
@@ -479,18 +531,20 @@ template <> void Mem::BackupWrite<u32>(u32 addr, u32 val) {
   }
 }
 
-template <> void Mem::BackupWrite<u8>(u32 addr, u8 val) {
+template <>
-  switch(saveType) {
+void Mem::BackupWrite<u8>(u32 addr, u8 val) {
+  switch (saveType) {
   case SAVE_NONE:
     Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
     break;
-    case SAVE_EEPROM_4k: case SAVE_EEPROM_16k:
+  case SAVE_EEPROM_4k:
+  case SAVE_EEPROM_16k:
     Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
   case SAVE_FLASH_1m:
     flash.Write<u8>(addr, val);
     break;
   case SAVE_SRAM_256k:
-      if(saveData.is_mapped()) {
+    if (saveData.is_mapped()) {
       assert(addr < saveData.size());
       saveData[addr] = val;
     } else {
@@ -517,9 +571,9 @@ std::vector<u8> Mem::Serialize() {
   return res;
 }
 
-void Mem::Deserialize(const std::vector<u8>& data) {
+void Mem::Deserialize(const std::vector<u8> &data) {
   mmio.Deserialize(std::vector<u8>(data.begin(), data.begin() + mmioSize));
   flash.Deserialize(std::vector<u8>(data.begin() + mmioSize, data.begin() + mmioSize + flashSize));
   memcpy(saveData.data(), data.data() + mmioSize + flashSize, saveData.size());
 }
-}
+} // namespace n64

src/backend/core/Mem.hpp

@@ -1,13 +1,13 @@
 #pragma once
-#include <common.hpp>
+#include <File.hpp>
-#include <backend/MemoryRegions.hpp>
+#include <GameDB.hpp>
-#include <backend/core/MMIO.hpp>
-#include <vector>
-#include <log.hpp>
 #include <Registers.hpp>
 #include <algorithm>
-#include <GameDB.hpp>
+#include <backend/MemoryRegions.hpp>
-#include <File.hpp>
+#include <backend/core/MMIO.hpp>
+#include <common.hpp>
+#include <log.hpp>
+#include <vector>
 
 namespace n64 {
 struct ROMHeader {
@@ -37,22 +37,20 @@ struct ROM {
   bool pal;
 };
 
-enum class FlashState : u8 {
+enum class FlashState : u8 { Idle, Erase, Write, Read, Status };
-  Idle, Erase, Write, Read, Status
-};
 
 struct Flash {
-  explicit Flash(mio::mmap_sink&);
+  explicit Flash(mio::mmap_sink &);
   ~Flash() = default;
   void Reset();
-  void Load(SaveType, const std::string&);
+  void Load(SaveType, const std::string &);
   FlashState state{};
   u64 status{};
   size_t eraseOffs{};
   size_t writeOffs{};
   std::array<u8, 128> writeBuf{};
   std::string flashPath{};
-  mio::mmap_sink& saveData;
+  mio::mmap_sink &saveData;
 
   enum FlashCommands : u8 {
     FLASH_COMMAND_EXECUTE = 0xD2,
@@ -72,7 +70,7 @@ struct Flash {
   void CommandWrite();
   void CommandRead();
   std::vector<u8> Serialize();
-  void Deserialize(const std::vector<u8>& data);
+  void Deserialize(const std::vector<u8> &data);
   template <typename T>
   void Write(u32 index, T val);
   template <typename T>
@@ -81,28 +79,24 @@ struct Flash {
 
 struct Mem {
   ~Mem() = default;
-  Mem(Registers&, ParallelRDP&);
+  Mem(Registers &, ParallelRDP &);
   void Reset();
   void LoadSRAM(SaveType, fs::path);
-  static std::vector<u8> OpenROM(const std::string&, size_t&);
+  static std::vector<u8> OpenROM(const std::string &, size_t &);
-  static std::vector<u8> OpenArchive(const std::string&, size_t&);
+  static std::vector<u8> OpenArchive(const std::string &, size_t &);
-  void LoadROM(bool, const std::string&);
+  void LoadROM(bool, const std::string &);
-  [[nodiscard]] auto GetRDRAMPtr() -> u8* {
+  [[nodiscard]] auto GetRDRAMPtr() -> u8 * { return mmio.rdp.rdram.data(); }
-    return mmio.rdp.rdram.data();
-  }
 
-  [[nodiscard]] auto GetRDRAM() -> std::vector<u8>& {
+  [[nodiscard]] auto GetRDRAM() -> std::vector<u8> & { return mmio.rdp.rdram; }
-    return mmio.rdp.rdram;
-  }
 
   std::vector<u8> Serialize();
-  void Deserialize(const std::vector<u8>&);
+  void Deserialize(const std::vector<u8> &);
 
   template <typename T>
-  T Read(Registers&, u32);
+  T Read(Registers &, u32);
   template <typename T>
-  void Write(Registers&, u32, u32);
+  void Write(Registers &, u32, u32);
-  void Write(Registers&, u32, u64);
+  void Write(Registers &, u32, u64);
 
   template <typename T>
   T BackupRead(u32);
@@ -135,6 +129,7 @@ struct Mem {
   ROM rom;
   SaveType saveType = SAVE_NONE;
   Flash flash;
+
 private:
   friend struct SI;
   friend struct PI;
@@ -148,9 +143,7 @@ private:
 
   FORCE_INLINE bool IsROMPAL() {
     static const char pal_codes[] = {'D', 'F', 'I', 'P', 'S', 'U', 'X', 'Y'};
-    return std::any_of(std::begin(pal_codes), std::end(pal_codes), [this](char a) {
+    return std::any_of(std::begin(pal_codes), std::end(pal_codes), [this](char a) { return rom.cart[0x3d] == a; });
-      return rom.cart[0x3d] == a;
-    });
   }
 };
-}
+} // namespace n64

src/backend/core/jit/instructions.cpp

@@ -3,108 +3,85 @@
 #define check_signed_overflow(op1, op2, res) (((~((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
 #define check_signed_underflow(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
 
-namespace n64 {
+namespace n64
-void JIT::lui(u32 instr) {
+{
+  void JIT::lui(u32 instr) {
     u64 val = s64((s16)instr);
     val <<= 16;
-  if (RT(instr) != 0) [[likely]] {
     regs.Write(RT(instr), val);
-    regs.gprIsConstant[RT(instr)] = true;
   }
-}
 
-void JIT::add(u32 instr) {
+  void JIT::add(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       u32 rs = regs.Read<s32>(RS(instr));
       u32 rt = regs.Read<s32>(RT(instr));
       u32 result = rs + rt;
-    if(check_signed_overflow(rs, rt, result)) {
+      if (check_signed_overflow(rs, rt, result)) {
         //regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
         Util::panic("[JIT]: Unhandled Overflow exception in ADD!");
       }
-
-    if (RD(instr) != 0) [[likely]] {
       regs.Write(RD(instr), s32(result));
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant ADD");
     }
-}
+  }
 
-void JIT::addu(u32 instr) {
+  void JIT::addu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       s32 rs = regs.Read<s32>(RS(instr));
       s32 rt = regs.Read<s32>(RT(instr));
       s32 result = rs + rt;
-
-    if (RD(instr) != 0) [[likely]] {
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant ADDI");
     }
-}
+  }
 
-void JIT::addi(u32 instr) {
+  void JIT::addi(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
+    if (regs.IsRegConstant(RS(instr))) {
       auto rs = regs.Read<u32>(RS(instr));
       u32 imm = s32(s16(instr));
       u32 result = rs + imm;
-    if(check_signed_overflow(rs, imm, result)) {
+      if (check_signed_overflow(rs, imm, result)) {
         Util::panic("[JIT]: Unhandled Overflow exception in ADDI!");
       } else {
-      if (RT(instr) != 0) [[likely]] {
         regs.Write(RT(instr), s32(result));
-        regs.gprIsConstant[RT(instr)] = true;
-      }
       }
     } else {
       Util::panic("[JIT]: Implement non constant ADDI!");
     }
-}
+  }
 
-void JIT::addiu(u32 instr) {
+  void JIT::addiu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
+    if (regs.IsRegConstant(RS(instr))) {
       auto rs = regs.Read<u32>(RS(instr));
       u32 imm = s32(s16(instr));
       u32 result = rs + imm;
-
-    if (RT(instr) != 0) [[likely]] {
       regs.Write(RT(instr), s32(result));
-      regs.gprIsConstant[RT(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant ADDIU!");
     }
-}
-
-void JIT::andi(u32 instr) {
-  s64 imm = (u16)instr;
-  if(regs.IsRegConstant(RS(instr))) {
-    if (RT(instr) != 0) [[likely]] {
-      regs.Write(RT(instr), regs.Read<s64>(RS(instr)) & imm);
-      regs.gprIsConstant[RT(instr)] = true;
   }
+
+  void JIT::andi(u32 instr) {
+    s64 imm = (u16)instr;
+    if (regs.IsRegConstant(RS(instr))) {
+      regs.Write(RT(instr), regs.Read<s64>(RS(instr)) & imm);
     } else {
       Util::panic("[JIT]: Implement non constant ANDI!");
     }
-}
-
-void JIT::and_(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
-      regs.Write(RD(instr), regs.Read<s64>(RS(instr)) & regs.Read<s64>(RT(instr)));
-      regs.gprIsConstant[RD(instr)] = true;
   }
+
+  void JIT::and_(u32 instr) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
+      regs.Write(RD(instr), regs.Read<s64>(RS(instr)) & regs.Read<s64>(RT(instr)));
     } else {
       Util::panic("[JIT]: Implement non constant AND!");
     }
-}
+  }
 
-void JIT::dadd(u32 instr) {
+  void JIT::dadd(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       auto rs = regs.Read<u64>(RS(instr));
       auto rt = regs.Read<u64>(RT(instr));
       u64 result = rt + rs;
@@ -112,31 +89,24 @@ void JIT::dadd(u32 instr) {
         //regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
         Util::panic("[JIT]: Unhandled Overflow exception in DADD!");
       }
-
-    if (RD(instr) != 0) [[likely]] {
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DADD!");
     }
-}
+  }
 
-void JIT::daddu(u32 instr) {
+  void JIT::daddu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto rs = regs.Read<s64>(RS(instr));
       auto rt = regs.Read<s64>(RT(instr));
       regs.Write(RD(instr), rt + rs);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DADD!");
     }
-}
+  }
 
-void JIT::daddi(u32 instr) {
+  void JIT::daddi(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
+    if (regs.IsRegConstant(RS(instr))) {
       u64 imm = s64(s16(instr));
       auto rs = regs.Read<u64>(RS(instr));
       u64 result = imm + rs;
@@ -144,39 +114,32 @@ void JIT::daddi(u32 instr) {
         //regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
         Util::panic("[JIT]: Unhandled Overflow exception in DADDI!");
       }
-
-    if (RT(instr) != 0) [[likely]] {
       regs.Write(RT(instr), result);
-      regs.gprIsConstant[RT(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DADDI!");
     }
-}
+  }
 
-void JIT::daddiu(u32 instr) {
+  void JIT::daddiu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
+    if (regs.IsRegConstant(RS(instr))) {
-    if (RT(instr) != 0) [[likely]] {
       s16 imm = s16(instr);
       auto rs = regs.Read<s64>(RS(instr));
       regs.Write(RT(instr), imm + rs);
-      regs.gprIsConstant[RT(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DADDI!");
     }
-}
+  }
 
-void JIT::ddiv(u32 instr) {
+  void JIT::ddiv(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       auto dividend = regs.Read<s64>(RS(instr));
       auto divisor = regs.Read<s64>(RT(instr));
       if (dividend == 0x8000000000000000 && divisor == 0xFFFFFFFFFFFFFFFF) {
         regs.lo = dividend;
         regs.hi = 0;
-    } else if(divisor == 0) {
+      } else if (divisor == 0) {
         regs.hi = dividend;
-      if(dividend >= 0) {
+        if (dividend >= 0) {
           regs.lo = -1;
         } else {
           regs.lo = 1;
@@ -193,20 +156,20 @@ void JIT::ddiv(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant DDIV!");
     }
-}
+  }
 
-void JIT::ddivu(u32 instr) {
+  void JIT::ddivu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       auto dividend = regs.Read<u64>(RS(instr));
       auto divisor = regs.Read<u64>(RT(instr));
       if (divisor == 0) {
         regs.lo = -1;
-      regs.hi = (s64) dividend;
+        regs.hi = (s64)dividend;
       } else {
         u64 quotient = dividend / divisor;
         u64 remainder = dividend % divisor;
-      regs.lo = (s64) quotient;
+        regs.lo = (s64)quotient;
-      regs.hi = (s64) remainder;
+        regs.hi = (s64)remainder;
       }
 
       regs.loIsConstant = true;
@@ -214,10 +177,10 @@ void JIT::ddivu(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant DDIVU!");
     }
-}
+  }
 
-void JIT::div(u32 instr) {
+  void JIT::div(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       s64 dividend = regs.Read<s32>(RS(instr));
       s64 divisor = regs.Read<s32>(RT(instr));
 
@@ -240,18 +203,18 @@ void JIT::div(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant DIV!");
     }
-}
+  }
 
-void JIT::divu(u32 instr) {
+  void JIT::divu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
       auto dividend = regs.Read<u32>(RS(instr));
       auto divisor = regs.Read<u32>(RT(instr));
       if (divisor == 0) {
         regs.lo = -1;
-      regs.hi = (s32) dividend;
+        regs.hi = (s32)dividend;
       } else {
-      s32 quotient = (s32) (dividend / divisor);
+        s32 quotient = (s32)(dividend / divisor);
-      s32 remainder = (s32) (dividend % divisor);
+        s32 remainder = (s32)(dividend % divisor);
         regs.lo = quotient;
         regs.hi = remainder;
       }
@@ -261,10 +224,10 @@ void JIT::divu(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant DIVU!");
     }
-}
+  }
 
-void JIT::dmult(u32 instr) {
+  void JIT::dmult(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
       auto rt = regs.Read<s64>(RT(instr));
       auto rs = regs.Read<s64>(RS(instr));
       s128 result = (s128)rt * (s128)rs;
@@ -275,10 +238,10 @@ void JIT::dmult(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant DMULT!");
     }
-}
+  }
 
-void JIT::dmultu(u32 instr) {
+  void JIT::dmultu(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
       auto rt = regs.Read<u64>(RT(instr));
       auto rs = regs.Read<u64>(RS(instr));
       u128 result = (u128)rt * (u128)rs;
@@ -289,134 +252,107 @@ void JIT::dmultu(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant DMULT!");
     }
-}
+  }
 
-void JIT::dsll(u32 instr) {
+  void JIT::dsll(u32 instr) {
-  if(regs.IsRegConstant(RT(instr))) {
+    if (regs.IsRegConstant(RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       u8 sa = ((instr >> 6) & 0x1f);
       auto result = regs.Read<s64>(RT(instr)) << sa;
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSLL!");
     }
-}
+  }
 
-void JIT::dsllv(u32 instr) {
+  void JIT::dsllv(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto sa = regs.Read<s64>(RS(instr)) & 63;
       auto result = regs.Read<s64>(RT(instr)) << sa;
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSLLV!");
     }
-}
+  }
 
-void JIT::dsll32(u32 instr) {
+  void JIT::dsll32(u32 instr) {
-  if(regs.IsRegConstant(RT(instr))) {
+    if (regs.IsRegConstant(RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       u8 sa = ((instr >> 6) & 0x1f);
       auto result = regs.Read<s64>(RT(instr)) << (sa + 32);
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSLL32!");
     }
-}
+  }
 
-void JIT::dsra(u32 instr) {
+  void JIT::dsra(u32 instr) {
-  if(regs.IsRegConstant(RT(instr))) {
+    if (regs.IsRegConstant(RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto rt = regs.Read<s64>(RT(instr));
       u8 sa = ((instr >> 6) & 0x1f);
       s64 result = rt >> sa;
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSRA!");
     }
-}
+  }
 
-void JIT::dsrav(u32 instr) {
+  void JIT::dsrav(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto rt = regs.Read<s64>(RT(instr));
       auto rs = regs.Read<s64>(RS(instr));
       s64 sa = rs & 63;
       s64 result = rt >> sa;
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSRAV!");
     }
-}
+  }
 
-void JIT::dsra32(u32 instr) {
+  void JIT::dsra32(u32 instr) {
-  if(regs.IsRegConstant(RT(instr))) {
+    if (regs.IsRegConstant(RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto rt = regs.Read<s64>(RT(instr));
       u8 sa = ((instr >> 6) & 0x1f);
       s64 result = rt >> (sa + 32);
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSRA32!");
     }
-}
+  }
 
-void JIT::dsrl(u32 instr) {
+  void JIT::dsrl(u32 instr) {
-  if(regs.IsRegConstant(RT(instr))) {
+    if (regs.IsRegConstant(RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto rt = regs.Read<u64>(RT(instr));
       u8 sa = ((instr >> 6) & 0x1f);
       u64 result = rt >> sa;
       regs.Write(RD(instr), s64(result));
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSRL!");
     }
-}
+  }
 
-void JIT::dsrlv(u32 instr) {
+  void JIT::dsrlv(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       u8 amount = regs.Read<u8>(RS(instr)) & 63;
       auto rt = regs.Read<u64>(RT(instr));
       u64 result = rt >> amount;
       regs.Write(RD(instr), s64(result));
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSRLV!");
     }
-}
+  }
 
-void JIT::dsrl32(u32 instr) {
+  void JIT::dsrl32(u32 instr) {
-  if(regs.IsRegConstant(RT(instr))) {
+    if (regs.IsRegConstant(RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       auto rt = regs.Read<u64>(RT(instr));
       u8 sa = ((instr >> 6) & 0x1f);
       u64 result = rt >> (sa + 32);
       regs.Write(RD(instr), s64(result));
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSRL32!");
     }
-}
+  }
 
-void JIT::dsub(u32 instr) {
+  void JIT::dsub(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
       auto rt = regs.Read<s64>(RT(instr));
       auto rs = regs.Read<s64>(RS(instr));
       s64 result = rs - rt;
@@ -424,65 +360,56 @@ void JIT::dsub(u32 instr) {
         // regs.cop0.FireException(ExceptionCode::Overflow, 0, regs.oldPC);
         Util::panic("[JIT]: Unhandled Overflow exception in DSUB!");
       } else {
-      if (RD(instr) != 0) [[likely]] {
         regs.Write(RD(instr), result);
-        regs.gprIsConstant[RD(instr)] = true;
-      }
       }
     } else {
       Util::panic("[JIT]: Implement non constant DSUB!");
     }
-}
+  }
 
-void JIT::dsubu(u32 instr) {
+  void JIT::dsubu(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
       auto rt = regs.Read<s64>(RT(instr));
       auto rs = regs.Read<s64>(RS(instr));
       s64 result = rs - rt;
-
-    if (RD(instr) != 0) [[likely]] {
       regs.Write(RD(instr), result);
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant DSUBU!");
     }
-}
+  }
 
-void JIT::mfhi(u32 instr) {
+  void JIT::mfhi(u32 instr) {
-  if(regs.hiIsConstant) {
+    if (regs.hiIsConstant) {
       regs.Write(RD(instr), regs.hi);
-    regs.gprIsConstant[RD(instr)] = true;
     } else {
       Util::panic("[JIT]: Implement non constant MFHI!");
     }
-}
+  }
 
-void JIT::mflo(u32 instr) {
+  void JIT::mflo(u32 instr) {
-  if(regs.loIsConstant) {
+    if (regs.loIsConstant) {
       regs.Write(RD(instr), regs.lo);
-    regs.gprIsConstant[RD(instr)] = true;
     } else {
       Util::panic("[JIT]: Implement non constant MFLO!");
     }
-}
+  }
 
-void JIT::mult(u32 instr) {
+  void JIT::mult(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
       auto rt = regs.Read<s32>(RT(instr));
       auto rs = regs.Read<s32>(RS(instr));
-    s64 result = (s64) rt * (s64) rs;
+      s64 result = (s64)rt * (s64)rs;
-    regs.lo = (s64) ((s32) result);
+      regs.lo = (s64)((s32)result);
       regs.loIsConstant = true;
-    regs.hi = (s64) ((s32) (result >> 32));
+      regs.hi = (s64)((s32)(result >> 32));
       regs.hiIsConstant = true;
     } else {
       Util::panic("[JIT]: Implement non constant MULT!");
     }
-}
+  }
 
-void JIT::multu(u32 instr) {
+  void JIT::multu(u32 instr) {
-  if(regs.IsRegConstant(RT(instr), RS(instr))) {
+    if (regs.IsRegConstant(RT(instr), RS(instr))) {
       auto rt = regs.Read<u32>(RT(instr));
       auto rs = regs.Read<u32>(RS(instr));
       u64 result = (u64)rt * (u64)rs;
@@ -493,128 +420,124 @@ void JIT::multu(u32 instr) {
     } else {
       Util::panic("[JIT]: Implement non constant MULTU!");
     }
-}
+  }
 
-void JIT::mthi(u32 instr) {
+  void JIT::mthi(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
+    if (regs.IsRegConstant(RS(instr))) {
       regs.hi = regs.Read<s64>(RS(instr));
       regs.hiIsConstant = true;
     } else {
       Util::panic("[JIT]: Implement non constant MTHI!");
     }
-}
+  }
 
-void JIT::mtlo(u32 instr) {
+  void JIT::mtlo(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
+    if (regs.IsRegConstant(RS(instr))) {
       regs.lo = regs.Read<s64>(RS(instr));
       regs.loIsConstant = true;
     } else {
       Util::panic("[JIT]: Implement non constant MTLO!");
     }
-}
-
-void JIT::nor(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
-      regs.Write(RD(instr), ~(regs.Read<s64>(RS(instr)) | regs.Read<s64>(RT(instr))));
-      regs.gprIsConstant[RD(instr)] = true;
   }
+
+  void JIT::nor(u32 instr) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
+      regs.Write(RD(instr), ~(regs.Read<s64>(RS(instr)) | regs.Read<s64>(RT(instr))));
     } else {
       Util::panic("[JIT]: Implement non constant NOR!");
     }
-}
-
-void JIT::slti(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
-    s16 imm = instr;
-    if (RT(instr) != 0) [[likely]] {
-      regs.Write(RT(instr), regs.Read<s64>(RS(instr)) < imm);
-      regs.gprIsConstant[RT(instr)] = true;
   }
+
+  void JIT::slti(u32 instr) {
+    if (regs.IsRegConstant(RS(instr))) {
+      s16 imm = instr;
+      regs.Write(RT(instr), regs.Read<s64>(RS(instr)) < imm);
     } else {
       Util::panic("[JIT]: Implement non constant SLTI!");
     }
-}
-
-void JIT::sltiu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr))) {
-    s16 imm = instr;
-    if (RT(instr) != 0) [[likely]] {
-      regs.Write(RT(instr), regs.Read<u64>(RS(instr)) < imm);
-      regs.gprIsConstant[RT(instr)] = true;
   }
+
+  void JIT::sltiu(u32 instr) {
+    if (regs.IsRegConstant(RS(instr))) {
+      s16 imm = instr;
+      regs.Write(RT(instr), regs.Read<u64>(RS(instr)) < imm);
     } else {
       Util::panic("[JIT]: Implement non constant SLTIU!");
     }
-}
+  }
 
-void JIT::slt(u32 instr) {
+  void JIT::slt(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       regs.Write(RD(instr), regs.Read<s64>(RS(instr)) < regs.Read<s64>(RT(instr)));
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant SLT!");
     }
-}
+  }
 
-void JIT::sltu(u32 instr) {
+  void JIT::sltu(u32 instr) {
-  if(regs.IsRegConstant(RS(instr), RT(instr))) {
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
-    if (RD(instr) != 0) [[likely]] {
       regs.Write(RD(instr), regs.Read<u64>(RS(instr)) < regs.Read<u64>(RT(instr)));
-      regs.gprIsConstant[RD(instr)] = true;
-    }
     } else {
       Util::panic("[JIT]: Implement non constant SLT!");
     }
-}
+  }
-
+
-void JIT::sll(u32) {
+  void JIT::sll(u32 instr) {
-
+    if (regs.IsRegConstant(RT(instr))) {
-}
+      u8 sa = ((instr >> 6) & 0x1f);
-
+      s32 result = regs.Read<s64>(RT(instr)) << sa;
-void JIT::sllv(u32) {
+      regs.Write(RD(instr), (s64)result);
-
+    } else {
-}
+      Util::panic("[JIT]: Implement non constant SLL!");
-
+    }
-void JIT::sub(u32) {
+  }
-
+
-}
+  void JIT::sllv(u32 instr) {
-
+    if (regs.IsRegConstant(RS(instr), RT(instr))) {
-void JIT::subu(u32) {
+      u8 sa = (regs.Read<s64>(RS(instr))) & 0x1F;
-
+      u32 rt = regs.Read<s64>(RT(instr));
-}
+      s32 result = rt << sa;
-
+      regs.Write(RD(instr), (s64)result);
-void JIT::sra(u32) {
+    }
-
+  }
-}
+
-
+  void JIT::sub(u32) {
-void JIT::srav(u32) {
+
-
+  }
-}
+
-
+  void JIT::subu(u32) {
-void JIT::srl(u32) {
+
-
+  }
-}
+
-
+  void JIT::sra(u32) {
-void JIT::srlv(u32) {
+
-
+  }
-}
+
-
+  void JIT::srav(u32) {
-void JIT::or_(u32) {
+
-
+  }
-}
+
-
+  void JIT::srl(u32) {
-void JIT::ori(u32) {
+
-
+  }
-}
+
-
+  void JIT::srlv(u32) {
-void JIT::xor_(u32) {
+
-
+  }
-}
+
-
+  void JIT::or_(u32) {
-void JIT::xori(u32) {
+
-
+  }
-}
+
+  void JIT::ori(u32) {
+
+  }
+
+  void JIT::xor_(u32) {
+
+  }
+
+  void JIT::xori(u32) {
+
+  }
 }

src/backend/core/registers/Registers.cpp

@@ -1,16 +1,15 @@
 #include <core/registers/Registers.hpp>
 
 namespace n64 {
-Registers::Registers() : cop0(*this), cop1(*this) {
+Registers::Registers() : cop0(*this), cop1(*this) { Reset(); }
-  Reset();
-}
 
 void Registers::Reset() {
   hi = 0;
   lo = 0;
   delaySlot = false;
   prevDelaySlot = false;
-  memset(gpr, 0, 32*sizeof(s64));
+  gpr.fill(0);
+  gprIsConstant.fill(false);
 
   cop0.Reset();
   cop1.Reset();
@@ -31,79 +30,112 @@ void Registers::SetPC32(s32 val) {
   nextPC = pc + 4;
 }
 
-template <> u64 Registers::Read<u64>(size_t idx) {
+template <>
+u64 Registers::Read<u64>(size_t idx) {
   return idx == 0 ? 0 : gpr[idx];
 }
 
-template <> s64 Registers::Read<s64>(size_t idx) {
+template <>
+s64 Registers::Read<s64>(size_t idx) {
   return s64(Read<u64>(idx));
 }
 
-template <> u32 Registers::Read<u32>(size_t idx) {
+template <>
+u32 Registers::Read<u32>(size_t idx) {
   return idx == 0 ? 0 : gpr[idx];
 }
 
-template <> s32 Registers::Read<s32>(size_t idx) {
+template <>
+s32 Registers::Read<s32>(size_t idx) {
   return s32(Read<u32>(idx));
 }
 
-template <> u16 Registers::Read<u16>(size_t idx) {
+template <>
+u16 Registers::Read<u16>(size_t idx) {
   return idx == 0 ? 0 : gpr[idx];
 }
 
-template <> s16 Registers::Read<s16>(size_t idx) {
+template <>
+s16 Registers::Read<s16>(size_t idx) {
   return s16(Read<u16>(idx));
 }
 
-template <> u8 Registers::Read<u8>(size_t idx) {
+template <>
+u8 Registers::Read<u8>(size_t idx) {
   return idx == 0 ? 0 : gpr[idx];
 }
 
-template <> s8 Registers::Read<s8>(size_t idx) {
+template <>
+s8 Registers::Read<s8>(size_t idx) {
   return s8(Read<u8>(idx));
 }
 
-template <> void Registers::Write<bool>(size_t idx, bool v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<bool>(size_t idx, bool v) {
+  if (idx == 0)
+    return;
   gpr[idx] = v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<u64>(size_t idx, u64 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<u64>(size_t idx, u64 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<s64>(size_t idx, s64 v) {
+template <>
+void Registers::Write<s64>(size_t idx, s64 v) {
   Write<u64>(idx, v);
 }
 
-template <> void Registers::Write<u32>(size_t idx, u32 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<u32>(size_t idx, u32 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = (u32)v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<s32>(size_t idx, s32 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<s32>(size_t idx, s32 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<u16>(size_t idx, u16 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<u16>(size_t idx, u16 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = (u16)v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<s16>(size_t idx, s16 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<s16>(size_t idx, s16 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<u8>(size_t idx, u8 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<u8>(size_t idx, u8 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = (u8)v;
+  gprIsConstant[idx] = true;
 }
 
-template <> void Registers::Write<s8>(size_t idx, s8 v) {
+template <>
-  if(idx == 0) return;
+void Registers::Write<s8>(size_t idx, s8 v) {
+  if (idx == 0)
+    return;
   gpr[idx] = v;
+  gprIsConstant[idx] = true;
 }
-}
+} // namespace n64

src/backend/core/registers/Registers.hpp

@@ -1,4 +1,5 @@
 #pragma once
+#include <array>
 #include <backend/core/registers/Cop1.hpp>
 
 namespace n64 {
@@ -9,15 +10,14 @@ struct Registers {
   void SetPC32(s32);
 
   bool IsRegConstant(u32 index) {
-    if(index == 0) return true;
+    if (index == 0)
+      return true;
     return gprIsConstant[index];
   }
 
-  bool IsRegConstant(u32 first, u32 second) {
+  bool IsRegConstant(u32 first, u32 second) { return IsRegConstant(first) && IsRegConstant(second); }
-    return IsRegConstant(first) && IsRegConstant(second);
-  }
 
-  bool gprIsConstant[32]{};
+  std::array<bool, 32> gprIsConstant{};
   bool loIsConstant = false, hiIsConstant = false;
   Cop0 cop0;
   Cop1 cop1;
@@ -27,9 +27,7 @@ struct Registers {
   u32 steps = 0;
   u32 extraCycles = 0;
 
-  void CpuStall(u32 cycles) {
+  void CpuStall(u32 cycles) { extraCycles += cycles; }
-    extraCycles += cycles;
-  }
 
   u32 PopStalledCycles() {
     u32 ret = extraCycles;
@@ -41,7 +39,8 @@ struct Registers {
   T Read(size_t);
   template <typename T>
   void Write(size_t, T);
+
 private:
-  s64 gpr[32]{};
+  std::array<s64, 32> gpr{};
 };
-}
+} // namespace n64

src/frontend/KaizenQt.cpp

@@ -7,7 +7,8 @@
 
 namespace fs = std::filesystem;
 
-KaizenQt::KaizenQt() noexcept : QWidget(nullptr) {
+KaizenQt::KaizenQt() noexcept :
+  QWidget(nullptr) {
   mainWindow = std::make_unique<MainWindowController>();
   settingsWindow = std::make_unique<SettingsWindow>();
   emuThread = std::make_unique<EmuThread>(
@@ -43,18 +44,18 @@ void KaizenQt::ConnectMainWindowSignalsToSlots() noexcept {
   connect(mainWindow.get(), &MainWindowController::Pause, emuThread.get(), &EmuThread::TogglePause);
 }
 
-void KaizenQt::dragEnterEvent(QDragEnterEvent* event) {
+void KaizenQt::dragEnterEvent(QDragEnterEvent *event) {
   if (event->mimeData()->hasUrls()) {
     event->acceptProposedAction();
   }
 }
 
-void KaizenQt::dropEvent(QDropEvent* event) {
+void KaizenQt::dropEvent(QDropEvent *event) {
   auto path = event->mimeData()->urls()[0].toLocalFile();
   LoadROM(path);
 }
 
-void KaizenQt::LoadROM(const QString& fileName) noexcept {
+void KaizenQt::LoadROM(const QString &fileName) noexcept {
   mainWindow->view.actionPause->setEnabled(true);
   mainWindow->view.actionReset->setEnabled(true);
   mainWindow->view.actionStop->setEnabled(true);
@@ -64,25 +65,25 @@ void KaizenQt::LoadROM(const QString& fileName) noexcept {
 }
 
 void KaizenQt::Quit() noexcept {
-  if(emuThread) {
+  if (emuThread) {
     emuThread->SetRender(false);
     emuThread->Stop();
   }
   QApplication::quit();
 }
 
-void KaizenQt::LoadTAS(const QString& fileName) const noexcept {
+void KaizenQt::LoadTAS(const QString &fileName) const noexcept {
   emuThread->core.LoadTAS(fs::path(fileName.toStdString()));
 }
 
 void KaizenQt::keyPressEvent(QKeyEvent *e) {
   emuThread->core.pause = true;
-  n64::Mem& mem = emuThread->core.cpu->GetMem();
+  n64::Mem &mem = emuThread->core.cpu->GetMem();
-  n64::PIF& pif = mem.mmio.si.pif;
+  n64::PIF &pif = mem.mmio.si.pif;
 
   auto k = static_cast<Qt::Key>(e->key());
-  for(int i = 0; i < 14; i++) {
+  for (int i = 0; i < 14; i++) {
-    if(k == settingsWindow->keyMap[i])
+    if (k == settingsWindow->keyMap[i])
       pif.UpdateButton(0, static_cast<n64::Controller::Key>(i), true);
   }
 
@@ -101,12 +102,12 @@ void KaizenQt::keyPressEvent(QKeyEvent *e) {
 
 void KaizenQt::keyReleaseEvent(QKeyEvent *e) {
   emuThread->core.pause = true;
-  n64::Mem& mem = emuThread->core.cpu->GetMem();
+  n64::Mem &mem = emuThread->core.cpu->GetMem();
-  n64::PIF& pif = mem.mmio.si.pif;
+  n64::PIF &pif = mem.mmio.si.pif;
 
   auto k = static_cast<Qt::Key>(e->key());
-  for(int i = 0; i < 14; i++) {
+  for (int i = 0; i < 14; i++) {
-    if(k == settingsWindow->keyMap[i])
+    if (k == settingsWindow->keyMap[i])
       pif.UpdateButton(0, static_cast<n64::Controller::Key>(i), false);
   }