iris/kaizen
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Finally clangformat

Browse Source
This commit is contained in:
SimoneN64
2024-08-27 21:18:10 +02:00
parent e98b36d083
commit b3a4a302cb
14 changed files with 1141 additions and 1080 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
.clang-format Normal file
View File

@@ -0,0 +1,52 @@
---
Language: Cpp
BasedOnStyle: LLVM
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignOperands: false
AlignTrailingComments: false
AlwaysBreakTemplateDeclarations: Yes
BreakBeforeBraces: Custom
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: true
BeforeElse: false
BeforeLambdaBody: false
BeforeWhile: true
SplitEmptyFunction: false
SplitEmptyRecord: false
SplitEmptyNamespace: false
BreakConstructorInitializers: AfterColon
BreakConstructorInitializersBeforeComma: false
ColumnLimit: 120
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ContinuationIndentWidth: 2
IncludeCategories:
- Regex: '^<.*'
Priority: 1
- Regex: '^".*'
Priority: 2
- Regex: '.*'
Priority: 3
IncludeIsMainRegex: '([-_](test|unittest))?$'
IndentCaseBlocks: true
InsertNewlineAtEOF: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 2
NamespaceIndentation: Inner
SpaceInEmptyParentheses: false
SpacesInAngles: false
SpacesInConditionalStatement: false
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
TabWidth: 2
...

10
src/backend/core/BaseCPU.hpp
View File

@@ -1,6 +1,6 @@
#pragma once #pragma once
#include <Registers.hpp>
#include <Mem.hpp> #include <Mem.hpp>
#include <Registers.hpp>
namespace n64 { namespace n64 {
struct BaseCPU { struct BaseCPU {
@@ -10,8 +10,8 @@ struct BaseCPU {
virtual bool ShouldServiceInterrupt() = 0; virtual bool ShouldServiceInterrupt() = 0;
virtual void CheckCompareInterrupt() = 0; virtual void CheckCompareInterrupt() = 0;
virtual std::vector<u8> Serialize() = 0; virtual std::vector<u8> Serialize() = 0;
virtual void Deserialize(const std::vector<u8>&) = 0; virtual void Deserialize(const std::vector<u8> &) = 0;
virtual Mem& GetMem() = 0; virtual Mem &GetMem() = 0;
virtual Registers& GetRegs() = 0; virtual Registers &GetRegs() = 0;
}; };
} } // namespace n64

249
src/backend/core/CpuDefinitions.hpp
View File

@@ -1,129 +1,130 @@
#pragma once #pragma once
#include <common.hpp> #include <common.hpp>
namespace n64 { namespace n64 {
constexpr u8 SPECIAL = 0b000000; constexpr u8 SPECIAL = 0b000000;
constexpr u8 REGIMM = 0b000001; constexpr u8 REGIMM = 0b000001;
constexpr u8 J = 0b000010; constexpr u8 J = 0b000010;
constexpr u8 JAL = 0b000011; constexpr u8 JAL = 0b000011;
constexpr u8 BEQ = 0b000100; constexpr u8 BEQ = 0b000100;
constexpr u8 BNE = 0b000101; constexpr u8 BNE = 0b000101;
constexpr u8 BLEZ = 0b000110; constexpr u8 BLEZ = 0b000110;
constexpr u8 BGTZ = 0b000111; constexpr u8 BGTZ = 0b000111;
constexpr u8 ADDI = 0b001000; constexpr u8 ADDI = 0b001000;
constexpr u8 ADDIU = 0b001001; constexpr u8 ADDIU = 0b001001;
constexpr u8 SLTI = 0b001010; constexpr u8 SLTI = 0b001010;
constexpr u8 SLTIU = 0b001011; constexpr u8 SLTIU = 0b001011;
constexpr u8 ANDI = 0b001100; constexpr u8 ANDI = 0b001100;
constexpr u8 ORI = 0b001101; constexpr u8 ORI = 0b001101;
constexpr u8 XORI = 0b001110; constexpr u8 XORI = 0b001110;
constexpr u8 LUI = 0b001111; constexpr u8 LUI = 0b001111;
constexpr u8 COP0 = 0b010000; constexpr u8 COP0 = 0b010000;
constexpr u8 COP1 = 0b010001; constexpr u8 COP1 = 0b010001;
constexpr u8 COP2 = 0b010010; constexpr u8 COP2 = 0b010010;
constexpr u8 BEQL = 0b010100; constexpr u8 BEQL = 0b010100;
constexpr u8 BNEL = 0b010101; constexpr u8 BNEL = 0b010101;
constexpr u8 BLEZL = 0b010110; constexpr u8 BLEZL = 0b010110;
constexpr u8 BGTZL = 0b010111; constexpr u8 BGTZL = 0b010111;
constexpr u8 DADDI = 0b011000; constexpr u8 DADDI = 0b011000;
constexpr u8 DADDIU = 0b011001; constexpr u8 DADDIU = 0b011001;
constexpr u8 LDL = 0b011010; constexpr u8 LDL = 0b011010;
constexpr u8 LDR = 0b011011; constexpr u8 LDR = 0b011011;
constexpr u8 LB = 0b100000; constexpr u8 LB = 0b100000;
constexpr u8 LH = 0b100001; constexpr u8 LH = 0b100001;
constexpr u8 LWL = 0b100010; constexpr u8 LWL = 0b100010;
constexpr u8 LW = 0b100011; constexpr u8 LW = 0b100011;
constexpr u8 LBU = 0b100100; constexpr u8 LBU = 0b100100;
constexpr u8 LHU = 0b100101; constexpr u8 LHU = 0b100101;
constexpr u8 LWR = 0b100110; constexpr u8 LWR = 0b100110;
constexpr u8 LWU = 0b100111; constexpr u8 LWU = 0b100111;
constexpr u8 SB = 0b101000; constexpr u8 SB = 0b101000;
constexpr u8 SH = 0b101001; constexpr u8 SH = 0b101001;
constexpr u8 SWL = 0b101010; constexpr u8 SWL = 0b101010;
constexpr u8 SW = 0b101011; constexpr u8 SW = 0b101011;
constexpr u8 SDL = 0b101100; constexpr u8 SDL = 0b101100;
constexpr u8 SDR = 0b101101; constexpr u8 SDR = 0b101101;
constexpr u8 SWR = 0b101110; constexpr u8 SWR = 0b101110;
constexpr u8 CACHE = 0b101111; constexpr u8 CACHE = 0b101111;
constexpr u8 LL = 0b110000; constexpr u8 LL = 0b110000;
constexpr u8 LWC1 = 0b110001; constexpr u8 LWC1 = 0b110001;
constexpr u8 LWC2 = 0b110010; constexpr u8 LWC2 = 0b110010;
constexpr u8 LLD = 0b110100; constexpr u8 LLD = 0b110100;
constexpr u8 LDC1 = 0b110101; constexpr u8 LDC1 = 0b110101;
constexpr u8 LDC2 = 0b110110; constexpr u8 LDC2 = 0b110110;
constexpr u8 LD = 0b110111; constexpr u8 LD = 0b110111;
constexpr u8 SC = 0b111000; constexpr u8 SC = 0b111000;
constexpr u8 SWC1 = 0b111001; constexpr u8 SWC1 = 0b111001;
constexpr u8 SWC2 = 0b111010; constexpr u8 SWC2 = 0b111010;
constexpr u8 SCD = 0b111100; constexpr u8 SCD = 0b111100;
constexpr u8 SDC1 = 0b111101; constexpr u8 SDC1 = 0b111101;
constexpr u8 SDC2 = 0b111110; constexpr u8 SDC2 = 0b111110;
constexpr u8 SD = 0b111111; constexpr u8 SD = 0b111111;
// special // special
constexpr u8 SLL = 0b000000; constexpr u8 SLL = 0b000000;
constexpr u8 SRL = 0b000010; constexpr u8 SRL = 0b000010;
constexpr u8 SRA = 0b000011; constexpr u8 SRA = 0b000011;
constexpr u8 SLLV = 0b000100; constexpr u8 SLLV = 0b000100;
constexpr u8 SRLV = 0b000110; constexpr u8 SRLV = 0b000110;
constexpr u8 SRAV = 0b000111; constexpr u8 SRAV = 0b000111;
constexpr u8 JR = 0b001000; constexpr u8 JR = 0b001000;
constexpr u8 JALR = 0b001001; constexpr u8 JALR = 0b001001;
constexpr u8 SYSCALL = 0b001100; constexpr u8 SYSCALL = 0b001100;
constexpr u8 BREAK = 0b001101; constexpr u8 BREAK = 0b001101;
constexpr u8 SYNC = 0b001111; constexpr u8 SYNC = 0b001111;
constexpr u8 MFHI = 0b010000; constexpr u8 MFHI = 0b010000;
constexpr u8 MTHI = 0b010001; constexpr u8 MTHI = 0b010001;
constexpr u8 MFLO = 0b010010; constexpr u8 MFLO = 0b010010;
constexpr u8 MTLO = 0b010011; constexpr u8 MTLO = 0b010011;
constexpr u8 DSLLV = 0b010100; constexpr u8 DSLLV = 0b010100;
constexpr u8 DSRLV = 0b010110; constexpr u8 DSRLV = 0b010110;
constexpr u8 DSRAV = 0b010111; constexpr u8 DSRAV = 0b010111;
constexpr u8 MULT = 0b011000; constexpr u8 MULT = 0b011000;
constexpr u8 MULTU = 0b011001; constexpr u8 MULTU = 0b011001;
constexpr u8 DIV = 0b011010; constexpr u8 DIV = 0b011010;
constexpr u8 DIVU = 0b011011; constexpr u8 DIVU = 0b011011;
constexpr u8 DMULT = 0b011100; constexpr u8 DMULT = 0b011100;
constexpr u8 DMULTU = 0b011101; constexpr u8 DMULTU = 0b011101;
constexpr u8 DDIV = 0b011110; constexpr u8 DDIV = 0b011110;
constexpr u8 DDIVU = 0b011111; constexpr u8 DDIVU = 0b011111;
constexpr u8 ADD = 0b100000; constexpr u8 ADD = 0b100000;
constexpr u8 ADDU = 0b100001; constexpr u8 ADDU = 0b100001;
constexpr u8 SUB = 0b100010; constexpr u8 SUB = 0b100010;
constexpr u8 SUBU = 0b100011; constexpr u8 SUBU = 0b100011;
constexpr u8 AND = 0b100100; constexpr u8 AND = 0b100100;
constexpr u8 OR = 0b100101; constexpr u8 OR = 0b100101;
constexpr u8 XOR = 0b100110; constexpr u8 XOR = 0b100110;
constexpr u8 NOR = 0b100111; constexpr u8 NOR = 0b100111;
constexpr u8 SLT = 0b101010; constexpr u8 SLT = 0b101010;
constexpr u8 SLTU = 0b101011; constexpr u8 SLTU = 0b101011;
constexpr u8 DADD = 0b101100; constexpr u8 DADD = 0b101100;
constexpr u8 DADDU = 0b101101; constexpr u8 DADDU = 0b101101;
constexpr u8 DSUB = 0b101110; constexpr u8 DSUB = 0b101110;
constexpr u8 DSUBU = 0b101111; constexpr u8 DSUBU = 0b101111;
constexpr u8 TGE = 0b110000; constexpr u8 TGE = 0b110000;
constexpr u8 TGEU = 0b110001; constexpr u8 TGEU = 0b110001;
constexpr u8 TLT = 0b110010; constexpr u8 TLT = 0b110010;
constexpr u8 TLTU = 0b110011; constexpr u8 TLTU = 0b110011;
constexpr u8 TEQ = 0b110100; constexpr u8 TEQ = 0b110100;
constexpr u8 TNE = 0b110110; constexpr u8 TNE = 0b110110;
constexpr u8 DSLL = 0b111000; constexpr u8 DSLL = 0b111000;
constexpr u8 DSRL = 0b111010; constexpr u8 DSRL = 0b111010;
constexpr u8 DSRA = 0b111011; constexpr u8 DSRA = 0b111011;
constexpr u8 DSLL32 = 0b111100; constexpr u8 DSLL32 = 0b111100;
constexpr u8 DSRL32 = 0b111110; constexpr u8 DSRL32 = 0b111110;
constexpr u8 DSRA32 = 0b111111; constexpr u8 DSRA32 = 0b111111;
// regimm // regimm
constexpr u8 BLTZ = 0b00000; constexpr u8 BLTZ = 0b00000;
constexpr u8 BGEZ = 0b00001; constexpr u8 BGEZ = 0b00001;
constexpr u8 BLTZL = 0b00010; constexpr u8 BLTZL = 0b00010;
constexpr u8 BGEZL = 0b00011; constexpr u8 BGEZL = 0b00011;
constexpr u8 TGEI = 0b01000; constexpr u8 TGEI = 0b01000;
constexpr u8 TGEIU = 0b01001; constexpr u8 TGEIU = 0b01001;
constexpr u8 TLTI = 0b01010; constexpr u8 TLTI = 0b01010;
constexpr u8 TLTIU = 0b01011; constexpr u8 TLTIU = 0b01011;
constexpr u8 TEQI = 0b01100; constexpr u8 TEQI = 0b01100;
constexpr u8 TNEI = 0b01110; constexpr u8 TNEI = 0b01110;
constexpr u8 BLTZAL = 0b10000; constexpr u8 BLTZAL = 0b10000;
constexpr u8 BGEZAL = 0b10001; constexpr u8 BGEZAL = 0b10001;
constexpr u8 BLTZALL = 0b10010; constexpr u8 BLTZALL = 0b10010;
constexpr u8 BGEZALL = 0b10011; constexpr u8 BGEZALL = 0b10011;
} } // namespace n64

19
src/backend/core/Interpreter.cpp
View File

@@ -1,7 +1,7 @@
#include <Core.hpp> #include <Core.hpp>
namespace n64 { namespace n64 {
Interpreter::Interpreter(ParallelRDP& parallel) : mem(regs, parallel) { } Interpreter::Interpreter(ParallelRDP &parallel) : mem(regs, parallel) {}
bool Interpreter::ShouldServiceInterrupt() { bool Interpreter::ShouldServiceInterrupt() {
bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0; bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0;
@@ -9,14 +9,13 @@ bool Interpreter::ShouldServiceInterrupt() {
bool currently_handling_exception = regs.cop0.status.exl == 1; bool currently_handling_exception = regs.cop0.status.exl == 1;
bool currently_handling_error = regs.cop0.status.erl == 1; bool currently_handling_error = regs.cop0.status.erl == 1;
return interrupts_pending && interrupts_enabled && return interrupts_pending && interrupts_enabled && !currently_handling_exception && !currently_handling_error;
!currently_handling_exception && !currently_handling_error;
} }
void Interpreter::CheckCompareInterrupt() { void Interpreter::CheckCompareInterrupt() {
regs.cop0.count++; regs.cop0.count++;
regs.cop0.count &= 0x1FFFFFFFF; regs.cop0.count &= 0x1FFFFFFFF;
if(regs.cop0.count == (u64)regs.cop0.compare << 1) { if (regs.cop0.count == (u64)regs.cop0.compare << 1) {
regs.cop0.cause.ip7 = 1; regs.cop0.cause.ip7 = 1;
mem.mmio.mi.UpdateInterrupt(); mem.mmio.mi.UpdateInterrupt();
} }
@@ -28,14 +27,14 @@ int Interpreter::Step() {
regs.prevDelaySlot = regs.delaySlot; regs.prevDelaySlot = regs.delaySlot;
regs.delaySlot = false; regs.delaySlot = false;
if(check_address_error(0b11, u64(regs.pc))) [[unlikely]] { if (check_address_error(0b11, u64(regs.pc))) [[unlikely]] {
regs.cop0.HandleTLBException(regs.pc); regs.cop0.HandleTLBException(regs.pc);
regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.pc); regs.cop0.FireException(ExceptionCode::AddressErrorLoad, 0, regs.pc);
return 1; return 1;
} }
u32 paddr = 0; u32 paddr = 0;
if(!regs.cop0.MapVAddr(Cop0::LOAD, regs.pc, paddr)) { if (!regs.cop0.MapVAddr(Cop0::LOAD, regs.pc, paddr)) {
regs.cop0.HandleTLBException(regs.pc); regs.cop0.HandleTLBException(regs.pc);
regs.cop0.FireException(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.pc); regs.cop0.FireException(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.pc);
return 1; return 1;
@@ -43,7 +42,7 @@ int Interpreter::Step() {
u32 instruction = mem.Read<u32>(regs, paddr); u32 instruction = mem.Read<u32>(regs, paddr);
if(ShouldServiceInterrupt()) { if (ShouldServiceInterrupt()) {
regs.cop0.FireException(ExceptionCode::Interrupt, 0, regs.pc); regs.cop0.FireException(ExceptionCode::Interrupt, 0, regs.pc);
return 1; return 1;
} }
@@ -67,7 +66,5 @@ std::vector<u8> Interpreter::Serialize() {
return res; return res;
} }
void Interpreter::Deserialize(const std::vector<u8> &data) { void Interpreter::Deserialize(const std::vector<u8> &data) { memcpy(&regs, data.data(), sizeof(Registers)); }
memcpy(&regs, data.data(), sizeof(Registers)); } // namespace n64
}
}

22
src/backend/core/Interpreter.hpp
View File

@@ -1,37 +1,37 @@
#pragma once #pragma once
#include <BaseCPU.hpp>
#include <Mem.hpp> #include <Mem.hpp>
#include <vector> #include <vector>
#include <BaseCPU.hpp>
namespace n64 { namespace n64 {
struct Core; struct Core;
struct Interpreter : BaseCPU { struct Interpreter : BaseCPU {
explicit Interpreter(ParallelRDP&); explicit Interpreter(ParallelRDP &);
~Interpreter() override = default; ~Interpreter() override = default;
int Step() override; int Step() override;
void Reset() override { void Reset() override {
regs.Reset(); regs.Reset();
mem.Reset(); mem.Reset();
cop2Latch = {}; cop2Latch = {};
} }
Mem& GetMem() override { Mem &GetMem() override { return mem; }
return mem;
} Registers &GetRegs() override { return regs; }
Registers& GetRegs() override {
return regs;
}
private: private:
Registers regs; Registers regs;
Mem mem; Mem mem;
u64 cop2Latch{}; u64 cop2Latch{};
friend struct Cop1; friend struct Cop1;
#define check_address_error(mask, vaddr) (((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0)) #define check_address_error(mask, vaddr) \
(((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
bool ShouldServiceInterrupt() override; bool ShouldServiceInterrupt() override;
void CheckCompareInterrupt() override; void CheckCompareInterrupt() override;
std::vector<u8> Serialize() override; std::vector<u8> Serialize() override;
void Deserialize(const std::vector<u8>&) override; void Deserialize(const std::vector<u8> &) override;
void cop2Decode(u32); void cop2Decode(u32);
void special(u32); void special(u32);
@@ -130,4 +130,4 @@ private:
void ctc2(u32); void ctc2(u32);
void cfc2(u32); void cfc2(u32);
}; };
} } // namespace n64

30
src/backend/core/JIT.cpp
View File

@@ -2,10 +2,7 @@
#include <jit/helpers.hpp> #include <jit/helpers.hpp>
namespace n64 { namespace n64 {
JIT::JIT(ParallelRDP& parallel) : mem(regs, parallel) { JIT::JIT(ParallelRDP &parallel) : mem(regs, parallel) {}
regs.gpr[0] = 0;
regs.gprIsConstant[0] = true;
}
bool JIT::ShouldServiceInterrupt() { bool JIT::ShouldServiceInterrupt() {
bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0; bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0;
@@ -13,14 +10,13 @@ bool JIT::ShouldServiceInterrupt() {
bool currently_handling_exception = regs.cop0.status.exl == 1; bool currently_handling_exception = regs.cop0.status.exl == 1;
bool currently_handling_error = regs.cop0.status.erl == 1; bool currently_handling_error = regs.cop0.status.erl == 1;
return interrupts_pending && interrupts_enabled && return interrupts_pending && interrupts_enabled && !currently_handling_exception && !currently_handling_error;
!currently_handling_exception && !currently_handling_error;
} }
void JIT::CheckCompareInterrupt() { void JIT::CheckCompareInterrupt() {
regs.cop0.count++; regs.cop0.count++;
regs.cop0.count &= 0x1FFFFFFFF; regs.cop0.count &= 0x1FFFFFFFF;
if(regs.cop0.count == (u64)regs.cop0.compare << 1) { if (regs.cop0.count == (u64)regs.cop0.compare << 1) {
regs.cop0.cause.ip7 = 1; regs.cop0.cause.ip7 = 1;
mem.mmio.mi.UpdateInterrupt(); mem.mmio.mi.UpdateInterrupt();
} }
@@ -31,10 +27,10 @@ int JIT::Step() {
s64 pc = regs.pc; s64 pc = regs.pc;
do { do {
//CheckCompareInterrupt(); // CheckCompareInterrupt();
//regs.prevDelaySlot = regs.delaySlot; // regs.prevDelaySlot = regs.delaySlot;
//regs.delaySlot = false; // regs.delaySlot = false;
/*if (check_address_error(0b11, u64(pc))) [[unlikely]] { /*if (check_address_error(0b11, u64(pc))) [[unlikely]] {
regs.cop0.HandleTLBException(pc); regs.cop0.HandleTLBException(pc);
@@ -47,7 +43,8 @@ int JIT::Step() {
/*regs.cop0.HandleTLBException(pc); /*regs.cop0.HandleTLBException(pc);
regs.cop0.FireException(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, pc); regs.cop0.FireException(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, pc);
return 1;*/ return 1;*/
Util::panic("[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address!", static_cast<int>(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD))); Util::panic("[JIT]: Unhandled exception TLB exception {} when retrieving PC physical address!",
static_cast<int>(regs.cop0.GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD)));
} }
instruction = mem.Read<u32>(regs, paddr); instruction = mem.Read<u32>(regs, paddr);
@@ -59,8 +56,9 @@ int JIT::Step() {
pc += 4; pc += 4;
//Exec(instruction); // Exec(instruction);
} while (!InstrEndsBlock(instruction)); }
while (!InstrEndsBlock(instruction));
return 1; return 1;
} }
@@ -75,7 +73,5 @@ std::vector<u8> JIT::Serialize() {
return res; return res;
} }
void JIT::Deserialize(const std::vector<u8> &data) { void JIT::Deserialize(const std::vector<u8> &data) { memcpy(&regs, data.data(), sizeof(Registers)); }
memcpy(&regs, data.data(), sizeof(Registers)); } // namespace n64
}
}

22
src/backend/core/JIT.hpp
View File

@@ -1,36 +1,36 @@
#pragma once #pragma once
#include <BaseCPU.hpp>
#include <Mem.hpp> #include <Mem.hpp>
#include <vector> #include <vector>
#include <BaseCPU.hpp>
namespace n64 { namespace n64 {
struct Core; struct Core;
struct JIT : BaseCPU { struct JIT : BaseCPU {
explicit JIT(ParallelRDP&); explicit JIT(ParallelRDP &);
~JIT() override = default; ~JIT() override = default;
int Step() override; int Step() override;
void Reset() override { void Reset() override {
regs.Reset(); regs.Reset();
mem.Reset(); mem.Reset();
} }
Mem& GetMem() override { Mem &GetMem() override { return mem; }
return mem;
} Registers &GetRegs() override { return regs; }
Registers& GetRegs() override {
return regs;
}
private: private:
Registers regs; Registers regs;
Mem mem; Mem mem;
u64 cop2Latch{}; u64 cop2Latch{};
friend struct Cop1; friend struct Cop1;
#define check_address_error(mask, vaddr) (((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0)) #define check_address_error(mask, vaddr) \
(((!regs.cop0.is64BitAddressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
bool ShouldServiceInterrupt() override; bool ShouldServiceInterrupt() override;
void CheckCompareInterrupt() override; void CheckCompareInterrupt() override;
std::vector<u8> Serialize() override; std::vector<u8> Serialize() override;
void Deserialize(const std::vector<u8>&) override; void Deserialize(const std::vector<u8> &) override;
void Emit(u32); void Emit(u32);
void cop2Decode(u32); void cop2Decode(u32);
@@ -129,4 +129,4 @@ private:
void ctc2(u32); void ctc2(u32);
void cfc2(u32); void cfc2(u32);
}; };
} } // namespace n64

83
src/backend/core/MMIO.cpp
View File

@@ -15,31 +15,55 @@ void MMIO::Reset() {
u32 MMIO::Read(u32 addr) { u32 MMIO::Read(u32 addr) {
switch (addr) { switch (addr) {
case RSP_REGION: return rsp.Read(addr); case RSP_REGION:
case RDP_REGION: return rdp.Read(addr); return rsp.Read(addr);
case MI_REGION: return mi.Read(addr); case RDP_REGION:
case VI_REGION: return vi.Read(addr); return rdp.Read(addr);
case AI_REGION: return ai.Read(addr); case MI_REGION:
case PI_REGION: return pi.Read(addr); return mi.Read(addr);
case RI_REGION: return ri.Read(addr); case VI_REGION:
case SI_REGION: return si.Read(addr); return vi.Read(addr);
default: case AI_REGION:
Util::panic("Unhandled mmio read at addr {:08X}", addr); return ai.Read(addr);
case PI_REGION:
return pi.Read(addr);
case RI_REGION:
return ri.Read(addr);
case SI_REGION:
return si.Read(addr);
default:
Util::panic("Unhandled mmio read at addr {:08X}", addr);
} }
} }
void MMIO::Write(u32 addr, u32 val) { void MMIO::Write(u32 addr, u32 val) {
switch (addr) { switch (addr) {
case RSP_REGION: rsp.Write(addr, val); break; case RSP_REGION:
case RDP_REGION: rdp.Write(addr, val); break; rsp.Write(addr, val);
case MI_REGION: mi.Write(addr, val); break; break;
case VI_REGION: vi.Write(addr, val); break; case RDP_REGION:
case AI_REGION: ai.Write(addr, val); break; rdp.Write(addr, val);
case PI_REGION: pi.Write(addr, val); break; break;
case RI_REGION: ri.Write(addr, val); break; case MI_REGION:
case SI_REGION: si.Write(addr, val); break; mi.Write(addr, val);
default: break;
Util::panic("Unhandled mmio write at addr {:08X} with val {:08X}", addr, val); case VI_REGION:
vi.Write(addr, val);
break;
case AI_REGION:
ai.Write(addr, val);
break;
case PI_REGION:
pi.Write(addr, val);
break;
case RI_REGION:
ri.Write(addr, val);
break;
case SI_REGION:
si.Write(addr, val);
break;
default:
Util::panic("Unhandled mmio write at addr {:08X} with val {:08X}", addr, val);
} }
} }
@@ -47,20 +71,9 @@ std::vector<u8> MMIO::Serialize() {
std::vector<u8> res{}; std::vector<u8> res{};
auto sPIF = si.pif.Serialize(); auto sPIF = si.pif.Serialize();
constexpr u32 rdpSize = sizeof(DPC) + constexpr u32 rdpSize = sizeof(DPC) + 0xFFFFF + RDRAM_SIZE;
0xFFFFF + res.resize(rdpSize + sizeof(RSP) + sizeof(MI) + sizeof(VI) + sizeof(SI) + sizeof(PI) + sizeof(RI) + sizeof(AI) +
RDRAM_SIZE; sizeof(u32) * 2 + sizeof(SIStatus));
res.resize(
rdpSize +
sizeof(RSP) +
sizeof(MI) +
sizeof(VI) +
sizeof(SI) +
sizeof(PI) +
sizeof(RI) +
sizeof(AI) +
sizeof(u32)*2 +
sizeof(SIStatus));
u32 index = 0; u32 index = 0;
memcpy(res.data(), &rsp, sizeof(RSP)); memcpy(res.data(), &rsp, sizeof(RSP));
@@ -118,4 +131,4 @@ void MMIO::Deserialize(const std::vector<u8> &data) {
index += sizeof(u32); index += sizeof(u32);
memcpy(&si.status, data.data() + index, sizeof(SIStatus)); memcpy(&si.status, data.data() + index, sizeof(SIStatus));
} }
} } // namespace n64

650
src/backend/core/Mem.cpp
View File

@@ -1,14 +1,14 @@
#include <Mem.hpp>
#include <core/registers/Registers.hpp>
#include <core/registers/Cop0.hpp>
#include <core/Interpreter.hpp>
#include <backend/RomHelpers.hpp>
#include <File.hpp> #include <File.hpp>
#include <unarr.h> #include <Mem.hpp>
#include <backend/RomHelpers.hpp>
#include <cassert> #include <cassert>
#include <core/Interpreter.hpp>
#include <core/registers/Cop0.hpp>
#include <core/registers/Registers.hpp>
#include <unarr.h>
namespace n64 { namespace n64 {
Mem::Mem(Registers& regs, ParallelRDP& parallel) : flash(saveData), mmio(*this, regs, parallel) { Mem::Mem(Registers &regs, ParallelRDP &parallel) : flash(saveData), mmio(*this, regs, parallel) {
rom.cart.resize(CART_SIZE); rom.cart.resize(CART_SIZE);
std::fill(rom.cart.begin(), rom.cart.end(), 0); std::fill(rom.cart.begin(), rom.cart.end(), 0);
} }
@@ -19,27 +19,31 @@ void Mem::Reset() {
if (saveData.is_mapped()) { if (saveData.is_mapped()) {
std::error_code error; std::error_code error;
saveData.sync(error); saveData.sync(error);
if (error) { Util::panic("Could not sync save data"); } if (error) {
Util::panic("Could not sync save data");
}
saveData.unmap(); saveData.unmap();
} }
mmio.Reset(); mmio.Reset();
} }
void Mem::LoadSRAM(SaveType save_type, fs::path path) { void Mem::LoadSRAM(SaveType save_type, fs::path path) {
if(save_type == SAVE_SRAM_256k) { if (save_type == SAVE_SRAM_256k) {
std::error_code error; std::error_code error;
if (!savePath.empty()) { if (!savePath.empty()) {
path = savePath / path.filename(); path = savePath / path.filename();
} }
sramPath = path.replace_extension(".sram").string(); sramPath = path.replace_extension(".sram").string();
if(saveData.is_mapped()) { if (saveData.is_mapped()) {
saveData.sync(error); saveData.sync(error);
if(error) { Util::panic("Could not sync {}", sramPath); } if (error) {
Util::panic("Could not sync {}", sramPath);
}
saveData.unmap(); saveData.unmap();
} }
auto sramVec = Util::ReadFileBinary(sramPath); auto sramVec = Util::ReadFileBinary(sramPath);
if(sramVec.empty()) { if (sramVec.empty()) {
Util::WriteFileBinary(std::array<u8, SRAM_SIZE>{}, sramPath); Util::WriteFileBinary(std::array<u8, SRAM_SIZE>{}, sramPath);
sramVec = Util::ReadFileBinary(sramPath); sramVec = Util::ReadFileBinary(sramPath);
} }
@@ -48,56 +52,70 @@ void Mem::LoadSRAM(SaveType save_type, fs::path path) {
Util::panic("Corrupt SRAM!"); Util::panic("Corrupt SRAM!");
} }
saveData = mio::make_mmap_sink( saveData = mio::make_mmap_sink(sramPath, 0, mio::map_entire_file, error);
sramPath, 0, mio::map_entire_file, error); if (error) {
if (error) { Util::panic("Could not mmap {}", sramPath); } Util::panic("Could not mmap {}", sramPath);
}
} }
} }
FORCE_INLINE void SetROMCIC(u32 checksum, ROM& rom) { FORCE_INLINE void SetROMCIC(u32 checksum, ROM &rom) {
switch (checksum) { switch (checksum) {
case 0xEC8B1325: rom.cicType = CIC_NUS_7102; break; // 7102 case 0xEC8B1325:
case 0x1DEB51A9: rom.cicType = CIC_NUS_6101; break; // 6101 rom.cicType = CIC_NUS_7102;
case 0xC08E5BD6: rom.cicType = CIC_NUS_6102_7101; break; break; // 7102
case 0x03B8376A: rom.cicType = CIC_NUS_6103_7103; break; case 0x1DEB51A9:
case 0xCF7F41DC: rom.cicType = CIC_NUS_6105_7105; break; rom.cicType = CIC_NUS_6101;
case 0xD1059C6A: rom.cicType = CIC_NUS_6106_7106; break; break; // 6101
default: case 0xC08E5BD6:
Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum); rom.cicType = CIC_NUS_6102_7101;
rom.cicType = UNKNOWN_CIC_TYPE; break;
break; case 0x03B8376A:
rom.cicType = CIC_NUS_6103_7103;
break;
case 0xCF7F41DC:
rom.cicType = CIC_NUS_6105_7105;
break;
case 0xD1059C6A:
rom.cicType = CIC_NUS_6106_7106;
break;
default:
Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum);
rom.cicType = UNKNOWN_CIC_TYPE;
break;
} }
} }
std::vector<u8> Mem::OpenArchive(const std::string &path, size_t& sizeAdjusted) { std::vector<u8> Mem::OpenArchive(const std::string &path, size_t &sizeAdjusted) {
auto stream = ar_open_file(fs::path(path).u8string().c_str()); auto stream = ar_open_file(fs::path(path).u8string().c_str());
if(!stream) { if (!stream) {
Util::panic("Could not open archive! Are you sure it's an archive?"); Util::panic("Could not open archive! Are you sure it's an archive?");
} }
ar_archive* archive = ar_open_zip_archive(stream, false); ar_archive *archive = ar_open_zip_archive(stream, false);
if(!archive) archive = ar_open_rar_archive(stream); if (!archive)
if(!archive) archive = ar_open_7z_archive(stream); archive = ar_open_rar_archive(stream);
if(!archive) archive = ar_open_tar_archive(stream); if (!archive)
archive = ar_open_7z_archive(stream);
if (!archive)
archive = ar_open_tar_archive(stream);
if(!archive) { if (!archive) {
ar_close(stream); ar_close(stream);
Util::panic("Could not open archive! Are you sure it's a supported archive? (7z, zip, rar and tar are supported)"); Util::panic("Could not open archive! Are you sure it's a supported archive? (7z, zip, rar and tar are supported)");
} }
std::vector<u8> buf{}; std::vector<u8> buf{};
std::vector<std::string> rom_exts{".n64",".z64",".v64",".N64",".Z64",".V64"}; std::vector<std::string> rom_exts{".n64", ".z64", ".v64", ".N64", ".Z64", ".V64"};
while(ar_parse_entry(archive)) { while (ar_parse_entry(archive)) {
auto filename = ar_entry_get_name(archive); auto filename = ar_entry_get_name(archive);
auto extension = fs::path(filename).extension(); auto extension = fs::path(filename).extension();
if(std::any_of(rom_exts.begin(), rom_exts.end(), [&](auto x) { if (std::any_of(rom_exts.begin(), rom_exts.end(), [&](auto x) { return extension == x; })) {
return extension == x;
})) {
auto size = ar_entry_get_size(archive); auto size = ar_entry_get_size(archive);
sizeAdjusted = Util::NextPow2(size); sizeAdjusted = Util::NextPow2(size);
buf.resize(sizeAdjusted); buf.resize(sizeAdjusted);
@@ -115,13 +133,13 @@ std::vector<u8> Mem::OpenArchive(const std::string &path, size_t& sizeAdjusted)
return buf; return buf;
} }
std::vector<u8> Mem::OpenROM(const std::string& filename, size_t& sizeAdjusted) { std::vector<u8> Mem::OpenROM(const std::string &filename, size_t &sizeAdjusted) {
auto buf = Util::ReadFileBinary(filename); auto buf = Util::ReadFileBinary(filename);
sizeAdjusted = Util::NextPow2(buf.size()); sizeAdjusted = Util::NextPow2(buf.size());
return buf; return buf;
} }
void Mem::LoadROM(bool isArchive, const std::string& filename) { void Mem::LoadROM(bool isArchive, const std::string &filename) {
size_t sizeAdjusted; size_t sizeAdjusted;
u32 endianness; u32 endianness;
{ {
@@ -132,7 +150,7 @@ void Mem::LoadROM(bool isArchive, const std::string& filename) {
buf = OpenROM(filename, sizeAdjusted); buf = OpenROM(filename, sizeAdjusted);
} }
endianness = be32toh(*reinterpret_cast<u32*>(buf.data())); endianness = be32toh(*reinterpret_cast<u32 *>(buf.data()));
Util::SwapN64Rom<true>(buf, endianness); Util::SwapN64Rom<true>(buf, endianness);
std::copy(buf.begin(), buf.end(), rom.cart.begin()); std::copy(buf.begin(), buf.end(), rom.cart.begin());
@@ -162,289 +180,322 @@ void Mem::LoadROM(bool isArchive, const std::string& filename) {
u32 checksum = Util::crc32(0, &rom.cart[0x40], 0x9c0); u32 checksum = Util::crc32(0, &rom.cart[0x40], 0x9c0);
SetROMCIC(checksum, rom); SetROMCIC(checksum, rom);
endianness = be32toh(*reinterpret_cast<u32*>(rom.cart.data())); endianness = be32toh(*reinterpret_cast<u32 *>(rom.cart.data()));
Util::SwapN64Rom(rom.cart, endianness); Util::SwapN64Rom(rom.cart, endianness);
rom.pal = IsROMPAL(); rom.pal = IsROMPAL();
} }
template<> u8 Mem::Read(n64::Registers &regs, u32 paddr) { template <>
SI& si = mmio.si; u8 Mem::Read(n64::Registers &regs, u32 paddr) {
SI &si = mmio.si;
switch (paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
return mmio.rdp.ReadRDRAM<u8>(paddr); return mmio.rdp.ReadRDRAM<u8>(paddr);
case RSP_MEM_REGION: { case RSP_MEM_REGION:
auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; {
auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
return src[BYTE_ADDRESS(paddr & 0xfff)]; return src[BYTE_ADDRESS(paddr & 0xfff)];
} }
case REGION_CART: case REGION_CART:
return mmio.pi.BusRead<u8, false>(paddr); return mmio.pi.BusRead<u8, false>(paddr);
case 0x04040000 ... 0x040FFFFF: case 0x04040000 ... 0x040FFFFF:
case 0x04100000 ... 0x041FFFFF: case 0x04100000 ... 0x041FFFFF:
case 0x04600000 ... 0x048FFFFF: case 0x04600000 ... 0x048FFFFF:
case 0x04300000 ... 0x044FFFFF: case 0x04300000 ... 0x044FFFFF:
Util::panic("MMIO Read<u8>!\n"); Util::panic("MMIO Read<u8>!\n");
case AI_REGION: { case AI_REGION:
{
u32 w = mmio.ai.Read(paddr & ~3); u32 w = mmio.ai.Read(paddr & ~3);
int offs = 3 - (paddr & 3); int offs = 3 - (paddr & 3);
return (w >> (offs * 8)) & 0xff; return (w >> (offs * 8)) & 0xff;
} }
case PIF_ROM_REGION: case PIF_ROM_REGION:
return si.pif.bootrom[BYTE_ADDRESS(paddr) - PIF_ROM_REGION_START]; return si.pif.bootrom[BYTE_ADDRESS(paddr) - PIF_ROM_REGION_START];
case PIF_RAM_REGION: case PIF_RAM_REGION:
return si.pif.ram[paddr - PIF_RAM_REGION_START]; return si.pif.ram[paddr - PIF_RAM_REGION_START];
case 0x00800000 ... 0x03EFFFFF: // unused case 0x00800000 ... 0x03EFFFFF: // unused
case 0x04200000 ... 0x042FFFFF: // unused case 0x04200000 ... 0x042FFFFF: // unused
case 0x04900000 ... 0x04FFFFFF: // unused case 0x04900000 ... 0x04FFFFFF: // unused
case 0x1FC00800 ... 0xFFFFFFFF: // unused case 0x1FC00800 ... 0xFFFFFFFF: // unused
return 0; return 0;
default: default:
Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc); Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
} }
} }
template<> u16 Mem::Read(n64::Registers &regs, u32 paddr) { template <>
SI& si = mmio.si; u16 Mem::Read(n64::Registers &regs, u32 paddr) {
SI &si = mmio.si;
switch (paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
return mmio.rdp.ReadRDRAM<u16>(paddr); return mmio.rdp.ReadRDRAM<u16>(paddr);
case RSP_MEM_REGION: { case RSP_MEM_REGION:
auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; {
auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
return Util::ReadAccess<u16>(src, HALF_ADDRESS(paddr & 0xfff)); return Util::ReadAccess<u16>(src, HALF_ADDRESS(paddr & 0xfff));
} }
case MMIO_REGION: case MMIO_REGION:
return mmio.Read(paddr); return mmio.Read(paddr);
case REGION_CART: case REGION_CART:
return mmio.pi.BusRead<u16, false>(paddr); return mmio.pi.BusRead<u16, false>(paddr);
case PIF_ROM_REGION: case PIF_ROM_REGION:
return Util::ReadAccess<u16>(si.pif.bootrom, HALF_ADDRESS(paddr) - PIF_ROM_REGION_START); return Util::ReadAccess<u16>(si.pif.bootrom, HALF_ADDRESS(paddr) - PIF_ROM_REGION_START);
case PIF_RAM_REGION: case PIF_RAM_REGION:
return be16toh(Util::ReadAccess<u16>(si.pif.ram, paddr - PIF_RAM_REGION_START)); return be16toh(Util::ReadAccess<u16>(si.pif.ram, paddr - PIF_RAM_REGION_START));
case 0x00800000 ... 0x03EFFFFF: case 0x00800000 ... 0x03EFFFFF:
case 0x04200000 ... 0x042FFFFF: case 0x04200000 ... 0x042FFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x04900000 ... 0x04FFFFFF:
case 0x1FC00800 ... 0xFFFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF:
return 0; return 0;
default: default:
Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc); Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
} }
} }
template<> u32 Mem::Read(n64::Registers &regs, u32 paddr) { template <>
SI& si = mmio.si; u32 Mem::Read(n64::Registers &regs, u32 paddr) {
SI &si = mmio.si;
switch(paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
return mmio.rdp.ReadRDRAM<u32>(paddr); return mmio.rdp.ReadRDRAM<u32>(paddr);
case RSP_MEM_REGION: { case RSP_MEM_REGION:
auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; {
auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
return Util::ReadAccess<u32>(src, paddr & 0xfff); return Util::ReadAccess<u32>(src, paddr & 0xfff);
} }
case MMIO_REGION: case MMIO_REGION:
return mmio.Read(paddr); return mmio.Read(paddr);
case REGION_CART: case REGION_CART:
return mmio.pi.BusRead<u32, false>(paddr); return mmio.pi.BusRead<u32, false>(paddr);
case PIF_ROM_REGION: case PIF_ROM_REGION:
return Util::ReadAccess<u32>(si.pif.bootrom, paddr - PIF_ROM_REGION_START); return Util::ReadAccess<u32>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
case PIF_RAM_REGION: case PIF_RAM_REGION:
return be32toh(Util::ReadAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START)); return be32toh(Util::ReadAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START));
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF: case 0x00800000 ... 0x03FFFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0; case 0x04200000 ... 0x042FFFFF:
default: case 0x04900000 ... 0x04FFFFFF:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc); case 0x1FC00800 ... 0xFFFFFFFF:
return 0;
default:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
} }
} }
template<> u64 Mem::Read(n64::Registers &regs, u32 paddr) { template <>
SI& si = mmio.si; u64 Mem::Read(n64::Registers &regs, u32 paddr) {
SI &si = mmio.si;
switch (paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
return mmio.rdp.ReadRDRAM<u64>(paddr); return mmio.rdp.ReadRDRAM<u64>(paddr);
case RSP_MEM_REGION: { case RSP_MEM_REGION:
auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; {
auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
return Util::ReadAccess<u64>(src, paddr & 0xfff); return Util::ReadAccess<u64>(src, paddr & 0xfff);
} }
case MMIO_REGION: case MMIO_REGION:
return mmio.Read(paddr); return mmio.Read(paddr);
case REGION_CART: case REGION_CART:
return mmio.pi.BusRead<u64, false>(paddr); return mmio.pi.BusRead<u64, false>(paddr);
case PIF_ROM_REGION: case PIF_ROM_REGION:
return Util::ReadAccess<u64>(si.pif.bootrom, paddr - PIF_ROM_REGION_START); return Util::ReadAccess<u64>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
case PIF_RAM_REGION: case PIF_RAM_REGION:
return be64toh(Util::ReadAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START)); return be64toh(Util::ReadAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START));
case 0x00800000 ... 0x03EFFFFF: case 0x00800000 ... 0x03EFFFFF:
case 0x04200000 ... 0x042FFFFF: case 0x04200000 ... 0x042FFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x04900000 ... 0x04FFFFFF:
case 0x1FC00800 ... 0xFFFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF:
return 0; return 0;
default: default:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc); Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
} }
} }
template<> void Mem::Write<u8>(Registers& regs, u32 paddr, u32 val) { template <>
SI& si = mmio.si; void Mem::Write<u8>(Registers &regs, u32 paddr, u32 val) {
SI &si = mmio.si;
switch (paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
mmio.rdp.WriteRDRAM<u8>(paddr, val); mmio.rdp.WriteRDRAM<u8>(paddr, val);
break; break;
case RSP_MEM_REGION: { case RSP_MEM_REGION:
{
val = val << (8 * (3 - (paddr & 3))); val = val << (8 * (3 - (paddr & 3)));
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
paddr = (paddr & 0xFFF) & ~3; paddr = (paddr & 0xFFF) & ~3;
Util::WriteAccess<u32>(dest, paddr, val); Util::WriteAccess<u32>(dest, paddr, val);
} break; }
case REGION_CART: break;
Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val); case REGION_CART:
mmio.pi.BusWrite<u8, false>(paddr, val); Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
break; mmio.pi.BusWrite<u8, false>(paddr, val);
case MMIO_REGION: break;
Util::panic("MMIO Write<u8>!"); case MMIO_REGION:
case PIF_RAM_REGION: Util::panic("MMIO Write<u8>!");
val = val << (8 * (3 - (paddr & 3))); case PIF_RAM_REGION:
paddr = (paddr - PIF_RAM_REGION_START) & ~3; val = val << (8 * (3 - (paddr & 3)));
Util::WriteAccess<u32>(si.pif.ram, paddr, htobe32(val)); paddr = (paddr - PIF_RAM_REGION_START) & ~3;
si.pif.ProcessCommands(*this); Util::WriteAccess<u32>(si.pif.ram, paddr, htobe32(val));
break; si.pif.ProcessCommands(*this);
case 0x00800000 ... 0x03EFFFFF: break;
case 0x04200000 ... 0x042FFFFF: case 0x00800000 ... 0x03EFFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x04200000 ... 0x042FFFFF:
case PIF_ROM_REGION: case 0x04900000 ... 0x04FFFFFF:
case 0x1FC00800 ... 0x7FFFFFFF: case PIF_ROM_REGION:
case 0x80000000 ... 0xFFFFFFFF: case 0x1FC00800 ... 0x7FFFFFFF:
break; case 0x80000000 ... 0xFFFFFFFF:
default: break;
Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val, default:
(u64) regs.pc); Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
} }
} }
template<> void Mem::Write<u16>(Registers& regs, u32 paddr, u32 val) { template <>
SI& si = mmio.si; void Mem::Write<u16>(Registers &regs, u32 paddr, u32 val) {
SI &si = mmio.si;
switch (paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
mmio.rdp.WriteRDRAM<u16>(paddr, val); mmio.rdp.WriteRDRAM<u16>(paddr, val);
break; break;
case RSP_MEM_REGION: { case RSP_MEM_REGION:
{
val = val << (16 * !(paddr & 2)); val = val << (16 * !(paddr & 2));
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
paddr = (paddr & 0xFFF) & ~3; paddr = (paddr & 0xFFF) & ~3;
Util::WriteAccess<u32>(dest, paddr, val); Util::WriteAccess<u32>(dest, paddr, val);
} break; }
case REGION_CART: break;
Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val); case REGION_CART:
mmio.pi.BusWrite<u16, false>(paddr, val); Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
break; mmio.pi.BusWrite<u16, false>(paddr, val);
case MMIO_REGION: break;
Util::panic("MMIO Write<u16>!"); case MMIO_REGION:
case PIF_RAM_REGION: Util::panic("MMIO Write<u16>!");
val = val << (16 * !(paddr & 2)); case PIF_RAM_REGION:
paddr &= ~3; val = val << (16 * !(paddr & 2));
Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val)); paddr &= ~3;
si.pif.ProcessCommands(*this); Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val));
break; si.pif.ProcessCommands(*this);
case 0x00800000 ... 0x03EFFFFF: break;
case 0x04200000 ... 0x042FFFFF: case 0x00800000 ... 0x03EFFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x04200000 ... 0x042FFFFF:
case PIF_ROM_REGION: case 0x04900000 ... 0x04FFFFFF:
case 0x1FC00800 ... 0x7FFFFFFF: case PIF_ROM_REGION:
case 0x80000000 ... 0xFFFFFFFF: case 0x1FC00800 ... 0x7FFFFFFF:
break; case 0x80000000 ... 0xFFFFFFFF:
default: break;
Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val, default:
(u64) regs.pc); Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
} }
} }
template<> void Mem::Write<u32>(Registers& regs, u32 paddr, u32 val) { template <>
SI& si = mmio.si; void Mem::Write<u32>(Registers &regs, u32 paddr, u32 val) {
SI &si = mmio.si;
switch(paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
mmio.rdp.WriteRDRAM<u32>(paddr, val); mmio.rdp.WriteRDRAM<u32>(paddr, val);
break; break;
case RSP_MEM_REGION: { case RSP_MEM_REGION:
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; {
auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
Util::WriteAccess<u32>(dest, paddr & 0xfff, val); Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
} break; }
case REGION_CART: break;
Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val); case REGION_CART:
mmio.pi.BusWrite<u32, false>(paddr, val); Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
break; mmio.pi.BusWrite<u32, false>(paddr, val);
case MMIO_REGION: break;
mmio.Write(paddr, val); case MMIO_REGION:
break; mmio.Write(paddr, val);
case PIF_RAM_REGION: break;
Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val)); case PIF_RAM_REGION:
si.pif.ProcessCommands(*this); Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val));
break; si.pif.ProcessCommands(*this);
case 0x00800000 ... 0x03EFFFFF: break;
case 0x04200000 ... 0x042FFFFF: case 0x00800000 ... 0x03EFFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x04200000 ... 0x042FFFFF:
case PIF_ROM_REGION: case 0x04900000 ... 0x04FFFFFF:
case 0x1FC00800 ... 0x7FFFFFFF: case PIF_ROM_REGION:
case 0x80000000 ... 0xFFFFFFFF: break; case 0x1FC00800 ... 0x7FFFFFFF:
default: Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val, (u64)regs.pc); case 0x80000000 ... 0xFFFFFFFF:
break;
default:
Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
} }
} }
void Mem::Write(Registers& regs, u32 paddr, u64 val) { void Mem::Write(Registers &regs, u32 paddr, u64 val) {
SI& si = mmio.si; SI &si = mmio.si;
switch (paddr) { switch (paddr) {
case RDRAM_REGION: case RDRAM_REGION:
mmio.rdp.WriteRDRAM<u64>(paddr, val); mmio.rdp.WriteRDRAM<u64>(paddr, val);
break; break;
case RSP_MEM_REGION: { case RSP_MEM_REGION:
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem; {
auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
val >>= 32; val >>= 32;
Util::WriteAccess<u32>(dest, paddr & 0xfff, val); Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
} break; }
case REGION_CART: break;
Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val); case REGION_CART:
mmio.pi.BusWrite<false>(paddr, val); Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
break; mmio.pi.BusWrite<false>(paddr, val);
case MMIO_REGION: break;
Util::panic("MMIO Write!"); case MMIO_REGION:
case PIF_RAM_REGION: Util::panic("MMIO Write!");
Util::WriteAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe64(val)); case PIF_RAM_REGION:
si.pif.ProcessCommands(*this); Util::WriteAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe64(val));
break; si.pif.ProcessCommands(*this);
case 0x00800000 ... 0x03EFFFFF: break;
case 0x04200000 ... 0x042FFFFF: case 0x00800000 ... 0x03EFFFFF:
case 0x04900000 ... 0x04FFFFFF: case 0x04200000 ... 0x042FFFFF:
case 0x1FC00000 ... 0x1FC007BF: case 0x04900000 ... 0x04FFFFFF:
case 0x1FC00800 ... 0x7FFFFFFF: case 0x1FC00000 ... 0x1FC007BF:
case 0x80000000 ... 0xFFFFFFFF: break; case 0x1FC00800 ... 0x7FFFFFFF:
default: case 0x80000000 ... 0xFFFFFFFF:
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val, break;
(u64) regs.pc); default:
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64)regs.pc);
} }
} }
template <> u32 Mem::BackupRead<u32>(u32 addr) { template <>
switch(saveType) { u32 Mem::BackupRead<u32>(u32 addr) {
case SAVE_NONE: return 0;
case SAVE_EEPROM_4k: case SAVE_EEPROM_16k:
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
return 0;
case SAVE_FLASH_1m:
return flash.Read<u32>(addr);
case SAVE_SRAM_256k:
return 0xFFFFFFFF;
default:
Util::panic("Backup read word with unknown save type");
}
}
template <> u8 Mem::BackupRead<u8>(u32 addr) {
switch (saveType) { switch (saveType) {
case SAVE_NONE: return 0; case SAVE_NONE:
case SAVE_EEPROM_4k: case SAVE_EEPROM_16k: return 0;
case SAVE_EEPROM_4k:
case SAVE_EEPROM_16k:
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
return 0;
case SAVE_FLASH_1m:
return flash.Read<u32>(addr);
case SAVE_SRAM_256k:
return 0xFFFFFFFF;
default:
Util::panic("Backup read word with unknown save type");
}
}
template <>
u8 Mem::BackupRead<u8>(u32 addr) {
switch (saveType) {
case SAVE_NONE:
return 0;
case SAVE_EEPROM_4k:
case SAVE_EEPROM_16k:
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read"); Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
return 0; return 0;
case SAVE_FLASH_1m: case SAVE_FLASH_1m:
@@ -453,8 +504,7 @@ template <> u8 Mem::BackupRead<u8>(u32 addr) {
if (saveData.is_mapped()) { if (saveData.is_mapped()) {
assert(addr < saveData.size()); assert(addr < saveData.size());
return saveData[addr]; return saveData[addr];
} } else {
else {
Util::panic("Invalid backup Read<u8> if save data is not initialized"); Util::panic("Invalid backup Read<u8> if save data is not initialized");
} }
default: default:
@@ -462,43 +512,47 @@ template <> u8 Mem::BackupRead<u8>(u32 addr) {
} }
} }
template <> void Mem::BackupWrite<u32>(u32 addr, u32 val) { template <>
switch(saveType) { void Mem::BackupWrite<u32>(u32 addr, u32 val) {
case SAVE_NONE: switch (saveType) {
Util::warn("Accessing cartridge with save type SAVE_NONE in write word"); case SAVE_NONE:
break; Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
case SAVE_EEPROM_4k: case SAVE_EEPROM_16k: break;
Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word"); case SAVE_EEPROM_4k:
case SAVE_FLASH_1m: case SAVE_EEPROM_16k:
flash.Write<u32>(addr, val); Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
break; case SAVE_FLASH_1m:
case SAVE_SRAM_256k: flash.Write<u32>(addr, val);
break; break;
default: case SAVE_SRAM_256k:
Util::panic("Backup read word with unknown save type"); break;
default:
Util::panic("Backup read word with unknown save type");
} }
} }
template <> void Mem::BackupWrite<u8>(u32 addr, u8 val) { template <>
switch(saveType) { void Mem::BackupWrite<u8>(u32 addr, u8 val) {
case SAVE_NONE: switch (saveType) {
Util::warn("Accessing cartridge with save type SAVE_NONE in write word"); case SAVE_NONE:
break; Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
case SAVE_EEPROM_4k: case SAVE_EEPROM_16k: break;
Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word"); case SAVE_EEPROM_4k:
case SAVE_FLASH_1m: case SAVE_EEPROM_16k:
flash.Write<u8>(addr, val); Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
break; case SAVE_FLASH_1m:
case SAVE_SRAM_256k: flash.Write<u8>(addr, val);
if(saveData.is_mapped()) { break;
assert(addr < saveData.size()); case SAVE_SRAM_256k:
saveData[addr] = val; if (saveData.is_mapped()) {
} else { assert(addr < saveData.size());
Util::panic("Invalid backup Write<u8> if save data is not initialized"); saveData[addr] = val;
} } else {
break; Util::panic("Invalid backup Write<u8> if save data is not initialized");
default: }
Util::panic("Backup read word with unknown save type"); break;
default:
Util::panic("Backup read word with unknown save type");
} }
} }
@@ -517,9 +571,9 @@ std::vector<u8> Mem::Serialize() {
return res; return res;
} }
void Mem::Deserialize(const std::vector<u8>& data) { void Mem::Deserialize(const std::vector<u8> &data) {
mmio.Deserialize(std::vector<u8>(data.begin(), data.begin() + mmioSize)); mmio.Deserialize(std::vector<u8>(data.begin(), data.begin() + mmioSize));
flash.Deserialize(std::vector<u8>(data.begin() + mmioSize, data.begin() + mmioSize + flashSize)); flash.Deserialize(std::vector<u8>(data.begin() + mmioSize, data.begin() + mmioSize + flashSize));
memcpy(saveData.data(), data.data() + mmioSize + flashSize, saveData.size()); memcpy(saveData.data(), data.data() + mmioSize + flashSize, saveData.size());
} }
} } // namespace n64

57
src/backend/core/Mem.hpp
View File

@@ -1,13 +1,13 @@
#pragma once #pragma once
#include <common.hpp> #include <File.hpp>
#include <backend/MemoryRegions.hpp> #include <GameDB.hpp>
#include <backend/core/MMIO.hpp>
#include <vector>
#include <log.hpp>
#include <Registers.hpp> #include <Registers.hpp>
#include <algorithm> #include <algorithm>
#include <GameDB.hpp> #include <backend/MemoryRegions.hpp>
#include <File.hpp> #include <backend/core/MMIO.hpp>
#include <common.hpp>
#include <log.hpp>
#include <vector>
namespace n64 { namespace n64 {
struct ROMHeader { struct ROMHeader {
@@ -37,22 +37,20 @@ struct ROM {
bool pal; bool pal;
}; };
enum class FlashState : u8 { enum class FlashState : u8 { Idle, Erase, Write, Read, Status };
Idle, Erase, Write, Read, Status
};
struct Flash { struct Flash {
explicit Flash(mio::mmap_sink&); explicit Flash(mio::mmap_sink &);
~Flash() = default; ~Flash() = default;
void Reset(); void Reset();
void Load(SaveType, const std::string&); void Load(SaveType, const std::string &);
FlashState state{}; FlashState state{};
u64 status{}; u64 status{};
size_t eraseOffs{}; size_t eraseOffs{};
size_t writeOffs{}; size_t writeOffs{};
std::array<u8, 128> writeBuf{}; std::array<u8, 128> writeBuf{};
std::string flashPath{}; std::string flashPath{};
mio::mmap_sink& saveData; mio::mmap_sink &saveData;
enum FlashCommands : u8 { enum FlashCommands : u8 {
FLASH_COMMAND_EXECUTE = 0xD2, FLASH_COMMAND_EXECUTE = 0xD2,
@@ -72,7 +70,7 @@ struct Flash {
void CommandWrite(); void CommandWrite();
void CommandRead(); void CommandRead();
std::vector<u8> Serialize(); std::vector<u8> Serialize();
void Deserialize(const std::vector<u8>& data); void Deserialize(const std::vector<u8> &data);
template <typename T> template <typename T>
void Write(u32 index, T val); void Write(u32 index, T val);
template <typename T> template <typename T>
@@ -81,28 +79,24 @@ struct Flash {
struct Mem { struct Mem {
~Mem() = default; ~Mem() = default;
Mem(Registers&, ParallelRDP&); Mem(Registers &, ParallelRDP &);
void Reset(); void Reset();
void LoadSRAM(SaveType, fs::path); void LoadSRAM(SaveType, fs::path);
static std::vector<u8> OpenROM(const std::string&, size_t&); static std::vector<u8> OpenROM(const std::string &, size_t &);
static std::vector<u8> OpenArchive(const std::string&, size_t&); static std::vector<u8> OpenArchive(const std::string &, size_t &);
void LoadROM(bool, const std::string&); void LoadROM(bool, const std::string &);
[[nodiscard]] auto GetRDRAMPtr() -> u8* { [[nodiscard]] auto GetRDRAMPtr() -> u8 * { return mmio.rdp.rdram.data(); }
return mmio.rdp.rdram.data();
}
[[nodiscard]] auto GetRDRAM() -> std::vector<u8>& { [[nodiscard]] auto GetRDRAM() -> std::vector<u8> & { return mmio.rdp.rdram; }
return mmio.rdp.rdram;
}
std::vector<u8> Serialize(); std::vector<u8> Serialize();
void Deserialize(const std::vector<u8>&); void Deserialize(const std::vector<u8> &);
template <typename T> template <typename T>
T Read(Registers&, u32); T Read(Registers &, u32);
template <typename T> template <typename T>
void Write(Registers&, u32, u32); void Write(Registers &, u32, u32);
void Write(Registers&, u32, u64); void Write(Registers &, u32, u64);
template <typename T> template <typename T>
T BackupRead(u32); T BackupRead(u32);
@@ -135,6 +129,7 @@ struct Mem {
ROM rom; ROM rom;
SaveType saveType = SAVE_NONE; SaveType saveType = SAVE_NONE;
Flash flash; Flash flash;
private: private:
friend struct SI; friend struct SI;
friend struct PI; friend struct PI;
@@ -148,9 +143,7 @@ private:
FORCE_INLINE bool IsROMPAL() { FORCE_INLINE bool IsROMPAL() {
static const char pal_codes[] = {'D', 'F', 'I', 'P', 'S', 'U', 'X', 'Y'}; static const char pal_codes[] = {'D', 'F', 'I', 'P', 'S', 'U', 'X', 'Y'};
return std::any_of(std::begin(pal_codes), std::end(pal_codes), [this](char a) { return std::any_of(std::begin(pal_codes), std::end(pal_codes), [this](char a) { return rom.cart[0x3d] == a; });
return rom.cart[0x3d] == a;
});
} }
}; };
} } // namespace n64

877
src/backend/core/jit/instructions.cpp
View File

File diff suppressed because it is too large Load Diff

92
src/backend/core/registers/Registers.cpp
View File

@@ -1,16 +1,15 @@
#include <core/registers/Registers.hpp> #include <core/registers/Registers.hpp>
namespace n64 { namespace n64 {
Registers::Registers() : cop0(*this), cop1(*this) { Registers::Registers() : cop0(*this), cop1(*this) { Reset(); }
Reset();
}
void Registers::Reset() { void Registers::Reset() {
hi = 0; hi = 0;
lo = 0; lo = 0;
delaySlot = false; delaySlot = false;
prevDelaySlot = false; prevDelaySlot = false;
memset(gpr, 0, 32*sizeof(s64)); gpr.fill(0);
gprIsConstant.fill(false);
cop0.Reset(); cop0.Reset();
cop1.Reset(); cop1.Reset();
@@ -31,79 +30,112 @@ void Registers::SetPC32(s32 val) {
nextPC = pc + 4; nextPC = pc + 4;
} }
template <> u64 Registers::Read<u64>(size_t idx) { template <>
u64 Registers::Read<u64>(size_t idx) {
return idx == 0 ? 0 : gpr[idx]; return idx == 0 ? 0 : gpr[idx];
} }
template <> s64 Registers::Read<s64>(size_t idx) { template <>
s64 Registers::Read<s64>(size_t idx) {
return s64(Read<u64>(idx)); return s64(Read<u64>(idx));
} }
template <> u32 Registers::Read<u32>(size_t idx) { template <>
u32 Registers::Read<u32>(size_t idx) {
return idx == 0 ? 0 : gpr[idx]; return idx == 0 ? 0 : gpr[idx];
} }
template <> s32 Registers::Read<s32>(size_t idx) { template <>
s32 Registers::Read<s32>(size_t idx) {
return s32(Read<u32>(idx)); return s32(Read<u32>(idx));
} }
template <> u16 Registers::Read<u16>(size_t idx) { template <>
u16 Registers::Read<u16>(size_t idx) {
return idx == 0 ? 0 : gpr[idx]; return idx == 0 ? 0 : gpr[idx];
} }
template <> s16 Registers::Read<s16>(size_t idx) { template <>
s16 Registers::Read<s16>(size_t idx) {
return s16(Read<u16>(idx)); return s16(Read<u16>(idx));
} }
template <> u8 Registers::Read<u8>(size_t idx) { template <>
u8 Registers::Read<u8>(size_t idx) {
return idx == 0 ? 0 : gpr[idx]; return idx == 0 ? 0 : gpr[idx];
} }
template <> s8 Registers::Read<s8>(size_t idx) { template <>
s8 Registers::Read<s8>(size_t idx) {
return s8(Read<u8>(idx)); return s8(Read<u8>(idx));
} }
template <> void Registers::Write<bool>(size_t idx, bool v) { template <>
if(idx == 0) return; void Registers::Write<bool>(size_t idx, bool v) {
if (idx == 0)
return;
gpr[idx] = v; gpr[idx] = v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<u64>(size_t idx, u64 v) { template <>
if(idx == 0) return; void Registers::Write<u64>(size_t idx, u64 v) {
if (idx == 0)
return;
gpr[idx] = v; gpr[idx] = v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<s64>(size_t idx, s64 v) { template <>
void Registers::Write<s64>(size_t idx, s64 v) {
Write<u64>(idx, v); Write<u64>(idx, v);
} }
template <> void Registers::Write<u32>(size_t idx, u32 v) { template <>
if(idx == 0) return; void Registers::Write<u32>(size_t idx, u32 v) {
if (idx == 0)
return;
gpr[idx] = (u32)v; gpr[idx] = (u32)v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<s32>(size_t idx, s32 v) { template <>
if(idx == 0) return; void Registers::Write<s32>(size_t idx, s32 v) {
if (idx == 0)
return;
gpr[idx] = v; gpr[idx] = v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<u16>(size_t idx, u16 v) { template <>
if(idx == 0) return; void Registers::Write<u16>(size_t idx, u16 v) {
if (idx == 0)
return;
gpr[idx] = (u16)v; gpr[idx] = (u16)v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<s16>(size_t idx, s16 v) { template <>
if(idx == 0) return; void Registers::Write<s16>(size_t idx, s16 v) {
if (idx == 0)
return;
gpr[idx] = v; gpr[idx] = v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<u8>(size_t idx, u8 v) { template <>
if(idx == 0) return; void Registers::Write<u8>(size_t idx, u8 v) {
if (idx == 0)
return;
gpr[idx] = (u8)v; gpr[idx] = (u8)v;
gprIsConstant[idx] = true;
} }
template <> void Registers::Write<s8>(size_t idx, s8 v) { template <>
if(idx == 0) return; void Registers::Write<s8>(size_t idx, s8 v) {
if (idx == 0)
return;
gpr[idx] = v; gpr[idx] = v;
gprIsConstant[idx] = true;
} }
} } // namespace n64

19
src/backend/core/registers/Registers.hpp
View File

@@ -1,4 +1,5 @@
#pragma once #pragma once
#include <array>
#include <backend/core/registers/Cop1.hpp> #include <backend/core/registers/Cop1.hpp>
namespace n64 { namespace n64 {
@@ -9,15 +10,14 @@ struct Registers {
void SetPC32(s32); void SetPC32(s32);
bool IsRegConstant(u32 index) { bool IsRegConstant(u32 index) {
if(index == 0) return true; if (index == 0)
return true;
return gprIsConstant[index]; return gprIsConstant[index];
} }
bool IsRegConstant(u32 first, u32 second) { bool IsRegConstant(u32 first, u32 second) { return IsRegConstant(first) && IsRegConstant(second); }
return IsRegConstant(first) && IsRegConstant(second);
}
bool gprIsConstant[32]{}; std::array<bool, 32> gprIsConstant{};
bool loIsConstant = false, hiIsConstant = false; bool loIsConstant = false, hiIsConstant = false;
Cop0 cop0; Cop0 cop0;
Cop1 cop1; Cop1 cop1;
@@ -27,9 +27,7 @@ struct Registers {
u32 steps = 0; u32 steps = 0;
u32 extraCycles = 0; u32 extraCycles = 0;
void CpuStall(u32 cycles) { void CpuStall(u32 cycles) { extraCycles += cycles; }
extraCycles += cycles;
}
u32 PopStalledCycles() { u32 PopStalledCycles() {
u32 ret = extraCycles; u32 ret = extraCycles;
@@ -41,7 +39,8 @@ struct Registers {
T Read(size_t); T Read(size_t);
template <typename T> template <typename T>
void Write(size_t, T); void Write(size_t, T);
private: private:
s64 gpr[32]{}; std::array<s64, 32> gpr{};
}; };
} } // namespace n64

37
src/frontend/KaizenQt.cpp
View File

@@ -7,14 +7,15 @@
namespace fs = std::filesystem; namespace fs = std::filesystem;
KaizenQt::KaizenQt() noexcept : QWidget(nullptr) { KaizenQt::KaizenQt() noexcept :
QWidget(nullptr) {
mainWindow = std::make_unique<MainWindowController>(); mainWindow = std::make_unique<MainWindowController>();
settingsWindow = std::make_unique<SettingsWindow>(); settingsWindow = std::make_unique<SettingsWindow>();
emuThread = std::make_unique<EmuThread>( emuThread = std::make_unique<EmuThread>(
std::move(mainWindow->view.vulkanWidget->instance), std::move(mainWindow->view.vulkanWidget->instance),
std::move(mainWindow->view.vulkanWidget->wsiPlatform), std::move(mainWindow->view.vulkanWidget->wsiPlatform),
std::move(mainWindow->view.vulkanWidget->windowInfo), std::move(mainWindow->view.vulkanWidget->windowInfo),
*settingsWindow); *settingsWindow);
ConnectMainWindowSignalsToSlots(); ConnectMainWindowSignalsToSlots();
@@ -43,18 +44,18 @@ void KaizenQt::ConnectMainWindowSignalsToSlots() noexcept {
connect(mainWindow.get(), &MainWindowController::Pause, emuThread.get(), &EmuThread::TogglePause); connect(mainWindow.get(), &MainWindowController::Pause, emuThread.get(), &EmuThread::TogglePause);
} }
void KaizenQt::dragEnterEvent(QDragEnterEvent* event) { void KaizenQt::dragEnterEvent(QDragEnterEvent *event) {
if (event->mimeData()->hasUrls()) { if (event->mimeData()->hasUrls()) {
event->acceptProposedAction(); event->acceptProposedAction();
} }
} }
void KaizenQt::dropEvent(QDropEvent* event) { void KaizenQt::dropEvent(QDropEvent *event) {
auto path = event->mimeData()->urls()[0].toLocalFile(); auto path = event->mimeData()->urls()[0].toLocalFile();
LoadROM(path); LoadROM(path);
} }
void KaizenQt::LoadROM(const QString& fileName) noexcept { void KaizenQt::LoadROM(const QString &fileName) noexcept {
mainWindow->view.actionPause->setEnabled(true); mainWindow->view.actionPause->setEnabled(true);
mainWindow->view.actionReset->setEnabled(true); mainWindow->view.actionReset->setEnabled(true);
mainWindow->view.actionStop->setEnabled(true); mainWindow->view.actionStop->setEnabled(true);
@@ -64,25 +65,25 @@ void KaizenQt::LoadROM(const QString& fileName) noexcept {
} }
void KaizenQt::Quit() noexcept { void KaizenQt::Quit() noexcept {
if(emuThread) { if (emuThread) {
emuThread->SetRender(false); emuThread->SetRender(false);
emuThread->Stop(); emuThread->Stop();
} }
QApplication::quit(); QApplication::quit();
} }
void KaizenQt::LoadTAS(const QString& fileName) const noexcept { void KaizenQt::LoadTAS(const QString &fileName) const noexcept {
emuThread->core.LoadTAS(fs::path(fileName.toStdString())); emuThread->core.LoadTAS(fs::path(fileName.toStdString()));
} }
void KaizenQt::keyPressEvent(QKeyEvent *e) { void KaizenQt::keyPressEvent(QKeyEvent *e) {
emuThread->core.pause = true; emuThread->core.pause = true;
n64::Mem& mem = emuThread->core.cpu->GetMem(); n64::Mem &mem = emuThread->core.cpu->GetMem();
n64::PIF& pif = mem.mmio.si.pif; n64::PIF &pif = mem.mmio.si.pif;
auto k = static_cast<Qt::Key>(e->key()); auto k = static_cast<Qt::Key>(e->key());
for(int i = 0; i < 14; i++) { for (int i = 0; i < 14; i++) {
if(k == settingsWindow->keyMap[i]) if (k == settingsWindow->keyMap[i])
pif.UpdateButton(0, static_cast<n64::Controller::Key>(i), true); pif.UpdateButton(0, static_cast<n64::Controller::Key>(i), true);
} }
@@ -101,12 +102,12 @@ void KaizenQt::keyPressEvent(QKeyEvent *e) {
void KaizenQt::keyReleaseEvent(QKeyEvent *e) { void KaizenQt::keyReleaseEvent(QKeyEvent *e) {
emuThread->core.pause = true; emuThread->core.pause = true;
n64::Mem& mem = emuThread->core.cpu->GetMem(); n64::Mem &mem = emuThread->core.cpu->GetMem();
n64::PIF& pif = mem.mmio.si.pif; n64::PIF &pif = mem.mmio.si.pif;
auto k = static_cast<Qt::Key>(e->key()); auto k = static_cast<Qt::Key>(e->key());
for(int i = 0; i < 14; i++) { for (int i = 0; i < 14; i++) {
if(k == settingsWindow->keyMap[i]) if (k == settingsWindow->keyMap[i])
pif.UpdateButton(0, static_cast<n64::Controller::Key>(i), false); pif.UpdateButton(0, static_cast<n64::Controller::Key>(i), false);
} }