start implementing cached interpreter

src/backend/core/Interpreter.cpp

@@ -21,7 +21,19 @@ void Interpreter::CheckCompareInterrupt() const {
     }
 }
 
-u32 Interpreter::Step() {
+bool Interpreter::Fetch(Instruction &instr) {
+    u32 paddr = 0;
+    if (!regs.cop0.MapVAddr(Cop0::LOAD, regs.pc, paddr)) {
+        regs.cop0.HandleTLBException(regs.pc);
+        regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.pc);
+        return false;
+    }
+
+    instr = mem.Read<u32>(paddr);
+    return true;
+}
+
+bool Interpreter::MaybeAdvance() {
     CheckCompareInterrupt();
 
     regs.prevDelaySlot = regs.delaySlot;
@@ -30,29 +42,57 @@ u32 Interpreter::Step() {
     if (check_address_error(0b11, u64(regs.pc))) [[unlikely]] {
         regs.cop0.HandleTLBException(regs.pc);
         regs.cop0.FireException(Cop0::ExceptionCode::AddressErrorLoad, 0, regs.pc);
-        return 1;
+        return false;
     }
 
-    u32 paddr = 0;
-    if (!regs.cop0.MapVAddr(Cop0::LOAD, regs.pc, paddr)) {
-        regs.cop0.HandleTLBException(regs.pc);
-        regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::LOAD), 0, regs.pc);
-        return 1;
-    }
-
-    const u32 instruction = mem.Read<u32>(paddr);
-
     if (ShouldServiceInterrupt()) {
         regs.cop0.FireException(Cop0::ExceptionCode::Interrupt, 0, regs.pc);
-        return 1;
+        return false;
     }
 
     regs.oldPC = regs.pc;
     regs.pc = regs.nextPC;
     regs.nextPC += 4;
 
-    Exec(instruction);
+    return true;
+}
+
+bool Interpreter::FetchThenMaybeAdvance(Instruction &instr) {
+    CheckCompareInterrupt();
+
+    regs.prevDelaySlot = regs.delaySlot;
+    regs.delaySlot = false;
+
+    if (check_address_error(0b11, u64(regs.pc))) [[unlikely]] {
+        regs.cop0.HandleTLBException(regs.pc);
+        regs.cop0.FireException(Cop0::ExceptionCode::AddressErrorLoad, 0, regs.pc);
+        return false;
+    }
+
+    if (!Fetch(instr))
+        return false;
+
+    if (ShouldServiceInterrupt()) {
+        regs.cop0.FireException(Cop0::ExceptionCode::Interrupt, 0, regs.pc);
+        return false;
+    }
+
+    regs.oldPC = regs.pc;
+    regs.pc = regs.nextPC;
+    regs.nextPC += 4;
+
+    return true;
+}
+
+u32 Interpreter::Step() {
+    Instruction instr;
+    if (!FetchThenMaybeAdvance(instr))
+        return 1;
+
+    DecodeExecute(instr);
 
     return 1;
 }
+
+u32 Interpreter::ExecuteCached() {}
 } // namespace n64