Start work on a debug view

src/backend/core/BaseCPU.hpp

@@ -12,6 +12,6 @@ struct BaseCPU {
   virtual void Deserialize(const std::vector<u8> &) = 0;
   virtual Mem &GetMem() = 0;
   virtual Registers &GetRegs() = 0;
-  [[nodiscard]] virtual Disassembler::DisassemblyResult Disassemble(u32, u32) const = 0;
+  [[nodiscard]] virtual Disassembler::DisassemblyResult Disassemble(u32) = 0;
 };
 } // namespace n64

src/backend/core/Disassembler.hpp

@@ -13,7 +13,7 @@ struct Disassembler {
     std::array<std::string, 3> ops{};
   };
 
-  static Disassembler &instance(bool rsp = false) {
+  static Disassembler &GetInstance(bool rsp = false) {
     static Disassembler ret(rsp);
     return ret;
   }

src/backend/core/Interpreter.cpp

@@ -21,8 +21,12 @@ void Interpreter::CheckCompareInterrupt() {
   }
 }
 
-Disassembler::DisassemblyResult Interpreter::Disassemble(const u32 address, const u32 instruction) const {
-  return Disassembler::instance().Disassemble(address, instruction);
+Disassembler::DisassemblyResult Interpreter::Disassemble(const u32 address) {
+  u32 paddr;
+  if (!regs.cop0.MapVAddr(Cop0::LOAD, address, paddr)) {
+    return {};
+  }
+  return Disassembler::GetInstance().Disassemble(address, mem.Read<u32>(regs, paddr));
 }
 
 int Interpreter::Step() {

src/backend/core/Interpreter.hpp

@@ -20,7 +20,7 @@ struct Interpreter : BaseCPU {
   Mem &GetMem() override { return mem; }
 
   Registers &GetRegs() override { return regs; }
-  [[nodiscard]] Disassembler::DisassemblyResult Disassemble(u32, u32) const override;
+  [[nodiscard]] Disassembler::DisassemblyResult Disassemble(u32) override;
 
 private:
   Registers regs;

src/backend/core/JIT.hpp

@@ -40,7 +40,7 @@ struct JIT : BaseCPU {
 
   Registers &GetRegs() override { return regs; }
 
-  [[nodiscard]] Disassembler::DisassemblyResult Disassemble(u32, u32) const override { return {}; }
+  [[nodiscard]] Disassembler::DisassemblyResult Disassemble(u32) override { return {}; }
 
 private:
   Xbyak::CodeGenerator code{kCodeCacheAllocSize};