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Dynarec + CMake restructure

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This commit is contained in:
CocoSimone
2023-01-02 21:44:24 +01:00
parent 91dc3eabba
commit c915ebc11d
43 changed files with 2004 additions and 422 deletions
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4
src/backend/core/interpreter/CMakeLists.txt Normal file
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@@ -0,0 +1,4 @@
file(GLOB_RECURSE SOURCES *.cpp)
file(GLOB_RECURSE HEADERS *.hpp)
add_library(interpreter ${SOURCES} ${HEADERS})

26
src/backend/core/interpreter/cop/cop1instructions.cpp
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@@ -26,7 +26,7 @@ inline int PushRoundingMode(const FCR31& fcr31) {
if(isnanf(fs) || isnanf(ft)) { \
regs.cop1.fcr31.flag_invalid_operation = true; \
regs.cop1.fcr31.cause_invalid_operation = true; \
FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
FireException(regs, ExceptionCode::FloatingPointError, 1, true); \
return; \
}
@@ -34,7 +34,7 @@ inline int PushRoundingMode(const FCR31& fcr31) {
if(isnan(fs) || isnan(ft)) { \
regs.cop1.fcr31.flag_invalid_operation = true; \
regs.cop1.fcr31.cause_invalid_operation = true; \
FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
FireException(regs, ExceptionCode::FloatingPointError, 1, true); \
return; \
}
#else
@@ -42,7 +42,7 @@ inline int PushRoundingMode(const FCR31& fcr31) {
if(isnanf(fs) || isnanf(ft)) { \
regs.cop1.fcr31.flag_invalid_operation = true; \
regs.cop1.fcr31.cause_invalid_operation = true; \
FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
FireException(regs, ExceptionCode::FloatingPointError, 1, true); \
return; \
}
@@ -50,7 +50,7 @@ inline int PushRoundingMode(const FCR31& fcr31) {
if(isnan(fs) || isnan(ft)) { \
regs.cop1.fcr31.flag_invalid_operation = true; \
regs.cop1.fcr31.cause_invalid_operation = true; \
FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
FireException(regs, ExceptionCode::FloatingPointError, 1, true); \
return; \
}
#endif
@@ -264,7 +264,7 @@ inline bool CalculateCondition(Registers& regs, T fs, T ft, CompConds cond) {
if(std::isnan(fs) || std::isnan(ft)) {
regs.cop1.fcr31.flag_invalid_operation = true;
regs.cop1.fcr31.cause_invalid_operation = true;
FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC);
FireException(regs, ExceptionCode::FloatingPointError, 1, true);
return false;
}
@@ -469,19 +469,19 @@ void Cop1::floorwd(Registers& regs, u32 instr) {
void Cop1::lwc1(Registers& regs, Mem& mem, u32 instr) {
if(!regs.cop0.status.cu1) {
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, true);
return;
}
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
if(addr & 3) {
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
}
u32 physical;
if(!MapVAddr(regs, LOAD, addr, physical)) {
HandleTLBException(regs, addr);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
u32 data = mem.Read32<false>(regs, physical, regs.oldPC);
SetReg<u32>(regs.cop0, FT(instr), data);
@@ -490,19 +490,19 @@ void Cop1::lwc1(Registers& regs, Mem& mem, u32 instr) {
void Cop1::swc1(Registers& regs, Mem& mem, u32 instr) {
if(!regs.cop0.status.cu1) {
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, true);
return;
}
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
if(addr & 3) {
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorStore, 0, true);
}
u32 physical;
if(!MapVAddr(regs, STORE, addr, physical)) {
HandleTLBException(regs, addr);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
mem.Write32<false>(regs, physical, GetReg<u32>(regs.cop0, FT(instr)), regs.oldPC);
}
@@ -510,13 +510,13 @@ void Cop1::swc1(Registers& regs, Mem& mem, u32 instr) {
void Cop1::ldc1(Registers& regs, Mem& mem, u32 instr) {
if(!regs.cop0.status.cu1) {
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, true);
return;
}
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
if(addr & 7) {
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
}
u32 physical;

14
src/backend/core/interpreter/decode.cpp
View File

@@ -2,7 +2,7 @@
#include <log.hpp>
namespace n64 {
void Interpreter::special(Registers& regs, Mem& mem, u32 instr) {
void Interpreter::special(Registers& regs, u32 instr) {
u8 mask = (instr & 0x3F);
// 00rr_rccc
switch (mask) { // TODO: named constants for clearer code
@@ -18,8 +18,8 @@ void Interpreter::special(Registers& regs, Mem& mem, u32 instr) {
case 0x07: srav(regs, instr); break;
case 0x08: jr(regs, instr); break;
case 0x09: jalr(regs, instr); break;
case 0x0C: FireException(regs, ExceptionCode::Syscall, 0, regs.oldPC); break;
case 0x0D: FireException(regs, ExceptionCode::Breakpoint, 0, regs.oldPC); break;
case 0x0C: FireException(regs, ExceptionCode::Syscall, 0, true); break;
case 0x0D: FireException(regs, ExceptionCode::Breakpoint, 0, true); break;
case 0x0F: break; // SYNC
case 0x10: mfhi(regs, instr); break;
case 0x11: mthi(regs, instr); break;
@@ -92,7 +92,7 @@ void Interpreter::regimm(Registers& regs, u32 instr) {
void Interpreter::cop2Decode(Registers& regs, u32 instr) {
if(!regs.cop0.status.cu2) {
FireException(regs, ExceptionCode::CoprocessorUnusable, 2, regs.oldPC);
FireException(regs, ExceptionCode::CoprocessorUnusable, 2, true);
return;
}
switch(RS(instr)) {
@@ -103,7 +103,7 @@ void Interpreter::cop2Decode(Registers& regs, u32 instr) {
case 0x05: dmtc2(regs, instr); break;
case 0x06: ctc2(regs, instr); break;
default:
FireException(regs, ExceptionCode::ReservedInstruction, 2, regs.oldPC);
FireException(regs, ExceptionCode::ReservedInstruction, 2, true);
}
}
@@ -111,7 +111,7 @@ void Interpreter::Exec(Registers& regs, Mem& mem, u32 instr) {
u8 mask = (instr >> 26) & 0x3f;
// 00rr_rccc
switch(mask) { // TODO: named constants for clearer code
case 0x00: special(regs, mem, instr); break;
case 0x00: special(regs, instr); break;
case 0x01: regimm(regs, instr); break;
case 0x02: j(regs, instr); break;
case 0x03: jal(regs, instr); break;
@@ -141,7 +141,7 @@ void Interpreter::Exec(Registers& regs, Mem& mem, u32 instr) {
case 0x19: daddiu(regs, instr); break;
case 0x1A: ldl(regs, mem, instr); break;
case 0x1B: ldr(regs, mem, instr); break;
case 0x1F: FireException(regs, ExceptionCode::ReservedInstruction, 0, regs.oldPC); break;
case 0x1F: FireException(regs, ExceptionCode::ReservedInstruction, 0, true); break;
case 0x20: lb(regs, mem, instr); break;
case 0x21: lh(regs, mem, instr); break;
case 0x22: lwl(regs, mem, instr); break;

58
src/backend/core/interpreter/instructions.cpp
View File

@@ -11,7 +11,7 @@ void Interpreter::add(Registers& regs, u32 instr) {
u32 rt = (s32)regs.gpr[RT(instr)];
u32 result = rs + rt;
if(check_signed_overflow(rs, rt, result)) {
FireException(regs, ExceptionCode::Overflow, 0, regs.oldPC);
FireException(regs, ExceptionCode::Overflow, 0, true);
} else {
regs.gpr[RD(instr)] = s32(result);
}
@@ -29,7 +29,7 @@ void Interpreter::addi(Registers& regs, u32 instr) {
u32 imm = s32(s16(instr));
u32 result = rs + imm;
if(check_signed_overflow(rs, imm, result)) {
FireException(regs, ExceptionCode::Overflow, 0, regs.oldPC);
FireException(regs, ExceptionCode::Overflow, 0, true);
} else {
regs.gpr[RT(instr)] = s32(result);
}
@@ -47,7 +47,7 @@ void Interpreter::dadd(Registers& regs, u32 instr) {
u64 rt = regs.gpr[RT(instr)];
u64 result = rt + rs;
if(check_signed_overflow(rs, rt, result)) {
FireException(regs, ExceptionCode::Overflow, 0, regs.oldPC);
FireException(regs, ExceptionCode::Overflow, 0, true);
} else {
regs.gpr[RD(instr)] = result;
}
@@ -64,7 +64,7 @@ void Interpreter::daddi(Registers& regs, u32 instr) {
u64 rs = regs.gpr[RS(instr)];
u64 result = imm + rs;
if(check_signed_overflow(rs, imm, result)) {
FireException(regs, ExceptionCode::Overflow, 0, regs.oldPC);
FireException(regs, ExceptionCode::Overflow, 0, true);
} else {
regs.gpr[RT(instr)] = result;
}
@@ -201,7 +201,7 @@ void Interpreter::lh(Registers& regs, Mem& mem, u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b1)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
return;
}
@@ -213,14 +213,14 @@ void Interpreter::lw(Registers& regs, Mem& mem, u32 instr) {
u64 address = regs.gpr[RS(instr)] + offset;
if (check_address_error(address, 0b11)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
return;
}
u32 physical;
if (!MapVAddr(regs, LOAD, address, physical)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
regs.gpr[RT(instr)] = (s32)mem.Read32<false>(regs, physical, regs.oldPC);
}
@@ -231,7 +231,7 @@ void Interpreter::ll(Registers& regs, Mem& mem, u32 instr) {
u32 physical;
if (!MapVAddr(regs, LOAD, address, physical)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
regs.gpr[RT(instr)] = (s32)mem.Read32<false>(regs, physical, regs.oldPC);
}
@@ -245,7 +245,7 @@ void Interpreter::lwl(Registers& regs, Mem& mem, u32 instr) {
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
u32 shift = 8 * ((address ^ 0) & 3);
u32 mask = 0xFFFFFFFF << shift;
@@ -260,7 +260,7 @@ void Interpreter::lwr(Registers& regs, Mem& mem, u32 instr) {
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
u32 shift = 8 * ((address ^ 3) & 3);
u32 mask = 0xFFFFFFFF >> shift;
@@ -274,7 +274,7 @@ void Interpreter::ld(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b111)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
return;
}
@@ -287,7 +287,7 @@ void Interpreter::lld(Registers& regs, Mem& mem, u32 instr) {
u32 paddr;
if (!MapVAddr(regs, LOAD, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
regs.gpr[RT(instr)] = mem.Read64<false>(regs, paddr, regs.oldPC);
}
@@ -301,7 +301,7 @@ void Interpreter::ldl(Registers& regs, Mem& mem, u32 instr) {
u32 paddr = 0;
if (!MapVAddr(regs, LOAD, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
s32 shift = 8 * ((address ^ 0) & 7);
u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
@@ -316,7 +316,7 @@ void Interpreter::ldr(Registers& regs, Mem& mem, u32 instr) {
u32 paddr;
if (!MapVAddr(regs, LOAD, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, true);
} else {
s32 shift = 8 * ((address ^ 7) & 7);
u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
@@ -336,7 +336,7 @@ void Interpreter::lhu(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b1)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
return;
}
@@ -348,7 +348,7 @@ void Interpreter::lwu(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b11)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorLoad, 0, true);
return;
}
@@ -365,7 +365,7 @@ void Interpreter::sc(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b11)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorStore, 0, true);
}
if(regs.cop0.llbit) {
@@ -380,7 +380,7 @@ void Interpreter::scd(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b111)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorStore, 0, true);
return;
}
@@ -396,14 +396,14 @@ void Interpreter::sh(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b1)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorStore, 0, true);
return;
}
u32 physical;
if(!MapVAddr(regs, STORE, address, physical)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
mem.Write16<false>(regs, physical, regs.gpr[RT(instr)], regs.oldPC);
}
@@ -414,14 +414,14 @@ void Interpreter::sw(Registers& regs, Mem& mem, u32 instr) {
u64 address = regs.gpr[RS(instr)] + offset;
if (check_address_error(address, 0b11)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorStore, 0, true);
return;
}
u32 physical;
if(!MapVAddr(regs, STORE, address, physical)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
mem.Write32<false>(regs, physical, regs.gpr[RT(instr)], regs.oldPC);
}
@@ -431,14 +431,14 @@ void Interpreter::sd(Registers& regs, Mem& mem, u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(address, 0b11)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
FireException(regs, ExceptionCode::AddressErrorStore, 0, true);
return;
}
u32 physical;
if(!MapVAddr(regs, STORE, address, physical)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
mem.Write64<false>(regs, physical, regs.gpr[RT(instr)], regs.oldPC);
}
@@ -450,7 +450,7 @@ void Interpreter::sdl(Registers& regs, Mem& mem, u32 instr) {
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
s32 shift = 8 * ((address ^ 0) & 7);
u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
@@ -465,7 +465,7 @@ void Interpreter::sdr(Registers& regs, Mem& mem, u32 instr) {
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
s32 shift = 8 * ((address ^ 7) & 7);
u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
@@ -480,7 +480,7 @@ void Interpreter::swl(Registers& regs, Mem& mem, u32 instr) {
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
u32 shift = 8 * ((address ^ 0) & 3);
u32 mask = 0xFFFFFFFF >> shift;
@@ -495,7 +495,7 @@ void Interpreter::swr(Registers& regs, Mem& mem, u32 instr) {
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
HandleTLBException(regs, address);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, true);
} else {
u32 shift = 8 * ((address ^ 3) & 3);
u32 mask = 0xFFFFFFFF << shift;
@@ -524,7 +524,7 @@ void Interpreter::j(Registers& regs, u32 instr) {
s64 address = (regs.oldPC & ~0xfffffff) | target;
if (check_address_error(address, 0b11)) {
HandleTLBException(regs, address);
FireException(regs, ExceptionCode::DataBusError, 0, regs.oldPC);
FireException(regs, ExceptionCode::DataBusError, 0, true);
}
branch(regs, true, address);