Better management of RDRAM accesses
This commit is contained in:
SimoneN64
@@ -9,16 +9,6 @@
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namespace n64 {
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Mem::Mem(Registers& regs, ParallelRDP& parallel) : flash(saveData), mmio(*this, regs, parallel) {
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memset(readPages, 0, PAGE_COUNT);
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memset(writePages, 0, PAGE_COUNT);
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for(u64 i = 0; i < RDRAM_SIZE / PAGE_SIZE; i++) {
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const auto addr = (i * PAGE_SIZE) & RDRAM_DSIZE;
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const auto pointer = (uintptr_t) &mmio.rdp.rdram[addr];
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readPages[i] = pointer;
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writePages[i] = pointer;
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}
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rom.cart.resize(CART_SIZE);
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std::fill(rom.cart.begin(), rom.cart.end(), 0);
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}
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@@ -33,15 +23,6 @@ void Mem::Reset() {
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saveData.unmap();
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}
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mmio.Reset();
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memset(readPages, 0, PAGE_COUNT);
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memset(writePages, 0, PAGE_COUNT);
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for(u64 i = 0; i < RDRAM_SIZE / PAGE_SIZE; i++) {
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const auto addr = (i * PAGE_SIZE) & RDRAM_DSIZE;
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const auto pointer = (uintptr_t) &mmio.rdp.rdram[addr];
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readPages[i] = pointer;
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writePages[i] = pointer;
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}
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}
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void Mem::LoadSRAM(SaveType save_type, fs::path path) {
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@@ -187,317 +168,261 @@ void Mem::LoadROM(bool isArchive, const std::string& filename) {
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}
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template<> u8 Mem::Read(n64::Registers ®s, u32 paddr) {
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const auto page = paddr >> 12;
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const auto offset = paddr & 0xFFF;
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const auto pointer = readPages[page];
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SI& si = mmio.si;
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if(pointer) {
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return ((u8*)pointer)[BYTE_ADDRESS(offset)];
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} else {
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.rdram[BYTE_ADDRESS(paddr)];
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return src[BYTE_ADDRESS(paddr & 0xfff)];
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}
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case REGION_CART:
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return mmio.pi.BusRead<u8, false>(paddr);
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case 0x04040000 ... 0x040FFFFF:
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case 0x04100000 ... 0x041FFFFF:
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case 0x04600000 ... 0x048FFFFF:
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case 0x04300000 ... 0x044FFFFF:
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Util::panic("MMIO Read<u8>!\n");
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case AI_REGION: {
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u32 w = mmio.ai.Read(paddr & ~3);
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int offs = 3 - (paddr & 3);
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return (w >> (offs * 8)) & 0xff;
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}
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case PIF_ROM_REGION:
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return si.pif.bootrom[BYTE_ADDRESS(paddr) - PIF_ROM_REGION_START];
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case PIF_RAM_REGION:
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return si.pif.ram[paddr - PIF_RAM_REGION_START];
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case 0x00800000 ... 0x03EFFFFF: // unused
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case 0x04200000 ... 0x042FFFFF: // unused
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case 0x04900000 ... 0x04FFFFFF: // unused
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case 0x1FC00800 ... 0xFFFFFFFF: // unused
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return 0;
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default:
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Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u8>(paddr);
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return src[BYTE_ADDRESS(paddr & 0xfff)];
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}
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case REGION_CART:
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return mmio.pi.BusRead<u8, false>(paddr);
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case 0x04040000 ... 0x040FFFFF:
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case 0x04100000 ... 0x041FFFFF:
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case 0x04600000 ... 0x048FFFFF:
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case 0x04300000 ... 0x044FFFFF:
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Util::panic("MMIO Read<u8>!\n");
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case AI_REGION: {
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u32 w = mmio.ai.Read(paddr & ~3);
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int offs = 3 - (paddr & 3);
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return (w >> (offs * 8)) & 0xff;
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}
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case PIF_ROM_REGION:
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return si.pif.bootrom[BYTE_ADDRESS(paddr) - PIF_ROM_REGION_START];
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case PIF_RAM_REGION:
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return si.pif.ram[paddr - PIF_RAM_REGION_START];
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case 0x00800000 ... 0x03EFFFFF: // unused
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case 0x04200000 ... 0x042FFFFF: // unused
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case 0x04900000 ... 0x04FFFFFF: // unused
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case 0x1FC00800 ... 0xFFFFFFFF: // unused
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return 0;
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default:
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Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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}
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}
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template<> u16 Mem::Read(n64::Registers ®s, u32 paddr) {
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const auto page = paddr >> 12;
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const auto offset = paddr & 0xFFF;
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const auto pointer = readPages[page];
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SI& si = mmio.si;
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if(pointer) {
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return Util::ReadAccess<u16>((u8*)pointer, HALF_ADDRESS(offset));
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} else {
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switch (paddr) {
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case RDRAM_REGION:
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return Util::ReadAccess<u16>(mmio.rdp.rdram, HALF_ADDRESS(paddr));
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u16>(src, HALF_ADDRESS(paddr & 0xfff));
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u16, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u16>(si.pif.bootrom, HALF_ADDRESS(paddr) - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return be16toh(Util::ReadAccess<u16>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u16>(paddr);
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u16>(src, HALF_ADDRESS(paddr & 0xfff));
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u16, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u16>(si.pif.bootrom, HALF_ADDRESS(paddr) - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return be16toh(Util::ReadAccess<u16>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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}
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}
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template<> u32 Mem::Read(n64::Registers ®s, u32 paddr) {
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const auto page = paddr >> 12;
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const auto offset = paddr & 0xFFF;
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const auto pointer = readPages[page];
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SI& si = mmio.si;
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if(pointer) {
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return Util::ReadAccess<u32>((u8*)pointer, offset);
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} else {
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switch(paddr) {
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case RDRAM_REGION:
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return Util::ReadAccess<u32>(mmio.rdp.rdram, paddr);
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u32>(src, paddr & 0xfff);
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u32, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u32>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return be32toh(Util::ReadAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default:
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Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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switch(paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u32>(paddr);
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u32>(src, paddr & 0xfff);
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u32, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u32>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return be32toh(Util::ReadAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default:
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Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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}
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}
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template<> u64 Mem::Read(n64::Registers ®s, u32 paddr) {
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const auto page = paddr >> 12;
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const auto offset = paddr & 0xFFF;
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const auto pointer = readPages[page];
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SI& si = mmio.si;
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if(pointer) {
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return Util::ReadAccess<u64>((u8*)pointer, offset);
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} else {
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switch (paddr) {
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case RDRAM_REGION:
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return Util::ReadAccess<u64>(mmio.rdp.rdram, paddr);
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u64>(src, paddr & 0xfff);
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u64, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u64>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return be64toh(Util::ReadAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u64>(paddr);
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case RSP_MEM_REGION: {
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auto& src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u64>(src, paddr & 0xfff);
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u64, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u64>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return be64toh(Util::ReadAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
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}
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}
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template<> void Mem::Write<u8>(Registers& regs, u32 paddr, u32 val) {
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const auto page = paddr >> 12;
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const auto offset = paddr & 0xFFF;
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const auto pointer = writePages[page];
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SI& si = mmio.si;
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if(pointer) {
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((u8*)pointer)[BYTE_ADDRESS(offset)] = val;
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} else {
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switch (paddr) {
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case RDRAM_REGION:
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mmio.rdp.rdram[BYTE_ADDRESS(paddr)] = val;
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break;
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case RSP_MEM_REGION: {
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val = val << (8 * (3 - (paddr & 3)));
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auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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paddr = (paddr & 0xFFF) & ~3;
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Util::WriteAccess<u32>(dest, paddr, val);
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} break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
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mmio.pi.BusWrite<u8, false>(paddr, val);
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break;
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case MMIO_REGION:
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Util::panic("MMIO Write<u8>!");
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case PIF_RAM_REGION:
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val = val << (8 * (3 - (paddr & 3)));
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paddr = (paddr - PIF_RAM_REGION_START) & ~3;
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Util::WriteAccess<u32>(si.pif.ram, paddr, htobe32(val));
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si.pif.ProcessCommands(*this);
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break;
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case PIF_ROM_REGION:
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case 0x1FC00800 ... 0x7FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF:
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break;
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default:
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Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
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(u64) regs.pc);
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}
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switch (paddr) {
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case RDRAM_REGION:
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mmio.rdp.WriteRDRAM<u8>(paddr, val);
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break;
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case RSP_MEM_REGION: {
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val = val << (8 * (3 - (paddr & 3)));
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auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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paddr = (paddr & 0xFFF) & ~3;
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Util::WriteAccess<u32>(dest, paddr, val);
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} break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
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mmio.pi.BusWrite<u8, false>(paddr, val);
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break;
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case MMIO_REGION:
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Util::panic("MMIO Write<u8>!");
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case PIF_RAM_REGION:
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val = val << (8 * (3 - (paddr & 3)));
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paddr = (paddr - PIF_RAM_REGION_START) & ~3;
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Util::WriteAccess<u32>(si.pif.ram, paddr, htobe32(val));
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si.pif.ProcessCommands(*this);
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break;
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case PIF_ROM_REGION:
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case 0x1FC00800 ... 0x7FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF:
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break;
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default:
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Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
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(u64) regs.pc);
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}
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}
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template<> void Mem::Write<u16>(Registers& regs, u32 paddr, u32 val) {
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const auto page = paddr >> 12;
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const auto offset = paddr & 0xFFF;
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const auto pointer = writePages[page];
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SI& si = mmio.si;
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if(pointer) {
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Util::WriteAccess<u16>((u8*)pointer, HALF_ADDRESS(offset), val);
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} else {
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switch (paddr) {
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case RDRAM_REGION:
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Util::WriteAccess<u16>(mmio.rdp.rdram, HALF_ADDRESS(paddr), val);
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break;
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case RSP_MEM_REGION: {
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val = val << (16 * !(paddr & 2));
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auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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paddr = (paddr & 0xFFF) & ~3;
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Util::WriteAccess<u32>(dest, paddr, val);
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} break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
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mmio.pi.BusWrite<u16, false>(paddr, val);
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break;
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case MMIO_REGION:
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Util::panic("MMIO Write<u16>!");
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case PIF_RAM_REGION:
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val = val << (16 * !(paddr & 2));
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paddr &= ~3;
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Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val));
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si.pif.ProcessCommands(*this);
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break;
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case PIF_ROM_REGION:
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case 0x1FC00800 ... 0x7FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF:
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break;
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default:
|
||||
Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
switch (paddr) {
|
||||
case RDRAM_REGION:
|
||||
mmio.rdp.WriteRDRAM<u16>(paddr, val);
|
||||
break;
|
||||
case RSP_MEM_REGION: {
|
||||
val = val << (16 * !(paddr & 2));
|
||||
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
|
||||
paddr = (paddr & 0xFFF) & ~3;
|
||||
Util::WriteAccess<u32>(dest, paddr, val);
|
||||
} break;
|
||||
case REGION_CART:
|
||||
Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
|
||||
mmio.pi.BusWrite<u16, false>(paddr, val);
|
||||
break;
|
||||
case MMIO_REGION:
|
||||
Util::panic("MMIO Write<u16>!");
|
||||
case PIF_RAM_REGION:
|
||||
val = val << (16 * !(paddr & 2));
|
||||
paddr &= ~3;
|
||||
Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val));
|
||||
si.pif.ProcessCommands(*this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03EFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x04900000 ... 0x04FFFFFF:
|
||||
case PIF_ROM_REGION:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF:
|
||||
break;
|
||||
default:
|
||||
Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
}
|
||||
|
||||
template<> void Mem::Write<u32>(Registers& regs, u32 paddr, u32 val) {
|
||||
const auto page = paddr >> 12;
|
||||
const auto offset = paddr & 0xFFF;
|
||||
const auto pointer = writePages[page];
|
||||
SI& si = mmio.si;
|
||||
|
||||
if(pointer) {
|
||||
Util::WriteAccess<u32>((u8*)pointer, offset, val);
|
||||
} else {
|
||||
switch(paddr) {
|
||||
case RDRAM_REGION:
|
||||
Util::WriteAccess<u32>(mmio.rdp.rdram, paddr, val);
|
||||
break;
|
||||
case RSP_MEM_REGION: {
|
||||
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
|
||||
Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
|
||||
} break;
|
||||
case REGION_CART:
|
||||
Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
|
||||
mmio.pi.BusWrite<u32, false>(paddr, val);
|
||||
break;
|
||||
case MMIO_REGION:
|
||||
mmio.Write(paddr, val);
|
||||
break;
|
||||
case PIF_RAM_REGION:
|
||||
Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val));
|
||||
si.pif.ProcessCommands(*this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03EFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x04900000 ... 0x04FFFFFF:
|
||||
case PIF_ROM_REGION:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default: Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val, (u64)regs.pc);
|
||||
}
|
||||
switch(paddr) {
|
||||
case RDRAM_REGION:
|
||||
mmio.rdp.WriteRDRAM<u32>(paddr, val);
|
||||
break;
|
||||
case RSP_MEM_REGION: {
|
||||
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
|
||||
Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
|
||||
} break;
|
||||
case REGION_CART:
|
||||
Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
|
||||
mmio.pi.BusWrite<u32, false>(paddr, val);
|
||||
break;
|
||||
case MMIO_REGION:
|
||||
mmio.Write(paddr, val);
|
||||
break;
|
||||
case PIF_RAM_REGION:
|
||||
Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe32(val));
|
||||
si.pif.ProcessCommands(*this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03EFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x04900000 ... 0x04FFFFFF:
|
||||
case PIF_ROM_REGION:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default: Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val, (u64)regs.pc);
|
||||
}
|
||||
}
|
||||
|
||||
void Mem::Write(Registers& regs, u32 paddr, u64 val) {
|
||||
const auto page = paddr >> 12;
|
||||
const auto offset = paddr & 0xFFF;
|
||||
const auto pointer = writePages[page];
|
||||
SI& si = mmio.si;
|
||||
|
||||
if(pointer) {
|
||||
Util::WriteAccess<u64>((u8*)pointer, offset, val);
|
||||
} else {
|
||||
switch (paddr) {
|
||||
case RDRAM_REGION:
|
||||
Util::WriteAccess<u64>(mmio.rdp.rdram, paddr, val);
|
||||
break;
|
||||
case RSP_MEM_REGION: {
|
||||
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
|
||||
val >>= 32;
|
||||
Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
|
||||
} break;
|
||||
case REGION_CART:
|
||||
Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
|
||||
mmio.pi.BusWrite<false>(paddr, val);
|
||||
break;
|
||||
case MMIO_REGION:
|
||||
Util::panic("MMIO Write!");
|
||||
case PIF_RAM_REGION:
|
||||
Util::WriteAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe64(val));
|
||||
si.pif.ProcessCommands(*this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03EFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x04900000 ... 0x04FFFFFF:
|
||||
case 0x1FC00000 ... 0x1FC007BF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default:
|
||||
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
switch (paddr) {
|
||||
case RDRAM_REGION:
|
||||
mmio.rdp.WriteRDRAM<u64>(paddr, val);
|
||||
break;
|
||||
case RSP_MEM_REGION: {
|
||||
auto& dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
|
||||
val >>= 32;
|
||||
Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
|
||||
} break;
|
||||
case REGION_CART:
|
||||
Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
|
||||
mmio.pi.BusWrite<false>(paddr, val);
|
||||
break;
|
||||
case MMIO_REGION:
|
||||
Util::panic("MMIO Write!");
|
||||
case PIF_RAM_REGION:
|
||||
Util::WriteAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START, htobe64(val));
|
||||
si.pif.ProcessCommands(*this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03EFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x04900000 ... 0x04FFFFFF:
|
||||
case 0x1FC00000 ... 0x1FC007BF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default:
|
||||
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user