small MI refactor in preparation of (eventually) implementing the RDRAM interface properly

2026-04-03 11:28:51 +02:00
parent 694b45341a
commit d5024ebbf6
5 changed files with 61 additions and 71 deletions
@@ -28,7 +28,7 @@ auto SI::Read(u32 addr) const -> u32 {
      val |= status.dmaBusy;
      val |= (0 << 1);
      val |= (0 << 3);
-      val |= (mem.mmio.mi.miIntr.si << 12);
+      val |= (mem.mmio.mi.intr.si << 12);
      return val;
    }
  default: