Squashed 'external/parallel-rdp/parallel-rdp-standalone/' content from commit 3f59f61f2c
git-subtree-dir: external/parallel-rdp/parallel-rdp-standalone git-subtree-split: 3f59f61f2c1c56424356003041df5e4a10612049
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SimoneN64
284
parallel-rdp/rdp_device.hpp
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284
parallel-rdp/rdp_device.hpp
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/* Copyright (c) 2020 Themaister
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <memory>
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#include <thread>
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#include <queue>
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#include "device.hpp"
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#include "video_interface.hpp"
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#include "rdp_renderer.hpp"
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#include "rdp_common.hpp"
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#include "command_ring.hpp"
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#include "worker_thread.hpp"
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#include "rdp_dump_write.hpp"
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namespace RDP
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{
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struct RGBA
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{
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uint8_t r, g, b, a;
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};
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enum CommandProcessorFlagBits
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{
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COMMAND_PROCESSOR_FLAG_HOST_VISIBLE_HIDDEN_RDRAM_BIT = 1 << 0,
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COMMAND_PROCESSOR_FLAG_HOST_VISIBLE_TMEM_BIT = 1 << 1,
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COMMAND_PROCESSOR_FLAG_UPSCALING_2X_BIT = 1 << 2,
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COMMAND_PROCESSOR_FLAG_UPSCALING_4X_BIT = 1 << 3,
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COMMAND_PROCESSOR_FLAG_UPSCALING_8X_BIT = 1 << 4,
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COMMAND_PROCESSOR_FLAG_SUPER_SAMPLED_READ_BACK_BIT = 1 << 5,
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COMMAND_PROCESSOR_FLAG_SUPER_SAMPLED_DITHER_BIT = 1 << 6
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};
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using CommandProcessorFlags = uint32_t;
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struct CoherencyCopy
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{
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size_t src_offset = 0;
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size_t mask_offset = 0;
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size_t dst_offset = 0;
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size_t size = 0;
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std::atomic_uint32_t *counter_base = nullptr;
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unsigned counters = 0;
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};
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struct CoherencyOperation
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{
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Vulkan::Fence fence;
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uint64_t timeline_value = 0;
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uint8_t *dst = nullptr;
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const Vulkan::Buffer *src = nullptr;
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std::vector<CoherencyCopy> copies;
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std::atomic_uint32_t *unlock_cookie = nullptr;
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};
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// These options control various behavior when upscaling to workaround glitches which arise naturally as part of upscaling.
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struct Quirks
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{
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inline Quirks()
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{
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u.options.native_resolution_tex_rect = true;
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u.options.native_texture_lod = false;
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}
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inline void set_native_resolution_tex_rect(bool enable)
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{
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u.options.native_resolution_tex_rect = enable;
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}
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inline void set_native_texture_lod(bool enable)
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{
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u.options.native_texture_lod = enable;
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}
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union
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{
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struct Opts
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{
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// If true, force TEX_RECT and TEX_RECT_FLIP to render without upscaling.
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// Works around bilinear filtering bugs in Cycle1/Cycle2 mode where game assumed 1:1 pixel transfer.
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bool native_resolution_tex_rect;
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// Forces LOD to be computed as 1x upscale.
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// Fixes content which relies on LOD computation to select textures in clever ways.
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bool native_texture_lod;
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} options;
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uint32_t words[1];
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} u;
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};
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class CommandProcessor
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{
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public:
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CommandProcessor(Vulkan::Device &device,
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void *rdram_ptr,
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size_t rdram_offset,
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size_t rdram_size,
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size_t hidden_rdram_size,
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CommandProcessorFlags flags);
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~CommandProcessor();
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void set_validation_interface(ValidationInterface *iface);
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bool device_is_supported() const;
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// Synchronization.
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void flush();
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uint64_t signal_timeline();
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void wait_for_timeline(uint64_t index);
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void idle();
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void begin_frame_context();
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// Queues up state and drawing commands.
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void enqueue_command(unsigned num_words, const uint32_t *words);
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void enqueue_command_direct(unsigned num_words, const uint32_t *words);
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void set_quirks(const Quirks &quirks);
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// Interact with memory.
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void *begin_read_rdram();
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void end_write_rdram();
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void *begin_read_hidden_rdram();
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void end_write_hidden_rdram();
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size_t get_rdram_size() const;
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size_t get_hidden_rdram_size() const;
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void *get_tmem();
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// Sets VI register
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void set_vi_register(VIRegister reg, uint32_t value);
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Vulkan::ImageHandle scanout(const ScanoutOptions &opts = {});
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void scanout_sync(std::vector<RGBA> &colors, unsigned &width, unsigned &height, const ScanoutOptions &opts = {});
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void scanout_async_buffer(VIScanoutBuffer &buffer, const ScanoutOptions &opts = {});
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// Support for modifying certain registers per-scanline.
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// The idea is that before we scanout(), we use set_vi_register() to
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// set frame-global VI register state.
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// While scanning out, we can support changing some state, in particular HStart and XStart
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// which allows various raster effects ala HDMA.
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// For sanity's sake, scanout() reads all memory at once. A fully beam-raced implementation
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// would render out images every scanline, but that would cripple performance and it's questionable
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// how this is useful, especially on a 3D console. The only failure case of this style of implementation
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// would be if a demo attempted to modify VRAM *after* it has been scanned out, i.e. a write-after-read
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// hazard.
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// Latch registers are initialized to the values in set_vi_register() for each respective register.
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// After scanout(), the flags state is cleared to 0.
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void begin_vi_register_per_scanline(VideoInterface::PerScanlineRegisterFlags flags);
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void set_vi_register_for_scanline(VideoInterface::PerScanlineRegisterBits reg, uint32_t value);
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// Between begin_vi_register_per_scanline() and scanout(), line must be monotonically increasing,
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// or the call is ignored. Initial value for the line counter is 0
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// (to set parameters for line 0, use global VI register state).
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// Currently set registers in set_vi_register_for_scanline() are considered to be the active VI register
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// values starting with VI line "vi_line", until the bottom of the frame or a new vi_line is set.
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// Register state is assumed to have been fixed from the last latched scanline up until vi_line.
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//
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// The units used for this value matches the hardware YStart registers,
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// i.e. the first active scanline is not 0, but VI_H_OFFSET_{NTSC,PAL}.
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// For every scanned line, vi_line should increment by 2.
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// vi_line must be less than VI_V_END_MAX (really, VI_V_END_{NTSC,PAL}), or it is ignored.
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void latch_vi_register_for_scanline(unsigned vi_line);
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// Assumes that scanline register state does not change until end of frame.
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// Must be called before scanout(), or all per-scanline register state is ignored for the scanout.
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void end_vi_register_per_scanline();
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// Intended flow is something like:
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// set_vi_register(reg, value0) // value0 used for line [0, 99]
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// begin_vi_register_per_scanline(flags);
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// set_vi_register_for_scanline(reg, value1); // value1 used for line [100, 199]
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// latch_vi_register_for_scanline(100);
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// set_vi_register_for_scanline(reg, value2);
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// latch_vi_register_for_scanline(200); // value2 used for line [200, VBlank]
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// end_vi_register_per_scanline();
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// scanout();
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private:
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Vulkan::Device &device;
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Vulkan::BufferHandle rdram;
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Vulkan::BufferHandle hidden_rdram;
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Vulkan::BufferHandle tmem;
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size_t rdram_offset;
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size_t rdram_size;
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CommandProcessorFlags flags;
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#ifndef PARALLEL_RDP_SHADER_DIR
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std::unique_ptr<ShaderBank> shader_bank;
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#endif
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// Tear-down order is important here.
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Renderer renderer;
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VideoInterface vi;
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CommandRing ring;
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void clear_hidden_rdram();
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void clear_tmem();
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void clear_buffer(Vulkan::Buffer &buffer, uint32_t value);
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void init_renderer();
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void enqueue_command_inner(unsigned num_words, const uint32_t *words);
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Vulkan::ImageHandle scanout(const ScanoutOptions &opts, VkImageLayout target_layout);
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#define OP(x) void op_##x(const uint32_t *words)
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OP(fill_triangle); OP(fill_z_buffer_triangle); OP(texture_triangle); OP(texture_z_buffer_triangle);
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OP(shade_triangle); OP(shade_z_buffer_triangle); OP(shade_texture_triangle); OP(shade_texture_z_buffer_triangle);
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OP(texture_rectangle); OP(texture_rectangle_flip); OP(sync_load); OP(sync_pipe);
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OP(sync_tile); OP(sync_full); OP(set_key_gb); OP(set_key_r);
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OP(set_convert); OP(set_scissor); OP(set_prim_depth); OP(set_other_modes);
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OP(load_tlut); OP(set_tile_size); OP(load_block);
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OP(load_tile); OP(set_tile); OP(fill_rectangle); OP(set_fill_color);
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OP(set_fog_color); OP(set_blend_color); OP(set_prim_color); OP(set_env_color);
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OP(set_combine); OP(set_texture_image); OP(set_mask_image); OP(set_color_image);
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#undef OP
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ScissorState scissor_state = {};
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StaticRasterizationState static_state = {};
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DepthBlendState depth_blend = {};
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struct
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{
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uint32_t addr;
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uint32_t width;
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TextureFormat fmt;
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TextureSize size;
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} texture_image = {};
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uint64_t timeline_value = 0;
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uint64_t thread_timeline_value = 0;
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struct FenceExecutor
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{
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explicit inline FenceExecutor(Vulkan::Device *device_, uint64_t *ptr)
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: device(device_), value(ptr)
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{
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}
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Vulkan::Device *device;
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uint64_t *value;
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bool is_sentinel(const CoherencyOperation &work) const;
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void perform_work(CoherencyOperation &work);
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void notify_work_locked(const CoherencyOperation &work);
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};
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WorkerThread<CoherencyOperation, FenceExecutor> timeline_worker;
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uint8_t *host_rdram = nullptr;
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bool measure_stall_time = false;
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bool single_threaded_processing = false;
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bool is_supported = false;
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bool is_host_coherent = true;
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bool timestamp = false;
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friend class Renderer;
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void enqueue_coherency_operation(CoherencyOperation &&op);
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void drain_command_ring();
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void decode_triangle_setup(TriangleSetup &setup, const uint32_t *words) const;
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Quirks quirks;
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std::unique_ptr<RDPDumpWriter> dump_writer;
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bool dump_in_command_list = false;
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};
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}
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