Continue big Instruction struct rewrite
This commit is contained in:
irisz64
@@ -7,9 +7,11 @@ namespace n64 {
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Core::Core() {
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auto cpuType = Options::GetInstance().GetValue<std::string>("cpu", "type");
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if (cpuType == "interpreter") {
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cpuType = Interpreted;
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cpu = std::make_unique<Interpreter>(parallel, *mem, regs);
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} else if(cpuType == "jit") {
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#ifndef __aarch64__
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cpuType = DynamicRecompiler;
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cpu = std::make_unique<JIT>(parallel, *mem, regs);
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#else
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panic("JIT currently unsupported on aarch64");
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@@ -11,7 +11,7 @@ struct Core {
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Interpreted,
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DynamicRecompiler,
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CachedInterpreter
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};
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} cpuType = Interpreted;
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explicit Core();
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@@ -28,6 +28,20 @@ struct Core {
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return *GetInstance().mem;
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}
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static Interpreter& GetInterpreter() {
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if(GetInstance().cpuType == Interpreted)
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return *dynamic_cast<Interpreter*>(GetInstance().cpu.get());
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panic("Tried to get interpreter when other cpu type is used.");
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}
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static JIT& GetDynamicRecompiler() {
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if(GetInstance().cpuType == DynamicRecompiler)
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return *dynamic_cast<JIT*>(GetInstance().cpu.get());
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panic("Tried to get interpreter when other cpu type is used.");
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}
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int StepCPU();
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void StepRSP(int cpuCycles);
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void Stop();
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@@ -26,100 +26,100 @@ private:
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void CheckCompareInterrupt();
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void cop2Decode(u32);
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void special(u32);
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void regimm(u32);
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void Exec(u32);
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void add(u32);
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void addu(u32);
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void addi(u32);
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void addiu(u32);
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void andi(u32);
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void and_(u32);
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void special(Instruction);
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void regimm(Instruction);
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void Exec(Instruction);
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void add(Instruction);
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void addu(Instruction);
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void addi(Instruction);
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void addiu(Instruction);
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void andi(Instruction);
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void and_(Instruction);
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void branch(bool, s64);
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void branch_likely(bool, s64);
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void b(u32, bool);
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void blink(u32, bool);
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void bl(u32, bool);
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void bllink(u32, bool);
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void dadd(u32);
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void daddu(u32);
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void daddi(u32);
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void daddiu(u32);
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void ddiv(u32);
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void ddivu(u32);
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void div(u32);
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void divu(u32);
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void dmult(u32);
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void dmultu(u32);
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void dsll(u32);
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void dsllv(u32);
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void dsll32(u32);
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void dsra(u32);
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void dsrav(u32);
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void dsra32(u32);
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void dsrl(u32);
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void dsrlv(u32);
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void dsrl32(u32);
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void dsub(u32);
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void dsubu(u32);
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void j(u32);
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void jr(u32);
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void jal(u32);
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void jalr(u32);
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void lui(u32);
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void lbu(u32);
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void lb(u32);
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void ld(u32);
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void ldl(u32);
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void ldr(u32);
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void lh(u32);
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void lhu(u32);
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void ll(u32);
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void lld(u32);
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void lw(u32);
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void lwl(u32);
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void lwu(u32);
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void lwr(u32);
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void mfhi(u32);
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void mflo(u32);
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void mult(u32);
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void multu(u32);
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void mthi(u32);
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void mtlo(u32);
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void nor(u32);
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void sb(u32);
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void sc(u32);
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void scd(u32);
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void sd(u32);
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void sdl(u32);
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void sdr(u32);
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void sh(u32);
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void sw(u32);
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void swl(u32);
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void swr(u32);
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void slti(u32);
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void sltiu(u32);
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void slt(u32);
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void sltu(u32);
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void sll(u32);
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void sllv(u32);
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void sub(u32);
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void subu(u32);
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void sra(u32);
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void srav(u32);
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void srl(u32);
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void srlv(u32);
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void b(Instruction, bool);
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void blink(Instruction, bool);
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void bl(Instruction, bool);
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void bllink(Instruction, bool);
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void dadd(Instruction);
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void daddu(Instruction);
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void daddi(Instruction);
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void daddiu(Instruction);
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void ddiv(Instruction);
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void ddivu(Instruction);
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void div(Instruction);
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void divu(Instruction);
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void dmult(Instruction);
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void dmultu(Instruction);
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void dsll(Instruction);
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void dsllv(Instruction);
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void dsll32(Instruction);
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void dsra(Instruction);
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void dsrav(Instruction);
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void dsra32(Instruction);
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void dsrl(Instruction);
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void dsrlv(Instruction);
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void dsrl32(Instruction);
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void dsub(Instruction);
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void dsubu(Instruction);
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void j(Instruction);
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void jr(Instruction);
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void jal(Instruction);
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void jalr(Instruction);
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void lui(Instruction);
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void lbu(Instruction);
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void lb(Instruction);
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void ld(Instruction);
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void ldl(Instruction);
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void ldr(Instruction);
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void lh(Instruction);
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void lhu(Instruction);
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void ll(Instruction);
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void lld(Instruction);
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void lw(Instruction);
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void lwl(Instruction);
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void lwu(Instruction);
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void lwr(Instruction);
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void mfhi(Instruction);
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void mflo(Instruction);
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void mult(Instruction);
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void multu(Instruction);
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void mthi(Instruction);
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void mtlo(Instruction);
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void nor(Instruction);
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void sb(Instruction);
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void sc(Instruction);
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void scd(Instruction);
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void sd(Instruction);
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void sdl(Instruction);
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void sdr(Instruction);
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void sh(Instruction);
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void sw(Instruction);
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void swl(Instruction);
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void swr(Instruction);
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void slti(Instruction);
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void sltiu(Instruction);
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void slt(Instruction);
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void sltu(Instruction);
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void sll(Instruction);
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void sllv(Instruction);
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void sub(Instruction);
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void subu(Instruction);
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void sra(Instruction);
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void srav(Instruction);
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void srl(Instruction);
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void srlv(Instruction);
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void trap(bool) const;
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void or_(u32);
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void ori(u32);
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void xor_(u32);
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void xori(u32);
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void or_(Instruction);
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void ori(Instruction);
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void xor_(Instruction);
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void xori(Instruction);
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void mtc2(u32);
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void mfc2(u32);
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void dmtc2(u32);
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void dmfc2(u32);
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void ctc2(u32);
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void cfc2(u32);
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void mtc2(Instruction);
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void mfc2(Instruction);
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void dmtc2(Instruction);
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void dmfc2(Instruction);
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void ctc2(Instruction);
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void cfc2(Instruction);
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};
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} // namespace n64
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@@ -4,12 +4,11 @@
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#include <Instruction.hpp>
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namespace n64 {
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void Interpreter::special(const u32 instr) {
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Instruction helper(instr);
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void Interpreter::special(const Instruction instr) {
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// 00rr_rccc
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switch (helper.special()) {
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switch (instr.instr.opcode.special) {
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case Instruction::SLL:
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if (instr != 0) {
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if (instr.instr.raw != 0) {
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sll(instr);
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}
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break;
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@@ -130,22 +129,22 @@ void Interpreter::special(const u32 instr) {
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dsubu(instr);
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break;
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case Instruction::TGE:
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trap(regs.Read<s64>(RS(instr)) >= regs.Read<s64>(RT(instr)));
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trap(regs.Read<s64>(instr.rs()) >= regs.Read<s64>(instr.rt()));
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break;
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case Instruction::TGEU:
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trap(regs.Read<u64>(RS(instr)) >= regs.Read<u64>(RT(instr)));
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trap(regs.Read<u64>(instr.rs()) >= regs.Read<u64>(instr.rt()));
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break;
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case Instruction::TLT:
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trap(regs.Read<s64>(RS(instr)) < regs.Read<s64>(RT(instr)));
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trap(regs.Read<s64>(instr.rs()) < regs.Read<s64>(instr.rt()));
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break;
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case Instruction::TLTU:
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trap(regs.Read<u64>(RS(instr)) < regs.Read<u64>(RT(instr)));
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trap(regs.Read<u64>(instr.rs()) < regs.Read<u64>(instr.rt()));
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break;
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case Instruction::TEQ:
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trap(regs.Read<s64>(RS(instr)) == regs.Read<s64>(RT(instr)));
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trap(regs.Read<s64>(instr.rs()) == regs.Read<s64>(instr.rt()));
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break;
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case Instruction::TNE:
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trap(regs.Read<s64>(RS(instr)) != regs.Read<s64>(RT(instr)));
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trap(regs.Read<s64>(instr.rs()) != regs.Read<s64>(instr.rt()));
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break;
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case Instruction::DSLL:
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dsll(instr);
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@@ -166,59 +165,59 @@ void Interpreter::special(const u32 instr) {
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dsra32(instr);
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break;
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default:
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panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr,
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panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", instr.instr.opcode.special_hi, instr.instr.opcode.special_lo, instr.instr.raw,
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static_cast<u64>(regs.oldPC));
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}
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}
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void Interpreter::regimm(const u32 instr) {
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void Interpreter::regimm(const Instruction instr) {
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// 000r_rccc
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switch (const u8 mask = instr >> 16 & 0x1F) {
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case BLTZ:
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b(instr, regs.Read<s64>(RS(instr)) < 0);
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switch (instr.instr.opcode.regimm) {
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case Instruction::BLTZ:
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b(instr, regs.Read<s64>(instr.rs()) < 0);
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break;
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case BGEZ:
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b(instr, regs.Read<s64>(RS(instr)) >= 0);
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case Instruction::BGEZ:
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b(instr, regs.Read<s64>(instr.rs()) >= 0);
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break;
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case BLTZL:
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bl(instr, regs.Read<s64>(RS(instr)) < 0);
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case Instruction::BLTZL:
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bl(instr, regs.Read<s64>(instr.rs()) < 0);
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break;
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case BGEZL:
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bl(instr, regs.Read<s64>(RS(instr)) >= 0);
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case Instruction::BGEZL:
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bl(instr, regs.Read<s64>(instr.rs()) >= 0);
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break;
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case TGEI:
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trap(regs.Read<s64>(RS(instr)) >= static_cast<s64>(static_cast<s16>(instr)));
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case Instruction::TGEI:
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trap(regs.Read<s64>(instr.rs()) >= static_cast<s64>(static_cast<s16>(instr.instr.itype.imm)));
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break;
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case TGEIU:
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trap(regs.Read<u64>(RS(instr)) >= static_cast<u64>(static_cast<s64>(static_cast<s16>(instr))));
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case Instruction::TGEIU:
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trap(regs.Read<u64>(instr.rs()) >= static_cast<u64>(static_cast<s64>(static_cast<s16>(instr.instr.itype.imm))));
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break;
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case TLTI:
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trap(regs.Read<s64>(RS(instr)) < static_cast<s64>(static_cast<s16>(instr)));
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case Instruction::TLTI:
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trap(regs.Read<s64>(instr.rs()) < static_cast<s64>(static_cast<s16>(instr.instr.itype.imm)));
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break;
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case TLTIU:
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trap(regs.Read<u64>(RS(instr)) < static_cast<u64>(static_cast<s64>(static_cast<s16>(instr))));
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case Instruction::TLTIU:
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trap(regs.Read<u64>(instr.rs()) < static_cast<u64>(static_cast<s64>(static_cast<s16>(instr.instr.itype.imm))));
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break;
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case TEQI:
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trap(regs.Read<s64>(RS(instr)) == static_cast<s64>(static_cast<s16>(instr)));
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case Instruction::TEQI:
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trap(regs.Read<s64>(instr.rs()) == static_cast<s64>(static_cast<s16>(instr.instr.itype.imm)));
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break;
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case TNEI:
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trap(regs.Read<s64>(RS(instr)) != static_cast<s64>(static_cast<s16>(instr)));
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case Instruction::TNEI:
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trap(regs.Read<s64>(instr.rs()) != static_cast<s64>(static_cast<s16>(instr.instr.itype.imm)));
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break;
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case BLTZAL:
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blink(instr, regs.Read<s64>(RS(instr)) < 0);
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case Instruction::BLTZAL:
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blink(instr, regs.Read<s64>(instr.rs()) < 0);
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break;
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case BGEZAL:
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blink(instr, regs.Read<s64>(RS(instr)) >= 0);
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case Instruction::BGEZAL:
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blink(instr, regs.Read<s64>(instr.rs()) >= 0);
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break;
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case BLTZALL:
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bllink(instr, regs.Read<s64>(RS(instr)) < 0);
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case Instruction::BLTZALL:
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bllink(instr, regs.Read<s64>(instr.rs()) < 0);
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break;
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case BGEZALL:
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bllink(instr, regs.Read<s64>(RS(instr)) >= 0);
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case Instruction::BGEZALL:
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bllink(instr, regs.Read<s64>(instr.rs()) >= 0);
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break;
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default:
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panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr,
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static_cast<u64>(regs.oldPC));
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panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", instr.instr.opcode.regimm_hi,
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instr.instr.opcode.regimm_lo, instr, static_cast<u64>(regs.oldPC));
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}
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}
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@@ -251,203 +250,172 @@ void Interpreter::cop2Decode(const u32 instr) {
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}
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}
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void Interpreter::Exec(const u32 instr) {
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void Interpreter::Exec(const Instruction instr) {
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// 00rr_rccc
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switch (const u8 mask = instr >> 26 & 0x3f) {
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case SPECIAL:
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switch (instr.instr.opcode.op) {
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case Instruction::SPECIAL:
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special(instr);
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break;
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case REGIMM:
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case Instruction::REGIMM:
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regimm(instr);
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break;
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case J:
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case Instruction::J:
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j(instr);
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break;
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case JAL:
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case Instruction::JAL:
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jal(instr);
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break;
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case BEQ:
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b(instr, regs.Read<s64>(RS(instr)) == regs.Read<s64>(RT(instr)));
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case Instruction::BEQ:
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b(instr, regs.Read<s64>(instr.rs()) == regs.Read<s64>(instr.rt()));
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break;
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case BNE:
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b(instr, regs.Read<s64>(RS(instr)) != regs.Read<s64>(RT(instr)));
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case Instruction::BNE:
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b(instr, regs.Read<s64>(instr.rs()) != regs.Read<s64>(instr.rt()));
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break;
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case BLEZ:
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b(instr, regs.Read<s64>(RS(instr)) <= 0);
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case Instruction::BLEZ:
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b(instr, regs.Read<s64>(instr.rs()) <= 0);
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break;
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case BGTZ:
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b(instr, regs.Read<s64>(RS(instr)) > 0);
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case Instruction::BGTZ:
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b(instr, regs.Read<s64>(instr.rs()) > 0);
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break;
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case ADDI:
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case Instruction::ADDI:
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addi(instr);
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break;
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case ADDIU:
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case Instruction::ADDIU:
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addiu(instr);
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break;
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case SLTI:
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case Instruction::SLTI:
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slti(instr);
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break;
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case SLTIU:
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case Instruction::SLTIU:
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sltiu(instr);
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break;
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case ANDI:
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case Instruction::ANDI:
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andi(instr);
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break;
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case ORI:
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case Instruction::ORI:
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ori(instr);
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break;
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case XORI:
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case Instruction::XORI:
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xori(instr);
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break;
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case LUI:
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case Instruction::LUI:
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lui(instr);
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break;
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case COP0:
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case Instruction::COP0:
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regs.cop0.decode(instr);
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break;
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case COP1:
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{
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const u8 mask_sub = (instr >> 21) & 0x1F;
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const u8 mask_branch = (instr >> 16) & 0x1F;
|
||||
if (mask_sub == 0x08) {
|
||||
switch (mask_branch) {
|
||||
case 0:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
b(instr, !regs.cop1.fcr31.compare);
|
||||
break;
|
||||
case 1:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
b(instr, regs.cop1.fcr31.compare);
|
||||
break;
|
||||
case 2:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
bl(instr, !regs.cop1.fcr31.compare);
|
||||
break;
|
||||
case 3:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
bl(instr, regs.cop1.fcr31.compare);
|
||||
break;
|
||||
default:
|
||||
panic("Undefined BC COP1 {:02X}", mask_branch);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case Instruction::COP1:
|
||||
regs.cop1.decode(instr);
|
||||
}
|
||||
break;
|
||||
case COP2:
|
||||
case Instruction::COP2:
|
||||
cop2Decode(instr);
|
||||
break;
|
||||
case BEQL:
|
||||
bl(instr, regs.Read<s64>(RS(instr)) == regs.Read<s64>(RT(instr)));
|
||||
case Instruction::BEQL:
|
||||
bl(instr, regs.Read<s64>(instr.rs()) == regs.Read<s64>(instr.rt()));
|
||||
break;
|
||||
case BNEL:
|
||||
bl(instr, regs.Read<s64>(RS(instr)) != regs.Read<s64>(RT(instr)));
|
||||
case Instruction::BNEL:
|
||||
bl(instr, regs.Read<s64>(instr.rs()) != regs.Read<s64>(instr.rt()));
|
||||
break;
|
||||
case BLEZL:
|
||||
bl(instr, regs.Read<s64>(RS(instr)) <= 0);
|
||||
case Instruction::BLEZL:
|
||||
bl(instr, regs.Read<s64>(instr.rs()) <= 0);
|
||||
break;
|
||||
case BGTZL:
|
||||
bl(instr, regs.Read<s64>(RS(instr)) > 0);
|
||||
case Instruction::BGTZL:
|
||||
bl(instr, regs.Read<s64>(instr.rs()) > 0);
|
||||
break;
|
||||
case DADDI:
|
||||
case Instruction::DADDI:
|
||||
daddi(instr);
|
||||
break;
|
||||
case DADDIU:
|
||||
case Instruction::DADDIU:
|
||||
daddiu(instr);
|
||||
break;
|
||||
case LDL:
|
||||
case Instruction::LDL:
|
||||
ldl(instr);
|
||||
break;
|
||||
case LDR:
|
||||
case Instruction::LDR:
|
||||
ldr(instr);
|
||||
break;
|
||||
case 0x1F:
|
||||
regs.cop0.FireException(ExceptionCode::ReservedInstruction, 0, regs.oldPC);
|
||||
break;
|
||||
case LB:
|
||||
case Instruction::LB:
|
||||
lb(instr);
|
||||
break;
|
||||
case LH:
|
||||
case Instruction::LH:
|
||||
lh(instr);
|
||||
break;
|
||||
case LWL:
|
||||
case Instruction::LWL:
|
||||
lwl(instr);
|
||||
break;
|
||||
case LW:
|
||||
case Instruction::LW:
|
||||
lw(instr);
|
||||
break;
|
||||
case LBU:
|
||||
case Instruction::LBU:
|
||||
lbu(instr);
|
||||
break;
|
||||
case LHU:
|
||||
case Instruction::LHU:
|
||||
lhu(instr);
|
||||
break;
|
||||
case LWR:
|
||||
case Instruction::LWR:
|
||||
lwr(instr);
|
||||
break;
|
||||
case LWU:
|
||||
case Instruction::LWU:
|
||||
lwu(instr);
|
||||
break;
|
||||
case SB:
|
||||
case Instruction::SB:
|
||||
sb(instr);
|
||||
break;
|
||||
case SH:
|
||||
case Instruction::SH:
|
||||
sh(instr);
|
||||
break;
|
||||
case SWL:
|
||||
case Instruction::SWL:
|
||||
swl(instr);
|
||||
break;
|
||||
case SW:
|
||||
case Instruction::SW:
|
||||
sw(instr);
|
||||
break;
|
||||
case SDL:
|
||||
case Instruction::SDL:
|
||||
sdl(instr);
|
||||
break;
|
||||
case SDR:
|
||||
case Instruction::SDR:
|
||||
sdr(instr);
|
||||
break;
|
||||
case SWR:
|
||||
case Instruction::SWR:
|
||||
swr(instr);
|
||||
break;
|
||||
case CACHE:
|
||||
case Instruction::CACHE:
|
||||
break; // CACHE
|
||||
case LL:
|
||||
case Instruction::LL:
|
||||
ll(instr);
|
||||
break;
|
||||
case LWC1:
|
||||
case Instruction::LWC1:
|
||||
regs.cop1.lwc1(instr);
|
||||
break;
|
||||
case LLD:
|
||||
case Instruction::LLD:
|
||||
lld(instr);
|
||||
break;
|
||||
case LDC1:
|
||||
case Instruction::LDC1:
|
||||
regs.cop1.ldc1(instr);
|
||||
break;
|
||||
case LD:
|
||||
case Instruction::LD:
|
||||
ld(instr);
|
||||
break;
|
||||
case SC:
|
||||
case Instruction::SC:
|
||||
sc(instr);
|
||||
break;
|
||||
case SWC1:
|
||||
case Instruction::SWC1:
|
||||
regs.cop1.swc1(instr);
|
||||
break;
|
||||
case SCD:
|
||||
case Instruction::SCD:
|
||||
scd(instr);
|
||||
break;
|
||||
case SDC1:
|
||||
case Instruction::SDC1:
|
||||
regs.cop1.sdc1(instr);
|
||||
break;
|
||||
case SD:
|
||||
case Instruction::SD:
|
||||
sd(instr);
|
||||
break;
|
||||
default:
|
||||
panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, static_cast<u64>(regs.oldPC));
|
||||
panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", instr.instr.opcode.op, u32(instr), static_cast<u64>(regs.oldPC));
|
||||
}
|
||||
}
|
||||
} // namespace n64
|
||||
|
||||
@@ -451,25 +451,23 @@ ExceptionCode Cop0::GetTLBExceptionCode(const TLBError error, const TLBAccessTyp
|
||||
}
|
||||
}
|
||||
|
||||
void Cop0::decode(const u32 instr) {
|
||||
void Cop0::decode(const Instruction instr) {
|
||||
Registers& regs = Core::GetRegs();
|
||||
const u8 mask_cop = instr >> 21 & 0x1F;
|
||||
const u8 mask_cop2 = instr & 0x3F;
|
||||
switch (mask_cop) {
|
||||
switch (instr.cop_rs()) {
|
||||
case 0x00:
|
||||
mfc0(instr);
|
||||
mfc0(u32(instr));
|
||||
break;
|
||||
case 0x01:
|
||||
dmfc0(instr);
|
||||
dmfc0(u32(instr));
|
||||
break;
|
||||
case 0x04:
|
||||
mtc0(instr);
|
||||
mtc0(u32(instr));
|
||||
break;
|
||||
case 0x05:
|
||||
dmtc0(instr);
|
||||
dmtc0(u32(instr));
|
||||
break;
|
||||
case 0x10 ... 0x1F:
|
||||
switch (mask_cop2) {
|
||||
switch (instr.cop_funct()) {
|
||||
case 0x01:
|
||||
tlbr();
|
||||
break;
|
||||
@@ -486,7 +484,7 @@ void Cop0::decode(const u32 instr) {
|
||||
eret();
|
||||
break;
|
||||
default:
|
||||
panic("Unimplemented COP0 function {} {} ({:08X}) ({:016X})", mask_cop2 >> 3, mask_cop2 & 7, instr,
|
||||
panic("Unimplemented COP0 function {} ({:08X}) ({:016X})", instr.cop_funct(), u32(instr),
|
||||
regs.oldPC);
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
#include <common.hpp>
|
||||
#include <log.hpp>
|
||||
#include <unordered_map>
|
||||
#include <Instruction.hpp>
|
||||
|
||||
namespace n64 {
|
||||
#define STATUS_MASK 0xFF57FFFF
|
||||
@@ -264,7 +265,7 @@ struct Cop0 {
|
||||
TLBEntry *TLBTryMatch(u64 vaddr);
|
||||
void HandleTLBException(u64 vaddr);
|
||||
static ExceptionCode GetTLBExceptionCode(TLBError error, TLBAccessType accessType);
|
||||
void decode(u32);
|
||||
void decode(const Instruction);
|
||||
|
||||
private:
|
||||
[[nodiscard]] FORCE_INLINE u32 GetWired() const { return wired & 0x3F; }
|
||||
|
||||
@@ -10,11 +10,9 @@ void Cop1::Reset() {
|
||||
memset(fgr, 0, 32 * sizeof(FloatingPointReg));
|
||||
}
|
||||
|
||||
void Cop1::decode(const u32 instr) {
|
||||
const u8 mask_sub = (instr >> 21) & 0x1F;
|
||||
const u8 mask_fun = instr & 0x3F;
|
||||
const u8 mask_branch = (instr >> 16) & 0x1F;
|
||||
switch (mask_sub) {
|
||||
void Cop1::decode(const Instruction instr) {
|
||||
auto cpu = Core::GetInstance().cpuType == Core::Interpreted ? Core::GetInterpreter() : Core::GetDynamicRecompiler();
|
||||
switch (instr.cop_rs()) {
|
||||
// 000r_rccc
|
||||
case 0x00:
|
||||
mfc1(instr);
|
||||
@@ -40,8 +38,34 @@ void Cop1::decode(const u32 instr) {
|
||||
case 0x07:
|
||||
unimplemented();
|
||||
break;
|
||||
case 0x08:
|
||||
switch (instr.cop_rt()) {
|
||||
case 0:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
cpu.b(instr, !regs.cop1.fcr31.compare);
|
||||
break;
|
||||
case 1:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
cpu.b(instr, regs.cop1.fcr31.compare);
|
||||
break;
|
||||
case 2:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
cpu.bl(instr, !regs.cop1.fcr31.compare);
|
||||
break;
|
||||
case 3:
|
||||
if (!regs.cop1.CheckFPUUsable())
|
||||
return;
|
||||
cpu.bl(instr, regs.cop1.fcr31.compare);
|
||||
break;
|
||||
default:
|
||||
panic("Undefined BC COP1 {:02X}", instr.cop_rt());
|
||||
}
|
||||
break;
|
||||
case 0x10: // s
|
||||
switch (mask_fun) {
|
||||
switch (instr.cop_funct()) {
|
||||
case 0x00:
|
||||
adds(instr);
|
||||
break;
|
||||
@@ -152,7 +176,7 @@ void Cop1::decode(const u32 instr) {
|
||||
}
|
||||
break;
|
||||
case 0x11: // d
|
||||
switch (mask_fun) {
|
||||
switch (instr.cop_funct()) {
|
||||
case 0x00:
|
||||
addd(instr);
|
||||
break;
|
||||
@@ -263,7 +287,7 @@ void Cop1::decode(const u32 instr) {
|
||||
}
|
||||
break;
|
||||
case 0x14: // w
|
||||
switch (mask_fun) {
|
||||
switch (instr.cop_funct()) {
|
||||
case 0x20:
|
||||
cvtsw(instr);
|
||||
break;
|
||||
@@ -275,7 +299,7 @@ void Cop1::decode(const u32 instr) {
|
||||
}
|
||||
break;
|
||||
case 0x15: // l
|
||||
switch (mask_fun) {
|
||||
switch (instr.cop_funct()) {
|
||||
case 0x20:
|
||||
cvtsl(instr);
|
||||
break;
|
||||
@@ -287,7 +311,7 @@ void Cop1::decode(const u32 instr) {
|
||||
}
|
||||
break;
|
||||
default:
|
||||
panic("Unimplemented COP1 instruction {} {}", mask_sub >> 3, mask_sub & 7);
|
||||
panic("Unimplemented COP1 instruction {}", instr.cop_rs());
|
||||
}
|
||||
}
|
||||
} // namespace n64
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
#pragma once
|
||||
#include <core/registers/Cop0.hpp>
|
||||
#include <cstring>
|
||||
#include <Instruction.hpp>
|
||||
|
||||
namespace n64 {
|
||||
struct Cop1;
|
||||
@@ -117,7 +118,7 @@ struct Cop1 {
|
||||
bool fgrIsConstant[32]{};
|
||||
|
||||
void Reset();
|
||||
void decode(u32);
|
||||
void decode(const Instruction);
|
||||
friend struct Interpreter;
|
||||
friend struct JIT;
|
||||
|
||||
@@ -156,91 +157,91 @@ private:
|
||||
auto FGR_S(const Cop0Status &, u32) -> T &;
|
||||
template <typename T>
|
||||
auto FGR_D(const Cop0Status &, u32) -> T &;
|
||||
void absd(u32 instr);
|
||||
void abss(u32 instr);
|
||||
void adds(u32 instr);
|
||||
void addd(u32 instr);
|
||||
void subs(u32 instr);
|
||||
void subd(u32 instr);
|
||||
void ceills(u32 instr);
|
||||
void ceilws(u32 instr);
|
||||
void ceilld(u32 instr);
|
||||
void ceilwd(u32 instr);
|
||||
void cfc1(u32 instr);
|
||||
void ctc1(u32 instr);
|
||||
void absd(const Instruction instr);
|
||||
void abss(const Instruction instr);
|
||||
void adds(const Instruction instr);
|
||||
void addd(const Instruction instr);
|
||||
void subs(const Instruction instr);
|
||||
void subd(const Instruction instr);
|
||||
void ceills(const Instruction instr);
|
||||
void ceilws(const Instruction instr);
|
||||
void ceilld(const Instruction instr);
|
||||
void ceilwd(const Instruction instr);
|
||||
void cfc1(const Instruction instr);
|
||||
void ctc1(const Instruction instr);
|
||||
void unimplemented();
|
||||
void roundls(u32 instr);
|
||||
void roundld(u32 instr);
|
||||
void roundws(u32 instr);
|
||||
void roundwd(u32 instr);
|
||||
void floorls(u32 instr);
|
||||
void floorld(u32 instr);
|
||||
void floorws(u32 instr);
|
||||
void floorwd(u32 instr);
|
||||
void cvtls(u32 instr);
|
||||
void cvtws(u32 instr);
|
||||
void cvtds(u32 instr);
|
||||
void cvtsw(u32 instr);
|
||||
void cvtdw(u32 instr);
|
||||
void cvtsd(u32 instr);
|
||||
void cvtwd(u32 instr);
|
||||
void cvtld(u32 instr);
|
||||
void cvtdl(u32 instr);
|
||||
void cvtsl(u32 instr);
|
||||
void roundls(const Instruction instr);
|
||||
void roundld(const Instruction instr);
|
||||
void roundws(const Instruction instr);
|
||||
void roundwd(const Instruction instr);
|
||||
void floorls(const Instruction instr);
|
||||
void floorld(const Instruction instr);
|
||||
void floorws(const Instruction instr);
|
||||
void floorwd(const Instruction instr);
|
||||
void cvtls(const Instruction instr);
|
||||
void cvtws(const Instruction instr);
|
||||
void cvtds(const Instruction instr);
|
||||
void cvtsw(const Instruction instr);
|
||||
void cvtdw(const Instruction instr);
|
||||
void cvtsd(const Instruction instr);
|
||||
void cvtwd(const Instruction instr);
|
||||
void cvtld(const Instruction instr);
|
||||
void cvtdl(const Instruction instr);
|
||||
void cvtsl(const Instruction instr);
|
||||
template <typename T>
|
||||
void cf(u32 instr);
|
||||
void cf(const Instruction instr);
|
||||
template <typename T>
|
||||
void cun(u32 instr);
|
||||
void cun(const Instruction instr);
|
||||
template <typename T>
|
||||
void ceq(u32 instr);
|
||||
void ceq(const Instruction instr);
|
||||
template <typename T>
|
||||
void cueq(u32 instr);
|
||||
void cueq(const Instruction instr);
|
||||
template <typename T>
|
||||
void colt(u32 instr);
|
||||
void colt(const Instruction instr);
|
||||
template <typename T>
|
||||
void cult(u32 instr);
|
||||
void cult(const Instruction instr);
|
||||
template <typename T>
|
||||
void cole(u32 instr);
|
||||
void cole(const Instruction instr);
|
||||
template <typename T>
|
||||
void cule(u32 instr);
|
||||
void cule(const Instruction instr);
|
||||
template <typename T>
|
||||
void csf(u32 instr);
|
||||
void csf(const Instruction instr);
|
||||
template <typename T>
|
||||
void cngle(u32 instr);
|
||||
void cngle(const Instruction instr);
|
||||
template <typename T>
|
||||
void cseq(u32 instr);
|
||||
void cseq(const Instruction instr);
|
||||
template <typename T>
|
||||
void cngl(u32 instr);
|
||||
void cngl(const Instruction instr);
|
||||
template <typename T>
|
||||
void clt(u32 instr);
|
||||
void clt(const Instruction instr);
|
||||
template <typename T>
|
||||
void cnge(u32 instr);
|
||||
void cnge(const Instruction instr);
|
||||
template <typename T>
|
||||
void cle(u32 instr);
|
||||
void cle(const Instruction instr);
|
||||
template <typename T>
|
||||
void cngt(u32 instr);
|
||||
void divs(u32 instr);
|
||||
void divd(u32 instr);
|
||||
void muls(u32 instr);
|
||||
void muld(u32 instr);
|
||||
void movs(u32 instr);
|
||||
void movd(u32 instr);
|
||||
void negs(u32 instr);
|
||||
void negd(u32 instr);
|
||||
void sqrts(u32 instr);
|
||||
void sqrtd(u32 instr);
|
||||
void cngt(const Instruction instr);
|
||||
void divs(const Instruction instr);
|
||||
void divd(const Instruction instr);
|
||||
void muls(const Instruction instr);
|
||||
void muld(const Instruction instr);
|
||||
void movs(const Instruction instr);
|
||||
void movd(const Instruction instr);
|
||||
void negs(const Instruction instr);
|
||||
void negd(const Instruction instr);
|
||||
void sqrts(const Instruction instr);
|
||||
void sqrtd(const Instruction instr);
|
||||
void lwc1(u32);
|
||||
void swc1(u32);
|
||||
void ldc1(u32);
|
||||
void sdc1(u32);
|
||||
|
||||
void mfc1(u32 instr);
|
||||
void dmfc1(u32 instr);
|
||||
void mtc1(u32 instr);
|
||||
void dmtc1(u32 instr);
|
||||
void truncws(u32 instr);
|
||||
void truncwd(u32 instr);
|
||||
void truncls(u32 instr);
|
||||
void truncld(u32 instr);
|
||||
void mfc1(const Instruction instr);
|
||||
void dmfc1(const Instruction instr);
|
||||
void mtc1(const Instruction instr);
|
||||
void dmtc1(const Instruction instr);
|
||||
void truncws(const Instruction instr);
|
||||
void truncwd(const Instruction instr);
|
||||
void truncls(const Instruction instr);
|
||||
void truncld(const Instruction instr);
|
||||
};
|
||||
} // namespace n64
|
||||
|
||||
@@ -4,17 +4,82 @@
|
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namespace n64 {
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struct Instruction {
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Instruction(u32 v) : raw(v) {}
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void operator=(u32 v) { raw = v; }
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Instruction(u32 v) { instr.raw = v; }
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void operator=(u32 v) { instr.raw = v; }
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auto operator u32() { return instr.raw; }
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inline u8 rs() const { return instr.rtype.rs; }
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inline u8 rt() const { return instr.rtype.rt; }
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inline u8 rd() const { return instr.rtype.rd; }
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inline u8 sa() const { return instr.rtype.sa; }
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inline u16 imm() const { return instr.itype.imm; }
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inline u32 target() const { return instr.jtype.target; }
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inline u8 cop_rs() const { return instr.opcode.cop_rs; }
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inline u8 cop_rt() const { return instr.opcode.cop_rt; }
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inline u8 cop_funct() const { return instr.opcode.funct; }
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union {
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struct {
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unsigned imm:16;
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unsigned rt:5;
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unsigned rs:5;
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unsigned op:6;
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} itype;
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struct {
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unsigned target:26;
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unsigned op:6;
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} jtype;
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struct {
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unsigned funct:6;
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unsigned sa:5;
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unsigned rd:5;
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unsigned rt:5;
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unsigned rs:5;
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unsigned op:6;
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} rtype;
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union {
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struct {
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unsigned special_lo:3;
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unsigned special_hi:3;
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unsigned:26;
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};
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struct {
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unsigned special:6;
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unsigned:26;
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};
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struct {
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unsigned:16;
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unsigned regimm_lo:3;
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unsigned regimm_hi:2;
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unsigned:11;
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};
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struct {
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unsigned:16;
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unsigned regimm:5;
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unsigned:11;
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};
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struct {
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unsigned:26;
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unsigned op:6;
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};
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struct {
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unsigned funct:6;
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unsigned:10;
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unsigned cop_rt:5;
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unsigned cop_rs:5;
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unsigned:6;
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};
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} opcode;
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u32 raw;
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FORCE_INLINE u8 special() const { return raw & 0x3F; }
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FORCE_INLINE u8 cop_funct() const { return special(); }
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FORCE_INLINE u8 regimm() const { return (raw >> 16) & 0x1F; }
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FORCE_INLINE u8 branch() const { return regimm(); }
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FORCE_INLINE u8 decode() const { return (raw >> 26) & 0x3F; }
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FORCE_INLINE u8 cop() const { return (raw >> 21) & 0x1F; }
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} instr{};
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static constexpr u8 SPECIAL = 0b000000;
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static constexpr u8 REGIMM = 0b000001;
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