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logging overhaul

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This commit is contained in:
SimoneN64
2023-06-05 17:07:20 +02:00
parent 9e37e961ba
commit df3775a559
26 changed files with 145 additions and 145 deletions
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2
src/backend/core/mmio/AI.cpp
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@@ -69,7 +69,7 @@ void AI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dac.precision = bitrate + 1;
break;
default:
Util::panic("Unhandled AI write at addr {:08X} with val {:08X}\n", addr, val);
Util::panic("Unhandled AI write at addr {:08X} with val {:08X}", addr, val);
}
}

4
src/backend/core/mmio/MI.cpp
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@@ -23,7 +23,7 @@ auto MI::Read(u32 paddr) const -> u32 {
case 0x8: return miIntr.raw & 0x3F;
case 0xC: return miIntrMask.raw & 0x3F;
default:
Util::panic("Unhandled MI[{:08X}] read\n", paddr);
Util::panic("Unhandled MI[{:08X}] read", paddr);
}
}
@@ -78,7 +78,7 @@ void MI::Write(Registers& regs, u32 paddr, u32 val) {
UpdateInterrupt(*this, regs);
break;
default:
Util::panic("Unhandled MI[{:08X}] write ({:08X})\n", val, paddr);
Util::panic("Unhandled MI[{:08X}] write ({:08X})", val, paddr);
}
}
}

8
src/backend/core/mmio/PI.cpp
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@@ -34,7 +34,7 @@ auto PI::Read(MI& mi, u32 addr) const -> u32 {
case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030:
return stub[(addr & 0xff) - 5];
default:
Util::panic("Unhandled PI[{:08X}] read\n", addr);
Util::panic("Unhandled PI[{:08X}] read", addr);
}
}
@@ -57,7 +57,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dramAddr = dram_addr + len;
cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
//Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})\n", len, dramAddr, cartAddr);
//Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
} break;
case 0x0460000C: {
u32 len = (val & 0x00FFFFFF) + 1;
@@ -73,7 +73,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dramAddr = dram_addr + len;
cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
//Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})\n", len, cart_addr, dram_addr);
//Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cart_addr, dram_addr);
} break;
case 0x04600010:
if(val & 2) {
@@ -84,7 +84,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
stub[(addr & 0xff) - 5] = val & 0xff;
break;
default:
Util::panic("Unhandled PI[{:08X}] write ({:08X})\n", val, addr);
Util::panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
}
}
}

12
src/backend/core/mmio/PIF.cpp
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@@ -27,7 +27,7 @@ void PIF::LoadMempak(fs::path path) {
size_t actualSize = ftell(f);
fseek(f, 0, SEEK_SET);
if (actualSize != MEMPAK_SIZE) {
Util::panic("Corrupt mempak!\n");
Util::panic("Corrupt mempak!");
}
fread(mempak, 1, MEMPAK_SIZE, f);
@@ -47,7 +47,7 @@ inline size_t getSaveSize(SaveType saveType) {
case SAVE_FLASH_1m:
return 131072;
default:
Util::panic("Unknown save type!\n");
Util::panic("Unknown save type!");
}
}
@@ -70,7 +70,7 @@ void PIF::LoadEeprom(SaveType saveType, fs::path path) {
size_t actualSize = ftell(f);
fseek(f, 0, SEEK_SET);
if (actualSize != eepromSize) {
Util::panic("Corrupt eeprom!\n");
Util::panic("Corrupt eeprom!");
}
fread(eeprom, 1, eepromSize, f);
@@ -284,7 +284,7 @@ void PIF::EepromWrite(u8* cmd, u8* res, const Mem& mem) const {
if (channel == 4) {
u8 offset = cmd[3];
if ((offset * 8) >= getSaveSize(mem.saveType)) {
Util::panic("Out of range EEPROM write! offset: {:02X}\n", offset);
Util::panic("Out of range EEPROM write! offset: {:02X}", offset);
}
for (int i = 0; i < 8; i++) {
@@ -407,7 +407,7 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
switch(cicType) {
case UNKNOWN_CIC_TYPE:
Util::warn("Unknown CIC type!\n");
Util::warn("Unknown CIC type!");
break;
case CIC_NUS_6101:
regs.gpr[0] = 0x0000000000000000;
@@ -673,7 +673,7 @@ void PIF::ExecutePIF(Mem& mem, Registers& regs) {
mem.Write32(regs, PIF_RAM_REGION_START + 0x24, cicSeeds[cicType]);
switch(cicType) {
case UNKNOWN_CIC_TYPE:
Util::warn("Unknown CIC type!\n");
Util::warn("Unknown CIC type!");
break;
case CIC_NUS_6101 ... CIC_NUS_6103_7103:
mem.Write32(regs, 0x318, RDRAM_SIZE);

4
src/backend/core/mmio/RI.cpp
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@@ -20,7 +20,7 @@ auto RI::Read(u32 addr) const -> u32 {
case 0x0470000C: return select;
case 0x04700010: return refresh;
default:
Util::panic("Unhandled RI[{:08X}] read\n", addr);
Util::panic("Unhandled RI[{:08X}] read", addr);
}
}
@@ -31,7 +31,7 @@ void RI::Write(u32 addr, u32 val) {
case 0x0470000C: select = val; break;
case 0x04700010: refresh = val; break;
default:
Util::panic("Unhandled RI[{:08X}] write with val {:08X}\n", addr, val);
Util::panic("Unhandled RI[{:08X}] write with val {:08X}", addr, val);
}
}
}

8
src/backend/core/mmio/SI.cpp
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@@ -30,7 +30,7 @@ auto SI::Read(MI& mi, u32 addr) const -> u32 {
return val;
}
default:
Util::panic("Unhandled SI[{:08X}] read\n", addr);
Util::panic("Unhandled SI[{:08X}] read", addr);
}
}
@@ -42,12 +42,12 @@ void DMA(Mem& mem, Registers& regs) {
for(int i = 0; i < 64; i++) {
mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)] = si.pif.Read(si.pifAddr + i);
}
//Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})\n", si.pifAddr, si.dramAddr);
//Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})", si.pifAddr, si.dramAddr);
} else {
for(int i = 0; i < 64; i++) {
si.pif.Write(si.pifAddr + i, mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)]);
}
//Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", si.dramAddr, si.pifAddr);
//Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})", si.dramAddr, si.pifAddr);
si.pif.ProcessCommands(mem);
}
InterruptRaise(mem.mmio.mi, regs, Interrupt::SI);
@@ -74,7 +74,7 @@ void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
InterruptLower(mem.mmio.mi, regs, Interrupt::SI);
break;
default:
Util::panic("Unhandled SI[{:08X}] write ({:08X})\n", addr, val);
Util::panic("Unhandled SI[{:08X}] write ({:08X})", addr, val);
}
}
}

4
src/backend/core/mmio/VI.cpp
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@@ -39,7 +39,7 @@ u32 VI::Read(u32 paddr) const {
case 0x04400030: return xscale.raw;
case 0x04400034: return yscale.raw;
default:
Util::panic("Unimplemented VI[%08X] read\n", paddr);
Util::panic("Unimplemented VI[%08X] read", paddr);
}
}
@@ -81,7 +81,7 @@ void VI::Write(MI& mi, Registers& regs, u32 paddr, u32 val) {
case 0x04400030: xscale.raw = val; break;
case 0x04400034: yscale.raw = val; break;
default:
Util::panic("Unimplemented VI[%08X] write (%08X)\n", paddr, val);
Util::panic("Unimplemented VI[%08X] write (%08X)", paddr, val);
}
}
}