logging overhaul

This commit is contained in:
SimoneN64
2023-06-05 17:07:20 +02:00
parent 9e37e961ba
commit df3775a559
26 changed files with 145 additions and 145 deletions

View File

@@ -34,7 +34,7 @@ auto PI::Read(MI& mi, u32 addr) const -> u32 {
case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030:
return stub[(addr & 0xff) - 5];
default:
Util::panic("Unhandled PI[{:08X}] read\n", addr);
Util::panic("Unhandled PI[{:08X}] read", addr);
}
}
@@ -57,7 +57,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dramAddr = dram_addr + len;
cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
//Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})\n", len, dramAddr, cartAddr);
//Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
} break;
case 0x0460000C: {
u32 len = (val & 0x00FFFFFF) + 1;
@@ -73,7 +73,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dramAddr = dram_addr + len;
cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI);
//Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})\n", len, cart_addr, dram_addr);
//Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cart_addr, dram_addr);
} break;
case 0x04600010:
if(val & 2) {
@@ -84,7 +84,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
stub[(addr & 0xff) - 5] = val & 0xff;
break;
default:
Util::panic("Unhandled PI[{:08X}] write ({:08X})\n", val, addr);
Util::panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
}
}
}