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logging overhaul

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This commit is contained in:
SimoneN64
2023-06-05 17:07:20 +02:00
parent 9e37e961ba
commit df3775a559
26 changed files with 145 additions and 145 deletions
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2
src/backend/Core.cpp
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@@ -4,7 +4,7 @@
namespace n64 { namespace n64 {
Core::Core() { Core::Core() {
if(SDL_GameControllerAddMappingsFromFile("resources/gamecontrollerdb.txt") < 0) { if(SDL_GameControllerAddMappingsFromFile("resources/gamecontrollerdb.txt") < 0) {
Util::warn("Failed to load game controller DB\n"); Util::warn("Failed to load game controller DB");
} }
} }

4
src/backend/GameDB.cpp
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@@ -20,14 +20,14 @@ void GameDB::match(Mem& mem) {
mem.rom.gameNameDB = i.name; mem.rom.gameNameDB = i.name;
return; return;
} else { } else {
Util::warn("Matched code for %s, but not region! Game supposedly exists in regions [{}] but this image has region {}\n", Util::warn("Matched code for %s, but not region! Game supposedly exists in regions [{}] but this image has region {}",
i.name, i.regions, rom.header.countryCode[0]); i.name, i.regions, rom.header.countryCode[0]);
} }
} }
} }
Util::debug("Did not match any Game DB entries. Code: {} Region: {}\n", mem.rom.code, mem.rom.header.countryCode[0]); Util::debug("Did not match any Game DB entries. Code: {} Region: {}", mem.rom.code, mem.rom.header.countryCode[0]);
mem.rom.gameNameDB = ""; mem.rom.gameNameDB = "";
mem.saveType = SAVE_NONE; mem.saveType = SAVE_NONE;

38
src/backend/MupenMovie.cpp
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@@ -105,11 +105,11 @@ void LoadTAS(const char* filename) {
// TODO: check ROM CRC32 here // TODO: check ROM CRC32 here
Util::print("Loaded movie '{}' ", loaded_tas_movie_header.movie_description); Util::print("Loaded movie '{}' ", loaded_tas_movie_header.movie_description);
Util::print("by {}\n", loaded_tas_movie_header.author_name); Util::print("by {}", loaded_tas_movie_header.author_name);
Util::print("{} controller(s) connected\n", loaded_tas_movie_header.numControllers); Util::print("{} controller(s) connected", loaded_tas_movie_header.numControllers);
if (loaded_tas_movie_header.numControllers != 1) { if (loaded_tas_movie_header.numControllers != 1) {
Util::panic("Currently, only movies with 1 controller connected are supported.\n"); Util::panic("Currently, only movies with 1 controller connected are supported.");
} }
loaded_tas_movie_index = sizeof(TASMovieHeader) - 4; // skip header loaded_tas_movie_index = sizeof(TASMovieHeader) - 4; // skip header
@@ -120,22 +120,22 @@ bool TasMovieLoaded() {
} }
inline void LogController(const n64::Controller& controller) { inline void LogController(const n64::Controller& controller) {
Util::print("c_right: {}\n", controller.c_right); Util::print("c_right: {}", controller.c_right);
Util::print("c_left: {}\n", controller.c_left); Util::print("c_left: {}", controller.c_left);
Util::print("c_down: {}\n", controller.c_down); Util::print("c_down: {}", controller.c_down);
Util::print("c_up: {}\n", controller.c_up); Util::print("c_up: {}", controller.c_up);
Util::print("r: {}\n", controller.r); Util::print("r: {}", controller.r);
Util::print("l: {}\n", controller.l); Util::print("l: {}", controller.l);
Util::print("dp_right: {}\n", controller.dp_right); Util::print("dp_right: {}", controller.dp_right);
Util::print("dp_left: {}\n", controller.dp_left); Util::print("dp_left: {}", controller.dp_left);
Util::print("dp_down: {}\n", controller.dp_down); Util::print("dp_down: {}", controller.dp_down);
Util::print("dp_up: {}\n", controller.dp_up); Util::print("dp_up: {}", controller.dp_up);
Util::print("z: {}\n", controller.z); Util::print("z: {}", controller.z);
Util::print("b: {}\n", controller.b); Util::print("b: {}", controller.b);
Util::print("a: {}\n", controller.a); Util::print("a: {}", controller.a);
Util::print("start: {}\n", controller.start); Util::print("start: {}", controller.start);
Util::print("joy_x: {}\n", controller.joy_x); Util::print("joy_x: {}", controller.joy_x);
Util::print("joy_y: {}\n\n", controller.joy_y); Util::print("joy_y: {}", controller.joy_y);
} }
n64::Controller TasNextInputs() { n64::Controller TasNextInputs() {

2
src/backend/RomHelpers.hpp
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@@ -24,7 +24,7 @@ inline void SwapN64Rom(size_t size, u8 *rom, u32 endianness) {
SwapBuffer32(size, rom); SwapBuffer32(size, rom);
break; break;
default: default:
panic("Unrecognized rom format! Make sure this is a valid Nintendo 64 ROM dump!\n"); panic("Unrecognized rom format! Make sure this is a valid Nintendo 64 ROM dump!");
} }
} }
} }

4
src/backend/core/MMIO.cpp
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@@ -26,7 +26,7 @@ u32 MMIO::Read(u32 addr) {
case 0x04700000 ... 0x047FFFFF: return ri.Read(addr); case 0x04700000 ... 0x047FFFFF: return ri.Read(addr);
case 0x04800000 ... 0x048FFFFF: return si.Read(mi, addr); case 0x04800000 ... 0x048FFFFF: return si.Read(mi, addr);
default: default:
Util::panic("Unhandled mmio read at addr {:08X}\n", addr); Util::panic("Unhandled mmio read at addr {:08X}", addr);
} }
} }
@@ -41,7 +41,7 @@ void MMIO::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
case 0x04700000 ... 0x047FFFFF: ri.Write(addr, val); break; case 0x04700000 ... 0x047FFFFF: ri.Write(addr, val); break;
case 0x04800000 ... 0x048FFFFF: si.Write(mem, regs, addr, val); break; case 0x04800000 ... 0x048FFFFF: si.Write(mem, regs, addr, val); break;
default: default:
Util::panic("Unhandled mmio write at addr {:08X} with val {:08X}\n", addr, val); Util::panic("Unhandled mmio write at addr {:08X} with val {:08X}", addr, val);
} }
} }
} }

26
src/backend/core/Mem.cpp
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@@ -36,7 +36,7 @@ inline void SetROMCIC(u32 checksum, ROM& rom) {
case 0xCF7F41DC: rom.cicType = CIC_NUS_6105_7105; break; case 0xCF7F41DC: rom.cicType = CIC_NUS_6105_7105; break;
case 0xD1059C6A: rom.cicType = CIC_NUS_6106_7106; break; case 0xD1059C6A: rom.cicType = CIC_NUS_6106_7106; break;
default: default:
Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!\n", checksum); Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum);
rom.cicType = UNKNOWN_CIC_TYPE; rom.cicType = UNKNOWN_CIC_TYPE;
break; break;
} }
@@ -134,7 +134,7 @@ u8 Mem::Read8(n64::Registers &regs, u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF:
return 0; return 0;
default: default:
Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc); Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
} }
} }
} }
@@ -174,7 +174,7 @@ u16 Mem::Read16(n64::Registers &regs, u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF:
return 0; return 0;
default: default:
Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc); Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
} }
} }
} }
@@ -208,7 +208,7 @@ u32 Mem::Read32(n64::Registers &regs, u32 paddr) {
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF: case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0; case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
default: default:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc); Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
} }
} }
} }
@@ -247,7 +247,7 @@ u64 Mem::Read64(n64::Registers &regs, u32 paddr) {
case 0x1FC00800 ... 0xFFFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF:
return 0; return 0;
default: default:
Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc); Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64) regs.pc);
} }
} }
} }
@@ -277,7 +277,7 @@ void Mem::Write8(Registers& regs, u32 paddr, u32 val) {
case 0x04100000 ... 0x041FFFFF: case 0x04100000 ... 0x041FFFFF:
case 0x04300000 ... 0x044FFFFF: case 0x04300000 ... 0x044FFFFF:
case 0x04500000 ... 0x048FFFFF: case 0x04500000 ... 0x048FFFFF:
Util::panic("MMIO Write8!\n"); Util::panic("MMIO Write8!");
case 0x10000000 ... 0x1FBFFFFF: case 0x10000000 ... 0x1FBFFFFF:
break; break;
case PIF_RAM_REGION: case PIF_RAM_REGION:
@@ -289,7 +289,7 @@ void Mem::Write8(Registers& regs, u32 paddr, u32 val) {
case 0x00800000 ... 0x03FFFFFF: case 0x00800000 ... 0x03FFFFFF:
case 0x04200000 ... 0x042FFFFF: case 0x04200000 ... 0x042FFFFF:
case 0x08000000 ... 0x0FFFFFFF: case 0x08000000 ... 0x0FFFFFFF:
Util::debug("SRAM 8 bit write {:02X}\n", val); Util::debug("SRAM 8 bit write {:02X}", val);
break; break;
case 0x04900000 ... 0x07FFFFFF: case 0x04900000 ... 0x07FFFFFF:
case 0x1FC00000 ... 0x1FC007BF: case 0x1FC00000 ... 0x1FC007BF:
@@ -297,7 +297,7 @@ void Mem::Write8(Registers& regs, u32 paddr, u32 val) {
case 0x80000000 ... 0xFFFFFFFF: case 0x80000000 ... 0xFFFFFFFF:
break; break;
default: default:
Util::panic("Unimplemented 8-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, Util::panic("Unimplemented 8-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64) regs.pc); (u64) regs.pc);
} }
} }
@@ -328,7 +328,7 @@ void Mem::Write16(Registers& regs, u32 paddr, u32 val) {
case 0x04100000 ... 0x041FFFFF: case 0x04100000 ... 0x041FFFFF:
case 0x04300000 ... 0x044FFFFF: case 0x04300000 ... 0x044FFFFF:
case 0x04500000 ... 0x048FFFFF: case 0x04500000 ... 0x048FFFFF:
Util::panic("MMIO Write16!\n"); Util::panic("MMIO Write16!");
case 0x10000000 ... 0x1FBFFFFF: case 0x10000000 ... 0x1FBFFFFF:
break; break;
case PIF_RAM_REGION: case PIF_RAM_REGION:
@@ -346,7 +346,7 @@ void Mem::Write16(Registers& regs, u32 paddr, u32 val) {
case 0x80000000 ... 0xFFFFFFFF: case 0x80000000 ... 0xFFFFFFFF:
break; break;
default: default:
Util::panic("Unimplemented 16-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, Util::panic("Unimplemented 16-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64) regs.pc); (u64) regs.pc);
} }
} }
@@ -394,7 +394,7 @@ void Mem::Write32(Registers& regs, u32 paddr, u32 val) {
case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF: case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
case 0x1FC00000 ... 0x1FC007BF: case 0x1FC00800 ... 0x7FFFFFFF: case 0x1FC00000 ... 0x1FC007BF: case 0x1FC00800 ... 0x7FFFFFFF:
case 0x80000000 ... 0xFFFFFFFF: break; case 0x80000000 ... 0xFFFFFFFF: break;
default: Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc); default: Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val, (u64)regs.pc);
} }
} }
} }
@@ -423,7 +423,7 @@ void Mem::Write64(Registers& regs, u32 paddr, u64 val) {
case 0x04100000 ... 0x041FFFFF: case 0x04100000 ... 0x041FFFFF:
case 0x04300000 ... 0x044FFFFF: case 0x04300000 ... 0x044FFFFF:
case 0x04500000 ... 0x048FFFFF: case 0x04500000 ... 0x048FFFFF:
Util::panic("MMIO Write64!\n"); Util::panic("MMIO Write64!");
case 0x10000000 ... 0x1FBFFFFF: case 0x10000000 ... 0x1FBFFFFF:
break; break;
case PIF_RAM_REGION: case PIF_RAM_REGION:
@@ -439,7 +439,7 @@ void Mem::Write64(Registers& regs, u32 paddr, u64 val) {
case 0x80000000 ... 0xFFFFFFFF: case 0x80000000 ... 0xFFFFFFFF:
break; break;
default: default:
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
(u64) regs.pc); (u64) regs.pc);
} }
} }

76
src/backend/core/RDP.cpp
View File

@@ -36,7 +36,7 @@ auto RDP::Read(u32 addr) const -> u32 {
case 0x04100018: return dpc.status.pipeBusy; case 0x04100018: return dpc.status.pipeBusy;
case 0x0410001C: return dpc.tmem; case 0x0410001C: return dpc.tmem;
default: default:
Util::panic("Unhandled DP Command Registers read (addr: {:08X})\n", addr); Util::panic("Unhandled DP Command Registers read (addr: {:08X})", addr);
} }
} }
@@ -46,7 +46,7 @@ void RDP::Write(MI& mi, Registers& regs, RSP& rsp, u32 addr, u32 val) {
case 0x04100004: WriteEnd(mi, regs, rsp, val); break; case 0x04100004: WriteEnd(mi, regs, rsp, val); break;
case 0x0410000C: WriteStatus(mi, regs, rsp, val); break; case 0x0410000C: WriteStatus(mi, regs, rsp, val); break;
default: default:
Util::panic("Unhandled DP Command Registers write (addr: {:08X}, val: {:08X})\n", addr, val); Util::panic("Unhandled DP Command Registers write (addr: {:08X}, val: {:08X})", addr, val);
} }
} }
@@ -75,41 +75,41 @@ void RDP::WriteStatus(MI& mi, Registers& regs, RSP& rsp, u32 val) {
inline void logCommand(u8 cmd) { inline void logCommand(u8 cmd) {
switch(cmd) { switch(cmd) {
case 0x08: Util::debug("Fill triangle\n"); break; case 0x08: Util::debug("Fill triangle"); break;
case 0x09: Util::debug("Fill, zbuf triangle\n"); break; case 0x09: Util::debug("Fill, zbuf triangle"); break;
case 0x0a: Util::debug("Texture triangle\n"); break; case 0x0a: Util::debug("Texture triangle"); break;
case 0x0b: Util::debug("Texture, zbuf triangle\n"); break; case 0x0b: Util::debug("Texture, zbuf triangle"); break;
case 0x0c: Util::debug("Shade triangle\n"); break; case 0x0c: Util::debug("Shade triangle"); break;
case 0x0d: Util::debug("Shade, zbuf triangle\n"); break; case 0x0d: Util::debug("Shade, zbuf triangle"); break;
case 0x0e: Util::debug("Shade, texture triangle\n"); break; case 0x0e: Util::debug("Shade, texture triangle"); break;
case 0x0f: Util::debug("Shade, texture, zbuf triangle\n"); break; case 0x0f: Util::debug("Shade, texture, zbuf triangle"); break;
case 0x24: Util::debug("Texture rectangle\n"); break; case 0x24: Util::debug("Texture rectangle"); break;
case 0x25: Util::debug("Texture rectangle flip\n"); break; case 0x25: Util::debug("Texture rectangle flip"); break;
case 0x26: Util::debug("Sync load\n"); break; case 0x26: Util::debug("Sync load"); break;
case 0x27: Util::debug("Sync pipe\n"); break; case 0x27: Util::debug("Sync pipe"); break;
case 0x28: Util::debug("Sync tile\n"); break; case 0x28: Util::debug("Sync tile"); break;
case 0x29: Util::debug("Sync full\n"); break; case 0x29: Util::debug("Sync full"); break;
case 0x2a: Util::debug("Set key gb\n"); break; case 0x2a: Util::debug("Set key gb"); break;
case 0x2b: Util::debug("Set key r\n"); break; case 0x2b: Util::debug("Set key r"); break;
case 0x2c: Util::debug("Set convert\n"); break; case 0x2c: Util::debug("Set convert"); break;
case 0x2d: Util::debug("Set scissor\n"); break; case 0x2d: Util::debug("Set scissor"); break;
case 0x2e: Util::debug("Set prim depth\n"); break; case 0x2e: Util::debug("Set prim depth"); break;
case 0x2f: Util::debug("Set other modes\n"); break; case 0x2f: Util::debug("Set other modes"); break;
case 0x30: Util::debug("Load TLUT\n"); break; case 0x30: Util::debug("Load TLUT"); break;
case 0x32: Util::debug("Set tile size\n"); break; case 0x32: Util::debug("Set tile size"); break;
case 0x33: Util::debug("Load block\n"); break; case 0x33: Util::debug("Load block"); break;
case 0x34: Util::debug("Load tile\n"); break; case 0x34: Util::debug("Load tile"); break;
case 0x35: Util::debug("Set tile\n"); break; case 0x35: Util::debug("Set tile"); break;
case 0x36: Util::debug("Fill rectangle\n"); break; case 0x36: Util::debug("Fill rectangle"); break;
case 0x37: Util::debug("Set fill color\n"); break; case 0x37: Util::debug("Set fill color"); break;
case 0x38: Util::debug("Set fog color\n"); break; case 0x38: Util::debug("Set fog color"); break;
case 0x39: Util::debug("Set blend color\n"); break; case 0x39: Util::debug("Set blend color"); break;
case 0x3a: Util::debug("Set prim color\n"); break; case 0x3a: Util::debug("Set prim color"); break;
case 0x3b: Util::debug("Set env color\n"); break; case 0x3b: Util::debug("Set env color"); break;
case 0x3c: Util::debug("Set combine\n"); break; case 0x3c: Util::debug("Set combine"); break;
case 0x3d: Util::debug("Set texture image\n"); break; case 0x3d: Util::debug("Set texture image"); break;
case 0x3e: Util::debug("Set mask image\n"); break; case 0x3e: Util::debug("Set mask image"); break;
case 0x3f: Util::debug("Set color image\n"); break; case 0x3f: Util::debug("Set color image"); break;
} }
} }
@@ -131,7 +131,7 @@ void RDP::RunCommand(MI& mi, Registers& regs, RSP& rsp) {
if (len <= 0) return; if (len <= 0) return;
if (len + (remaining_cmds * 4) > 0xFFFFF) { if (len + (remaining_cmds * 4) > 0xFFFFF) {
Util::panic("Too many RDP commands\n"); Util::panic("Too many RDP commands");
return; return;
} }

8
src/backend/core/RSP.cpp
View File

@@ -61,8 +61,8 @@ inline void logRSP(const RSP& rsp, const u32 instr) {
Util::debug("{:04X}", rsp.acc.l.element[i]); Util::debug("{:04X}", rsp.acc.l.element[i]);
} }
Util::debug(" {:04X} {:04X} {:02X}\n", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE()); Util::debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
Util::debug("DMEM: {:02X}{:02X}\n", rsp.dmem[0x3c4], rsp.dmem[0x3c5]); Util::debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
} }
*/ */
@@ -79,7 +79,7 @@ auto RSP::Read(u32 addr) -> u32{
return AcquireSemaphore(); return AcquireSemaphore();
case 0x04080000: return pc & 0xFFC; case 0x04080000: return pc & 0xFFC;
default: default:
Util::panic("Unimplemented SP register read {:08X}\n", addr); Util::panic("Unimplemented SP register read {:08X}", addr);
} }
} }
@@ -129,7 +129,7 @@ void RSP::Write(Mem& mem, Registers& regs, u32 addr, u32 value) {
SetPC(value); SetPC(value);
} break; } break;
default: default:
Util::panic("Unimplemented SP register write {:08X}, val: {:08X}\n", addr, value); Util::panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, value);
} }
} }
} }

4
src/backend/core/interpreter/cop/cop1instructions.cpp
View File

@@ -97,7 +97,7 @@ void Cop1::cfc1(Registers& regs, u32 instr) const {
case 31: case 31:
val = fcr31.raw; val = fcr31.raw;
break; break;
default: Util::panic("Undefined CFC1 with rd != 0 or 31\n"); default: Util::panic("Undefined CFC1 with rd != 0 or 31");
} }
regs.gpr[RT(instr)] = val; regs.gpr[RT(instr)] = val;
} }
@@ -111,7 +111,7 @@ void Cop1::ctc1(Registers& regs, u32 instr) {
val &= 0x183ffff; val &= 0x183ffff;
fcr31.raw = val; fcr31.raw = val;
} break; } break;
default: Util::panic("Undefined CTC1 with rd != 0 or 31\n"); default: Util::panic("Undefined CTC1 with rd != 0 or 31");
} }
} }

8
src/backend/core/interpreter/decode.cpp
View File

@@ -63,7 +63,7 @@ void Interpreter::special(u32 instr) {
case 0x3E: dsrl32(instr); break; case 0x3E: dsrl32(instr); break;
case 0x3F: dsra32(instr); break; case 0x3F: dsra32(instr); break;
default: default:
Util::panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})\n", (mask >> 3) & 7, mask & 7, instr, (u64)regs.oldPC); Util::panic("Unimplemented special {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 7, mask & 7, instr, (u64)regs.oldPC);
} }
} }
@@ -86,7 +86,7 @@ void Interpreter::regimm(u32 instr) {
case 0x12: bllink(instr, regs.gpr[RS(instr)] < 0); break; case 0x12: bllink(instr, regs.gpr[RS(instr)] < 0); break;
case 0x13: bllink(instr, regs.gpr[RS(instr)] >= 0); break; case 0x13: bllink(instr, regs.gpr[RS(instr)] >= 0); break;
default: default:
Util::panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})\n", (mask >> 3) & 3, mask & 7, instr, (u64)regs.oldPC); Util::panic("Unimplemented regimm {} {} ({:08X}) (pc: {:016X})", (mask >> 3) & 3, mask & 7, instr, (u64)regs.oldPC);
} }
} }
@@ -117,7 +117,7 @@ void Interpreter::Exec(u32 instr) {
case 0x03: jal(instr); break; case 0x03: jal(instr); break;
case 0x04: b(instr, regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break; case 0x04: b(instr, regs.gpr[RS(instr)] == regs.gpr[RT(instr)]); break;
case 0x05: { case 0x05: {
//fmt::print("RS: {:016X}, RT: {:016X}\n", (u64)regs.gpr[RS(instr)], (u64)regs.gpr[RT(instr)]); //fmt::print("RS: {:016X}, RT: {:016X}", (u64)regs.gpr[RS(instr)], (u64)regs.gpr[RT(instr)]);
b(instr, regs.gpr[RS(instr)] != regs.gpr[RT(instr)]); b(instr, regs.gpr[RS(instr)] != regs.gpr[RT(instr)]);
} break; } break;
case 0x06: b(instr, regs.gpr[RS(instr)] <= 0); break; case 0x06: b(instr, regs.gpr[RS(instr)] <= 0); break;
@@ -169,7 +169,7 @@ void Interpreter::Exec(u32 instr) {
case 0x3D: regs.cop1.sdc1(regs, mem, instr); break; case 0x3D: regs.cop1.sdc1(regs, mem, instr); break;
case 0x3F: sd(instr); break; case 0x3F: sd(instr); break;
default: default:
Util::panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})\n", mask, instr, (u64)regs.oldPC); Util::panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", mask, instr, (u64)regs.oldPC);
} }
} }
} }

2
src/backend/core/mmio/AI.cpp
View File

@@ -69,7 +69,7 @@ void AI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dac.precision = bitrate + 1; dac.precision = bitrate + 1;
break; break;
default: default:
Util::panic("Unhandled AI write at addr {:08X} with val {:08X}\n", addr, val); Util::panic("Unhandled AI write at addr {:08X} with val {:08X}", addr, val);
} }
} }

4
src/backend/core/mmio/MI.cpp
View File

@@ -23,7 +23,7 @@ auto MI::Read(u32 paddr) const -> u32 {
case 0x8: return miIntr.raw & 0x3F; case 0x8: return miIntr.raw & 0x3F;
case 0xC: return miIntrMask.raw & 0x3F; case 0xC: return miIntrMask.raw & 0x3F;
default: default:
Util::panic("Unhandled MI[{:08X}] read\n", paddr); Util::panic("Unhandled MI[{:08X}] read", paddr);
} }
} }
@@ -78,7 +78,7 @@ void MI::Write(Registers& regs, u32 paddr, u32 val) {
UpdateInterrupt(*this, regs); UpdateInterrupt(*this, regs);
break; break;
default: default:
Util::panic("Unhandled MI[{:08X}] write ({:08X})\n", val, paddr); Util::panic("Unhandled MI[{:08X}] write ({:08X})", val, paddr);
} }
} }
} }

8
src/backend/core/mmio/PI.cpp
View File

@@ -34,7 +34,7 @@ auto PI::Read(MI& mi, u32 addr) const -> u32 {
case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030: case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030:
return stub[(addr & 0xff) - 5]; return stub[(addr & 0xff) - 5];
default: default:
Util::panic("Unhandled PI[{:08X}] read\n", addr); Util::panic("Unhandled PI[{:08X}] read", addr);
} }
} }
@@ -57,7 +57,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dramAddr = dram_addr + len; dramAddr = dram_addr + len;
cartAddr = cart_addr + len; cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI); InterruptRaise(mi, regs, Interrupt::PI);
//Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})\n", len, dramAddr, cartAddr); //Util::debug("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
} break; } break;
case 0x0460000C: { case 0x0460000C: {
u32 len = (val & 0x00FFFFFF) + 1; u32 len = (val & 0x00FFFFFF) + 1;
@@ -73,7 +73,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
dramAddr = dram_addr + len; dramAddr = dram_addr + len;
cartAddr = cart_addr + len; cartAddr = cart_addr + len;
InterruptRaise(mi, regs, Interrupt::PI); InterruptRaise(mi, regs, Interrupt::PI);
//Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})\n", len, cart_addr, dram_addr); //Util::debug("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cart_addr, dram_addr);
} break; } break;
case 0x04600010: case 0x04600010:
if(val & 2) { if(val & 2) {
@@ -84,7 +84,7 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
stub[(addr & 0xff) - 5] = val & 0xff; stub[(addr & 0xff) - 5] = val & 0xff;
break; break;
default: default:
Util::panic("Unhandled PI[{:08X}] write ({:08X})\n", val, addr); Util::panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
} }
} }
} }

12
src/backend/core/mmio/PIF.cpp
View File

@@ -27,7 +27,7 @@ void PIF::LoadMempak(fs::path path) {
size_t actualSize = ftell(f); size_t actualSize = ftell(f);
fseek(f, 0, SEEK_SET); fseek(f, 0, SEEK_SET);
if (actualSize != MEMPAK_SIZE) { if (actualSize != MEMPAK_SIZE) {
Util::panic("Corrupt mempak!\n"); Util::panic("Corrupt mempak!");
} }
fread(mempak, 1, MEMPAK_SIZE, f); fread(mempak, 1, MEMPAK_SIZE, f);
@@ -47,7 +47,7 @@ inline size_t getSaveSize(SaveType saveType) {
case SAVE_FLASH_1m: case SAVE_FLASH_1m:
return 131072; return 131072;
default: default:
Util::panic("Unknown save type!\n"); Util::panic("Unknown save type!");
} }
} }
@@ -70,7 +70,7 @@ void PIF::LoadEeprom(SaveType saveType, fs::path path) {
size_t actualSize = ftell(f); size_t actualSize = ftell(f);
fseek(f, 0, SEEK_SET); fseek(f, 0, SEEK_SET);
if (actualSize != eepromSize) { if (actualSize != eepromSize) {
Util::panic("Corrupt eeprom!\n"); Util::panic("Corrupt eeprom!");
} }
fread(eeprom, 1, eepromSize, f); fread(eeprom, 1, eepromSize, f);
@@ -284,7 +284,7 @@ void PIF::EepromWrite(u8* cmd, u8* res, const Mem& mem) const {
if (channel == 4) { if (channel == 4) {
u8 offset = cmd[3]; u8 offset = cmd[3];
if ((offset * 8) >= getSaveSize(mem.saveType)) { if ((offset * 8) >= getSaveSize(mem.saveType)) {
Util::panic("Out of range EEPROM write! offset: {:02X}\n", offset); Util::panic("Out of range EEPROM write! offset: {:02X}", offset);
} }
for (int i = 0; i < 8; i++) { for (int i = 0; i < 8; i++) {
@@ -407,7 +407,7 @@ void PIF::DoPIFHLE(Mem& mem, Registers& regs, bool pal, CICType cicType) {
switch(cicType) { switch(cicType) {
case UNKNOWN_CIC_TYPE: case UNKNOWN_CIC_TYPE:
Util::warn("Unknown CIC type!\n"); Util::warn("Unknown CIC type!");
break; break;
case CIC_NUS_6101: case CIC_NUS_6101:
regs.gpr[0] = 0x0000000000000000; regs.gpr[0] = 0x0000000000000000;
@@ -673,7 +673,7 @@ void PIF::ExecutePIF(Mem& mem, Registers& regs) {
mem.Write32(regs, PIF_RAM_REGION_START + 0x24, cicSeeds[cicType]); mem.Write32(regs, PIF_RAM_REGION_START + 0x24, cicSeeds[cicType]);
switch(cicType) { switch(cicType) {
case UNKNOWN_CIC_TYPE: case UNKNOWN_CIC_TYPE:
Util::warn("Unknown CIC type!\n"); Util::warn("Unknown CIC type!");
break; break;
case CIC_NUS_6101 ... CIC_NUS_6103_7103: case CIC_NUS_6101 ... CIC_NUS_6103_7103:
mem.Write32(regs, 0x318, RDRAM_SIZE); mem.Write32(regs, 0x318, RDRAM_SIZE);

4
src/backend/core/mmio/RI.cpp
View File

@@ -20,7 +20,7 @@ auto RI::Read(u32 addr) const -> u32 {
case 0x0470000C: return select; case 0x0470000C: return select;
case 0x04700010: return refresh; case 0x04700010: return refresh;
default: default:
Util::panic("Unhandled RI[{:08X}] read\n", addr); Util::panic("Unhandled RI[{:08X}] read", addr);
} }
} }
@@ -31,7 +31,7 @@ void RI::Write(u32 addr, u32 val) {
case 0x0470000C: select = val; break; case 0x0470000C: select = val; break;
case 0x04700010: refresh = val; break; case 0x04700010: refresh = val; break;
default: default:
Util::panic("Unhandled RI[{:08X}] write with val {:08X}\n", addr, val); Util::panic("Unhandled RI[{:08X}] write with val {:08X}", addr, val);
} }
} }
} }

8
src/backend/core/mmio/SI.cpp
View File

@@ -30,7 +30,7 @@ auto SI::Read(MI& mi, u32 addr) const -> u32 {
return val; return val;
} }
default: default:
Util::panic("Unhandled SI[{:08X}] read\n", addr); Util::panic("Unhandled SI[{:08X}] read", addr);
} }
} }
@@ -42,12 +42,12 @@ void DMA(Mem& mem, Registers& regs) {
for(int i = 0; i < 64; i++) { for(int i = 0; i < 64; i++) {
mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)] = si.pif.Read(si.pifAddr + i); mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)] = si.pif.Read(si.pifAddr + i);
} }
//Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})\n", si.pifAddr, si.dramAddr); //Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})", si.pifAddr, si.dramAddr);
} else { } else {
for(int i = 0; i < 64; i++) { for(int i = 0; i < 64; i++) {
si.pif.Write(si.pifAddr + i, mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)]); si.pif.Write(si.pifAddr + i, mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)]);
} }
//Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", si.dramAddr, si.pifAddr); //Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})", si.dramAddr, si.pifAddr);
si.pif.ProcessCommands(mem); si.pif.ProcessCommands(mem);
} }
InterruptRaise(mem.mmio.mi, regs, Interrupt::SI); InterruptRaise(mem.mmio.mi, regs, Interrupt::SI);
@@ -74,7 +74,7 @@ void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
InterruptLower(mem.mmio.mi, regs, Interrupt::SI); InterruptLower(mem.mmio.mi, regs, Interrupt::SI);
break; break;
default: default:
Util::panic("Unhandled SI[{:08X}] write ({:08X})\n", addr, val); Util::panic("Unhandled SI[{:08X}] write ({:08X})", addr, val);
} }
} }
} }

4
src/backend/core/mmio/VI.cpp
View File

@@ -39,7 +39,7 @@ u32 VI::Read(u32 paddr) const {
case 0x04400030: return xscale.raw; case 0x04400030: return xscale.raw;
case 0x04400034: return yscale.raw; case 0x04400034: return yscale.raw;
default: default:
Util::panic("Unimplemented VI[%08X] read\n", paddr); Util::panic("Unimplemented VI[%08X] read", paddr);
} }
} }
@@ -81,7 +81,7 @@ void VI::Write(MI& mi, Registers& regs, u32 paddr, u32 val) {
case 0x04400030: xscale.raw = val; break; case 0x04400030: xscale.raw = val; break;
case 0x04400034: yscale.raw = val; break; case 0x04400034: yscale.raw = val; break;
default: default:
Util::panic("Unimplemented VI[%08X] write (%08X)\n", paddr, val); Util::panic("Unimplemented VI[%08X] write (%08X)", paddr, val);
} }
} }
} }

16
src/backend/core/registers/Cop0.cpp
View File

@@ -54,7 +54,7 @@ u32 Cop0::GetReg32(u8 addr) {
case 23: case 24: case 25: case 23: case 24: case 25:
case 31: return openbus; case 31: return openbus;
default: default:
Util::panic("Unsupported word read from COP0 register {}\n", index); Util::panic("Unsupported word read from COP0 register {}", index);
} }
} }
@@ -75,7 +75,7 @@ u64 Cop0::GetReg64(u8 addr) {
case 23: case 24: case 25: case 23: case 24: case 25:
case 31: return openbus; case 31: return openbus;
default: default:
Util::panic("Unsupported dword read from COP0 register {}\n", index); Util::panic("Unsupported dword read from COP0 register {}", index);
} }
} }
@@ -137,7 +137,7 @@ void Cop0::SetReg32(u8 addr, u32 value) {
case 23: case 24: case 25: case 23: case 24: case 25:
case 31: break; case 31: break;
default: default:
Util::panic("Unsupported word write from COP0 register {}\n", index); Util::panic("Unsupported word write from COP0 register {}", index);
} }
} }
@@ -165,7 +165,7 @@ void Cop0::SetReg64(u8 addr, u64 value) {
case COP0_REG_LLADDR: LLAddr = value; break; case COP0_REG_LLADDR: LLAddr = value; break;
case COP0_REG_ERROREPC: ErrorEPC = (s64)value; break; case COP0_REG_ERROREPC: ErrorEPC = (s64)value; break;
default: default:
Util::panic("Unsupported dword write to COP0 register {}\n", addr); Util::panic("Unsupported dword write to COP0 register {}", addr);
} }
} }
@@ -270,7 +270,7 @@ void FireException(Registers& regs, ExceptionCode code, int cop, bool useOldPC)
regs.cop0.cause.exceptionCode = static_cast<u8>(code); regs.cop0.cause.exceptionCode = static_cast<u8>(code);
if(regs.cop0.status.bev) { if(regs.cop0.status.bev) {
Util::panic("BEV bit set!\n"); Util::panic("BEV bit set!");
} else { } else {
switch(code) { switch(code) {
case ExceptionCode::Interrupt: case ExceptionCode::TLBModification: case ExceptionCode::Interrupt: case ExceptionCode::TLBModification:
@@ -291,7 +291,7 @@ void FireException(Registers& regs, ExceptionCode code, int cop, bool useOldPC)
regs.SetPC32(0x80000000); regs.SetPC32(0x80000000);
} }
break; break;
default: Util::panic("Unhandled exception! {}\n", static_cast<u8>(code)); default: Util::panic("Unhandled exception! {}", static_cast<u8>(code));
} }
} }
} }
@@ -309,7 +309,7 @@ void HandleTLBException(Registers& regs, u64 vaddr) {
ExceptionCode GetTLBExceptionCode(TLBError error, TLBAccessType accessType) { ExceptionCode GetTLBExceptionCode(TLBError error, TLBAccessType accessType) {
switch(error) { switch(error) {
case NONE: Util::panic("Getting TLB exception with error NONE\n"); case NONE: Util::panic("Getting TLB exception with error NONE");
case INVALID: case MISS: case INVALID: case MISS:
return accessType == LOAD ? return accessType == LOAD ?
ExceptionCode::TLBLoad : ExceptionCode::TLBStore; ExceptionCode::TLBLoad : ExceptionCode::TLBStore;
@@ -319,7 +319,7 @@ ExceptionCode GetTLBExceptionCode(TLBError error, TLBAccessType accessType) {
return accessType == LOAD ? return accessType == LOAD ?
ExceptionCode::AddressErrorLoad : ExceptionCode::AddressErrorStore; ExceptionCode::AddressErrorLoad : ExceptionCode::AddressErrorStore;
default: default:
Util::panic("Getting TLB exception for unknown error code! ({})\n", static_cast<u8>(error)); Util::panic("Getting TLB exception for unknown error code! ({})", static_cast<u8>(error));
} }
} }

4
src/backend/core/registers/Cop0.hpp
View File

@@ -282,9 +282,9 @@ static inline bool MapVAddr(Registers& regs, TLBAccessType accessType, u64 vaddr
case 4 ... 5: case 4 ... 5:
paddr = vaddr & 0x1FFFFFFF; paddr = vaddr & 0x1FFFFFFF;
return true; return true;
case 6: Util::panic("Unimplemented virtual mapping in KSSEG! ({:08X})\n", vaddr); case 6: Util::panic("Unimplemented virtual mapping in KSSEG! ({:08X})", vaddr);
default: default:
Util::panic("Should never end up in default case in map_vaddr! ({:08X})\n", vaddr); Util::panic("Should never end up in default case in map_vaddr! ({:08X})", vaddr);
} }
return false; return false;

2
src/backend/core/registers/Cop1.cpp
View File

@@ -39,7 +39,7 @@ void Cop1::decode(Registers& regs, Interpreter& cpu, u32 instr) {
case 1: cpu.b(instr, regs.cop1.fcr31.compare); break; case 1: cpu.b(instr, regs.cop1.fcr31.compare); break;
case 2: cpu.bl(instr, !regs.cop1.fcr31.compare); break; case 2: cpu.bl(instr, !regs.cop1.fcr31.compare); break;
case 3: cpu.bl(instr, regs.cop1.fcr31.compare); break; case 3: cpu.bl(instr, regs.cop1.fcr31.compare); break;
default: Util::panic("Undefined BC COP1 {:02X}\n", mask_branch); default: Util::panic("Undefined BC COP1 {:02X}", mask_branch);
} }
break; break;
case 0x10: // s case 0x10: // s

32
src/backend/core/rsp/decode.cpp
View File

@@ -7,7 +7,7 @@
namespace n64 { namespace n64 {
inline void special(MI& mi, Registers& regs, RSP& rsp, u32 instr) { inline void special(MI& mi, Registers& regs, RSP& rsp, u32 instr) {
u8 mask = instr & 0x3f; u8 mask = instr & 0x3f;
//Util::print("rsp special {:02X}\n", mask); //Util::print("rsp special {:02X}", mask);
switch(mask) { switch(mask) {
case 0x00: case 0x00:
if(instr != 0) { if(instr != 0) {
@@ -41,25 +41,25 @@ inline void special(MI& mi, Registers& regs, RSP& rsp, u32 instr) {
case 0x27: rsp.nor(instr); break; case 0x27: rsp.nor(instr); break;
case 0x2A: rsp.slt(instr); break; case 0x2A: rsp.slt(instr); break;
case 0x2B: rsp.sltu(instr); break; case 0x2B: rsp.sltu(instr); break;
default: Util::panic("Unhandled RSP special instruction ({:06b})\n", mask); default: Util::panic("Unhandled RSP special instruction ({:06b})", mask);
} }
} }
inline void regimm(RSP& rsp, u32 instr) { inline void regimm(RSP& rsp, u32 instr) {
u8 mask = ((instr >> 16) & 0x1F); u8 mask = ((instr >> 16) & 0x1F);
//Util::print("rsp regimm {:02X}\n", mask); //Util::print("rsp regimm {:02X}", mask);
switch(mask) { switch(mask) {
case 0x00: rsp.b(instr, (s32)rsp.gpr[RS(instr)] < 0); break; case 0x00: rsp.b(instr, (s32)rsp.gpr[RS(instr)] < 0); break;
case 0x01: rsp.b(instr, (s32)rsp.gpr[RS(instr)] >= 0); break; case 0x01: rsp.b(instr, (s32)rsp.gpr[RS(instr)] >= 0); break;
case 0x10: rsp.blink(instr, (s32)rsp.gpr[RS(instr)] < 0); break; case 0x10: rsp.blink(instr, (s32)rsp.gpr[RS(instr)] < 0); break;
case 0x11: rsp.blink(instr, (s32)rsp.gpr[RS(instr)] >= 0); break; case 0x11: rsp.blink(instr, (s32)rsp.gpr[RS(instr)] >= 0); break;
default: Util::panic("Unhandled RSP regimm instruction ({:05b})\n", mask); default: Util::panic("Unhandled RSP regimm instruction ({:05b})", mask);
} }
} }
inline void lwc2(RSP& rsp, u32 instr) { inline void lwc2(RSP& rsp, u32 instr) {
u8 mask = (instr >> 11) & 0x1F; u8 mask = (instr >> 11) & 0x1F;
//Util::print("lwc2 {:02X}\n", mask); //Util::print("lwc2 {:02X}", mask);
switch(mask) { switch(mask) {
case 0x00: rsp.lbv(instr); break; case 0x00: rsp.lbv(instr); break;
case 0x01: rsp.lsv(instr); break; case 0x01: rsp.lsv(instr); break;
@@ -73,13 +73,13 @@ inline void lwc2(RSP& rsp, u32 instr) {
case 0x09: rsp.lfv(instr); break; case 0x09: rsp.lfv(instr); break;
case 0x0A: break; case 0x0A: break;
case 0x0B: rsp.ltv(instr); break; case 0x0B: rsp.ltv(instr); break;
default: Util::panic("Unhandled RSP LWC2 {:05b}\n", mask); default: Util::panic("Unhandled RSP LWC2 {:05b}", mask);
} }
} }
inline void swc2(RSP& rsp, u32 instr) { inline void swc2(RSP& rsp, u32 instr) {
u8 mask = (instr >> 11) & 0x1F; u8 mask = (instr >> 11) & 0x1F;
//Util::print("swc2 {:02X}\n", mask); //Util::print("swc2 {:02X}", mask);
switch(mask) { switch(mask) {
case 0x00: rsp.sbv(instr); break; case 0x00: rsp.sbv(instr); break;
case 0x01: rsp.ssv(instr); break; case 0x01: rsp.ssv(instr); break;
@@ -93,14 +93,14 @@ inline void swc2(RSP& rsp, u32 instr) {
case 0x09: rsp.sfv(instr); break; case 0x09: rsp.sfv(instr); break;
case 0x0A: rsp.swv(instr); break; case 0x0A: rsp.swv(instr); break;
case 0x0B: rsp.stv(instr); break; case 0x0B: rsp.stv(instr); break;
default: Util::panic("Unhandled RSP SWC2 {:05b}\n", mask); default: Util::panic("Unhandled RSP SWC2 {:05b}", mask);
} }
} }
inline void cop2(RSP& rsp, u32 instr) { inline void cop2(RSP& rsp, u32 instr) {
u8 mask = instr & 0x3F; u8 mask = instr & 0x3F;
u8 mask_sub = (instr >> 21) & 0x1F; u8 mask_sub = (instr >> 21) & 0x1F;
//Util::print("Cop2 {:02X}\n", mask); //Util::print("Cop2 {:02X}", mask);
switch(mask) { switch(mask) {
case 0x00: case 0x00:
if((instr >> 25) & 1) { if((instr >> 25) & 1) {
@@ -111,7 +111,7 @@ inline void cop2(RSP& rsp, u32 instr) {
case 0x02: rsp.cfc2(instr); break; case 0x02: rsp.cfc2(instr); break;
case 0x04: rsp.mtc2(instr); break; case 0x04: rsp.mtc2(instr); break;
case 0x06: rsp.ctc2(instr); break; case 0x06: rsp.ctc2(instr); break;
default: Util::panic("Unhandled RSP COP2 sub ({:05b})\n", mask_sub); default: Util::panic("Unhandled RSP COP2 sub ({:05b})", mask_sub);
} }
} }
break; break;
@@ -172,7 +172,7 @@ inline void cop2(RSP& rsp, u32 instr) {
case 0x34: rsp.vrsq(instr); break; case 0x34: rsp.vrsq(instr); break;
case 0x38 ... 0x3E: rsp.vzero(instr); break; case 0x38 ... 0x3E: rsp.vzero(instr); break;
case 0x37: case 0x3F: break; case 0x37: case 0x3F: break;
default: Util::panic("Unhandled RSP COP2 ({:06b})\n", mask); default: Util::panic("Unhandled RSP COP2 ({:06b})", mask);
} }
} }
@@ -181,15 +181,15 @@ inline void cop0(Registers& regs, Mem& mem, u32 instr) {
MMIO& mmio = mem.mmio; MMIO& mmio = mem.mmio;
RSP& rsp = mmio.rsp; RSP& rsp = mmio.rsp;
RDP& rdp = mmio.rdp; RDP& rdp = mmio.rdp;
//Util::print("Cop0 {:02X}\n", mask); //Util::print("Cop0 {:02X}", mask);
if((instr & 0x7FF) == 0) { if((instr & 0x7FF) == 0) {
switch (mask) { switch (mask) {
case 0x00: rsp.mfc0(rdp, instr); break; case 0x00: rsp.mfc0(rdp, instr); break;
case 0x04: rsp.mtc0(regs, mem, instr); break; case 0x04: rsp.mtc0(regs, mem, instr); break;
default: Util::panic("Unhandled RSP COP0 ({:05b})\n", mask); default: Util::panic("Unhandled RSP COP0 ({:05b})", mask);
} }
} else { } else {
Util::panic("RSP COP0 unknown {:08X}\n", instr); Util::panic("RSP COP0 unknown {:08X}", instr);
} }
} }
@@ -198,7 +198,7 @@ void RSP::Exec(Registers &regs, Mem& mem, u32 instr) {
MMIO& mmio = mem.mmio; MMIO& mmio = mem.mmio;
RDP& rdp = mmio.rdp; RDP& rdp = mmio.rdp;
MI& mi = mmio.mi; MI& mi = mmio.mi;
//Util::print("RSP {:02X}\n", mask); //Util::print("RSP {:02X}", mask);
switch(mask) { switch(mask) {
case 0x00: special(mi, regs, *this, instr); break; case 0x00: special(mi, regs, *this, instr); break;
case 0x01: regimm(*this, instr); break; case 0x01: regimm(*this, instr); break;
@@ -237,7 +237,7 @@ void RSP::Exec(Registers &regs, Mem& mem, u32 instr) {
fwrite(temp, 1, IMEM_SIZE, fp); fwrite(temp, 1, IMEM_SIZE, fp);
free(temp); free(temp);
fclose(fp); fclose(fp);
Util::panic("Unhandled RSP instruction ({:06b}, {:04X})\n", mask, oldPC); Util::panic("Unhandled RSP instruction ({:06b}, {:04X})", mask, oldPC);
} }
} }
} }

8
src/backend/core/rsp/instructions.cpp
View File

@@ -46,7 +46,7 @@ inline auto GetCop0Reg(RSP& rsp, RDP& rdp, u8 index) -> u32{
case 13: return rdp.dpc.status.cmdBusy; case 13: return rdp.dpc.status.cmdBusy;
case 14: return rdp.dpc.status.pipeBusy; case 14: return rdp.dpc.status.pipeBusy;
case 15: return rdp.dpc.status.tmemBusy; case 15: return rdp.dpc.status.tmemBusy;
default: Util::panic("Unhandled RSP COP0 register read at index {}\n", index); default: Util::panic("Unhandled RSP COP0 register read at index {}", index);
} }
} }
@@ -71,13 +71,13 @@ inline void SetCop0Reg(Registers& regs, Mem& mem, u8 index, u32 val) {
if(val == 0) { if(val == 0) {
ReleaseSemaphore(rsp); ReleaseSemaphore(rsp);
} else { } else {
Util::panic("Write with non-zero value to RSP_COP0_RESERVED ({})\n", val); Util::panic("Write with non-zero value to RSP_COP0_RESERVED ({})", val);
} }
break; break;
case 8: rdp.WriteStart(val); break; case 8: rdp.WriteStart(val); break;
case 9: rdp.WriteEnd(mi, regs, rsp, val); break; case 9: rdp.WriteEnd(mi, regs, rsp, val); break;
case 11: rdp.WriteStatus(mi, regs, rsp, val); break; case 11: rdp.WriteStatus(mi, regs, rsp, val); break;
default: Util::panic("Unhandled RSP COP0 register write at index {}\n", index); default: Util::panic("Unhandled RSP COP0 register write at index {}", index);
} }
} }
@@ -899,7 +899,7 @@ void RSP::vmov(u32 instr) {
se = (e & 0b111) | (vs & 0b000); se = (e & 0b111) | (vs & 0b000);
break; break;
default: default:
Util::panic("VMOV: This should be unreachable!\n"); Util::panic("VMOV: This should be unreachable!");
} }
u8 de = vs & 7; u8 de = vs & 7;

2
src/frontend/App.cpp
View File

@@ -36,7 +36,7 @@ void App::Run() {
si.pif.gamepad = SDL_GameControllerOpen(index); si.pif.gamepad = SDL_GameControllerOpen(index);
si.pif.gamepadConnected = false; si.pif.gamepadConnected = false;
if (!si.pif.gamepad) { if (!si.pif.gamepad) {
Util::warn("[WARN]: Could not initialize gamepad: {}\n", SDL_GetError()); Util::warn("[WARN]: Could not initialize gamepad: {}", SDL_GetError());
} else { } else {
si.pif.gamepadConnected = true; si.pif.gamepadConnected = true;
} }

2
src/frontend/imgui/Settings.cpp
View File

@@ -91,7 +91,7 @@ void Settings::RenderWidget(bool& show) {
} }
break; break;
case SelectedSetting::COUNT: case SelectedSetting::COUNT:
Util::panic("BRUH\n"); Util::panic("BRUH");
} }
ImGui::EndPopup(); ImGui::EndPopup();

2
src/utils/File.hpp
View File

@@ -7,7 +7,7 @@ inline auto ReadFileBinary(const std::string& path, u32** buf) {
std::ifstream file(path, std::ios::binary); std::ifstream file(path, std::ios::binary);
file.unsetf(std::ios::skipws); file.unsetf(std::ios::skipws);
if(!file.is_open()) { if(!file.is_open()) {
panic("Could not load file '{}'!\n", path); panic("Could not load file '{}'!", path);
} }
file.seekg(0, std::ios::end); file.seekg(0, std::ios::end);

8
src/utils/log.hpp
View File

@@ -35,22 +35,22 @@ constexpr void print(const std::string& fmt, Args... args) {
template <typename ...Args> template <typename ...Args>
constexpr void panic(const std::string& fmt, Args... args) { constexpr void panic(const std::string& fmt, Args... args) {
print<Error>(fmt, args...); print<Error>(fmt + "\n", args...);
exit(-1); exit(-1);
} }
template <typename ...Args> template <typename ...Args>
constexpr void warn(const std::string& fmt, Args... args) { constexpr void warn(const std::string& fmt, Args... args) {
print<Warn>(fmt, args...); print<Warn>(fmt + "\n", args...);
} }
template <typename ...Args> template <typename ...Args>
constexpr void info(const std::string& fmt, Args... args) { constexpr void info(const std::string& fmt, Args... args) {
print(fmt, args...); print(fmt + "\n", args...);
} }
template <typename ...Args> template <typename ...Args>
constexpr void debug(const std::string& fmt, Args... args) { constexpr void debug(const std::string& fmt, Args... args) {
print<Debug>(fmt, args...); print<Debug>(fmt + "\n", args...);
} }
} }