Merge commit '16a2cf3873e00fa08e587d1b05c9132d98c24f50' into back-to-imgui

external/capstone/include/capstone/arc.h

@@ -0,0 +1,344 @@
+#ifndef CAPSTONE_ARC_H
+#define CAPSTONE_ARC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "platform.h"
+#include "cs_operand.h"
+
+/// Operand type for instruction's operands
+typedef enum arc_op_type {
+	ARC_OP_INVALID = CS_OP_INVALID, ///< Invalid
+	ARC_OP_REG = CS_OP_REG,	      ///< Register operand
+	ARC_OP_IMM = CS_OP_IMM,	      ///< Immediate operand
+} arc_op_type;
+
+/// Instruction operand
+typedef struct cs_arc_op {
+	arc_op_type type;	      //< operand type
+	union {
+		unsigned int reg;     /// register value for REG operand
+		int64_t imm;	      /// immediate value for IMM operand
+	};
+
+	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
+	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+	enum cs_ac_type access;
+} cs_arc_op;
+
+#define NUM_ARC_OPS 8
+
+/// Instruction structure
+typedef struct cs_arc {
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_arc_op operands[NUM_ARC_OPS]; ///< operands for this instruction.
+} cs_arc;
+
+/// ARC registers
+typedef enum arc_reg {
+	// generated content <ARCGenCSRegEnum.inc> begin
+	// clang-format off
+
+	ARC_REG_INVALID = 0,
+	ARC_REG_BLINK = 1,
+	ARC_REG_FP = 2,
+	ARC_REG_GP = 3,
+	ARC_REG_ILINK = 4,
+	ARC_REG_SP = 5,
+	ARC_REG_R0 = 6,
+	ARC_REG_R1 = 7,
+	ARC_REG_R2 = 8,
+	ARC_REG_R3 = 9,
+	ARC_REG_R4 = 10,
+	ARC_REG_R5 = 11,
+	ARC_REG_R6 = 12,
+	ARC_REG_R7 = 13,
+	ARC_REG_R8 = 14,
+	ARC_REG_R9 = 15,
+	ARC_REG_R10 = 16,
+	ARC_REG_R11 = 17,
+	ARC_REG_R12 = 18,
+	ARC_REG_R13 = 19,
+	ARC_REG_R14 = 20,
+	ARC_REG_R15 = 21,
+	ARC_REG_R16 = 22,
+	ARC_REG_R17 = 23,
+	ARC_REG_R18 = 24,
+	ARC_REG_R19 = 25,
+	ARC_REG_R20 = 26,
+	ARC_REG_R21 = 27,
+	ARC_REG_R22 = 28,
+	ARC_REG_R23 = 29,
+	ARC_REG_R24 = 30,
+	ARC_REG_R25 = 31,
+	ARC_REG_R30 = 32,
+	ARC_REG_R32 = 33,
+	ARC_REG_R33 = 34,
+	ARC_REG_R34 = 35,
+	ARC_REG_R35 = 36,
+	ARC_REG_R36 = 37,
+	ARC_REG_R37 = 38,
+	ARC_REG_R38 = 39,
+	ARC_REG_R39 = 40,
+	ARC_REG_R40 = 41,
+	ARC_REG_R41 = 42,
+	ARC_REG_R42 = 43,
+	ARC_REG_R43 = 44,
+	ARC_REG_R44 = 45,
+	ARC_REG_R45 = 46,
+	ARC_REG_R46 = 47,
+	ARC_REG_R47 = 48,
+	ARC_REG_R48 = 49,
+	ARC_REG_R49 = 50,
+	ARC_REG_R50 = 51,
+	ARC_REG_R51 = 52,
+	ARC_REG_R52 = 53,
+	ARC_REG_R53 = 54,
+	ARC_REG_R54 = 55,
+	ARC_REG_R55 = 56,
+	ARC_REG_R56 = 57,
+	ARC_REG_R57 = 58,
+	ARC_REG_R58 = 59,
+	ARC_REG_R59 = 60,
+	ARC_REG_R60 = 61,
+	ARC_REG_R61 = 62,
+	ARC_REG_R62 = 63,
+	ARC_REG_R63 = 64,
+	ARC_REG_STATUS32 = 65,
+	ARC_REG_ENDING, // 66
+
+	// clang-format on
+	// generated content <ARCGenCSRegEnum.inc> end
+} arc_reg;
+
+/// ARC instruction
+typedef enum arc_insn {
+	// generated content <ARCGenCSInsnEnum.inc> begin
+	// clang-format off
+
+	ARC_INS_INVALID,
+	ARC_INS_h,
+	ARC_INS_PBR,
+	ARC_INS_ERROR_FLS,
+	ARC_INS_ERROR_FFS,
+	ARC_INS_PLDFI,
+	ARC_INS_STB_FAR,
+	ARC_INS_STH_FAR,
+	ARC_INS_ST_FAR,
+	ARC_INS_ADC,
+	ARC_INS_ADC_F,
+	ARC_INS_ADD_S,
+	ARC_INS_ADD,
+	ARC_INS_ADD_F,
+	ARC_INS_AND,
+	ARC_INS_AND_F,
+	ARC_INS_ASL_S,
+	ARC_INS_ASL,
+	ARC_INS_ASL_F,
+	ARC_INS_ASR_S,
+	ARC_INS_ASR,
+	ARC_INS_ASR_F,
+	ARC_INS_BCLR_S,
+	ARC_INS_BEQ_S,
+	ARC_INS_BGE_S,
+	ARC_INS_BGT_S,
+	ARC_INS_BHI_S,
+	ARC_INS_BHS_S,
+	ARC_INS_BL,
+	ARC_INS_BLE_S,
+	ARC_INS_BLO_S,
+	ARC_INS_BLS_S,
+	ARC_INS_BLT_S,
+	ARC_INS_BL_S,
+	ARC_INS_BMSK_S,
+	ARC_INS_BNE_S,
+	ARC_INS_B,
+	ARC_INS_BREQ_S,
+	ARC_INS_BRNE_S,
+	ARC_INS_BR,
+	ARC_INS_BSET_S,
+	ARC_INS_BTST_S,
+	ARC_INS_B_S,
+	ARC_INS_CMP_S,
+	ARC_INS_CMP,
+	ARC_INS_LD_S,
+	ARC_INS_MOV_S,
+	ARC_INS_EI_S,
+	ARC_INS_ENTER_S,
+	ARC_INS_FFS_F,
+	ARC_INS_FFS,
+	ARC_INS_FLS_F,
+	ARC_INS_FLS,
+	ARC_INS_ABS_S,
+	ARC_INS_ADD1_S,
+	ARC_INS_ADD2_S,
+	ARC_INS_ADD3_S,
+	ARC_INS_AND_S,
+	ARC_INS_BIC_S,
+	ARC_INS_BRK_S,
+	ARC_INS_EXTB_S,
+	ARC_INS_EXTH_S,
+	ARC_INS_JEQ_S,
+	ARC_INS_JL_S,
+	ARC_INS_JL_S_D,
+	ARC_INS_JNE_S,
+	ARC_INS_J_S,
+	ARC_INS_J_S_D,
+	ARC_INS_LSR_S,
+	ARC_INS_MPYUW_S,
+	ARC_INS_MPYW_S,
+	ARC_INS_MPY_S,
+	ARC_INS_NEG_S,
+	ARC_INS_NOP_S,
+	ARC_INS_NOT_S,
+	ARC_INS_OR_S,
+	ARC_INS_SEXB_S,
+	ARC_INS_SEXH_S,
+	ARC_INS_SUB_S,
+	ARC_INS_SUB_S_NE,
+	ARC_INS_SWI_S,
+	ARC_INS_TRAP_S,
+	ARC_INS_TST_S,
+	ARC_INS_UNIMP_S,
+	ARC_INS_XOR_S,
+	ARC_INS_LDB_S,
+	ARC_INS_LDH_S,
+	ARC_INS_J,
+	ARC_INS_JL,
+	ARC_INS_JLI_S,
+	ARC_INS_LDB_AB,
+	ARC_INS_LDB_AW,
+	ARC_INS_LDB_DI_AB,
+	ARC_INS_LDB_DI_AW,
+	ARC_INS_LDB_DI,
+	ARC_INS_LDB_X_AB,
+	ARC_INS_LDB_X_AW,
+	ARC_INS_LDB_X_DI_AB,
+	ARC_INS_LDB_X_DI_AW,
+	ARC_INS_LDB_X_DI,
+	ARC_INS_LDB_X,
+	ARC_INS_LDB,
+	ARC_INS_LDH_AB,
+	ARC_INS_LDH_AW,
+	ARC_INS_LDH_DI_AB,
+	ARC_INS_LDH_DI_AW,
+	ARC_INS_LDH_DI,
+	ARC_INS_LDH_S_X,
+	ARC_INS_LDH_X_AB,
+	ARC_INS_LDH_X_AW,
+	ARC_INS_LDH_X_DI_AB,
+	ARC_INS_LDH_X_DI_AW,
+	ARC_INS_LDH_X_DI,
+	ARC_INS_LDH_X,
+	ARC_INS_LDH,
+	ARC_INS_LDI_S,
+	ARC_INS_LD_AB,
+	ARC_INS_LD_AW,
+	ARC_INS_LD_DI_AB,
+	ARC_INS_LD_DI_AW,
+	ARC_INS_LD_DI,
+	ARC_INS_LD_S_AS,
+	ARC_INS_LD,
+	ARC_INS_LEAVE_S,
+	ARC_INS_LR,
+	ARC_INS_LSR,
+	ARC_INS_LSR_F,
+	ARC_INS_MAX,
+	ARC_INS_MAX_F,
+	ARC_INS_MIN,
+	ARC_INS_MIN_F,
+	ARC_INS_MOV_S_NE,
+	ARC_INS_MOV,
+	ARC_INS_MOV_F,
+	ARC_INS_MPYMU,
+	ARC_INS_MPYMU_F,
+	ARC_INS_MPYM,
+	ARC_INS_MPYM_F,
+	ARC_INS_MPY,
+	ARC_INS_MPY_F,
+	ARC_INS_NORMH_F,
+	ARC_INS_NORMH,
+	ARC_INS_NORM_F,
+	ARC_INS_NORM,
+	ARC_INS_OR,
+	ARC_INS_OR_F,
+	ARC_INS_POP_S,
+	ARC_INS_PUSH_S,
+	ARC_INS_ROR,
+	ARC_INS_ROR_F,
+	ARC_INS_RSUB,
+	ARC_INS_RSUB_F,
+	ARC_INS_SBC,
+	ARC_INS_SBC_F,
+	ARC_INS_SETEQ,
+	ARC_INS_SETEQ_F,
+	ARC_INS_SEXB_F,
+	ARC_INS_SEXB,
+	ARC_INS_SEXH_F,
+	ARC_INS_SEXH,
+	ARC_INS_STB_S,
+	ARC_INS_ST_S,
+	ARC_INS_STB_AB,
+	ARC_INS_STB_AW,
+	ARC_INS_STB_DI_AB,
+	ARC_INS_STB_DI_AW,
+	ARC_INS_STB_DI,
+	ARC_INS_STB,
+	ARC_INS_STH_AB,
+	ARC_INS_STH_AW,
+	ARC_INS_STH_DI_AB,
+	ARC_INS_STH_DI_AW,
+	ARC_INS_STH_DI,
+	ARC_INS_STH_S,
+	ARC_INS_STH,
+	ARC_INS_ST_AB,
+	ARC_INS_ST_AW,
+	ARC_INS_ST_DI_AB,
+	ARC_INS_ST_DI_AW,
+	ARC_INS_ST_DI,
+	ARC_INS_ST,
+	ARC_INS_SUB1,
+	ARC_INS_SUB1_F,
+	ARC_INS_SUB2,
+	ARC_INS_SUB2_F,
+	ARC_INS_SUB3,
+	ARC_INS_SUB3_F,
+	ARC_INS_SUB,
+	ARC_INS_SUB_F,
+	ARC_INS_XOR,
+	ARC_INS_XOR_F,
+
+	// clang-format on
+	// generated content <ARCGenCSInsnEnum.inc> end
+} arc_insn;
+
+//> Group of ARC instructions
+typedef enum arc_insn_group {
+	ARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	/// Generic groups
+	/// all jump instructions (conditional+direct+indirect jumps)
+	ARC_GRP_JUMP, ///< = CS_GRP_JUMP
+	/// all call instructions
+	ARC_GRP_CALL, ///< = CS_GRP_CALL
+	/// all return instructions
+	ARC_GRP_RET, ///< = CS_GRP_RET
+	/// all relative branching instructions
+	ARC_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+	ARC_GRP_ENDING,
+} arc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

external/capstone/include/capstone/arm.h

@@ -303,7 +303,7 @@ typedef enum {
 	ARM_FIELD_CPSR_X = 32,
 	ARM_FIELD_CPSR_S = 64,
 	ARM_FIELD_CPSR_F = 128,
-} arm_spsr_cspr_bits;
+} arm_spsr_cpsr_bits;
 
 // From LLVM docs:
 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM field
@@ -855,7 +855,7 @@ typedef struct arm_op_mem {
 
 typedef struct {
   arm_sysop_reg reg; ///< The system or banked register.
-  arm_spsr_cspr_bits psr_bits; ///< SPSR/CPSR bits.
+  arm_spsr_cpsr_bits psr_bits; ///< SPSR/CPSR bits.
   uint16_t sysm; ///< Raw SYSm field. UINT16_MAX if unset.
   uint8_t msr_mask; ///< Mask of MSR instructions. UINT8_MAX if invalid.
 } arm_sysop;
@@ -889,7 +889,7 @@ typedef struct cs_arm_op {
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// This field is combined of cs_ac_type.
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
-	uint8_t access;
+	cs_ac_type access;
 
 	/// Neon lane index for NEON instructions (or -1 if irrelevant)
 	int8_t neon_lane;

external/capstone/include/capstone/arm64.h

@@ -25,6 +25,11 @@ typedef enum {
   ARM64_SFT_LSR = AARCH64_SFT_LSR,
   ARM64_SFT_ASR = AARCH64_SFT_ASR,
   ARM64_SFT_ROR = AARCH64_SFT_ROR,
+  ARM64_SFT_LSL_REG = AARCH64_SFT_LSL_REG,
+  ARM64_SFT_MSL_REG = AARCH64_SFT_MSL_REG,
+  ARM64_SFT_LSR_REG = AARCH64_SFT_LSR_REG,
+  ARM64_SFT_ASR_REG = AARCH64_SFT_ASR_REG,
+  ARM64_SFT_ROR_REG = AARCH64_SFT_ROR_REG,
 } arm64_shifter;
 
 typedef enum {
@@ -1926,7 +1931,10 @@ typedef enum {
 	ARM64_REG_WSP = AARCH64_REG_WSP,
 	ARM64_REG_WZR = AARCH64_REG_WZR,
 	ARM64_REG_XZR = AARCH64_REG_XZR,
+	ARM64_REG_X_LANE = AARCH64_REG_X_LANE,
+	ARM64_REG_Y_LANE = AARCH64_REG_Y_LANE,
 	ARM64_REG_ZA = AARCH64_REG_ZA,
+	ARM64_REG_Z_MATRIX = AARCH64_REG_Z_MATRIX,
 	ARM64_REG_B0 = AARCH64_REG_B0,
 	ARM64_REG_B1 = AARCH64_REG_B1,
 	ARM64_REG_B2 = AARCH64_REG_B2,
@@ -2687,6 +2695,7 @@ typedef enum {
 	ARM64_INS_ASRD = AARCH64_INS_ASRD,
 	ARM64_INS_ASRR = AARCH64_INS_ASRR,
 	ARM64_INS_ASR = AARCH64_INS_ASR,
+	ARM64_INS_AT_AS1ELX = AARCH64_INS_AT_AS1ELX,
 	ARM64_INS_AUTDA = AARCH64_INS_AUTDA,
 	ARM64_INS_AUTDB = AARCH64_INS_AUTDB,
 	ARM64_INS_AUTDZA = AARCH64_INS_AUTDZA,
@@ -2798,6 +2807,7 @@ typedef enum {
 	ARM64_INS_CFINV = AARCH64_INS_CFINV,
 	ARM64_INS_CLASTA = AARCH64_INS_CLASTA,
 	ARM64_INS_CLASTB = AARCH64_INS_CLASTB,
+	ARM64_INS_CLR = AARCH64_INS_CLR,
 	ARM64_INS_CLREX = AARCH64_INS_CLREX,
 	ARM64_INS_CLS = AARCH64_INS_CLS,
 	ARM64_INS_CLZ = AARCH64_INS_CLZ,
@@ -2969,6 +2979,8 @@ typedef enum {
 	ARM64_INS_EXTQ = AARCH64_INS_EXTQ,
 	ARM64_INS_MOVA = AARCH64_INS_MOVA,
 	ARM64_INS_EXTR = AARCH64_INS_EXTR,
+	ARM64_INS_EXTRX = AARCH64_INS_EXTRX,
+	ARM64_INS_EXTRY = AARCH64_INS_EXTRY,
 	ARM64_INS_EXT = AARCH64_INS_EXT,
 	ARM64_INS_F1CVTL2 = AARCH64_INS_F1CVTL2,
 	ARM64_INS_F1CVTLT = AARCH64_INS_F1CVTLT,
@@ -3034,6 +3046,9 @@ typedef enum {
 	ARM64_INS_FEXPA = AARCH64_INS_FEXPA,
 	ARM64_INS_FJCVTZS = AARCH64_INS_FJCVTZS,
 	ARM64_INS_FLOGB = AARCH64_INS_FLOGB,
+	ARM64_INS_FMA16 = AARCH64_INS_FMA16,
+	ARM64_INS_FMA32 = AARCH64_INS_FMA32,
+	ARM64_INS_FMA64 = AARCH64_INS_FMA64,
 	ARM64_INS_FMADD = AARCH64_INS_FMADD,
 	ARM64_INS_FMAD = AARCH64_INS_FMAD,
 	ARM64_INS_FMAX = AARCH64_INS_FMAX,
@@ -3071,6 +3086,9 @@ typedef enum {
 	ARM64_INS_FMOPA = AARCH64_INS_FMOPA,
 	ARM64_INS_FMOPS = AARCH64_INS_FMOPS,
 	ARM64_INS_FMOV = AARCH64_INS_FMOV,
+	ARM64_INS_FMS16 = AARCH64_INS_FMS16,
+	ARM64_INS_FMS32 = AARCH64_INS_FMS32,
+	ARM64_INS_FMS64 = AARCH64_INS_FMS64,
 	ARM64_INS_FMSB = AARCH64_INS_FMSB,
 	ARM64_INS_FMSUB = AARCH64_INS_FMSUB,
 	ARM64_INS_FMUL = AARCH64_INS_FMUL,
@@ -3118,6 +3136,9 @@ typedef enum {
 	ARM64_INS_GCSSS2 = AARCH64_INS_GCSSS2,
 	ARM64_INS_GCSSTR = AARCH64_INS_GCSSTR,
 	ARM64_INS_GCSSTTR = AARCH64_INS_GCSSTTR,
+	ARM64_INS_GENLUT = AARCH64_INS_GENLUT,
+	ARM64_INS_GENTER = AARCH64_INS_GENTER,
+	ARM64_INS_GEXIT = AARCH64_INS_GEXIT,
 	ARM64_INS_LD1B = AARCH64_INS_LD1B,
 	ARM64_INS_LD1D = AARCH64_INS_LD1D,
 	ARM64_INS_LD1H = AARCH64_INS_LD1H,
@@ -3353,21 +3374,28 @@ typedef enum {
 	ARM64_INS_LDURSB = AARCH64_INS_LDURSB,
 	ARM64_INS_LDURSH = AARCH64_INS_LDURSH,
 	ARM64_INS_LDURSW = AARCH64_INS_LDURSW,
+	ARM64_INS_LDX = AARCH64_INS_LDX,
 	ARM64_INS_LDXP = AARCH64_INS_LDXP,
 	ARM64_INS_LDXRB = AARCH64_INS_LDXRB,
 	ARM64_INS_LDXRH = AARCH64_INS_LDXRH,
 	ARM64_INS_LDXR = AARCH64_INS_LDXR,
+	ARM64_INS_LDY = AARCH64_INS_LDY,
+	ARM64_INS_LDZ = AARCH64_INS_LDZ,
+	ARM64_INS_LDZI = AARCH64_INS_LDZI,
 	ARM64_INS_LSLR = AARCH64_INS_LSLR,
 	ARM64_INS_LSL = AARCH64_INS_LSL,
 	ARM64_INS_LSRR = AARCH64_INS_LSRR,
 	ARM64_INS_LSR = AARCH64_INS_LSR,
 	ARM64_INS_LUTI2 = AARCH64_INS_LUTI2,
 	ARM64_INS_LUTI4 = AARCH64_INS_LUTI4,
+	ARM64_INS_MAC16 = AARCH64_INS_MAC16,
 	ARM64_INS_MADDPT = AARCH64_INS_MADDPT,
 	ARM64_INS_MADD = AARCH64_INS_MADD,
 	ARM64_INS_MADPT = AARCH64_INS_MADPT,
 	ARM64_INS_MAD = AARCH64_INS_MAD,
 	ARM64_INS_MATCH = AARCH64_INS_MATCH,
+	ARM64_INS_MATFP = AARCH64_INS_MATFP,
+	ARM64_INS_MATINT = AARCH64_INS_MATINT,
 	ARM64_INS_MLAPT = AARCH64_INS_MLAPT,
 	ARM64_INS_MLA = AARCH64_INS_MLA,
 	ARM64_INS_MLS = AARCH64_INS_MLS,
@@ -3389,6 +3417,8 @@ typedef enum {
 	ARM64_INS_MSRR = AARCH64_INS_MSRR,
 	ARM64_INS_MSUBPT = AARCH64_INS_MSUBPT,
 	ARM64_INS_MSUB = AARCH64_INS_MSUB,
+	ARM64_INS_MUL53HI = AARCH64_INS_MUL53HI,
+	ARM64_INS_MUL53LO = AARCH64_INS_MUL53LO,
 	ARM64_INS_MUL = AARCH64_INS_MUL,
 	ARM64_INS_MVNI = AARCH64_INS_MVNI,
 	ARM64_INS_NANDS = AARCH64_INS_NANDS,
@@ -3574,7 +3604,9 @@ typedef enum {
 	ARM64_INS_SDIVR = AARCH64_INS_SDIVR,
 	ARM64_INS_SDIV = AARCH64_INS_SDIV,
 	ARM64_INS_SDOT = AARCH64_INS_SDOT,
+	ARM64_INS_SDSB = AARCH64_INS_SDSB,
 	ARM64_INS_SEL = AARCH64_INS_SEL,
+	ARM64_INS_SET = AARCH64_INS_SET,
 	ARM64_INS_SETE = AARCH64_INS_SETE,
 	ARM64_INS_SETEN = AARCH64_INS_SETEN,
 	ARM64_INS_SETET = AARCH64_INS_SETET,
@@ -3817,13 +3849,17 @@ typedef enum {
 	ARM64_INS_STURB = AARCH64_INS_STURB,
 	ARM64_INS_STUR = AARCH64_INS_STUR,
 	ARM64_INS_STURH = AARCH64_INS_STURH,
+	ARM64_INS_STX = AARCH64_INS_STX,
 	ARM64_INS_STXP = AARCH64_INS_STXP,
 	ARM64_INS_STXRB = AARCH64_INS_STXRB,
 	ARM64_INS_STXRH = AARCH64_INS_STXRH,
 	ARM64_INS_STXR = AARCH64_INS_STXR,
+	ARM64_INS_STY = AARCH64_INS_STY,
+	ARM64_INS_STZ = AARCH64_INS_STZ,
 	ARM64_INS_STZ2G = AARCH64_INS_STZ2G,
 	ARM64_INS_STZGM = AARCH64_INS_STZGM,
 	ARM64_INS_STZG = AARCH64_INS_STZG,
+	ARM64_INS_STZI = AARCH64_INS_STZI,
 	ARM64_INS_SUBG = AARCH64_INS_SUBG,
 	ARM64_INS_SUBHNB = AARCH64_INS_SUBHNB,
 	ARM64_INS_SUBHNT = AARCH64_INS_SUBHNT,
@@ -4016,6 +4052,8 @@ typedef enum {
 	ARM64_INS_UZPQ1 = AARCH64_INS_UZPQ1,
 	ARM64_INS_UZPQ2 = AARCH64_INS_UZPQ2,
 	ARM64_INS_UZP = AARCH64_INS_UZP,
+	ARM64_INS_VECFP = AARCH64_INS_VECFP,
+	ARM64_INS_VECINT = AARCH64_INS_VECINT,
 	ARM64_INS_WFET = AARCH64_INS_WFET,
 	ARM64_INS_WFIT = AARCH64_INS_WFIT,
 	ARM64_INS_WHILEGE = AARCH64_INS_WHILEGE,
@@ -4028,6 +4066,8 @@ typedef enum {
 	ARM64_INS_WHILELT = AARCH64_INS_WHILELT,
 	ARM64_INS_WHILERW = AARCH64_INS_WHILERW,
 	ARM64_INS_WHILEWR = AARCH64_INS_WHILEWR,
+	ARM64_INS_WKDMC = AARCH64_INS_WKDMC,
+	ARM64_INS_WKDMD = AARCH64_INS_WKDMD,
 	ARM64_INS_WRFFR = AARCH64_INS_WRFFR,
 	ARM64_INS_XAFLAG = AARCH64_INS_XAFLAG,
 	ARM64_INS_XAR = AARCH64_INS_XAR,
@@ -4561,6 +4601,9 @@ typedef enum {
 	ARM64_FEATURE_HASGCS = AARCH64_FEATURE_HASGCS,
 	ARM64_FEATURE_HASCPA = AARCH64_FEATURE_HASCPA,
 	ARM64_FEATURE_USENEGATIVEIMMEDIATES = AARCH64_FEATURE_USENEGATIVEIMMEDIATES,
+	ARM64_FEATURE_HASAMX = AARCH64_FEATURE_HASAMX,
+	ARM64_FEATURE_HASMUL53 = AARCH64_FEATURE_HASMUL53,
+	ARM64_FEATURE_HASAPPLESYS = AARCH64_FEATURE_HASAPPLESYS,
 	ARM64_FEATURE_HASCCPP = AARCH64_FEATURE_HASCCPP,
 	ARM64_FEATURE_HASPAN = AARCH64_FEATURE_HASPAN,
 	ARM64_FEATURE_HASPSUAO = AARCH64_FEATURE_HASPSUAO,

external/capstone/include/capstone/bpf.h

@@ -11,6 +11,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable : 4201)
@@ -19,15 +20,14 @@ extern "C" {
 #define NUM_BPF_OPS 3
 /// Operand type for instruction's operands
 typedef enum bpf_op_type {
-	BPF_OP_INVALID = 0,
-
-	BPF_OP_REG,
-	BPF_OP_IMM,
-	BPF_OP_OFF,
-	BPF_OP_MEM,
-	BPF_OP_MMEM, ///< M[k] in cBPF
-	BPF_OP_MSH,  ///< corresponds to cBPF's BPF_MSH mode
-	BPF_OP_EXT,  ///< cBPF's extension (not eBPF)
+	BPF_OP_INVALID = CS_OP_INVALID,
+	BPF_OP_REG = CS_OP_REG,
+	BPF_OP_IMM = CS_OP_IMM,
+	BPF_OP_OFF = CS_OP_SPECIAL + 0,
+	BPF_OP_MSH = CS_OP_SPECIAL + 1,  ///< corresponds to cBPF's BPF_MSH mode
+	BPF_OP_EXT = CS_OP_SPECIAL + 2,  ///< cBPF's extension (not eBPF)
+	BPF_OP_MMEM = CS_OP_MEM | (CS_OP_SPECIAL + 3), ///< M[k] in cBPF
+	BPF_OP_MEM = CS_OP_MEM,
 } bpf_op_type;
 
 /// BPF registers
@@ -86,7 +86,7 @@ typedef struct cs_bpf_op {
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// This field is combined of cs_ac_type.
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
-	uint8_t access;
+	cs_ac_type access;
 } cs_bpf_op;
 
 /// Instruction structure

external/capstone/include/capstone/capstone.h

@@ -103,6 +103,7 @@ typedef enum cs_arch {
 	CS_ARCH_HPPA, 		///< HPPA architecture
 	CS_ARCH_LOONGARCH, 	///< LoongArch architecture
 	CS_ARCH_XTENSA, 	///< Xtensa architecture
+	CS_ARCH_ARC, 	    ///< ARC architecture
 	CS_ARCH_MAX,
 	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
 } cs_arch;
@@ -117,6 +118,10 @@ typedef enum cs_arch {
 // in X86 reduce mode.
 #define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
 
+/// The mode bits of the AArch64 ISA (not vendor specific).
+#define CS_MODE_AARCH64_ISA_BITS 0x00fffff8
+#define CS_MODE_VENDOR_AARCH64_BIT0 30
+
 /// Mode type
 typedef enum cs_mode {
 	CS_MODE_LITTLE_ENDIAN = 0,	///< little-endian mode (default mode)
@@ -124,10 +129,15 @@ typedef enum cs_mode {
 	CS_MODE_16 = 1 << 1,	///< 16-bit mode (X86)
 	CS_MODE_32 = 1 << 2,	///< 32-bit mode (X86)
 	CS_MODE_64 = 1 << 3,	///< 64-bit mode (X86, PPC)
+	// ARM
 	CS_MODE_THUMB = 1 << 4,	///< ARM's Thumb mode, including Thumb-2
 	CS_MODE_MCLASS = 1 << 5,	///< ARM's Cortex-M series
 	CS_MODE_V8 = 1 << 6,	///< ARMv8 A32 encodings for ARM
+	// AArch64
+	CS_MODE_APPLE_PROPRIETARY = 1 << CS_MODE_VENDOR_AARCH64_BIT0, ///< Enable Apple proprietary AArch64 instructions like AMX, MUL53, and others.
+	// SPARC
 	CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
+	// PPC
 	CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
 	CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
 	CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
@@ -210,6 +220,7 @@ typedef enum cs_mode {
 	CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
 	CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
 	CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
+	CS_MODE_TRICORE_180 = 1 << 8, ///< Tricore 1.8.0
 	CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1
 	CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0
 	CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide
@@ -358,6 +369,7 @@ typedef struct cs_opt_skipdata {
 	/// BPF:       8 bytes.
 	/// TriCore:   2 bytes.
 	/// LoongArch: 4 bytes.
+	/// ARC: 	   2 bytes.
 	cs_skipdata_cb_t callback; 	// default value is NULL
 
 	/// User-defined data to be passed to @callback function pointer.
@@ -391,6 +403,7 @@ typedef struct cs_opt_skipdata {
 #include "hppa.h"
 #include "loongarch.h"
 #include "xtensa.h"
+#include "arc.h"
 
 #define MAX_IMPL_W_REGS 47
 #define MAX_IMPL_R_REGS 20
@@ -448,6 +461,7 @@ typedef struct cs_detail {
 		cs_hppa hppa; ///< HPPA architecture
 		cs_loongarch loongarch; ///< LoongArch architecture
 		cs_xtensa xtensa; ///< Xtensa architecture
+		cs_arc arc; ///< ARC architecture
 	};
 } cs_detail;
 
@@ -496,6 +510,13 @@ typedef struct cs_insn {
 	/// False: The detail operands are from the real instruction.
 	bool usesAliasDetails;
 
+	/// True: The bytes disassemble to a valid instruction, but it is illegal by ISA definitions.
+	/// For example the instruction uses a register which is not allowed or it appears in
+	/// an invalid context.
+	///
+	/// False: The instruction decoded correctly and is valid.
+	bool illegal;
+
 	/// Pointer to cs_detail.
 	/// NOTE: detail pointer is only valid when both requirements below are met:
 	/// (1) CS_OP_DETAIL = CS_OPT_ON
@@ -599,6 +620,8 @@ CAPSTONE_EXPORT
 void CAPSTONE_API cs_arch_register_alpha(void);
 CAPSTONE_EXPORT
 void CAPSTONE_API cs_arch_register_loongarch(void);
+CAPSTONE_EXPORT
+void CAPSTONE_API cs_arch_register_arc(void);
 
 /**
  This API can be used to either ask for archs supported by this library,

external/capstone/include/capstone/evm.h

@@ -3,6 +3,7 @@
 
 /* Capstone Disassembly Engine */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */
+/* By Andelf <andelf@gmail.com>, 2025 */
 
 #ifdef __cplusplus
 extern "C" {
@@ -46,6 +47,9 @@ typedef enum evm_insn {
 	EVM_INS_XOR = 24,
 	EVM_INS_NOT = 25,
 	EVM_INS_BYTE = 26,
+	EVM_INS_SHL = 27,
+	EVM_INS_SHR = 28,
+	EVM_INS_SAR = 29,
 	EVM_INS_SHA3 = 32,
 	EVM_INS_ADDRESS = 48,
 	EVM_INS_BALANCE = 49,
@@ -68,6 +72,11 @@ typedef enum evm_insn {
 	EVM_INS_NUMBER = 67,
 	EVM_INS_DIFFICULTY = 68,
 	EVM_INS_GASLIMIT = 69,
+	EVM_INS_CHAINID = 70,
+	EVM_INS_SELFBALANCE = 71,
+	EVM_INS_BASEFEE = 72,
+	EVM_INS_BLOBHASH = 73,
+	EVM_INS_BLOBBASEFEE = 74,
 	EVM_INS_POP = 80,
 	EVM_INS_MLOAD = 81,
 	EVM_INS_MSTORE = 82,
@@ -80,6 +89,10 @@ typedef enum evm_insn {
 	EVM_INS_MSIZE = 89,
 	EVM_INS_GAS = 90,
 	EVM_INS_JUMPDEST = 91,
+	EVM_INS_TLOAD = 92,
+	EVM_INS_TSTORE = 93,
+	EVM_INS_MCOPY = 94,
+	EVM_INS_PUSH0 = 95,
 	EVM_INS_PUSH1 = 96,
 	EVM_INS_PUSH2 = 97,
 	EVM_INS_PUSH3 = 98,
@@ -154,12 +167,12 @@ typedef enum evm_insn {
 	EVM_INS_CALLCODE = 242,
 	EVM_INS_RETURN = 243,
 	EVM_INS_DELEGATECALL = 244,
-	EVM_INS_CALLBLACKBOX = 245,
+	EVM_INS_CREATE2 = 245,
 	EVM_INS_STATICCALL = 250,
 	EVM_INS_REVERT = 253,
-	EVM_INS_SUICIDE = 255,
+	EVM_INS_INVALID = 254,
+	EVM_INS_SELFDESTRUCT = 255, // originally called SUICIDE
 
-	EVM_INS_INVALID = 512,
 	EVM_INS_ENDING,   // <-- mark the end of the list of instructions
 } evm_insn;
 

external/capstone/include/capstone/hppa.h

@@ -14,15 +14,13 @@ extern "C" {
 
 /// Operand type for instruction's operands
 typedef enum hppa_op_type {
-	HPPA_OP_INVALID = 0,
-
-	HPPA_OP_REG,
-	HPPA_OP_IMM,
-	HPPA_OP_IDX_REG,
-	HPPA_OP_DISP,
-	HPPA_OP_MEM,
-	HPPA_OP_TARGET,
-
+	HPPA_OP_INVALID = CS_OP_INVALID,
+	HPPA_OP_REG = CS_OP_REG,
+	HPPA_OP_IMM = CS_OP_IMM,
+	HPPA_OP_IDX_REG = CS_OP_SPECIAL + 0,
+	HPPA_OP_DISP = CS_OP_SPECIAL + 1,
+	HPPA_OP_TARGET = CS_OP_SPECIAL + 2,
+	HPPA_OP_MEM = CS_OP_MEM,
 } hppa_op_type;
 
 //> HPPA registers

external/capstone/include/capstone/loongarch.h

@@ -43,7 +43,7 @@ typedef struct cs_loongarch_op {
 
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
-	uint8_t access;
+	cs_ac_type access;
 } cs_loongarch_op;
 
 /// LoongArch instruction formats. To get details about them please

external/capstone/include/capstone/m680x.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -53,14 +54,14 @@ typedef enum m680x_reg {
 
 /// Operand type for instruction's operands
 typedef enum m680x_op_type {
-	M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	M680X_OP_REGISTER,    ///< = Register operand.
-	M680X_OP_IMMEDIATE,   ///< = Immediate operand.
-	M680X_OP_INDEXED,     ///< = Indexed addressing operand.
-	M680X_OP_EXTENDED,    ///< = Extended addressing operand.
-	M680X_OP_DIRECT,      ///< = Direct addressing operand.
-	M680X_OP_RELATIVE,    ///< = Relative addressing operand.
-	M680X_OP_CONSTANT,    ///< = constant operand (Displayed as number only).
+	M680X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	M680X_OP_REGISTER = CS_OP_REG,    ///< = Register operand.
+	M680X_OP_IMMEDIATE = CS_OP_IMM,   ///< = Immediate operand.
+	M680X_OP_INDEXED = CS_OP_SPECIAL + 0,     ///< = Indexed addressing operand.
+	M680X_OP_EXTENDED = CS_OP_SPECIAL + 1,    ///< = Extended addressing operand.
+	M680X_OP_DIRECT = CS_OP_SPECIAL + 2,      ///< = Direct addressing operand.
+	M680X_OP_RELATIVE = CS_OP_SPECIAL + 3,    ///< = Relative addressing operand.
+	M680X_OP_CONSTANT = CS_OP_SPECIAL + 4,    ///< = constant operand (Displayed as number only).
 				///< Used e.g. for a bit index or page number.
 } m680x_op_type;
 
@@ -126,7 +127,7 @@ typedef struct cs_m680x_op {
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// This field is combined of cs_ac_type.
 	/// NOTE: this field is irrelevant if engine is compiled in DIET 
-	uint8_t access;
+	cs_ac_type access;
 } cs_m680x_op;
 
 /// Group of M680X instructions

external/capstone/include/capstone/m68k.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -110,15 +111,15 @@ typedef enum m68k_address_mode {
 
 /// Operand type for instruction's operands
 typedef enum m68k_op_type {
-	M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	M68K_OP_REG,         ///< = CS_OP_REG (Register operand).
-	M68K_OP_IMM,         ///< = CS_OP_IMM (Immediate operand).
-	M68K_OP_MEM,         ///< = CS_OP_MEM (Memory operand).
-	M68K_OP_FP_SINGLE,   ///< single precision Floating-Point operand
-	M68K_OP_FP_DOUBLE,   ///< double precision Floating-Point operand
-	M68K_OP_REG_BITS,    ///< Register bits move
-	M68K_OP_REG_PAIR,    ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
-	M68K_OP_BR_DISP,     ///< Branch displacement
+	M68K_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	M68K_OP_REG = CS_OP_REG,         ///< = CS_OP_REG (Register operand).
+	M68K_OP_IMM = CS_OP_IMM,         ///< = CS_OP_IMM (Immediate operand).
+	M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0,   ///< single precision Floating-Point operand
+	M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1,   ///< double precision Floating-Point operand
+	M68K_OP_REG_BITS = CS_OP_SPECIAL + 2,    ///< Register bits move
+	M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3,    ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
+	M68K_OP_BR_DISP = CS_OP_SPECIAL + 4,     ///< Branch displacement
+	M68K_OP_MEM = CS_OP_MEM,         ///< = CS_OP_MEM (Memory operand).
 } m68k_op_type;
 
 /// Instruction's operand referring to memory

external/capstone/include/capstone/mips.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 // GCC MIPS toolchain has a default macro called "mips" which breaks
 // compilation
@@ -20,10 +21,10 @@ extern "C" {
 
 /// Operand type for instruction's operands
 typedef enum mips_op_type {
-	MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	MIPS_OP_REG, ///< = CS_OP_REG (Register operand).
-	MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	MIPS_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	MIPS_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	MIPS_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	MIPS_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } mips_op_type;
 
 /// MIPS registers
@@ -693,7 +694,7 @@ typedef struct cs_mips_op {
 
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
-	uint8_t access;
+	cs_ac_type access;
 } cs_mips_op;
 
 #define NUM_MIPS_OPS 10
@@ -2189,6 +2190,12 @@ typedef enum mips_insn {
 
 	// clang-format on
 	// generated content <MipsGenCSAliasEnum.inc> end
+
+	// The followings aliases are not generated by LLVM table gen.
+	MIPS_INS_ALIAS_B,    // beq $zero, $zero, $L2 => b $L2
+	MIPS_INS_ALIAS_BEQZ, // beq $r0, $zero, $L2 => beqz $r0, $L2
+	MIPS_INS_ALIAS_BNEZ, // bne $r0, $zero, $L2 => bnez $r0, $L2
+	MIPS_INS_ALIAS_LI,   // addiu $rX, $r0, imm => li $r0, imm
 	MIPS_INS_ALIAS_END,
 } mips_insn;
 

external/capstone/include/capstone/mos65xx.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 /// MOS65XX registers and special registers
 typedef enum mos65xx_reg {
@@ -170,10 +171,10 @@ typedef enum mos65xx_group_type {
 
 /// Operand type for instruction's operands
 typedef enum mos65xx_op_type {
-	MOS65XX_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	MOS65XX_OP_REG, ///< = CS_OP_REG (Register operand).
-	MOS65XX_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	MOS65XX_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	MOS65XX_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	MOS65XX_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	MOS65XX_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	MOS65XX_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } mos65xx_op_type;
 
 /// Instruction operand

external/capstone/include/capstone/ppc.h

@@ -884,7 +884,10 @@ typedef struct {
 	uint8_t bi; ///< BI field of branch condition. UINT8_MAX if invalid.
 	ppc_cr_bit crX_bit; ///< CR field bit to test.
 	ppc_reg crX;	    ///< The CR field accessed.
-	ppc_br_hint hint;   ///< The encoded hint.
+	ppc_br_hint hint;   /** This is the hint encoded into the 'at' bits
+                           of the BO field. Not to be confused with
+                           the BH field.
+                      */
 	ppc_pred pred_cr;   ///< CR-bit branch predicate
 	ppc_pred pred_ctr;  ///< CTR branch predicate
 	ppc_bh bh;	    ///< The BH field hint if any is present.

external/capstone/include/capstone/riscv.h

@@ -2,7 +2,7 @@
 #define CAPSTONE_RISCV_H
 
 /* Capstone Disassembly Engine */
-/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> & 
+/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
    Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
 
 #ifdef __cplusplus
@@ -14,6 +14,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 // GCC MIPS toolchain has a default macro called "mips" which breaks
 // compilation
@@ -25,10 +26,10 @@ extern "C" {
 
 //> Operand type for instruction's operands
 typedef enum riscv_op_type {
-	RISCV_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
-	RISCV_OP_REG, // = CS_OP_REG (Register operand).
-	RISCV_OP_IMM, // = CS_OP_IMM (Immediate operand).
-	RISCV_OP_MEM, // = CS_OP_MEM (Memory operand).
+	RISCV_OP_INVALID = CS_OP_INVALID, // = CS_OP_INVALID (Uninitialized).
+	RISCV_OP_REG = CS_OP_REG, // = CS_OP_REG (Register operand).
+	RISCV_OP_IMM = CS_OP_IMM, // = CS_OP_IMM (Immediate operand).
+	RISCV_OP_MEM = CS_OP_MEM, // = CS_OP_MEM (Memory operand).
 } riscv_op_type;
 
 // Instruction's operand referring to memory
@@ -46,7 +47,7 @@ typedef struct cs_riscv_op {
 		int64_t imm;		// immediate value for IMM operand
 		riscv_op_mem mem;	// base/disp value for MEM operand
 	};
-	uint8_t access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
+	cs_ac_type access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
 } cs_riscv_op;
 
 #define NUM_RISCV_OPS 8
@@ -55,7 +56,7 @@ typedef struct cs_riscv_op {
 typedef struct cs_riscv {
 	// Does this instruction need effective address or not.
 	bool need_effective_addr;
-	// Number of operands of this instruction, 
+	// Number of operands of this instruction,
 	// or 0 when instruction has no operand.
 	uint8_t op_count;
 	cs_riscv_op operands[NUM_RISCV_OPS]; // operands for this instruction.
@@ -65,8 +66,8 @@ typedef struct cs_riscv {
 typedef enum riscv_reg {
 	RISCV_REG_INVALID = 0,
 	//> General purpose registers
-	RISCV_REG_X0,			// "zero" 
-	RISCV_REG_ZERO = RISCV_REG_X0, 	// "zero" 
+	RISCV_REG_X0,			// "zero"
+	RISCV_REG_ZERO = RISCV_REG_X0, 	// "zero"
 	RISCV_REG_X1, 			// "ra"
 	RISCV_REG_RA   = RISCV_REG_X1, 	// "ra"
 	RISCV_REG_X2, 			// "sp"
@@ -130,7 +131,7 @@ typedef enum riscv_reg {
 	RISCV_REG_T5   = RISCV_REG_X30,	// "t5"
 	RISCV_REG_X31,			// "t6"
 	RISCV_REG_T6   = RISCV_REG_X31,	// "t6"
-	
+
 	//> Floating-point registers
 	RISCV_REG_F0_32,		// "ft0"
 	RISCV_REG_F0_64,		// "ft0"
@@ -196,7 +197,7 @@ typedef enum riscv_reg {
 	RISCV_REG_F30_64,		// "ft10"
 	RISCV_REG_F31_32,		// "ft11"
 	RISCV_REG_F31_64,		// "ft11"
-	
+
 	RISCV_REG_ENDING,		// <-- mark the end of the list or registers
 } riscv_reg;
 
@@ -475,8 +476,8 @@ typedef enum riscv_insn {
   	RISCV_INS_URET,
   	RISCV_INS_WFI,
   	RISCV_INS_XOR,
-  	RISCV_INS_XORI,	
-	
+  	RISCV_INS_XORI,
+
   	RISCV_INS_ENDING,
 } riscv_insn;
 
@@ -499,7 +500,7 @@ typedef enum riscv_insn_group {
   	RISCV_GRP_PRIVILEGE,	///< = CS_GRP_PRIVILEGE
   	// all relative branching instructions
   	RISCV_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
-  
+
   	// Architecture-specific groups
   	RISCV_GRP_ISRV32 = 128,
   	RISCV_GRP_ISRV64,
@@ -508,21 +509,6 @@ typedef enum riscv_insn_group {
   	RISCV_GRP_HASSTDEXTD,
   	RISCV_GRP_HASSTDEXTF,
   	RISCV_GRP_HASSTDEXTM,
-  	/*
-  	RISCV_GRP_ISRVA,
-  	RISCV_GRP_ISRVC,
-  	RISCV_GRP_ISRVD,
-  	RISCV_GRP_ISRVCD,
-  	RISCV_GRP_ISRVF,
-  	RISCV_GRP_ISRV32C,
-  	RISCV_GRP_ISRV32CF,
-  	RISCV_GRP_ISRVM,
-  	RISCV_GRP_ISRV64A,
-  	RISCV_GRP_ISRV64C,
-  	RISCV_GRP_ISRV64D,
-  	RISCV_GRP_ISRV64F,
-  	RISCV_GRP_ISRV64M,
-  	*/
   	RISCV_GRP_ENDING,
 } riscv_insn_group;
 

external/capstone/include/capstone/sh.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -157,10 +158,10 @@ typedef enum {
 } sh_reg;
 
 typedef enum {
-	SH_OP_INVALID = 0,  ///< = CS_OP_INVALID (Uninitialized).
-	SH_OP_REG, ///< = CS_OP_REG (Register operand).
-	SH_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	SH_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	SH_OP_INVALID = CS_OP_INVALID,  ///< = CS_OP_INVALID (Uninitialized).
+	SH_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	SH_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	SH_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } sh_op_type;	
 
 typedef enum {

external/capstone/include/capstone/tms320c64x.h

@@ -10,17 +10,18 @@ extern "C" {
 
 #include <stdint.h>
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
 #endif
 
 typedef enum tms320c64x_op_type {
-	TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
-	TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
-	TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
+	TMS320C64X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	TMS320C64X_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	TMS320C64X_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL + 0, ///< Register pair for double word ops
+	TMS320C64X_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } tms320c64x_op_type;
 
 typedef enum tms320c64x_mem_disp {

external/capstone/include/capstone/tricore.h

@@ -44,7 +44,7 @@ typedef struct cs_tricore_op {
 	};
 	/// This field is combined of cs_ac_type.
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
-	uint8_t access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
+	cs_ac_type access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
 } cs_tricore_op;
 
 #define NUM_TRICORE_OPS 8
@@ -146,6 +146,8 @@ typedef enum tricore_insn {
 	TRICORE_INS_ABSS_H,
 	TRICORE_INS_ABSS,
 	TRICORE_INS_ABS_B,
+	TRICORE_INS_ABS_DF,
+	TRICORE_INS_ABS_F,
 	TRICORE_INS_ABS_H,
 	TRICORE_INS_ABS,
 	TRICORE_INS_ADDC,
@@ -163,6 +165,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_ADDX,
 	TRICORE_INS_ADD_A,
 	TRICORE_INS_ADD_B,
+	TRICORE_INS_ADD_DF,
 	TRICORE_INS_ADD_F,
 	TRICORE_INS_ADD_H,
 	TRICORE_INS_ADD,
@@ -208,6 +211,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_CMOVN,
 	TRICORE_INS_CMOV,
 	TRICORE_INS_CMPSWAP_W,
+	TRICORE_INS_CMP_DF,
 	TRICORE_INS_CMP_F,
 	TRICORE_INS_CRC32B_W,
 	TRICORE_INS_CRC32L_W,
@@ -219,8 +223,21 @@ typedef enum tricore_insn {
 	TRICORE_INS_CSUB,
 	TRICORE_INS_DEBUG,
 	TRICORE_INS_DEXTR,
+	TRICORE_INS_DFTOF,
+	TRICORE_INS_DFTOIN,
+	TRICORE_INS_DFTOIZ,
+	TRICORE_INS_DFTOI,
+	TRICORE_INS_DFTOLZ,
+	TRICORE_INS_DFTOL,
+	TRICORE_INS_DFTOULZ,
+	TRICORE_INS_DFTOUL,
+	TRICORE_INS_DFTOUZ,
+	TRICORE_INS_DFTOU,
 	TRICORE_INS_DIFSC_A,
 	TRICORE_INS_DISABLE,
+	TRICORE_INS_DIV64_U,
+	TRICORE_INS_DIV64,
+	TRICORE_INS_DIV_DF,
 	TRICORE_INS_DIV_F,
 	TRICORE_INS_DIV_U,
 	TRICORE_INS_DIV,
@@ -249,7 +266,9 @@ typedef enum tricore_insn {
 	TRICORE_INS_FCALLI,
 	TRICORE_INS_FCALL,
 	TRICORE_INS_FRET,
+	TRICORE_INS_FTODF,
 	TRICORE_INS_FTOHP,
+	TRICORE_INS_FTOIN,
 	TRICORE_INS_FTOIZ,
 	TRICORE_INS_FTOI,
 	TRICORE_INS_FTOQ31Z,
@@ -265,6 +284,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_INSN_T,
 	TRICORE_INS_INS_T,
 	TRICORE_INS_ISYNC,
+	TRICORE_INS_ITODF,
 	TRICORE_INS_ITOF,
 	TRICORE_INS_IXMAX_U,
 	TRICORE_INS_IXMAX,
@@ -312,6 +332,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_LHA,
 	TRICORE_INS_LOOPU,
 	TRICORE_INS_LOOP,
+	TRICORE_INS_LTODF,
 	TRICORE_INS_LT_A,
 	TRICORE_INS_LT_B,
 	TRICORE_INS_LT_BU,
@@ -342,6 +363,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_MADDS_Q,
 	TRICORE_INS_MADDS_U,
 	TRICORE_INS_MADDS,
+	TRICORE_INS_MADD_DF,
 	TRICORE_INS_MADD_F,
 	TRICORE_INS_MADD_H,
 	TRICORE_INS_MADD_Q,
@@ -349,6 +371,8 @@ typedef enum tricore_insn {
 	TRICORE_INS_MADD,
 	TRICORE_INS_MAX_B,
 	TRICORE_INS_MAX_BU,
+	TRICORE_INS_MAX_DF,
+	TRICORE_INS_MAX_F,
 	TRICORE_INS_MAX_H,
 	TRICORE_INS_MAX_HU,
 	TRICORE_INS_MAX_U,
@@ -356,6 +380,8 @@ typedef enum tricore_insn {
 	TRICORE_INS_MFCR,
 	TRICORE_INS_MIN_B,
 	TRICORE_INS_MIN_BU,
+	TRICORE_INS_MIN_DF,
+	TRICORE_INS_MIN_F,
 	TRICORE_INS_MIN_H,
 	TRICORE_INS_MIN_HU,
 	TRICORE_INS_MIN_U,
@@ -389,6 +415,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_MSUBS_Q,
 	TRICORE_INS_MSUBS_U,
 	TRICORE_INS_MSUBS,
+	TRICORE_INS_MSUB_DF,
 	TRICORE_INS_MSUB_F,
 	TRICORE_INS_MSUB_H,
 	TRICORE_INS_MSUB_Q,
@@ -403,6 +430,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_MULR_Q,
 	TRICORE_INS_MULS_U,
 	TRICORE_INS_MULS,
+	TRICORE_INS_MUL_DF,
 	TRICORE_INS_MUL_F,
 	TRICORE_INS_MUL_H,
 	TRICORE_INS_MUL_Q,
@@ -410,6 +438,8 @@ typedef enum tricore_insn {
 	TRICORE_INS_MUL,
 	TRICORE_INS_NAND_T,
 	TRICORE_INS_NAND,
+	TRICORE_INS_NEG_DF,
+	TRICORE_INS_NEG_F,
 	TRICORE_INS_NEZ_A,
 	TRICORE_INS_NE_A,
 	TRICORE_INS_NE,
@@ -435,7 +465,10 @@ typedef enum tricore_insn {
 	TRICORE_INS_PARITY,
 	TRICORE_INS_POPCNT_W,
 	TRICORE_INS_Q31TOF,
+	TRICORE_INS_QSEED_DF,
 	TRICORE_INS_QSEED_F,
+	TRICORE_INS_REM64_U,
+	TRICORE_INS_REM64,
 	TRICORE_INS_RESTORE,
 	TRICORE_INS_RET,
 	TRICORE_INS_RFE,
@@ -496,6 +529,7 @@ typedef enum tricore_insn {
 	TRICORE_INS_SUBX,
 	TRICORE_INS_SUB_A,
 	TRICORE_INS_SUB_B,
+	TRICORE_INS_SUB_DF,
 	TRICORE_INS_SUB_F,
 	TRICORE_INS_SUB_H,
 	TRICORE_INS_SUB,
@@ -512,8 +546,10 @@ typedef enum tricore_insn {
 	TRICORE_INS_TLBPROBE_I,
 	TRICORE_INS_TRAPSV,
 	TRICORE_INS_TRAPV,
+	TRICORE_INS_ULTODF,
 	TRICORE_INS_UNPACK,
 	TRICORE_INS_UPDFL,
+	TRICORE_INS_UTODF,
 	TRICORE_INS_UTOF,
 	TRICORE_INS_WAIT,
 	TRICORE_INS_XNOR_T,
@@ -553,18 +589,21 @@ typedef enum tricore_feature_t {
 	TRICORE_FEATURE_HASV160,
 	TRICORE_FEATURE_HASV161,
 	TRICORE_FEATURE_HASV162,
+	TRICORE_FEATURE_HASV180,
 	TRICORE_FEATURE_HASV120_UP,
 	TRICORE_FEATURE_HASV130_UP,
 	TRICORE_FEATURE_HASV131_UP,
 	TRICORE_FEATURE_HASV160_UP,
 	TRICORE_FEATURE_HASV161_UP,
 	TRICORE_FEATURE_HASV162_UP,
+	TRICORE_FEATURE_HASV180_UP,
 	TRICORE_FEATURE_HASV120_DN,
 	TRICORE_FEATURE_HASV130_DN,
 	TRICORE_FEATURE_HASV131_DN,
 	TRICORE_FEATURE_HASV160_DN,
 	TRICORE_FEATURE_HASV161_DN,
 	TRICORE_FEATURE_HASV162_DN,
+	TRICORE_FEATURE_HASV180_DN,
 
 	// clang-format on
 	// generated content <TriCoreGenCSFeatureEnum.inc> end

external/capstone/include/capstone/wasm.h

@@ -9,21 +9,22 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
 #endif
 
 typedef enum wasm_op_type {
-	WASM_OP_INVALID = 0,
-	WASM_OP_NONE,
-	WASM_OP_INT7,
-	WASM_OP_VARUINT32,
-	WASM_OP_VARUINT64,
-	WASM_OP_UINT32,
-	WASM_OP_UINT64,
-	WASM_OP_IMM,
-	WASM_OP_BRTABLE,
+	WASM_OP_INVALID = CS_OP_INVALID,
+	WASM_OP_IMM = CS_OP_IMM,
+	WASM_OP_NONE = CS_OP_SPECIAL + 0,
+	WASM_OP_INT7 = CS_OP_SPECIAL + 1,
+	WASM_OP_VARUINT32 = CS_OP_SPECIAL + 2,
+	WASM_OP_VARUINT64 = CS_OP_SPECIAL + 3,
+	WASM_OP_UINT32 = CS_OP_SPECIAL + 4,
+	WASM_OP_UINT64 = CS_OP_SPECIAL + 5,
+	WASM_OP_BRTABLE = CS_OP_SPECIAL + 6,
 } wasm_op_type;
 
 typedef struct cs_wasm_brtable {

external/capstone/include/capstone/x86.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 /// Calculate relative address for X86-64, given cs_insn structure
 #define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \
@@ -157,10 +158,10 @@ typedef enum x86_reg {
 
 /// Operand type for instruction's operands
 typedef enum x86_op_type {
-	X86_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	X86_OP_REG, ///< = CS_OP_REG (Register operand).
-	X86_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	X86_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	X86_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	X86_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	X86_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	X86_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } x86_op_type;
 
 /// XOP Code Condition type
@@ -288,7 +289,7 @@ typedef struct cs_x86_op {
 	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
 	/// This field is combined of cs_ac_type.
 	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
-	uint8_t access;
+	cs_ac_type access;
 
 	/// AVX broadcast type, or 0 if irrelevant
 	x86_avx_bcast avx_bcast;

external/capstone/include/capstone/xcore.h

@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -16,10 +17,10 @@ extern "C" {
 
 /// Operand type for instruction's operands
 typedef enum xcore_op_type {
-	XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	XCORE_OP_REG, ///< = CS_OP_REG (Register operand).
-	XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	XCORE_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	XCORE_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	XCORE_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	XCORE_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } xcore_op_type;
 
 /// XCore registers

external/capstone/include/capstone/xtensa.h

@@ -1691,24 +1691,27 @@ typedef enum cs_xtensa_op_type {
 	XTENSA_OP_REG = CS_OP_REG,	   ///< = (Register operand).
 	XTENSA_OP_IMM = CS_OP_IMM,	   ///< = (Immediate operand).
 	XTENSA_OP_MEM = CS_OP_MEM,	   ///< = (Memory operand).
-	XTENSA_OP_MEM_REG = CS_OP_MEM_REG, ///< = (Memory Register operand).
-	XTENSA_OP_MEM_IMM = CS_OP_MEM_IMM, ///< = (Memory Immediate operand).
-	XTENSA_OP_L32R,			   ///< = (L32R Target)
+	XTENSA_OP_L32R = CS_OP_SPECIAL + 0,			   ///< = (L32R Target)
 } cs_xtensa_op_type;
 
+/// Instruction's operand referring to memory
+/// This is associated with XTENSA_OP_MEM operand type above
 typedef struct cs_xtensa_op_mem {
-	uint8_t base;
-	int32_t disp;
+	uint8_t base;  ///< base register
+	int32_t disp;  ///< displacement/offset value
 } cs_xtensa_op_mem;
 
-typedef struct cs_xtensa_operand {
-	uint8_t type;
-	uint8_t access;
+/// Instruction operand
+typedef struct cs_xtensa_op {
+	cs_xtensa_op_type type;   //< operand type
+	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
+	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+	cs_ac_type access;
 
 	union {
-		uint8_t reg;
-		int32_t imm;
-		cs_xtensa_op_mem mem;
+		uint8_t reg;          /// register value for REG operand
+		int32_t imm;          /// immediate value for IMM operand
+		cs_xtensa_op_mem mem; /// base/disp value for MEM operand
 	};
 } cs_xtensa_op;