Merge commit '16a2cf3873e00fa08e587d1b05c9132d98c24f50' into back-to-imgui

2025-06-26 22:15:44 +02:00
parent 2ec3abbe14 16a2cf3873
commit e13270e41e
876 changed files with 168071 additions and 411897 deletions
--- a/external/capstone/tests/issues/issues.yaml
+++ b/external/capstone/tests/issues/issues.yaml
@@ -3904,7 +3904,7 @@ test_cases:
      name: "issue 426"
      bytes: [ 0xbb,0x70,0x00,0x00 ]
      arch: "CS_ARCH_SPARC"
-      options: [ CS_MODE_BIG_ENDIAN ]
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
      address: 0x0
    expected:
      insns:
@@ -4526,7 +4526,7 @@ test_cases:
      insns:
      -
        asm_text: "vcmpnlesd	xmm3, xmm0, xmm2"
-        id: 797
+        id: X86_INS_VCMP
  -
    input:
      name: "issue 2349"
@@ -5658,3 +5658,588 @@ test_cases:
                imm: 0
                access: CS_AC_READ
          regs_read: [ ra ]
+  - input:
+      name: "RISCV - #2632 - Memory operand type was 3 instead of 0x80"
+      bytes: [ 0x0c, 0xc2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_OPT_DETAIL, CS_MODE_RISCV32, CS_MODE_RISCVC ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "c.sw	a1, 0(a2)"
+        details:
+          riscv:
+            operands:
+              - type: CS_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              - type: CS_OP_MEM
+                mem_base: a2
+                access: CS_AC_WRITE
+  -
+    input:
+      name: "x86 - issue #2632 - Memory operand type was 3 instead of 0x80"
+      bytes: [ 0x4c, 0x89, 0x65, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov	qword ptr [rbp - 0x38], r12"
+        details:
+          x86:
+            operands:
+              -
+                type: CS_OP_MEM
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
+
+  - input:
+      name: "mipsel64r6 lapc as alias of addiupc with details & real"
+      bytes: [ 0x19, 0x00, 0x40, 0xec ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64R6, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "lapc $v0, 0x64"
+        id: MIPS_INS_ADDIUPC
+        is_alias: 1
+        alias_id: MIPS_INS_ALIAS_LAPC
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: v0
+                access: CS_AC_WRITE
+              - type: MIPS_OP_IMM
+                imm: 0x64
+                access: CS_AC_READ
+
+  - input:
+      name: "mips2 negu as alias of subu with details & real"
+      bytes: [ 0x00, 0x07, 0x18, 0x23 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS2, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "negu $v1, $a3"
+        id: MIPS_INS_SUBU
+        is_alias: 1
+        alias_id: MIPS_INS_ALIAS_NEGU
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: v1
+                access: CS_AC_WRITE
+              - type: MIPS_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              - type: MIPS_OP_REG
+                reg: a3
+                access: CS_AC_READ
+
+  - input:
+      name: "mips64r6 lapc as alias of addiupc with details & real"
+      bytes: [ 0x19, 0x00, 0x40, 0xec ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64R6, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "lapc $v0, 0x64"
+        id: MIPS_INS_ADDIUPC
+        is_alias: 1
+        alias_id: MIPS_INS_ALIAS_LAPC
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: v0
+                access: CS_AC_WRITE
+              - type: MIPS_OP_IMM
+                imm: 0x64
+                access: CS_AC_READ
+
+  - input:
+      name: "mips2 b as alias of beq with details & real"
+      bytes: [ 0x10, 0x00, 0x04, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS2, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "b 4664"
+        id: MIPS_INS_BEQ
+        is_alias: 1
+        alias_id: MIPS_INS_ALIAS_B
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              - type: MIPS_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              - type: MIPS_OP_IMM
+                imm: 0x1238
+                access: CS_AC_READ
+
+  - input:
+      name: "mips2 beqz as alias of beq with details & real"
+      bytes: [ 0x11, 0x40, 0x04, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS2, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "beqz $t2, 0x1238"
+        id: MIPS_INS_BEQ
+        is_alias: 1
+        alias_id: MIPS_INS_ALIAS_BEQZ
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: t2
+                access: CS_AC_READ
+              - type: MIPS_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              - type: MIPS_OP_IMM
+                imm: 0x1238
+                access: CS_AC_READ
+
+  - input:
+      name: "nanomips (i7200) li as alias of addiu with details & real"
+      bytes: [ 0x00, 0x01, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_I7200, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "li $a4, 0"
+        id: MIPS_INS_ADDIU
+        is_alias: 1
+        alias_id: MIPS_INS_ALIAS_LI
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              - type: MIPS_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              - type: MIPS_OP_IMM
+                imm: 0
+                access: CS_AC_READ
+
+  -
+    input:
+      name: "issue 2630 - missing call group for svc, hvc, smc."
+      bytes: [ 0xc2, 0x00, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "hvc #0x6"
+        details:
+          groups: [ call ]
+  -
+    input:
+      name: "issue 2630 - missing call group for svc, hvc, smc."
+      bytes: [ 0xe3, 0x00, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "smc #0x7"
+        details:
+          groups: [ call, HasEL3, privilege ]
+  -
+    input:
+      name: "issue 2630 - missing call group for svc, hvc, smc."
+      bytes: [ 0x01, 0x01, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "svc #0x8"
+        details:
+          groups: [ call, int ]
+  -
+    input:
+      name: "jalr on mips32r2"
+      bytes: [ 0x09, 0xf8, 0x20, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS32R2, CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jalr $t9"
+
+  -
+    input:
+      name: "ddiv on mips64r2"
+      bytes: [ 0x01, 0x11, 0x00, 0x1e, 0x01, 0x65, 0x00, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64R2, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NO_DOLLAR, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "ddiv zero, t0, s1"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: zero
+              - type: MIPS_OP_REG
+                reg: t0
+              - type: MIPS_OP_REG
+                reg: s1
+      - asm_text: "div zero, t3, a1"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: zero
+              - type: MIPS_OP_REG
+                reg: t3
+              - type: MIPS_OP_REG
+                reg: a1
+
+  - input:
+      name: "dclo on mips64r6 - Mips32r6_64r632"
+      bytes: [ 0x00, 0xa0, 0x30, 0x53 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64R6, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "dclo $a2, $a1"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: a2
+              - type: MIPS_OP_REG
+                reg: a1
+
+  - input:
+      name: "SIGRIE on mips32r6 - Mips32r6_64r632"
+      bytes: [ 0x04, 0x17, 0x0d, 0x53 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "sigrie 0xd53"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_IMM
+                imm: 0xd53
+
+  - input:
+      name: "mips32r6 - Mips32r6_64r6_Ambiguous32"
+      bytes: [ 0x18, 0x01, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x81, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+      - asm_text: "blezalc $at, 4100"
+      - asm_text: "blez $zero, 4104"
+      - asm_text: "bgeuc $a0, $at, 4108"
+
+  - input:
+      name: "mips64r6 - Mips32r6_64r6_Ambiguous32"
+      bytes: [ 0x18, 0x01, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x81, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64R6, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+      - asm_text: "blezalc $at, 4100"
+      - asm_text: "blez $zero, 4104"
+      - asm_text: "bgeuc $a0, $at, 4108"
+
+  - input:
+      name: "jr/jrc/ ra & div/divu zero on mips16"
+      bytes: [ 0xe8, 0x20,  0xe8, 0xa0,  0xeb, 0x5a,  0xeb, 0x5b,  0x63, 0x1e,  0xf0, 0x64, 0x63, 0x05 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS16, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NO_DOLLAR, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "jr ra"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: ra
+      - asm_text: "jrc ra"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: ra
+      - asm_text: "div zero, v1, v0"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: zero
+              - type: MIPS_OP_REG
+                reg: v1
+              - type: MIPS_OP_REG
+                reg: v0
+      - asm_text: "divu zero, v1, v0"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: zero
+              - type: MIPS_OP_REG
+                reg: v1
+              - type: MIPS_OP_REG
+                reg: v0
+      - asm_text: "addiu sp, 0x1e"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: sp
+              - type: MIPS_OP_IMM
+                imm: 0x1e
+      - asm_text: "addiu sp, 0x2065"
+        details:
+          mips:
+            operands:
+              - type: MIPS_OP_REG
+                reg: sp
+              - type: MIPS_OP_IMM
+                imm: 0x2065
+  - input:
+      name: "Test mips32 DSP"
+      bytes: [ 0x7e,0x32,0x83,0x11,0x7e,0x53,0x8d,0x11,0x7e,0x74,0x95,0x51,0x7e,0x95,0x9b,0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "precrq.qb.ph    $s0, $s1, $s2"
+      - asm_text: "precrq.ph.w     $s1, $s2, $s3"
+      - asm_text: "precrq_rs.ph.w  $s2, $s3, $s4"
+      - asm_text: "precrqu_s.qb.ph $s3, $s4, $s5"
+
+  - input:
+      name: "Test microMips32r3 DSP"
+      bytes: [ 0x00,0xa4,0x1c,0x0d,0x00,0xa4,0x1b,0x05,0x00,0x65,0x42,0xbc,0x00,0x64,0x92,0xbc ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MICRO32R3, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "addq_s.ph   $v1, $a0, $a1"
+      - asm_text: "addq_s.w    $v1, $a0, $a1"
+      - asm_text: "dpaq_s.w.ph $ac1, $a1, $v1"
+      - asm_text: "dpaq_sa.l.w $ac2, $a0, $v1"
+
+  - input:
+      name: "Test nanomips BNEC[16] (not available in NMS) - Conflict_Space16"
+      bytes: [ 0xd8, 0xf6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_NANOMIPS, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "bnec $a3, $s1, 14"
+
+  - input:
+      name: "Test mips64r6 - Mips32r6_64r6_BranchZero32"
+      bytes: [ 0x58, 0x63, 0x00, 0x00, 0x5C, 0x63, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64R6, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "bgezc  $v1, 4"
+      - asm_text: "bltzc  $v1, 8"
+
+  - input:
+      name: "Test mips32r6 - Mips32r6_64r6_BranchZero32"
+      bytes: [ 0x58, 0x63, 0x00, 0x00, 0x5C, 0x63, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "bgezc  $v1, 4"
+      - asm_text: "bltzc  $v1, 8"
+
+  - input:
+      name: "Test nanomips jalrc rd rt is not beqc rd rt 0"
+      bytes: [ 0xd9, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_NANOMIPS, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "jalrc $ra, $t0"
+
+  - input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x07, 0xB0, 0xBD, 0xE8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "pop	{r0, r1, r2, r12, sp, pc}"
+        illegal: 1
+
+  - input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0xf0, 0x00, 0xf0, 0xe7, 0x07, 0xB0, 0xBD, 0xE8, 0xf0, 0x00, 0xf0, 0xe7 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "udf #0"
+        illegal: -1
+      - asm_text: "pop	{r0, r1, r2, r12, sp, pc}"
+        illegal: 1
+      - asm_text: "udf #0"
+        illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x21, 0x04, 0x03, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov b1, v1.b[1]"
+        illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x04, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_ARC"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld %r0, [%r1,4]"
+        illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x63, 0xb8, 0xb5, 0x2c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvld $xr3, $sp, -0x292"
+          illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x03, 0x00, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $1,$2,$3"
+          illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x41, 0x60, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmt"
+          illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x37, 0x34, 0x00, 0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui s0, 3"
+          illegal: -1
+  -
+    input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0xfe, 0x0f ]
+      arch: "xcore"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+        -
+          asm_text: "get r11, ed"
+          illegal: -1
+  - input:
+      name: "Add flag for softfail case - #2703 and #1991."
+      bytes: [ 0x18, 0x23 ]
+      arch: "CS_ARCH_XTENSA"
+      options: [ ]
+    expected:
+      insns:
+        - asm_text: "l32i.n a1, a3, 8"
+          illegal: -1
+
+  -
+    input:
+      name: "#2722 - CS_OPT_UNSIGNED is ignored for most archs"
+      bytes: [ 0x20, 0xf0, 0x5f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_UNSIGNED ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "ldur x0, [x1, #0xffffffffffffffff]"
+  -
+    input:
+      name: "issue 2737 AArch64 RET misses implicit x32 read."
+      bytes: [ 0xc0, 0x03, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ret"
+        is_alias: 1
+        details:
+          aarch64:
+            operands: []
+          regs_read: [ x30 ]