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fix PI DMA not firing due to opy-paste error + disassembly

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This commit is contained in:
CocoSimone
2022-08-12 14:49:35 +02:00
parent 2e05e81c53
commit e4c6217fd0
22 changed files with 159 additions and 91 deletions
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4
src/n64/core/CMakeLists.txt
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@@ -4,6 +4,7 @@ project(core)
add_subdirectory(cpu)
add_subdirectory(../../../external/parallel-rdp temp)
add_subdirectory(../../../external/capstone temp1)
add_library(core
Cpu.hpp
@@ -44,6 +45,7 @@ target_include_directories(core PUBLIC
../../../external
../../../external/imgui/imgui
../../../external/imgui/imgui/backends
../../../external/capstone/include
mmio)
target_link_libraries(core PUBLIC cpu parallel-rdp)
target_link_libraries(core PUBLIC cpu parallel-rdp capstone)

53
src/n64/core/Cpu.cpp
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@@ -4,6 +4,20 @@
#include <util.hpp>
namespace n64 {
Cpu::Cpu() {
#ifndef NDEBUG
if (cs_open(CS_ARCH_MIPS, CS_MODE_MIPS64, &handle)) {
util::panic("Could not initialize capstone!\n");
}
#endif
}
Cpu::~Cpu() {
#ifndef NDEBUG
cs_close(&handle);
#endif
}
inline bool ShouldServiceInterrupt(Registers& regs) {
bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0;
bool interrupts_enabled = regs.cop0.status.ie == 1;
@@ -49,22 +63,22 @@ void FireException(Registers& regs, ExceptionCode code, int cop, s64 pc) {
regs.cop0.status.exl = true;
regs.cop0.cause.copError = cop;
regs.cop0.cause.exceptionCode = static_cast<u8>(code);
regs.cop0.cause.exceptionCode = code;
if(regs.cop0.status.bev) {
util::panic("BEV bit set!\n");
} else {
switch(code) {
case ExceptionCode::Interrupt: case ExceptionCode::TLBModification:
case ExceptionCode::AddressErrorLoad: case ExceptionCode::AddressErrorStore:
case ExceptionCode::InstructionBusError: case ExceptionCode::DataBusError:
case ExceptionCode::Syscall: case ExceptionCode::Breakpoint:
case ExceptionCode::ReservedInstruction: case ExceptionCode::CoprocessorUnusable:
case ExceptionCode::Overflow: case ExceptionCode::Trap:
case ExceptionCode::FloatingPointError: case ExceptionCode::Watch:
case Interrupt: case TLBModification:
case AddressErrorLoad: case AddressErrorStore:
case InstructionBusError: case DataBusError:
case Syscall: case Breakpoint:
case ReservedInstruction: case CoprocessorUnusable:
case Overflow: case Trap:
case FloatingPointError: case Watch:
regs.SetPC((s64)((s32)0x80000180));
break;
case ExceptionCode::TLBLoad: case ExceptionCode::TLBStore:
case TLBLoad: case TLBStore:
if(old_exl || regs.cop0.tlbError == INVALID) {
regs.SetPC((s64)((s32)0x80000180));
} else if(Is64BitAddressing(regs.cop0, regs.cop0.badVaddr)) {
@@ -73,7 +87,7 @@ void FireException(Registers& regs, ExceptionCode code, int cop, s64 pc) {
regs.SetPC((s64)((s32)0x80000000));
}
break;
default: util::panic("Unhandled exception! {}\n", static_cast<u8>(code));
default: util::panic("Unhandled exception! {}\n", code);
}
}
}
@@ -84,6 +98,24 @@ inline void HandleInterrupt(Registers& regs) {
}
}
void Cpu::LogInstruction(u32 instruction) {
#ifndef NDEBUG
u8 code[4]{};
u32 bswapped = be32toh(instruction);
memcpy(code, &instruction, 4);
count = cs_disasm(handle, code, 4, regs.pc, 0, &insn);
if (count > 0) {
for(auto j = 0; j < count; j++) {
printf("%016lX:\t%s\t\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
}
cs_free(insn, count);
} else {
util::panic("Failed to disassemble {:08X}!", instruction);
}
#endif
}
void Cpu::Step(Mem& mem) {
regs.gpr[0] = 0;
regs.prevDelaySlot = regs.delaySlot;
@@ -92,6 +124,7 @@ void Cpu::Step(Mem& mem) {
CheckCompareInterrupt(mem.mmio.mi, regs);
u32 instruction = mem.Read<u32>(regs, regs.pc, regs.pc);
LogInstruction(instruction);
HandleInterrupt(regs);

15
src/n64/core/Cpu.hpp
View File

@@ -1,14 +1,25 @@
#pragma once
#include <Registers.hpp>
#include <Mem.hpp>
#ifndef NDEBUG
#include <capstone/capstone.h>
#endif
namespace n64 {
struct Cpu {
Cpu() = default;
Cpu();
~Cpu();
void Step(Mem&);
Registers regs;
private:
#ifndef NDEBUG
csh handle{};
cs_insn *insn = nullptr;
size_t count{};
#endif
friend struct Cop1;
void LogInstruction(u32);
void special(Mem&, u32);
void regimm(u32);
void Exec(Mem&, u32);
@@ -99,7 +110,7 @@ private:
void xori(u32);
};
enum class ExceptionCode : u8 {
enum ExceptionCode : u8 {
Interrupt,
TLBModification,
TLBLoad,

2
src/n64/core/Mem.cpp
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@@ -106,7 +106,7 @@ void Mem::Write(Registers& regs, u32 vaddr, T val, s64 pc) {
case 0x04000000 ... 0x04000FFF: util::WriteAccess<T>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val); break;
case 0x04001000 ... 0x04001FFF: util::WriteAccess<T>(mmio.rsp.imem, paddr & IMEM_DSIZE, val); break;
case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: mmio.Read(paddr); break;
case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: mmio.Write(*this, regs, paddr, val); break;
case 0x10000000 ... 0x1FBFFFFF: util::WriteAccess<T>(cart.data(), paddr & romMask, val); break;
case 0x1FC00000 ... 0x1FC007BF: util::WriteAccess<T>(pifBootrom, paddr & PIF_BOOTROM_DSIZE, val); break;
case 0x1FC007C0 ... 0x1FC007FF: util::WriteAccess<T>(pifRam, paddr & PIF_RAM_DSIZE, val); break;

1
src/n64/core/cpu/CMakeLists.txt
View File

@@ -16,6 +16,7 @@ add_library(cpu
target_include_directories(cpu PUBLIC registers
. ..
../../../../external
../../../../external/capstone/include
../../../../src
../../
)

14
src/n64/core/cpu/instructions.cpp
View File

@@ -175,28 +175,27 @@ void Cpu::lui(u32 instr) {
void Cpu::lb(Mem& mem, u32 instr) {
u32 address = regs.gpr[RS(instr)] + (s16)instr;
regs.gpr[RT(instr)] = s64(mem.Read<s8>(regs, address, regs.oldPC));
regs.gpr[RT(instr)] = mem.Read<s8>(regs, address, regs.oldPC);
}
void Cpu::lh(Mem& mem, u32 instr) {
u32 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 1) != 0) {
HandleTLBException(regs, (s64)((s32)address));
HandleTLBException(regs, s64(s32(address)));
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
}
regs.gpr[RT(instr)] = (s64)(s16)mem.Read<u16>(regs, address, regs.oldPC);
regs.gpr[RT(instr)] = mem.Read<s16>(regs, address, regs.oldPC);
}
void Cpu::lw(Mem& mem, u32 instr) {
u32 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 3) != 0) {
HandleTLBException(regs, (s64)((s32)address));
HandleTLBException(regs, s64(s32(address)));
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
}
s32 value = mem.Read<s32>(regs, address, regs.oldPC);
regs.gpr[RT(instr)] = value;
regs.gpr[RT(instr)] = mem.Read<s32>(regs, address, regs.oldPC);
}
void Cpu::ll(Mem& mem, u32 instr) {
@@ -209,8 +208,7 @@ void Cpu::ll(Mem& mem, u32 instr) {
regs.LLBit = true;
regs.cop0.LLAddr = address;
s32 value = mem.Read<s32>(regs, address, regs.oldPC);
regs.gpr[RT(instr)] = value;
regs.gpr[RT(instr)] = mem.Read<s32>(regs, address, regs.oldPC);
}
void Cpu::lwl(Mem& mem, u32 instr) {

2
src/n64/core/cpu/registers/Cop0.hpp
View File

@@ -191,7 +191,7 @@ private:
};
struct Registers;
enum class ExceptionCode : u8;
enum ExceptionCode : u8;
TLBEntry* TLBTryMatch(Registers& regs, u32 vaddr, int* match);
bool ProbeTLB(Registers& regs, TLBAccessType access_type, u32 vaddr, u32& paddr, int* match);

6
src/n64/core/mmio/PI.cpp
View File

@@ -21,7 +21,8 @@ auto PI::Read(MI& mi, u32 addr) const -> u32 {
case 0x04600014: case 0x04600018: case 0x0460001C: case 0x04600020:
case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030:
return stub[(addr & 0xff) - 5];
default: util::panic("Unhandled PI[{:08X}] read\n", addr); return 0;
default:
util::panic("Unhandled PI[{:08X}] read\n", addr); return 0;
}
}
@@ -68,7 +69,8 @@ void PI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
case 0x04600024: case 0x04600028: case 0x0460002C: case 0x04600030:
stub[(addr & 0xff) - 5] = val & 0xff;
break;
default: util::panic("Unhandled PI[{:08X}] write ({:08X})\n", val, addr);
default:
util::panic("Unhandled PI[{:08X}] write ({:08X})\n", val, addr);
}
}

92
src/n64/core/rsp/decode.cpp
View File

@@ -6,20 +6,20 @@ namespace n64 {
inline void special(RSP& rsp, u32 instr) {
u8 mask = instr & 0x3f;
switch(mask) {
case 0x00: rsp.sll(instr); break;
case 0x04: rsp.sllv(instr); break;
case 0x08: rsp.jr(instr); break;
case 0x0C:
case 0x0D:
rsp.spStatus.halt = true;
rsp.spStatus.broke = true;
break;
case 0x20: case 0x21:
rsp.add(instr);
break;
case 0x24: rsp.and_(instr); break;
case 0x25: rsp.or_(instr); break;
case 0x27: rsp.nor(instr); break;
//case 0x00: rsp.sll(instr); break;
//case 0x04: rsp.sllv(instr); break;
//case 0x08: rsp.jr(instr); break;
//case 0x0C:
//case 0x0D:
// rsp.spStatus.halt = true;
// rsp.spStatus.broke = true;
// break;
//case 0x20: case 0x21:
// rsp.add(instr);
// break;
//case 0x24: rsp.and_(instr); break;
//case 0x25: rsp.or_(instr); break;
//case 0x27: rsp.nor(instr); break;
default: util::panic("Unhandled RSP special instruction %d %d\n", (mask >> 3) & 7, mask & 7);
}
}
@@ -27,8 +27,8 @@ inline void special(RSP& rsp, u32 instr) {
inline void regimm(RSP& rsp, u32 instr) {
u8 mask = ((instr >> 16) & 0x1F);
switch(mask) {
case 0x00: rsp.b(instr, (s32)rsp.gpr[RS(instr)] < 0); break;
case 0x01: rsp.b(instr, (s32)rsp.gpr[RS(instr)] >= 0); break;
//case 0x00: rsp.b(instr, (s32)rsp.gpr[RS(instr)] < 0); break;
//case 0x01: rsp.b(instr, (s32)rsp.gpr[RS(instr)] >= 0); break;
default: util::panic("Unhandled RSP regimm instruction %d %d\n", (mask >> 3) & 3, mask & 7);
}
}
@@ -36,7 +36,7 @@ inline void regimm(RSP& rsp, u32 instr) {
inline void lwc2(RSP& rsp, u32 instr) {
u8 mask = (instr >> 11) & 0x1F;
switch(mask) {
case 0x04: rsp.lqv(instr); break;
//case 0x04: rsp.lqv(instr); break;
default: util::panic("Unhandled RSP LWC2 %d %d\n", (mask >> 3) & 3, mask & 7);
}
}
@@ -44,7 +44,7 @@ inline void lwc2(RSP& rsp, u32 instr) {
inline void swc2(RSP& rsp, u32 instr) {
u8 mask = (instr >> 11) & 0x1F;
switch(mask) {
case 0x04: rsp.sqv(instr); break;
//case 0x04: rsp.sqv(instr); break;
default: util::panic("Unhandled RSP SWC2 %d %d\n", (mask >> 3) & 3, mask & 7);
}
}
@@ -55,15 +55,15 @@ inline void cop2(RSP& rsp, u32 instr) {
switch(mask) {
case 0x00:
switch(mask_sub) {
case 0x02: rsp.cfc2(instr); break;
//case 0x02: rsp.cfc2(instr); break;
default: util::panic("Unhandled RSP COP2 sub %d %d\n", (mask_sub >> 3) & 3, mask_sub & 3);
}
break;
case 0x13: rsp.vabs(instr); break;
case 0x1D: rsp.vsar(instr); break;
case 0x21: rsp.veq(instr); break;
case 0x22: rsp.vne(instr); break;
case 0x33: rsp.vmov(instr); break;
//case 0x13: rsp.vabs(instr); break;
//case 0x1D: rsp.vsar(instr); break;
//case 0x21: rsp.veq(instr); break;
//case 0x22: rsp.vne(instr); break;
//case 0x33: rsp.vmov(instr); break;
default: util::panic("Unhandled RSP COP2 %d %d\n", (mask >> 3) & 7, mask & 7);
}
}
@@ -71,8 +71,8 @@ inline void cop2(RSP& rsp, u32 instr) {
inline void cop0(MI& mi, Registers& regs, RSP& rsp, RDP& rdp, u32 instr) {
u8 mask = (instr >> 21) & 0x1F;
switch(mask) {
case 0x00: rsp.mfc0(rdp, instr); break;
case 0x04: rsp.mtc0(mi, regs, rdp, instr); break;
//case 0x00: rsp.mfc0(rdp, instr); break;
//case 0x04: rsp.mtc0(mi, regs, rdp, instr); break;
default: util::panic("Unhandled RSP COP0 %d %d\n", (mask >> 3) & 3, mask & 7);
}
}
@@ -80,26 +80,26 @@ inline void cop0(MI& mi, Registers& regs, RSP& rsp, RDP& rdp, u32 instr) {
void RSP::Exec(MI &mi, Registers &regs, RDP &rdp, u32 instr) {
u8 mask = (instr >> 26) & 0x3F;
switch(mask) {
case 0x00: special(*this, instr); break;
case 0x01: regimm(*this, instr); break;
case 0x02: j(instr); break;
case 0x03: jal(instr); break;
case 0x04: b(instr, gpr[RT(instr)] == gpr[RS(instr)]); break;
case 0x05: b(instr, gpr[RT(instr)] != gpr[RS(instr)]); break;
case 0x07: b(instr, gpr[RS(instr)] > 0); break;
case 0x08: case 0x09: addi(instr); break;
case 0x0C: andi(instr); break;
case 0x0D: ori(instr); break;
case 0x0F: lui(instr); break;
case 0x10: cop0(mi, regs, *this, rdp, instr); break;
case 0x12: cop2(*this, instr); break;
case 0x21: lh(instr); break;
case 0x23: lw(instr); break;
case 0x28: sb(instr); break;
case 0x29: sh(instr); break;
case 0x2B: sw(instr); break;
case 0x32: lwc2(*this, instr); break;
case 0x3A: swc2(*this, instr); break;
//case 0x00: special(*this, instr); break;
//case 0x01: regimm(*this, instr); break;
//case 0x02: j(instr); break;
//case 0x03: jal(instr); break;
//case 0x04: b(instr, gpr[RT(instr)] == gpr[RS(instr)]); break;
//case 0x05: b(instr, gpr[RT(instr)] != gpr[RS(instr)]); break;
//case 0x07: b(instr, gpr[RS(instr)] > 0); break;
//case 0x08: case 0x09: addi(instr); break;
//case 0x0C: andi(instr); break;
//case 0x0D: ori(instr); break;
//case 0x0F: lui(instr); break;
//case 0x10: cop0(mi, regs, *this, rdp, instr); break;
//case 0x12: cop2(*this, instr); break;
//case 0x21: lh(instr); break;
//case 0x23: lw(instr); break;
//case 0x28: sb(instr); break;
//case 0x29: sh(instr); break;
//case 0x2B: sw(instr); break;
//case 0x32: lwc2(*this, instr); break;
//case 0x3A: swc2(*this, instr); break;
default: util::panic("Unhandled RSP instruction %d %d\n", (mask >> 3) & 7, mask & 7);
}
}