Fuck git

external/capstone/arch/AArch64/AArch64BaseInfo.c

@@ -0,0 +1,175 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "AArch64BaseInfo.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define GET_AT_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_AT_IMPL
+
+#define GET_DBNXS_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_DBNXS_IMPL
+
+#define GET_DB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_DB_IMPL
+
+#define GET_DC_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_DC_IMPL
+
+#define GET_IC_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_IC_IMPL
+
+#define GET_ISB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_ISB_IMPL
+
+#define GET_TSB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_TSB_IMPL
+
+#define GET_PRCTX_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PRCTX_IMPL
+
+#define GET_PRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PRFM_IMPL
+
+#define GET_SVEPRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVEPRFM_IMPL
+
+#define GET_RPRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_RPRFM_IMPL
+
+// namespace AArch64RPRFM
+// namespace llvm
+
+#define GET_SVEPREDPAT_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVEPREDPAT_IMPL
+
+#define GET_SVEVECLENSPECIFIER_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVEVECLENSPECIFIER_IMPL
+
+// namespace AArch64SVEVecLenSpecifier
+// namespace llvm
+
+#define GET_EXACTFPIMM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_EXACTFPIMM_IMPL
+
+#define GET_PSTATEIMM0_15_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PSTATEIMM0_15_IMPL
+
+#define GET_PSTATEIMM0_1_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PSTATEIMM0_1_IMPL
+
+#define GET_PSB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PSB_IMPL
+
+#define GET_BTI_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_BTI_IMPL
+
+#define SysReg AArch64SysReg_SysReg
+#define GET_SYSREG_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SYSREG_IMPL
+
+#undef SysReg
+
+// return a string representing the number X
+// NOTE: result must be big enough to contain the data
+static void utostr(uint64_t X, bool isNeg, char *result)
+{
+	char Buffer[22];
+	char *BufPtr = Buffer + 21;
+
+	Buffer[21] = '\0';
+	if (X == 0)
+		*--BufPtr = '0'; // Handle special case...
+
+	while (X) {
+		*--BufPtr = X % 10 + '0';
+		X /= 10;
+	}
+
+	if (isNeg)
+		*--BufPtr = '-'; // Add negative sign...
+
+	// suppose that result is big enough
+	strncpy(result, BufPtr, sizeof(Buffer));
+}
+
+// NOTE: result must be big enough to contain the result
+void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
+{
+	CS_ASSERT_RET(Bits < 0x10000);
+	char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32];
+	int dummy;
+	uint32_t Op0 = (Bits >> 14) & 0x3;
+	uint32_t Op1 = (Bits >> 11) & 0x7;
+	uint32_t CRn = (Bits >> 7) & 0xf;
+	uint32_t CRm = (Bits >> 3) & 0xf;
+	uint32_t Op2 = Bits & 0x7;
+
+	utostr(Op0, false, Op0Str);
+	utostr(Op1, false, Op1Str);
+	utostr(Op2, false, Op2Str);
+	utostr(CRn, false, CRnStr);
+	utostr(CRm, false, CRmStr);
+
+	dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
+			    Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
+	(void)dummy;
+}
+
+#define GET_TLBITable_IMPL
+
+#include "AArch64GenSystemOperands.inc"
+#undef GET_TLBITable_IMPL
+
+#define GET_SVCR_IMPL
+
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVCR_IMPL

external/capstone/arch/AArch64/AArch64BaseInfo.h

@@ -0,0 +1,986 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the AArch64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
+#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
+
+// FIXME: Is it easiest to fix this layering violation by moving the .inc
+// #includes from AArch64MCTargetDesc.h to here?
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../MCInstPrinter.h"
+
+#include "../../utils.h"
+#include "capstone/aarch64.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "AArch64GenSubtargetInfo.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "AArch64GenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+static inline unsigned getWRegFromXReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_X0:
+		return AArch64_W0;
+	case AArch64_X1:
+		return AArch64_W1;
+	case AArch64_X2:
+		return AArch64_W2;
+	case AArch64_X3:
+		return AArch64_W3;
+	case AArch64_X4:
+		return AArch64_W4;
+	case AArch64_X5:
+		return AArch64_W5;
+	case AArch64_X6:
+		return AArch64_W6;
+	case AArch64_X7:
+		return AArch64_W7;
+	case AArch64_X8:
+		return AArch64_W8;
+	case AArch64_X9:
+		return AArch64_W9;
+	case AArch64_X10:
+		return AArch64_W10;
+	case AArch64_X11:
+		return AArch64_W11;
+	case AArch64_X12:
+		return AArch64_W12;
+	case AArch64_X13:
+		return AArch64_W13;
+	case AArch64_X14:
+		return AArch64_W14;
+	case AArch64_X15:
+		return AArch64_W15;
+	case AArch64_X16:
+		return AArch64_W16;
+	case AArch64_X17:
+		return AArch64_W17;
+	case AArch64_X18:
+		return AArch64_W18;
+	case AArch64_X19:
+		return AArch64_W19;
+	case AArch64_X20:
+		return AArch64_W20;
+	case AArch64_X21:
+		return AArch64_W21;
+	case AArch64_X22:
+		return AArch64_W22;
+	case AArch64_X23:
+		return AArch64_W23;
+	case AArch64_X24:
+		return AArch64_W24;
+	case AArch64_X25:
+		return AArch64_W25;
+	case AArch64_X26:
+		return AArch64_W26;
+	case AArch64_X27:
+		return AArch64_W27;
+	case AArch64_X28:
+		return AArch64_W28;
+	case AArch64_FP:
+		return AArch64_W29;
+	case AArch64_LR:
+		return AArch64_W30;
+	case AArch64_SP:
+		return AArch64_WSP;
+	case AArch64_XZR:
+		return AArch64_WZR;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline unsigned getXRegFromWReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_W0:
+		return AArch64_X0;
+	case AArch64_W1:
+		return AArch64_X1;
+	case AArch64_W2:
+		return AArch64_X2;
+	case AArch64_W3:
+		return AArch64_X3;
+	case AArch64_W4:
+		return AArch64_X4;
+	case AArch64_W5:
+		return AArch64_X5;
+	case AArch64_W6:
+		return AArch64_X6;
+	case AArch64_W7:
+		return AArch64_X7;
+	case AArch64_W8:
+		return AArch64_X8;
+	case AArch64_W9:
+		return AArch64_X9;
+	case AArch64_W10:
+		return AArch64_X10;
+	case AArch64_W11:
+		return AArch64_X11;
+	case AArch64_W12:
+		return AArch64_X12;
+	case AArch64_W13:
+		return AArch64_X13;
+	case AArch64_W14:
+		return AArch64_X14;
+	case AArch64_W15:
+		return AArch64_X15;
+	case AArch64_W16:
+		return AArch64_X16;
+	case AArch64_W17:
+		return AArch64_X17;
+	case AArch64_W18:
+		return AArch64_X18;
+	case AArch64_W19:
+		return AArch64_X19;
+	case AArch64_W20:
+		return AArch64_X20;
+	case AArch64_W21:
+		return AArch64_X21;
+	case AArch64_W22:
+		return AArch64_X22;
+	case AArch64_W23:
+		return AArch64_X23;
+	case AArch64_W24:
+		return AArch64_X24;
+	case AArch64_W25:
+		return AArch64_X25;
+	case AArch64_W26:
+		return AArch64_X26;
+	case AArch64_W27:
+		return AArch64_X27;
+	case AArch64_W28:
+		return AArch64_X28;
+	case AArch64_W29:
+		return AArch64_FP;
+	case AArch64_W30:
+		return AArch64_LR;
+	case AArch64_WSP:
+		return AArch64_SP;
+	case AArch64_WZR:
+		return AArch64_XZR;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline unsigned getXRegFromXRegTuple(unsigned RegTuple)
+{
+	switch (RegTuple) {
+	case AArch64_X0_X1_X2_X3_X4_X5_X6_X7:
+		return AArch64_X0;
+	case AArch64_X2_X3_X4_X5_X6_X7_X8_X9:
+		return AArch64_X2;
+	case AArch64_X4_X5_X6_X7_X8_X9_X10_X11:
+		return AArch64_X4;
+	case AArch64_X6_X7_X8_X9_X10_X11_X12_X13:
+		return AArch64_X6;
+	case AArch64_X8_X9_X10_X11_X12_X13_X14_X15:
+		return AArch64_X8;
+	case AArch64_X10_X11_X12_X13_X14_X15_X16_X17:
+		return AArch64_X10;
+	case AArch64_X12_X13_X14_X15_X16_X17_X18_X19:
+		return AArch64_X12;
+	case AArch64_X14_X15_X16_X17_X18_X19_X20_X21:
+		return AArch64_X14;
+	case AArch64_X16_X17_X18_X19_X20_X21_X22_X23:
+		return AArch64_X16;
+	case AArch64_X18_X19_X20_X21_X22_X23_X24_X25:
+		return AArch64_X18;
+	case AArch64_X20_X21_X22_X23_X24_X25_X26_X27:
+		return AArch64_X20;
+	case AArch64_X22_X23_X24_X25_X26_X27_X28_FP:
+		return AArch64_X22;
+	}
+	// For anything else, return it unchanged.
+	return RegTuple;
+}
+
+static inline unsigned getBRegFromDReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_D0:
+		return AArch64_B0;
+	case AArch64_D1:
+		return AArch64_B1;
+	case AArch64_D2:
+		return AArch64_B2;
+	case AArch64_D3:
+		return AArch64_B3;
+	case AArch64_D4:
+		return AArch64_B4;
+	case AArch64_D5:
+		return AArch64_B5;
+	case AArch64_D6:
+		return AArch64_B6;
+	case AArch64_D7:
+		return AArch64_B7;
+	case AArch64_D8:
+		return AArch64_B8;
+	case AArch64_D9:
+		return AArch64_B9;
+	case AArch64_D10:
+		return AArch64_B10;
+	case AArch64_D11:
+		return AArch64_B11;
+	case AArch64_D12:
+		return AArch64_B12;
+	case AArch64_D13:
+		return AArch64_B13;
+	case AArch64_D14:
+		return AArch64_B14;
+	case AArch64_D15:
+		return AArch64_B15;
+	case AArch64_D16:
+		return AArch64_B16;
+	case AArch64_D17:
+		return AArch64_B17;
+	case AArch64_D18:
+		return AArch64_B18;
+	case AArch64_D19:
+		return AArch64_B19;
+	case AArch64_D20:
+		return AArch64_B20;
+	case AArch64_D21:
+		return AArch64_B21;
+	case AArch64_D22:
+		return AArch64_B22;
+	case AArch64_D23:
+		return AArch64_B23;
+	case AArch64_D24:
+		return AArch64_B24;
+	case AArch64_D25:
+		return AArch64_B25;
+	case AArch64_D26:
+		return AArch64_B26;
+	case AArch64_D27:
+		return AArch64_B27;
+	case AArch64_D28:
+		return AArch64_B28;
+	case AArch64_D29:
+		return AArch64_B29;
+	case AArch64_D30:
+		return AArch64_B30;
+	case AArch64_D31:
+		return AArch64_B31;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline unsigned getDRegFromBReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_B0:
+		return AArch64_D0;
+	case AArch64_B1:
+		return AArch64_D1;
+	case AArch64_B2:
+		return AArch64_D2;
+	case AArch64_B3:
+		return AArch64_D3;
+	case AArch64_B4:
+		return AArch64_D4;
+	case AArch64_B5:
+		return AArch64_D5;
+	case AArch64_B6:
+		return AArch64_D6;
+	case AArch64_B7:
+		return AArch64_D7;
+	case AArch64_B8:
+		return AArch64_D8;
+	case AArch64_B9:
+		return AArch64_D9;
+	case AArch64_B10:
+		return AArch64_D10;
+	case AArch64_B11:
+		return AArch64_D11;
+	case AArch64_B12:
+		return AArch64_D12;
+	case AArch64_B13:
+		return AArch64_D13;
+	case AArch64_B14:
+		return AArch64_D14;
+	case AArch64_B15:
+		return AArch64_D15;
+	case AArch64_B16:
+		return AArch64_D16;
+	case AArch64_B17:
+		return AArch64_D17;
+	case AArch64_B18:
+		return AArch64_D18;
+	case AArch64_B19:
+		return AArch64_D19;
+	case AArch64_B20:
+		return AArch64_D20;
+	case AArch64_B21:
+		return AArch64_D21;
+	case AArch64_B22:
+		return AArch64_D22;
+	case AArch64_B23:
+		return AArch64_D23;
+	case AArch64_B24:
+		return AArch64_D24;
+	case AArch64_B25:
+		return AArch64_D25;
+	case AArch64_B26:
+		return AArch64_D26;
+	case AArch64_B27:
+		return AArch64_D27;
+	case AArch64_B28:
+		return AArch64_D28;
+	case AArch64_B29:
+		return AArch64_D29;
+	case AArch64_B30:
+		return AArch64_D30;
+	case AArch64_B31:
+		return AArch64_D31;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline bool atomicBarrierDroppedOnZero(unsigned Opcode)
+{
+	switch (Opcode) {
+	case AArch64_LDADDAB:
+	case AArch64_LDADDAH:
+	case AArch64_LDADDAW:
+	case AArch64_LDADDAX:
+	case AArch64_LDADDALB:
+	case AArch64_LDADDALH:
+	case AArch64_LDADDALW:
+	case AArch64_LDADDALX:
+	case AArch64_LDCLRAB:
+	case AArch64_LDCLRAH:
+	case AArch64_LDCLRAW:
+	case AArch64_LDCLRAX:
+	case AArch64_LDCLRALB:
+	case AArch64_LDCLRALH:
+	case AArch64_LDCLRALW:
+	case AArch64_LDCLRALX:
+	case AArch64_LDEORAB:
+	case AArch64_LDEORAH:
+	case AArch64_LDEORAW:
+	case AArch64_LDEORAX:
+	case AArch64_LDEORALB:
+	case AArch64_LDEORALH:
+	case AArch64_LDEORALW:
+	case AArch64_LDEORALX:
+	case AArch64_LDSETAB:
+	case AArch64_LDSETAH:
+	case AArch64_LDSETAW:
+	case AArch64_LDSETAX:
+	case AArch64_LDSETALB:
+	case AArch64_LDSETALH:
+	case AArch64_LDSETALW:
+	case AArch64_LDSETALX:
+	case AArch64_LDSMAXAB:
+	case AArch64_LDSMAXAH:
+	case AArch64_LDSMAXAW:
+	case AArch64_LDSMAXAX:
+	case AArch64_LDSMAXALB:
+	case AArch64_LDSMAXALH:
+	case AArch64_LDSMAXALW:
+	case AArch64_LDSMAXALX:
+	case AArch64_LDSMINAB:
+	case AArch64_LDSMINAH:
+	case AArch64_LDSMINAW:
+	case AArch64_LDSMINAX:
+	case AArch64_LDSMINALB:
+	case AArch64_LDSMINALH:
+	case AArch64_LDSMINALW:
+	case AArch64_LDSMINALX:
+	case AArch64_LDUMAXAB:
+	case AArch64_LDUMAXAH:
+	case AArch64_LDUMAXAW:
+	case AArch64_LDUMAXAX:
+	case AArch64_LDUMAXALB:
+	case AArch64_LDUMAXALH:
+	case AArch64_LDUMAXALW:
+	case AArch64_LDUMAXALX:
+	case AArch64_LDUMINAB:
+	case AArch64_LDUMINAH:
+	case AArch64_LDUMINAW:
+	case AArch64_LDUMINAX:
+	case AArch64_LDUMINALB:
+	case AArch64_LDUMINALH:
+	case AArch64_LDUMINALW:
+	case AArch64_LDUMINALX:
+	case AArch64_SWPAB:
+	case AArch64_SWPAH:
+	case AArch64_SWPAW:
+	case AArch64_SWPAX:
+	case AArch64_SWPALB:
+	case AArch64_SWPALH:
+	case AArch64_SWPALW:
+	case AArch64_SWPALX:
+		return true;
+	}
+	return false;
+}
+
+// MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h
+// MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h
+// MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h
+// MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h
+
+typedef struct SysAlias {
+	const char *Name;
+	aarch64_sysop_alias SysAlias;
+	uint16_t Encoding;
+	aarch64_insn_group FeaturesRequired[3];
+} SysAlias;
+
+typedef struct SysAliasReg {
+	const char *Name;
+	aarch64_sysop_reg SysReg;
+	uint16_t Encoding;
+	bool NeedsReg;
+	aarch64_insn_group FeaturesRequired[3];
+} SysAliasReg;
+
+typedef struct SysAliasImm {
+	const char *Name;
+	aarch64_sysop_imm SysImm;
+	uint16_t ImmValue;
+	uint16_t Encoding;
+	aarch64_insn_group FeaturesRequired[3];
+} SysAliasImm;
+
+// CS namespace begin: AArch64SVCR
+
+#define AArch64SVCR_SVCR SysAlias
+
+#define GET_SVCR_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVCR
+
+// CS namespace begin: AArch64AT
+
+#define AArch64AT_AT SysAlias
+
+#define GET_AT_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64AT
+
+// CS namespace begin: AArch64DB
+
+#define AArch64DB_DB SysAlias
+
+#define GET_DB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64DB
+
+// CS namespace begin: AArch64DBnXS
+
+#define AArch64DBnXS_DBnXS SysAliasImm
+
+#define GET_DBNXS_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64DBnXS
+
+// CS namespace begin: AArch64DC
+
+#define AArch64DC_DC SysAlias
+
+#define GET_DC_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64DC
+
+// CS namespace begin: AArch64IC
+
+#define AArch64IC_IC SysAliasReg
+
+#define GET_IC_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64IC
+
+// CS namespace begin: AArch64ISB
+
+#define AArch64ISB_ISB SysAlias
+
+#define GET_ISB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64ISB
+
+// CS namespace begin: AArch64TSB
+
+#define AArch64TSB_TSB SysAlias
+
+#define GET_TSB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64TSB
+
+// CS namespace begin: AArch64PRFM
+
+#define AArch64PRFM_PRFM SysAlias
+
+#define GET_PRFM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PRFM
+
+// CS namespace begin: AArch64SVEPRFM
+
+#define AArch64SVEPRFM_SVEPRFM SysAlias
+
+#define GET_SVEPRFM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVEPRFM
+
+// CS namespace begin: AArch64RPRFM
+
+#define AArch64RPRFM_RPRFM SysAlias
+
+#define GET_RPRFM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64RPRFM
+
+// CS namespace begin: AArch64SVEPredPattern
+
+typedef struct SVEPREDPAT {
+	const char *Name;
+	aarch64_sysop_alias SysAlias;
+	uint16_t Encoding;
+} AArch64SVEPredPattern_SVEPREDPAT;
+
+#define GET_SVEPREDPAT_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVEPredPattern
+
+// CS namespace begin: AArch64SVEVecLenSpecifier
+
+typedef struct SVEVECLENSPECIFIER {
+	const char *Name;
+	aarch64_sysop_alias SysAlias;
+	uint16_t Encoding;
+} AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER;
+
+#define GET_SVEVECLENSPECIFIER_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVEVecLenSpecifier
+
+// namespace AArch64SVEVecLenSpecifier
+
+/// Return the number of active elements for VL1 to VL256 predicate pattern,
+/// zero for all other patterns.
+static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
+{
+	switch (Pattern) {
+	default:
+		return 0;
+	case AARCH64_SVEPREDPAT_VL1:
+	case AARCH64_SVEPREDPAT_VL2:
+	case AARCH64_SVEPREDPAT_VL3:
+	case AARCH64_SVEPREDPAT_VL4:
+	case AARCH64_SVEPREDPAT_VL5:
+	case AARCH64_SVEPREDPAT_VL6:
+	case AARCH64_SVEPREDPAT_VL7:
+	case AARCH64_SVEPREDPAT_VL8:
+		return Pattern;
+	case AARCH64_SVEPREDPAT_VL16:
+		return 16;
+	case AARCH64_SVEPREDPAT_VL32:
+		return 32;
+	case AARCH64_SVEPREDPAT_VL64:
+		return 64;
+	case AARCH64_SVEPREDPAT_VL128:
+		return 128;
+	case AARCH64_SVEPREDPAT_VL256:
+		return 256;
+	}
+}
+
+/// Return specific VL predicate pattern based on the number of elements.
+static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
+{
+	switch (MinNumElts) {
+	default:
+		return 0;
+	case 1:
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+	case 8:
+		return MinNumElts;
+	case 16:
+		return AARCH64_SVEPREDPAT_VL16;
+	case 32:
+		return AARCH64_SVEPREDPAT_VL32;
+	case 64:
+		return AARCH64_SVEPREDPAT_VL64;
+	case 128:
+		return AARCH64_SVEPREDPAT_VL128;
+	case 256:
+		return AARCH64_SVEPREDPAT_VL256;
+	}
+}
+
+// CS namespace begin: AArch64ExactFPImm
+
+typedef struct ExactFPImm {
+	const char *Name;
+	aarch64_sysop_imm SysImm;
+	int Enum;
+	const char *Repr;
+} AArch64ExactFPImm_ExactFPImm;
+
+enum {
+	AArch64ExactFPImm_half = 1,
+	AArch64ExactFPImm_one = 2,
+	AArch64ExactFPImm_two = 3,
+	AArch64ExactFPImm_zero = 0,
+};
+
+#define GET_EXACTFPIMM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64ExactFPImm
+
+// CS namespace begin: AArch64PState
+
+#define AArch64PState_PStateImm0_15 SysAlias
+
+#define GET_PSTATEIMM0_15_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+#define AArch64PState_PStateImm0_1 SysAlias
+
+#define GET_PSTATEIMM0_1_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PState
+
+// CS namespace begin: AArch64PSBHint
+
+#define AArch64PSBHint_PSB SysAlias
+
+#define GET_PSB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PSBHint
+
+// CS namespace begin: AArch64BTIHint
+
+#define AArch64BTIHint_BTI SysAlias
+
+#define GET_BTI_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64BTIHint
+
+// CS namespace begin: AArch64SE
+
+typedef enum ShiftExtSpecifiers {
+	AArch64SE_Invalid = -1,
+	AArch64SE_LSL,
+	AArch64SE_MSL,
+	AArch64SE_LSR,
+	AArch64SE_ASR,
+	AArch64SE_ROR,
+
+	AArch64SE_UXTB,
+	AArch64SE_UXTH,
+	AArch64SE_UXTW,
+	AArch64SE_UXTX,
+
+	AArch64SE_SXTB,
+	AArch64SE_SXTH,
+	AArch64SE_SXTW,
+	AArch64SE_SXTX
+} AArch64SE_ShiftExtSpecifiers;
+
+// CS namespace end: AArch64SE
+
+// CS namespace begin: AArch64Layout
+
+// MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h
+// MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h
+// MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h
+
+// CS namespace end: AArch64Layout
+
+// CS namespace begin: AArch64SysReg
+
+typedef struct SysReg {
+	const char *Name;
+	aarch64_sysop_reg SysReg;
+	const char *AltName;
+	aarch64_sysop_reg AliasReg;
+	unsigned Encoding;
+	bool Readable;
+	bool Writeable;
+	aarch64_insn_group FeaturesRequired[3];
+} AArch64SysReg_SysReg;
+
+#define GET_SYSREG_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
+const AArch64SysReg_SysReg *
+AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
+#define AARCH64_GRS_LEN 128
+void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
+
+// CS namespace end: AArch64SysReg
+
+// CS namespace begin: AArch64TLBI
+
+#define AArch64TLBI_TLBI SysAliasReg
+
+#define GET_TLBITable_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64TLBI
+
+// CS namespace begin: AArch64PRCTX
+
+#define AArch64PRCTX_PRCTX SysAliasReg
+
+#define GET_PRCTX_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PRCTX
+
+// CS namespace begin: AArch64II
+
+/// Target Operand Flag enum.
+typedef enum TOF {
+	//===------------------------------------------------------------------===//
+	// AArch64 Specific MachineOperand flags.
+
+	AArch64II_MO_NO_FLAG,
+
+	AArch64II_MO_FRAGMENT = 0x7,
+
+	/// MO_PAGE - A symbol operand with this flag represents the pc-relative
+	/// offset of the 4K page containing the symbol.  This is used with the
+	/// ADRP instruction.
+	AArch64II_MO_PAGE = 1,
+
+	/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
+	/// that symbol within a 4K page.  This offset is added to the page address
+	/// to produce the complete address.
+	AArch64II_MO_PAGEOFF = 2,
+
+	/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
+	/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G3 = 3,
+
+	/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
+	/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G2 = 4,
+
+	/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
+	/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G1 = 5,
+
+	/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
+	/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G0 = 6,
+
+	/// MO_HI12 - This flag indicates that a symbol operand represents the bits
+	/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
+	/// by-12-bits instruction.
+	AArch64II_MO_HI12 = 7,
+
+	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
+	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
+	/// stub symbols on windows.
+	AArch64II_MO_COFFSTUB = 0x8,
+
+	/// MO_GOT - This flag indicates that a symbol operand represents the
+	/// address of the GOT entry for the symbol, rather than the address of
+	/// the symbol itself.
+	AArch64II_MO_GOT = 0x10,
+
+	/// MO_NC - Indicates whether the linker is expected to check the symbol
+	/// reference for overflow. For example in an ADRP/ADD pair of relocations
+	/// the ADRP usually does check, but not the ADD.
+	AArch64II_MO_NC = 0x20,
+
+	/// MO_TLS - Indicates that the operand being accessed is some kind of
+	/// thread-local symbol. On Darwin, only one type of thread-local access
+	/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
+	/// referee will affect interpretation.
+	AArch64II_MO_TLS = 0x40,
+
+	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
+	/// to the symbol is for an import stub.  This is used for DLL import
+	/// storage class indication on Windows.
+	AArch64II_MO_DLLIMPORT = 0x80,
+
+	/// MO_S - Indicates that the bits of the symbol operand represented by
+	/// MO_G0 etc are signed.
+	AArch64II_MO_S = 0x100,
+
+	/// MO_PREL - Indicates that the bits of the symbol operand represented by
+	/// MO_G0 etc are PC relative.
+	AArch64II_MO_PREL = 0x200,
+
+	/// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
+	/// in bits 56-63.
+	/// On a FrameIndex operand, indicates that the underlying memory is tagged
+	/// with an unknown tag value (MTE); this needs to be lowered either to an
+	/// SP-relative load or store instruction (which do not check tags), or to
+	/// an LDG instruction to obtain the tag value.
+	AArch64II_MO_TAGGED = 0x400,
+
+	/// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
+	/// of a symbol, not the original. For dllimport symbols, this means it
+	/// uses "__imp_aux".  For other symbols, this means it uses the mangled
+	/// ("#" prefix for C) name.
+	AArch64II_MO_ARM64EC_CALLMANGLE = 0x800,
+} AArch64II_TOF;
+
+// CS namespace end: AArch64II
+
+// end namespace AArch64II
+
+//===----------------------------------------------------------------------===//
+// v8.3a Pointer Authentication
+//
+
+// CS namespace begin: AArch64PACKey
+
+typedef enum ID {
+	AArch64PACKey_IA = 0,
+	AArch64PACKey_IB = 1,
+	AArch64PACKey_DA = 2,
+	AArch64PACKey_DB = 3,
+	AArch64PACKey_LAST = AArch64PACKey_DB,
+	AArch64PACKey_INVALID,
+} AArch64PACKey_ID;
+
+// CS namespace end: AArch64PACKey
+
+// namespace AArch64PACKey
+
+/// Return 2-letter identifier string for numeric key ID.
+static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
+{
+	switch (KeyID) {
+	default:
+		break;
+	case AArch64PACKey_IA:
+		return "ia";
+	case AArch64PACKey_IB:
+		return "ib";
+	case AArch64PACKey_DA:
+		return "da";
+	case AArch64PACKey_DB:
+		return "db";
+	}
+	return NULL;
+}
+
+/// Return numeric key ID for 2-letter identifier string.
+static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
+{
+	if (strcmp(Name, "ia") == 0)
+		return AArch64PACKey_IA;
+	if (strcmp(Name, "ib") == 0)
+		return AArch64PACKey_IB;
+	if (strcmp(Name, "da") == 0)
+		return AArch64PACKey_DA;
+	if (strcmp(Name, "db") == 0)
+		return AArch64PACKey_DB;
+	CS_ASSERT_RET_VAL(0 && "Invalid PAC key", AArch64PACKey_INVALID);
+	return AArch64PACKey_LAST;
+}
+
+// CS namespace begin: AArch64
+
+// The number of bits in a SVE register is architecturally defined
+// to be a multiple of this value.  If <M x t> has this number of bits,
+// a <n x M x t> vector can be stored in a SVE register without any
+// redundant bits.  If <M x t> has this number of bits divided by P,
+// a <n x M x t> vector is stored in a SVE register by placing index i
+// in index i*P of a <n x (M*P) x t> vector.  The other elements of the
+// <n x (M*P) x t> vector (such as index 1) are undefined.
+static const unsigned SVEBitsPerBlock = 128;
+
+static const unsigned SVEMaxBitsPerVector = 2048;
+
+// CS namespace end: AArch64
+
+// end namespace AArch64
+// end namespace llvm
+
+#endif

external/capstone/arch/AArch64/AArch64DisassemblerExtension.c

@@ -0,0 +1,28 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#include "AArch64DisassemblerExtension.h"
+#include "AArch64BaseInfo.h"
+
+bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	if (feature == AArch64_FeatureAMX || feature == AArch64_FeatureMUL53 ||
+			feature == AArch64_FeatureAppleSys) {
+		return mode & CS_MODE_APPLE_PROPRIETARY;
+	}
+	// we support everything
+	return true;
+}
+
+/// Tests a NULL terminated array of features if they are enabled.
+bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features)
+{
+	int i = 0;
+	while (features[i]) {
+		if (!AArch64_getFeatureBits(mode, features[i]))
+			return false;
+		++i;
+	}
+	return true;
+}

external/capstone/arch/AArch64/AArch64DisassemblerExtension.h

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_AARCH64_DISASSEMBLER_EXTENSION_H
+#define CS_AARCH64_DISASSEMBLER_EXTENSION_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../cs_priv.h"
+#include "AArch64AddressingModes.h"
+#include "capstone/aarch64.h"
+#include "capstone/capstone.h"
+
+bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
+bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features);
+
+#endif // CS_AARCH64_DISASSEMBLER_EXTENSION_H

external/capstone/arch/AArch64/AArch64GenCSAliasMnemMap.inc

@@ -0,0 +1,375 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ AARCH64_INS_ALIAS_ADDPT, "addpt" },
+	{ AARCH64_INS_ALIAS_GCSB, "gcsb" },
+	{ AARCH64_INS_ALIAS_GCSPOPM, "gcspopm" },
+	{ AARCH64_INS_ALIAS_LDAPUR, "ldapur" },
+	{ AARCH64_INS_ALIAS_STLLRB, "stllrb" },
+	{ AARCH64_INS_ALIAS_STLLRH, "stllrh" },
+	{ AARCH64_INS_ALIAS_STLLR, "stllr" },
+	{ AARCH64_INS_ALIAS_STLRB, "stlrb" },
+	{ AARCH64_INS_ALIAS_STLRH, "stlrh" },
+	{ AARCH64_INS_ALIAS_STLR, "stlr" },
+	{ AARCH64_INS_ALIAS_STLUR, "stlur" },
+	{ AARCH64_INS_ALIAS_SUBPT, "subpt" },
+	{ AARCH64_INS_ALIAS_LDRAA, "ldraa" },
+	{ AARCH64_INS_ALIAS_ADD, "add" },
+	{ AARCH64_INS_ALIAS_CMN, "cmn" },
+	{ AARCH64_INS_ALIAS_ADDS, "adds" },
+	{ AARCH64_INS_ALIAS_AND, "and" },
+	{ AARCH64_INS_ALIAS_ANDS, "ands" },
+	{ AARCH64_INS_ALIAS_LDR, "ldr" },
+	{ AARCH64_INS_ALIAS_STR, "str" },
+	{ AARCH64_INS_ALIAS_LDRB, "ldrb" },
+	{ AARCH64_INS_ALIAS_STRB, "strb" },
+	{ AARCH64_INS_ALIAS_LDRH, "ldrh" },
+	{ AARCH64_INS_ALIAS_STRH, "strh" },
+	{ AARCH64_INS_ALIAS_PRFM, "prfm" },
+	{ AARCH64_INS_ALIAS_LDAPURB, "ldapurb" },
+	{ AARCH64_INS_ALIAS_STLURB, "stlurb" },
+	{ AARCH64_INS_ALIAS_LDUR, "ldur" },
+	{ AARCH64_INS_ALIAS_STUR, "stur" },
+	{ AARCH64_INS_ALIAS_PRFUM, "prfum" },
+	{ AARCH64_INS_ALIAS_LDTR, "ldtr" },
+	{ AARCH64_INS_ALIAS_STTR, "sttr" },
+	{ AARCH64_INS_ALIAS_LDP, "ldp" },
+	{ AARCH64_INS_ALIAS_STGP, "stgp" },
+	{ AARCH64_INS_ALIAS_LDNP, "ldnp" },
+	{ AARCH64_INS_ALIAS_STNP, "stnp" },
+	{ AARCH64_INS_ALIAS_STG, "stg" },
+	{ AARCH64_INS_ALIAS_MOV, "mov" },
+	{ AARCH64_INS_ALIAS_LD1, "ld1" },
+	{ AARCH64_INS_ALIAS_LD1R, "ld1r" },
+	{ AARCH64_INS_ALIAS_STADDLB, "staddlb" },
+	{ AARCH64_INS_ALIAS_STADDLH, "staddlh" },
+	{ AARCH64_INS_ALIAS_STADDL, "staddl" },
+	{ AARCH64_INS_ALIAS_STADDB, "staddb" },
+	{ AARCH64_INS_ALIAS_STADDH, "staddh" },
+	{ AARCH64_INS_ALIAS_STADD, "stadd" },
+	{ AARCH64_INS_ALIAS_PTRUE, "ptrue" },
+	{ AARCH64_INS_ALIAS_PTRUES, "ptrues" },
+	{ AARCH64_INS_ALIAS_CNTB, "cntb" },
+	{ AARCH64_INS_ALIAS_SQINCH, "sqinch" },
+	{ AARCH64_INS_ALIAS_INCB, "incb" },
+	{ AARCH64_INS_ALIAS_SQINCB, "sqincb" },
+	{ AARCH64_INS_ALIAS_UQINCB, "uqincb" },
+	{ AARCH64_INS_ALIAS_ORR, "orr" },
+	{ AARCH64_INS_ALIAS_DUPM, "dupm" },
+	{ AARCH64_INS_ALIAS_FMOV, "fmov" },
+	{ AARCH64_INS_ALIAS_EOR3, "eor3" },
+	{ AARCH64_INS_ALIAS_ST1B, "st1b" },
+	{ AARCH64_INS_ALIAS_ST2B, "st2b" },
+	{ AARCH64_INS_ALIAS_ST2Q, "st2q" },
+	{ AARCH64_INS_ALIAS_STNT1B, "stnt1b" },
+	{ AARCH64_INS_ALIAS_LD1B, "ld1b" },
+	{ AARCH64_INS_ALIAS_LDNT1B, "ldnt1b" },
+	{ AARCH64_INS_ALIAS_LD1RQB, "ld1rqb" },
+	{ AARCH64_INS_ALIAS_LD1RB, "ld1rb" },
+	{ AARCH64_INS_ALIAS_LDFF1B, "ldff1b" },
+	{ AARCH64_INS_ALIAS_LDNF1B, "ldnf1b" },
+	{ AARCH64_INS_ALIAS_LD2B, "ld2b" },
+	{ AARCH64_INS_ALIAS_LD1SB, "ld1sb" },
+	{ AARCH64_INS_ALIAS_PRFB, "prfb" },
+	{ AARCH64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
+	{ AARCH64_INS_ALIAS_LD1ROB, "ld1rob" },
+	{ AARCH64_INS_ALIAS_LD1Q, "ld1q" },
+	{ AARCH64_INS_ALIAS_ST1Q, "st1q" },
+	{ AARCH64_INS_ALIAS_LD1W, "ld1w" },
+	{ AARCH64_INS_ALIAS_PMOV, "pmov" },
+	{ AARCH64_INS_ALIAS_SMSTART, "smstart" },
+	{ AARCH64_INS_ALIAS_SMSTOP, "smstop" },
+	{ AARCH64_INS_ALIAS_ZERO, "zero" },
+	{ AARCH64_INS_ALIAS_MOVT, "movt" },
+	{ AARCH64_INS_ALIAS_NOP, "nop" },
+	{ AARCH64_INS_ALIAS_YIELD, "yield" },
+	{ AARCH64_INS_ALIAS_WFE, "wfe" },
+	{ AARCH64_INS_ALIAS_WFI, "wfi" },
+	{ AARCH64_INS_ALIAS_SEV, "sev" },
+	{ AARCH64_INS_ALIAS_SEVL, "sevl" },
+	{ AARCH64_INS_ALIAS_DGH, "dgh" },
+	{ AARCH64_INS_ALIAS_ESB, "esb" },
+	{ AARCH64_INS_ALIAS_CSDB, "csdb" },
+	{ AARCH64_INS_ALIAS_BTI, "bti" },
+	{ AARCH64_INS_ALIAS_PSB, "psb" },
+	{ AARCH64_INS_ALIAS_CHKFEAT, "chkfeat" },
+	{ AARCH64_INS_ALIAS_PACIAZ, "paciaz" },
+	{ AARCH64_INS_ALIAS_PACIBZ, "pacibz" },
+	{ AARCH64_INS_ALIAS_AUTIAZ, "autiaz" },
+	{ AARCH64_INS_ALIAS_AUTIBZ, "autibz" },
+	{ AARCH64_INS_ALIAS_PACIASP, "paciasp" },
+	{ AARCH64_INS_ALIAS_PACIBSP, "pacibsp" },
+	{ AARCH64_INS_ALIAS_AUTIASP, "autiasp" },
+	{ AARCH64_INS_ALIAS_AUTIBSP, "autibsp" },
+	{ AARCH64_INS_ALIAS_PACIA1716, "pacia1716" },
+	{ AARCH64_INS_ALIAS_PACIB1716, "pacib1716" },
+	{ AARCH64_INS_ALIAS_AUTIA1716, "autia1716" },
+	{ AARCH64_INS_ALIAS_AUTIB1716, "autib1716" },
+	{ AARCH64_INS_ALIAS_XPACLRI, "xpaclri" },
+	{ AARCH64_INS_ALIAS_LDRAB, "ldrab" },
+	{ AARCH64_INS_ALIAS_PACM, "pacm" },
+	{ AARCH64_INS_ALIAS_CLREX, "clrex" },
+	{ AARCH64_INS_ALIAS_ISB, "isb" },
+	{ AARCH64_INS_ALIAS_SSBB, "ssbb" },
+	{ AARCH64_INS_ALIAS_PSSBB, "pssbb" },
+	{ AARCH64_INS_ALIAS_DFB, "dfb" },
+	{ AARCH64_INS_ALIAS_SYS, "sys" },
+	{ AARCH64_INS_ALIAS_MOVN, "movn" },
+	{ AARCH64_INS_ALIAS_MOVZ, "movz" },
+	{ AARCH64_INS_ALIAS_NGC, "ngc" },
+	{ AARCH64_INS_ALIAS_NGCS, "ngcs" },
+	{ AARCH64_INS_ALIAS_SUB, "sub" },
+	{ AARCH64_INS_ALIAS_CMP, "cmp" },
+	{ AARCH64_INS_ALIAS_SUBS, "subs" },
+	{ AARCH64_INS_ALIAS_NEG, "neg" },
+	{ AARCH64_INS_ALIAS_NEGS, "negs" },
+	{ AARCH64_INS_ALIAS_MUL, "mul" },
+	{ AARCH64_INS_ALIAS_MNEG, "mneg" },
+	{ AARCH64_INS_ALIAS_SMULL, "smull" },
+	{ AARCH64_INS_ALIAS_SMNEGL, "smnegl" },
+	{ AARCH64_INS_ALIAS_UMULL, "umull" },
+	{ AARCH64_INS_ALIAS_UMNEGL, "umnegl" },
+	{ AARCH64_INS_ALIAS_STCLRLB, "stclrlb" },
+	{ AARCH64_INS_ALIAS_STCLRLH, "stclrlh" },
+	{ AARCH64_INS_ALIAS_STCLRL, "stclrl" },
+	{ AARCH64_INS_ALIAS_STCLRB, "stclrb" },
+	{ AARCH64_INS_ALIAS_STCLRH, "stclrh" },
+	{ AARCH64_INS_ALIAS_STCLR, "stclr" },
+	{ AARCH64_INS_ALIAS_STEORLB, "steorlb" },
+	{ AARCH64_INS_ALIAS_STEORLH, "steorlh" },
+	{ AARCH64_INS_ALIAS_STEORL, "steorl" },
+	{ AARCH64_INS_ALIAS_STEORB, "steorb" },
+	{ AARCH64_INS_ALIAS_STEORH, "steorh" },
+	{ AARCH64_INS_ALIAS_STEOR, "steor" },
+	{ AARCH64_INS_ALIAS_STSETLB, "stsetlb" },
+	{ AARCH64_INS_ALIAS_STSETLH, "stsetlh" },
+	{ AARCH64_INS_ALIAS_STSETL, "stsetl" },
+	{ AARCH64_INS_ALIAS_STSETB, "stsetb" },
+	{ AARCH64_INS_ALIAS_STSETH, "stseth" },
+	{ AARCH64_INS_ALIAS_STSET, "stset" },
+	{ AARCH64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
+	{ AARCH64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
+	{ AARCH64_INS_ALIAS_STSMAXL, "stsmaxl" },
+	{ AARCH64_INS_ALIAS_STSMAXB, "stsmaxb" },
+	{ AARCH64_INS_ALIAS_STSMAXH, "stsmaxh" },
+	{ AARCH64_INS_ALIAS_STSMAX, "stsmax" },
+	{ AARCH64_INS_ALIAS_STSMINLB, "stsminlb" },
+	{ AARCH64_INS_ALIAS_STSMINLH, "stsminlh" },
+	{ AARCH64_INS_ALIAS_STSMINL, "stsminl" },
+	{ AARCH64_INS_ALIAS_STSMINB, "stsminb" },
+	{ AARCH64_INS_ALIAS_STSMINH, "stsminh" },
+	{ AARCH64_INS_ALIAS_STSMIN, "stsmin" },
+	{ AARCH64_INS_ALIAS_STUMAXLB, "stumaxlb" },
+	{ AARCH64_INS_ALIAS_STUMAXLH, "stumaxlh" },
+	{ AARCH64_INS_ALIAS_STUMAXL, "stumaxl" },
+	{ AARCH64_INS_ALIAS_STUMAXB, "stumaxb" },
+	{ AARCH64_INS_ALIAS_STUMAXH, "stumaxh" },
+	{ AARCH64_INS_ALIAS_STUMAX, "stumax" },
+	{ AARCH64_INS_ALIAS_STUMINLB, "stuminlb" },
+	{ AARCH64_INS_ALIAS_STUMINLH, "stuminlh" },
+	{ AARCH64_INS_ALIAS_STUMINL, "stuminl" },
+	{ AARCH64_INS_ALIAS_STUMINB, "stuminb" },
+	{ AARCH64_INS_ALIAS_STUMINH, "stuminh" },
+	{ AARCH64_INS_ALIAS_STUMIN, "stumin" },
+	{ AARCH64_INS_ALIAS_IRG, "irg" },
+	{ AARCH64_INS_ALIAS_LDG, "ldg" },
+	{ AARCH64_INS_ALIAS_STZG, "stzg" },
+	{ AARCH64_INS_ALIAS_ST2G, "st2g" },
+	{ AARCH64_INS_ALIAS_STZ2G, "stz2g" },
+	{ AARCH64_INS_ALIAS_BICS, "bics" },
+	{ AARCH64_INS_ALIAS_BIC, "bic" },
+	{ AARCH64_INS_ALIAS_EON, "eon" },
+	{ AARCH64_INS_ALIAS_EOR, "eor" },
+	{ AARCH64_INS_ALIAS_ORN, "orn" },
+	{ AARCH64_INS_ALIAS_MVN, "mvn" },
+	{ AARCH64_INS_ALIAS_TST, "tst" },
+	{ AARCH64_INS_ALIAS_ROR, "ror" },
+	{ AARCH64_INS_ALIAS_ASR, "asr" },
+	{ AARCH64_INS_ALIAS_SXTB, "sxtb" },
+	{ AARCH64_INS_ALIAS_SXTH, "sxth" },
+	{ AARCH64_INS_ALIAS_SXTW, "sxtw" },
+	{ AARCH64_INS_ALIAS_LSR, "lsr" },
+	{ AARCH64_INS_ALIAS_UXTB, "uxtb" },
+	{ AARCH64_INS_ALIAS_UXTH, "uxth" },
+	{ AARCH64_INS_ALIAS_UXTW, "uxtw" },
+	{ AARCH64_INS_ALIAS_CSET, "cset" },
+	{ AARCH64_INS_ALIAS_CSETM, "csetm" },
+	{ AARCH64_INS_ALIAS_CINC, "cinc" },
+	{ AARCH64_INS_ALIAS_CINV, "cinv" },
+	{ AARCH64_INS_ALIAS_CNEG, "cneg" },
+	{ AARCH64_INS_ALIAS_RET, "ret" },
+	{ AARCH64_INS_ALIAS_DCPS1, "dcps1" },
+	{ AARCH64_INS_ALIAS_DCPS2, "dcps2" },
+	{ AARCH64_INS_ALIAS_DCPS3, "dcps3" },
+	{ AARCH64_INS_ALIAS_LDPSW, "ldpsw" },
+	{ AARCH64_INS_ALIAS_LDRSH, "ldrsh" },
+	{ AARCH64_INS_ALIAS_LDRSB, "ldrsb" },
+	{ AARCH64_INS_ALIAS_LDRSW, "ldrsw" },
+	{ AARCH64_INS_ALIAS_LDURH, "ldurh" },
+	{ AARCH64_INS_ALIAS_LDURB, "ldurb" },
+	{ AARCH64_INS_ALIAS_LDURSH, "ldursh" },
+	{ AARCH64_INS_ALIAS_LDURSB, "ldursb" },
+	{ AARCH64_INS_ALIAS_LDURSW, "ldursw" },
+	{ AARCH64_INS_ALIAS_LDTRH, "ldtrh" },
+	{ AARCH64_INS_ALIAS_LDTRB, "ldtrb" },
+	{ AARCH64_INS_ALIAS_LDTRSH, "ldtrsh" },
+	{ AARCH64_INS_ALIAS_LDTRSB, "ldtrsb" },
+	{ AARCH64_INS_ALIAS_LDTRSW, "ldtrsw" },
+	{ AARCH64_INS_ALIAS_STP, "stp" },
+	{ AARCH64_INS_ALIAS_STURH, "sturh" },
+	{ AARCH64_INS_ALIAS_STURB, "sturb" },
+	{ AARCH64_INS_ALIAS_STLURH, "stlurh" },
+	{ AARCH64_INS_ALIAS_LDAPURSB, "ldapursb" },
+	{ AARCH64_INS_ALIAS_LDAPURH, "ldapurh" },
+	{ AARCH64_INS_ALIAS_LDAPURSH, "ldapursh" },
+	{ AARCH64_INS_ALIAS_LDAPURSW, "ldapursw" },
+	{ AARCH64_INS_ALIAS_STTRH, "sttrh" },
+	{ AARCH64_INS_ALIAS_STTRB, "sttrb" },
+	{ AARCH64_INS_ALIAS_BIC_4H, "bic_4h" },
+	{ AARCH64_INS_ALIAS_BIC_8H, "bic_8h" },
+	{ AARCH64_INS_ALIAS_BIC_2S, "bic_2s" },
+	{ AARCH64_INS_ALIAS_BIC_4S, "bic_4s" },
+	{ AARCH64_INS_ALIAS_ORR_4H, "orr_4h" },
+	{ AARCH64_INS_ALIAS_ORR_8H, "orr_8h" },
+	{ AARCH64_INS_ALIAS_ORR_2S, "orr_2s" },
+	{ AARCH64_INS_ALIAS_ORR_4S, "orr_4s" },
+	{ AARCH64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
+	{ AARCH64_INS_ALIAS_SXTL, "sxtl" },
+	{ AARCH64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
+	{ AARCH64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
+	{ AARCH64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
+	{ AARCH64_INS_ALIAS_SXTL2, "sxtl2" },
+	{ AARCH64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
+	{ AARCH64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
+	{ AARCH64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
+	{ AARCH64_INS_ALIAS_UXTL, "uxtl" },
+	{ AARCH64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
+	{ AARCH64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
+	{ AARCH64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
+	{ AARCH64_INS_ALIAS_UXTL2, "uxtl2" },
+	{ AARCH64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
+	{ AARCH64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
+	{ AARCH64_INS_ALIAS_LD2, "ld2" },
+	{ AARCH64_INS_ALIAS_LD3, "ld3" },
+	{ AARCH64_INS_ALIAS_LD4, "ld4" },
+	{ AARCH64_INS_ALIAS_ST1, "st1" },
+	{ AARCH64_INS_ALIAS_ST2, "st2" },
+	{ AARCH64_INS_ALIAS_ST3, "st3" },
+	{ AARCH64_INS_ALIAS_ST4, "st4" },
+	{ AARCH64_INS_ALIAS_LD2R, "ld2r" },
+	{ AARCH64_INS_ALIAS_LD3R, "ld3r" },
+	{ AARCH64_INS_ALIAS_LD4R, "ld4r" },
+	{ AARCH64_INS_ALIAS_CLRBHB, "clrbhb" },
+	{ AARCH64_INS_ALIAS_STILP, "stilp" },
+	{ AARCH64_INS_ALIAS_STL1, "stl1" },
+	{ AARCH64_INS_ALIAS_SYSP, "sysp" },
+	{ AARCH64_INS_ALIAS_LD1SW, "ld1sw" },
+	{ AARCH64_INS_ALIAS_LD1H, "ld1h" },
+	{ AARCH64_INS_ALIAS_LD1SH, "ld1sh" },
+	{ AARCH64_INS_ALIAS_LD1D, "ld1d" },
+	{ AARCH64_INS_ALIAS_LD1RSW, "ld1rsw" },
+	{ AARCH64_INS_ALIAS_LD1RH, "ld1rh" },
+	{ AARCH64_INS_ALIAS_LD1RSH, "ld1rsh" },
+	{ AARCH64_INS_ALIAS_LD1RW, "ld1rw" },
+	{ AARCH64_INS_ALIAS_LD1RSB, "ld1rsb" },
+	{ AARCH64_INS_ALIAS_LD1RD, "ld1rd" },
+	{ AARCH64_INS_ALIAS_LD1RQH, "ld1rqh" },
+	{ AARCH64_INS_ALIAS_LD1RQW, "ld1rqw" },
+	{ AARCH64_INS_ALIAS_LD1RQD, "ld1rqd" },
+	{ AARCH64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
+	{ AARCH64_INS_ALIAS_LDNF1H, "ldnf1h" },
+	{ AARCH64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
+	{ AARCH64_INS_ALIAS_LDNF1W, "ldnf1w" },
+	{ AARCH64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
+	{ AARCH64_INS_ALIAS_LDNF1D, "ldnf1d" },
+	{ AARCH64_INS_ALIAS_LDFF1SW, "ldff1sw" },
+	{ AARCH64_INS_ALIAS_LDFF1H, "ldff1h" },
+	{ AARCH64_INS_ALIAS_LDFF1SH, "ldff1sh" },
+	{ AARCH64_INS_ALIAS_LDFF1W, "ldff1w" },
+	{ AARCH64_INS_ALIAS_LDFF1SB, "ldff1sb" },
+	{ AARCH64_INS_ALIAS_LDFF1D, "ldff1d" },
+	{ AARCH64_INS_ALIAS_LD3B, "ld3b" },
+	{ AARCH64_INS_ALIAS_LD4B, "ld4b" },
+	{ AARCH64_INS_ALIAS_LD2H, "ld2h" },
+	{ AARCH64_INS_ALIAS_LD3H, "ld3h" },
+	{ AARCH64_INS_ALIAS_LD4H, "ld4h" },
+	{ AARCH64_INS_ALIAS_LD2W, "ld2w" },
+	{ AARCH64_INS_ALIAS_LD3W, "ld3w" },
+	{ AARCH64_INS_ALIAS_LD4W, "ld4w" },
+	{ AARCH64_INS_ALIAS_LD2D, "ld2d" },
+	{ AARCH64_INS_ALIAS_LD3D, "ld3d" },
+	{ AARCH64_INS_ALIAS_LD4D, "ld4d" },
+	{ AARCH64_INS_ALIAS_LD2Q, "ld2q" },
+	{ AARCH64_INS_ALIAS_LD3Q, "ld3q" },
+	{ AARCH64_INS_ALIAS_LD4Q, "ld4q" },
+	{ AARCH64_INS_ALIAS_LDNT1H, "ldnt1h" },
+	{ AARCH64_INS_ALIAS_LDNT1W, "ldnt1w" },
+	{ AARCH64_INS_ALIAS_LDNT1D, "ldnt1d" },
+	{ AARCH64_INS_ALIAS_ST1H, "st1h" },
+	{ AARCH64_INS_ALIAS_ST1W, "st1w" },
+	{ AARCH64_INS_ALIAS_ST1D, "st1d" },
+	{ AARCH64_INS_ALIAS_ST3B, "st3b" },
+	{ AARCH64_INS_ALIAS_ST4B, "st4b" },
+	{ AARCH64_INS_ALIAS_ST2H, "st2h" },
+	{ AARCH64_INS_ALIAS_ST3H, "st3h" },
+	{ AARCH64_INS_ALIAS_ST4H, "st4h" },
+	{ AARCH64_INS_ALIAS_ST2W, "st2w" },
+	{ AARCH64_INS_ALIAS_ST3W, "st3w" },
+	{ AARCH64_INS_ALIAS_ST4W, "st4w" },
+	{ AARCH64_INS_ALIAS_ST2D, "st2d" },
+	{ AARCH64_INS_ALIAS_ST3D, "st3d" },
+	{ AARCH64_INS_ALIAS_ST4D, "st4d" },
+	{ AARCH64_INS_ALIAS_ST3Q, "st3q" },
+	{ AARCH64_INS_ALIAS_ST4Q, "st4q" },
+	{ AARCH64_INS_ALIAS_STNT1H, "stnt1h" },
+	{ AARCH64_INS_ALIAS_STNT1W, "stnt1w" },
+	{ AARCH64_INS_ALIAS_STNT1D, "stnt1d" },
+	{ AARCH64_INS_ALIAS_PRFH, "prfh" },
+	{ AARCH64_INS_ALIAS_PRFW, "prfw" },
+	{ AARCH64_INS_ALIAS_PRFD, "prfd" },
+	{ AARCH64_INS_ALIAS_CNTH, "cnth" },
+	{ AARCH64_INS_ALIAS_CNTW, "cntw" },
+	{ AARCH64_INS_ALIAS_CNTD, "cntd" },
+	{ AARCH64_INS_ALIAS_DECB, "decb" },
+	{ AARCH64_INS_ALIAS_INCH, "inch" },
+	{ AARCH64_INS_ALIAS_DECH, "dech" },
+	{ AARCH64_INS_ALIAS_INCW, "incw" },
+	{ AARCH64_INS_ALIAS_DECW, "decw" },
+	{ AARCH64_INS_ALIAS_INCD, "incd" },
+	{ AARCH64_INS_ALIAS_DECD, "decd" },
+	{ AARCH64_INS_ALIAS_SQDECB, "sqdecb" },
+	{ AARCH64_INS_ALIAS_UQDECB, "uqdecb" },
+	{ AARCH64_INS_ALIAS_UQINCH, "uqinch" },
+	{ AARCH64_INS_ALIAS_SQDECH, "sqdech" },
+	{ AARCH64_INS_ALIAS_UQDECH, "uqdech" },
+	{ AARCH64_INS_ALIAS_SQINCW, "sqincw" },
+	{ AARCH64_INS_ALIAS_UQINCW, "uqincw" },
+	{ AARCH64_INS_ALIAS_SQDECW, "sqdecw" },
+	{ AARCH64_INS_ALIAS_UQDECW, "uqdecw" },
+	{ AARCH64_INS_ALIAS_SQINCD, "sqincd" },
+	{ AARCH64_INS_ALIAS_UQINCD, "uqincd" },
+	{ AARCH64_INS_ALIAS_SQDECD, "sqdecd" },
+	{ AARCH64_INS_ALIAS_UQDECD, "uqdecd" },
+	{ AARCH64_INS_ALIAS_MOVS, "movs" },
+	{ AARCH64_INS_ALIAS_NOT, "not" },
+	{ AARCH64_INS_ALIAS_NOTS, "nots" },
+	{ AARCH64_INS_ALIAS_LD1ROH, "ld1roh" },
+	{ AARCH64_INS_ALIAS_LD1ROW, "ld1row" },
+	{ AARCH64_INS_ALIAS_LD1ROD, "ld1rod" },
+	{ AARCH64_INS_ALIAS_BCAX, "bcax" },
+	{ AARCH64_INS_ALIAS_BSL, "bsl" },
+	{ AARCH64_INS_ALIAS_BSL1N, "bsl1n" },
+	{ AARCH64_INS_ALIAS_BSL2N, "bsl2n" },
+	{ AARCH64_INS_ALIAS_NBSL, "nbsl" },
+	{ AARCH64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
+	{ AARCH64_INS_ALIAS_LDNT1SW, "ldnt1sw" },

external/capstone/arch/AArch64/AArch64GenCSFeatureName.inc

@@ -0,0 +1,139 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ AARCH64_FEATURE_HASV8_0A, "HasV8_0a" },
+{ AARCH64_FEATURE_HASV8_1A, "HasV8_1a" },
+{ AARCH64_FEATURE_HASV8_2A, "HasV8_2a" },
+{ AARCH64_FEATURE_HASV8_3A, "HasV8_3a" },
+{ AARCH64_FEATURE_HASV8_4A, "HasV8_4a" },
+{ AARCH64_FEATURE_HASV8_5A, "HasV8_5a" },
+{ AARCH64_FEATURE_HASV8_6A, "HasV8_6a" },
+{ AARCH64_FEATURE_HASV8_7A, "HasV8_7a" },
+{ AARCH64_FEATURE_HASV8_8A, "HasV8_8a" },
+{ AARCH64_FEATURE_HASV8_9A, "HasV8_9a" },
+{ AARCH64_FEATURE_HASV9_0A, "HasV9_0a" },
+{ AARCH64_FEATURE_HASV9_1A, "HasV9_1a" },
+{ AARCH64_FEATURE_HASV9_2A, "HasV9_2a" },
+{ AARCH64_FEATURE_HASV9_3A, "HasV9_3a" },
+{ AARCH64_FEATURE_HASV9_4A, "HasV9_4a" },
+{ AARCH64_FEATURE_HASV8_0R, "HasV8_0r" },
+{ AARCH64_FEATURE_HASEL2VMSA, "HasEL2VMSA" },
+{ AARCH64_FEATURE_HASEL3, "HasEL3" },
+{ AARCH64_FEATURE_HASVH, "HasVH" },
+{ AARCH64_FEATURE_HASLOR, "HasLOR" },
+{ AARCH64_FEATURE_HASPAUTH, "HasPAuth" },
+{ AARCH64_FEATURE_HASPAUTHLR, "HasPAuthLR" },
+{ AARCH64_FEATURE_HASJS, "HasJS" },
+{ AARCH64_FEATURE_HASCCIDX, "HasCCIDX" },
+{ AARCH64_FEATURE_HASCOMPLXNUM, "HasComplxNum" },
+{ AARCH64_FEATURE_HASNV, "HasNV" },
+{ AARCH64_FEATURE_HASMPAM, "HasMPAM" },
+{ AARCH64_FEATURE_HASDIT, "HasDIT" },
+{ AARCH64_FEATURE_HASTRACEV8_4, "HasTRACEV8_4" },
+{ AARCH64_FEATURE_HASAM, "HasAM" },
+{ AARCH64_FEATURE_HASSEL2, "HasSEL2" },
+{ AARCH64_FEATURE_HASTLB_RMI, "HasTLB_RMI" },
+{ AARCH64_FEATURE_HASFLAGM, "HasFlagM" },
+{ AARCH64_FEATURE_HASRCPC_IMMO, "HasRCPC_IMMO" },
+{ AARCH64_FEATURE_HASFPARMV8, "HasFPARMv8" },
+{ AARCH64_FEATURE_HASNEON, "HasNEON" },
+{ AARCH64_FEATURE_HASSM4, "HasSM4" },
+{ AARCH64_FEATURE_HASSHA3, "HasSHA3" },
+{ AARCH64_FEATURE_HASSHA2, "HasSHA2" },
+{ AARCH64_FEATURE_HASAES, "HasAES" },
+{ AARCH64_FEATURE_HASDOTPROD, "HasDotProd" },
+{ AARCH64_FEATURE_HASCRC, "HasCRC" },
+{ AARCH64_FEATURE_HASCSSC, "HasCSSC" },
+{ AARCH64_FEATURE_HASLSE, "HasLSE" },
+{ AARCH64_FEATURE_HASRAS, "HasRAS" },
+{ AARCH64_FEATURE_HASRDM, "HasRDM" },
+{ AARCH64_FEATURE_HASFULLFP16, "HasFullFP16" },
+{ AARCH64_FEATURE_HASFP16FML, "HasFP16FML" },
+{ AARCH64_FEATURE_HASSPE, "HasSPE" },
+{ AARCH64_FEATURE_HASFUSEAES, "HasFuseAES" },
+{ AARCH64_FEATURE_HASSVE, "HasSVE" },
+{ AARCH64_FEATURE_HASSVE2, "HasSVE2" },
+{ AARCH64_FEATURE_HASSVE2P1, "HasSVE2p1" },
+{ AARCH64_FEATURE_HASSVE2AES, "HasSVE2AES" },
+{ AARCH64_FEATURE_HASSVE2SM4, "HasSVE2SM4" },
+{ AARCH64_FEATURE_HASSVE2SHA3, "HasSVE2SHA3" },
+{ AARCH64_FEATURE_HASSVE2BITPERM, "HasSVE2BitPerm" },
+{ AARCH64_FEATURE_HASB16B16, "HasB16B16" },
+{ AARCH64_FEATURE_HASSME, "HasSME" },
+{ AARCH64_FEATURE_HASSMEF64F64, "HasSMEF64F64" },
+{ AARCH64_FEATURE_HASSMEF16F16, "HasSMEF16F16" },
+{ AARCH64_FEATURE_HASSMEFA64, "HasSMEFA64" },
+{ AARCH64_FEATURE_HASSMEI16I64, "HasSMEI16I64" },
+{ AARCH64_FEATURE_HASSME2, "HasSME2" },
+{ AARCH64_FEATURE_HASSME2P1, "HasSME2p1" },
+{ AARCH64_FEATURE_HASFPMR, "HasFPMR" },
+{ AARCH64_FEATURE_HASFP8, "HasFP8" },
+{ AARCH64_FEATURE_HASFAMINMAX, "HasFAMINMAX" },
+{ AARCH64_FEATURE_HASFP8FMA, "HasFP8FMA" },
+{ AARCH64_FEATURE_HASSSVE_FP8FMA, "HasSSVE_FP8FMA" },
+{ AARCH64_FEATURE_HASFP8DOT2, "HasFP8DOT2" },
+{ AARCH64_FEATURE_HASSSVE_FP8DOT2, "HasSSVE_FP8DOT2" },
+{ AARCH64_FEATURE_HASFP8DOT4, "HasFP8DOT4" },
+{ AARCH64_FEATURE_HASSSVE_FP8DOT4, "HasSSVE_FP8DOT4" },
+{ AARCH64_FEATURE_HASLUT, "HasLUT" },
+{ AARCH64_FEATURE_HASSME_LUTV2, "HasSME_LUTv2" },
+{ AARCH64_FEATURE_HASSMEF8F16, "HasSMEF8F16" },
+{ AARCH64_FEATURE_HASSMEF8F32, "HasSMEF8F32" },
+{ AARCH64_FEATURE_HASSVEORSME, "HasSVEorSME" },
+{ AARCH64_FEATURE_HASSVE2ORSME, "HasSVE2orSME" },
+{ AARCH64_FEATURE_HASSVE2ORSME2, "HasSVE2orSME2" },
+{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME, "HasSVE2p1_or_HasSME" },
+{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2, "HasSVE2p1_or_HasSME2" },
+{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2P1, "HasSVE2p1_or_HasSME2p1" },
+{ AARCH64_FEATURE_HASNEONORSME, "HasNEONorSME" },
+{ AARCH64_FEATURE_HASRCPC, "HasRCPC" },
+{ AARCH64_FEATURE_HASALTNZCV, "HasAltNZCV" },
+{ AARCH64_FEATURE_HASFRINT3264, "HasFRInt3264" },
+{ AARCH64_FEATURE_HASSB, "HasSB" },
+{ AARCH64_FEATURE_HASPREDRES, "HasPredRes" },
+{ AARCH64_FEATURE_HASCCDP, "HasCCDP" },
+{ AARCH64_FEATURE_HASBTI, "HasBTI" },
+{ AARCH64_FEATURE_HASMTE, "HasMTE" },
+{ AARCH64_FEATURE_HASTME, "HasTME" },
+{ AARCH64_FEATURE_HASETE, "HasETE" },
+{ AARCH64_FEATURE_HASTRBE, "HasTRBE" },
+{ AARCH64_FEATURE_HASBF16, "HasBF16" },
+{ AARCH64_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
+{ AARCH64_FEATURE_HASMATMULFP32, "HasMatMulFP32" },
+{ AARCH64_FEATURE_HASMATMULFP64, "HasMatMulFP64" },
+{ AARCH64_FEATURE_HASXS, "HasXS" },
+{ AARCH64_FEATURE_HASWFXT, "HasWFxT" },
+{ AARCH64_FEATURE_HASLS64, "HasLS64" },
+{ AARCH64_FEATURE_HASBRBE, "HasBRBE" },
+{ AARCH64_FEATURE_HASSPE_EEF, "HasSPE_EEF" },
+{ AARCH64_FEATURE_HASHBC, "HasHBC" },
+{ AARCH64_FEATURE_HASMOPS, "HasMOPS" },
+{ AARCH64_FEATURE_HASCLRBHB, "HasCLRBHB" },
+{ AARCH64_FEATURE_HASSPECRES2, "HasSPECRES2" },
+{ AARCH64_FEATURE_HASITE, "HasITE" },
+{ AARCH64_FEATURE_HASTHE, "HasTHE" },
+{ AARCH64_FEATURE_HASRCPC3, "HasRCPC3" },
+{ AARCH64_FEATURE_HASLSE128, "HasLSE128" },
+{ AARCH64_FEATURE_HASD128, "HasD128" },
+{ AARCH64_FEATURE_HASCHK, "HasCHK" },
+{ AARCH64_FEATURE_HASGCS, "HasGCS" },
+{ AARCH64_FEATURE_HASCPA, "HasCPA" },
+{ AARCH64_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
+{ AARCH64_FEATURE_HASAMX, "HasAMX" },
+{ AARCH64_FEATURE_HASMUL53, "HasMUL53" },
+{ AARCH64_FEATURE_HASAPPLESYS, "HasAppleSys" },
+{ AARCH64_FEATURE_HASCCPP, "HasCCPP" },
+{ AARCH64_FEATURE_HASPAN, "HasPAN" },
+{ AARCH64_FEATURE_HASPSUAO, "HasPsUAO" },
+{ AARCH64_FEATURE_HASPAN_RWV, "HasPAN_RWV" },
+{ AARCH64_FEATURE_HASCONTEXTIDREL2, "HasCONTEXTIDREL2" },

external/capstone/arch/AArch64/AArch64GenCSOpGroup.inc

@@ -0,0 +1,181 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  AArch64_OP_GROUP_AMNoIndex = 0,
+  AArch64_OP_GROUP_AdrLabel = 1,
+  AArch64_OP_GROUP_AdrpLabel = 2,
+  AArch64_OP_GROUP_BTIHintOp = 3,
+  AArch64_OP_GROUP_ImplicitlyTypedVectorList = 4,
+  AArch64_OP_GROUP_InverseCondCode = 5,
+  AArch64_OP_GROUP_LogicalImm_int16_t = 6,
+  AArch64_OP_GROUP_LogicalImm_int8_t = 7,
+  AArch64_OP_GROUP_MatrixIndex_0 = 8,
+  AArch64_OP_GROUP_MatrixIndex_1 = 9,
+  AArch64_OP_GROUP_MatrixIndex_8 = 10,
+  AArch64_OP_GROUP_PSBHintOp = 11,
+  AArch64_OP_GROUP_PrefetchOp_1 = 12,
+  AArch64_OP_GROUP_SVELogicalImm_int16_t = 13,
+  AArch64_OP_GROUP_SVELogicalImm_int32_t = 14,
+  AArch64_OP_GROUP_SVELogicalImm_int64_t = 15,
+  AArch64_OP_GROUP_SVERegOp_0 = 16,
+  AArch64_OP_GROUP_VectorIndex_8 = 17,
+  AArch64_OP_GROUP_ZPRasFPR_128 = 18,
+  AArch64_OP_GROUP_Operand = 19,
+  AArch64_OP_GROUP_SVERegOp_b = 20,
+  AArch64_OP_GROUP_SVERegOp_d = 21,
+  AArch64_OP_GROUP_SVERegOp_h = 22,
+  AArch64_OP_GROUP_SVERegOp_s = 23,
+  AArch64_OP_GROUP_TypedVectorList_0_d = 24,
+  AArch64_OP_GROUP_TypedVectorList_0_s = 25,
+  AArch64_OP_GROUP_VRegOperand = 26,
+  AArch64_OP_GROUP_TypedVectorList_0_h = 27,
+  AArch64_OP_GROUP_VectorIndex_1 = 28,
+  AArch64_OP_GROUP_ImmRangeScale_2_1 = 29,
+  AArch64_OP_GROUP_AlignedLabel = 30,
+  AArch64_OP_GROUP_CondCode = 31,
+  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 32,
+  AArch64_OP_GROUP_TypedVectorList_0_b = 33,
+  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 34,
+  AArch64_OP_GROUP_ImmRangeScale_4_3 = 35,
+  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 36,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 37,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 38,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 39,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 40,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 41,
+  AArch64_OP_GROUP_ImmScale_8 = 42,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 43,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 44,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 45,
+  AArch64_OP_GROUP_ImmScale_2 = 46,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 47,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 48,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 49,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 50,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 51,
+  AArch64_OP_GROUP_ImmScale_4 = 52,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 53,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 54,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 55,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 56,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 57,
+  AArch64_OP_GROUP_PredicateAsCounter_0 = 58,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 59,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 60,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 61,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 62,
+  AArch64_OP_GROUP_SVCROp = 63,
+  AArch64_OP_GROUP_ImmScale_16 = 64,
+  AArch64_OP_GROUP_MatrixTile = 65,
+  AArch64_OP_GROUP_Shifter = 66,
+  AArch64_OP_GROUP_AddSubImm = 67,
+  AArch64_OP_GROUP_ShiftedRegister = 68,
+  AArch64_OP_GROUP_ExtendedRegister = 69,
+  AArch64_OP_GROUP_ArithExtend = 70,
+  AArch64_OP_GROUP_Matrix_64 = 71,
+  AArch64_OP_GROUP_Matrix_32 = 72,
+  AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 73,
+  AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 74,
+  AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 75,
+  AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 76,
+  AArch64_OP_GROUP_AdrAdrpLabel = 77,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 78,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 79,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 80,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 81,
+  AArch64_OP_GROUP_LogicalImm_int32_t = 82,
+  AArch64_OP_GROUP_LogicalImm_int64_t = 83,
+  AArch64_OP_GROUP_ZPRasFPR_8 = 84,
+  AArch64_OP_GROUP_ZPRasFPR_64 = 85,
+  AArch64_OP_GROUP_ZPRasFPR_16 = 86,
+  AArch64_OP_GROUP_ZPRasFPR_32 = 87,
+  AArch64_OP_GROUP_Matrix_16 = 88,
+  AArch64_OP_GROUP_Imm = 89,
+  AArch64_OP_GROUP_ImmHex = 90,
+  AArch64_OP_GROUP_ComplexRotationOp_180_90 = 91,
+  AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 92,
+  AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 93,
+  AArch64_OP_GROUP_ComplexRotationOp_90_0 = 94,
+  AArch64_OP_GROUP_SVEPattern = 95,
+  AArch64_OP_GROUP_PredicateAsCounter_8 = 96,
+  AArch64_OP_GROUP_SVEVecLenSpecifier = 97,
+  AArch64_OP_GROUP_PredicateAsCounter_64 = 98,
+  AArch64_OP_GROUP_PredicateAsCounter_16 = 99,
+  AArch64_OP_GROUP_PredicateAsCounter_32 = 100,
+  AArch64_OP_GROUP_Imm8OptLsl_int8_t = 101,
+  AArch64_OP_GROUP_Imm8OptLsl_int64_t = 102,
+  AArch64_OP_GROUP_Imm8OptLsl_int16_t = 103,
+  AArch64_OP_GROUP_Imm8OptLsl_int32_t = 104,
+  AArch64_OP_GROUP_BarrierOption = 105,
+  AArch64_OP_GROUP_BarriernXSOption = 106,
+  AArch64_OP_GROUP_SVERegOp_q = 107,
+  AArch64_OP_GROUP_MatrixTileVector_0 = 108,
+  AArch64_OP_GROUP_MatrixTileVector_1 = 109,
+  AArch64_OP_GROUP_FPImmOperand = 110,
+  AArch64_OP_GROUP_TypedVectorList_0_q = 111,
+  AArch64_OP_GROUP_SImm_8 = 112,
+  AArch64_OP_GROUP_SImm_16 = 113,
+  AArch64_OP_GROUP_TypedVectorList_16_b = 114,
+  AArch64_OP_GROUP_PostIncOperand_64 = 115,
+  AArch64_OP_GROUP_TypedVectorList_1_d = 116,
+  AArch64_OP_GROUP_PostIncOperand_32 = 117,
+  AArch64_OP_GROUP_TypedVectorList_2_d = 118,
+  AArch64_OP_GROUP_TypedVectorList_2_s = 119,
+  AArch64_OP_GROUP_TypedVectorList_4_h = 120,
+  AArch64_OP_GROUP_TypedVectorList_4_s = 121,
+  AArch64_OP_GROUP_TypedVectorList_8_b = 122,
+  AArch64_OP_GROUP_TypedVectorList_8_h = 123,
+  AArch64_OP_GROUP_PostIncOperand_16 = 124,
+  AArch64_OP_GROUP_PostIncOperand_8 = 125,
+  AArch64_OP_GROUP_ImmScale_32 = 126,
+  AArch64_OP_GROUP_PostIncOperand_1 = 127,
+  AArch64_OP_GROUP_PostIncOperand_4 = 128,
+  AArch64_OP_GROUP_PostIncOperand_2 = 129,
+  AArch64_OP_GROUP_PostIncOperand_48 = 130,
+  AArch64_OP_GROUP_PostIncOperand_24 = 131,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 132,
+  AArch64_OP_GROUP_ImmScale_3 = 133,
+  AArch64_OP_GROUP_PostIncOperand_3 = 134,
+  AArch64_OP_GROUP_PostIncOperand_12 = 135,
+  AArch64_OP_GROUP_PostIncOperand_6 = 136,
+  AArch64_OP_GROUP_GPR64x8 = 137,
+  AArch64_OP_GROUP_MemExtend_w_8 = 138,
+  AArch64_OP_GROUP_MemExtend_x_8 = 139,
+  AArch64_OP_GROUP_UImm12Offset_1 = 140,
+  AArch64_OP_GROUP_MemExtend_w_64 = 141,
+  AArch64_OP_GROUP_MemExtend_x_64 = 142,
+  AArch64_OP_GROUP_UImm12Offset_8 = 143,
+  AArch64_OP_GROUP_MemExtend_w_16 = 144,
+  AArch64_OP_GROUP_MemExtend_x_16 = 145,
+  AArch64_OP_GROUP_UImm12Offset_2 = 146,
+  AArch64_OP_GROUP_MemExtend_w_128 = 147,
+  AArch64_OP_GROUP_MemExtend_x_128 = 148,
+  AArch64_OP_GROUP_UImm12Offset_16 = 149,
+  AArch64_OP_GROUP_MemExtend_w_32 = 150,
+  AArch64_OP_GROUP_MemExtend_x_32 = 151,
+  AArch64_OP_GROUP_UImm12Offset_4 = 152,
+  AArch64_OP_GROUP_Matrix_0 = 153,
+  AArch64_OP_GROUP_TypedVectorList_0_0 = 154,
+  AArch64_OP_GROUP_SIMDType10Operand = 155,
+  AArch64_OP_GROUP_MRSSystemRegister = 156,
+  AArch64_OP_GROUP_MSRSystemRegister = 157,
+  AArch64_OP_GROUP_SystemPStateField = 158,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 159,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160,
+  AArch64_OP_GROUP_PrefetchOp_0 = 161,
+  AArch64_OP_GROUP_RPRFMOperand = 162,
+  AArch64_OP_GROUP_AppleSysBarrierOption = 163,
+  AArch64_OP_GROUP_GPR64as32 = 164,
+  AArch64_OP_GROUP_SysCROperand = 165,
+  AArch64_OP_GROUP_SyspXzrPair = 166,
+  AArch64_OP_GROUP_MatrixTileList = 167,

external/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc

@@ -0,0 +1,301 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  AArch64_FeatureAES = 0,
+  AArch64_FeatureALULSLFast = 1,
+  AArch64_FeatureAM = 2,
+  AArch64_FeatureAMVS = 3,
+  AArch64_FeatureAMX = 4,
+  AArch64_FeatureAddrLSLFast = 5,
+  AArch64_FeatureAggressiveFMA = 6,
+  AArch64_FeatureAll = 7,
+  AArch64_FeatureAltFPCmp = 8,
+  AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 9,
+  AArch64_FeatureAppleA7SysReg = 10,
+  AArch64_FeatureAppleSys = 11,
+  AArch64_FeatureArithmeticBccFusion = 12,
+  AArch64_FeatureArithmeticCbzFusion = 13,
+  AArch64_FeatureAscendStoreAddress = 14,
+  AArch64_FeatureB16B16 = 15,
+  AArch64_FeatureBF16 = 16,
+  AArch64_FeatureBRBE = 17,
+  AArch64_FeatureBalanceFPOps = 18,
+  AArch64_FeatureBranchTargetId = 19,
+  AArch64_FeatureCCIDX = 20,
+  AArch64_FeatureCCPP = 21,
+  AArch64_FeatureCHK = 22,
+  AArch64_FeatureCLRBHB = 23,
+  AArch64_FeatureCONTEXTIDREL2 = 24,
+  AArch64_FeatureCPA = 25,
+  AArch64_FeatureCRC = 26,
+  AArch64_FeatureCSSC = 27,
+  AArch64_FeatureCacheDeepPersist = 28,
+  AArch64_FeatureCallSavedX8 = 29,
+  AArch64_FeatureCallSavedX9 = 30,
+  AArch64_FeatureCallSavedX10 = 31,
+  AArch64_FeatureCallSavedX11 = 32,
+  AArch64_FeatureCallSavedX12 = 33,
+  AArch64_FeatureCallSavedX13 = 34,
+  AArch64_FeatureCallSavedX14 = 35,
+  AArch64_FeatureCallSavedX15 = 36,
+  AArch64_FeatureCallSavedX18 = 37,
+  AArch64_FeatureCmpBccFusion = 38,
+  AArch64_FeatureComplxNum = 39,
+  AArch64_FeatureCrypto = 40,
+  AArch64_FeatureD128 = 41,
+  AArch64_FeatureDIT = 42,
+  AArch64_FeatureDisableLatencySchedHeuristic = 43,
+  AArch64_FeatureDisableLdp = 44,
+  AArch64_FeatureDisableStp = 45,
+  AArch64_FeatureDotProd = 46,
+  AArch64_FeatureEL2VMSA = 47,
+  AArch64_FeatureEL3 = 48,
+  AArch64_FeatureETE = 49,
+  AArch64_FeatureEnableSelectOptimize = 50,
+  AArch64_FeatureEnhancedCounterVirtualization = 51,
+  AArch64_FeatureExperimentalZeroingPseudos = 52,
+  AArch64_FeatureExynosCheapAsMoveHandling = 53,
+  AArch64_FeatureFAMINMAX = 54,
+  AArch64_FeatureFMV = 55,
+  AArch64_FeatureFP8 = 56,
+  AArch64_FeatureFP8DOT2 = 57,
+  AArch64_FeatureFP8DOT4 = 58,
+  AArch64_FeatureFP8FMA = 59,
+  AArch64_FeatureFP16FML = 60,
+  AArch64_FeatureFPARMv8 = 61,
+  AArch64_FeatureFPMR = 62,
+  AArch64_FeatureFRInt3264 = 63,
+  AArch64_FeatureFineGrainedTraps = 64,
+  AArch64_FeatureFixCortexA53_835769 = 65,
+  AArch64_FeatureFlagM = 66,
+  AArch64_FeatureForce32BitJumpTables = 67,
+  AArch64_FeatureFullFP16 = 68,
+  AArch64_FeatureFuseAES = 69,
+  AArch64_FeatureFuseAddSub2RegAndConstOne = 70,
+  AArch64_FeatureFuseAddress = 71,
+  AArch64_FeatureFuseAdrpAdd = 72,
+  AArch64_FeatureFuseArithmeticLogic = 73,
+  AArch64_FeatureFuseCCSelect = 74,
+  AArch64_FeatureFuseCryptoEOR = 75,
+  AArch64_FeatureFuseLiterals = 76,
+  AArch64_FeatureGCS = 77,
+  AArch64_FeatureHBC = 78,
+  AArch64_FeatureHCX = 79,
+  AArch64_FeatureHardenSlsBlr = 80,
+  AArch64_FeatureHardenSlsNoComdat = 81,
+  AArch64_FeatureHardenSlsRetBr = 82,
+  AArch64_FeatureITE = 83,
+  AArch64_FeatureJS = 84,
+  AArch64_FeatureLOR = 85,
+  AArch64_FeatureLS64 = 86,
+  AArch64_FeatureLSE = 87,
+  AArch64_FeatureLSE2 = 88,
+  AArch64_FeatureLSE128 = 89,
+  AArch64_FeatureLUT = 90,
+  AArch64_FeatureLdpAlignedOnly = 91,
+  AArch64_FeatureMEC = 92,
+  AArch64_FeatureMOPS = 93,
+  AArch64_FeatureMPAM = 94,
+  AArch64_FeatureMTE = 95,
+  AArch64_FeatureMUL53 = 96,
+  AArch64_FeatureMatMulFP32 = 97,
+  AArch64_FeatureMatMulFP64 = 98,
+  AArch64_FeatureMatMulInt8 = 99,
+  AArch64_FeatureNEON = 100,
+  AArch64_FeatureNMI = 101,
+  AArch64_FeatureNV = 102,
+  AArch64_FeatureNoBTIAtReturnTwice = 103,
+  AArch64_FeatureNoNegativeImmediates = 104,
+  AArch64_FeatureNoSVEFPLD1R = 105,
+  AArch64_FeatureNoZCZeroingFP = 106,
+  AArch64_FeatureOutlineAtomics = 107,
+  AArch64_FeaturePAN = 108,
+  AArch64_FeaturePAN_RWV = 109,
+  AArch64_FeaturePAuth = 110,
+  AArch64_FeaturePAuthLR = 111,
+  AArch64_FeaturePRFM_SLC = 112,
+  AArch64_FeaturePerfMon = 113,
+  AArch64_FeaturePostRAScheduler = 114,
+  AArch64_FeaturePredRes = 115,
+  AArch64_FeaturePredictableSelectIsExpensive = 116,
+  AArch64_FeaturePsUAO = 117,
+  AArch64_FeatureRAS = 118,
+  AArch64_FeatureRASv2 = 119,
+  AArch64_FeatureRCPC = 120,
+  AArch64_FeatureRCPC3 = 121,
+  AArch64_FeatureRCPC_IMMO = 122,
+  AArch64_FeatureRDM = 123,
+  AArch64_FeatureRME = 124,
+  AArch64_FeatureRandGen = 125,
+  AArch64_FeatureReserveX1 = 126,
+  AArch64_FeatureReserveX2 = 127,
+  AArch64_FeatureReserveX3 = 128,
+  AArch64_FeatureReserveX4 = 129,
+  AArch64_FeatureReserveX5 = 130,
+  AArch64_FeatureReserveX6 = 131,
+  AArch64_FeatureReserveX7 = 132,
+  AArch64_FeatureReserveX9 = 133,
+  AArch64_FeatureReserveX10 = 134,
+  AArch64_FeatureReserveX11 = 135,
+  AArch64_FeatureReserveX12 = 136,
+  AArch64_FeatureReserveX13 = 137,
+  AArch64_FeatureReserveX14 = 138,
+  AArch64_FeatureReserveX15 = 139,
+  AArch64_FeatureReserveX18 = 140,
+  AArch64_FeatureReserveX20 = 141,
+  AArch64_FeatureReserveX21 = 142,
+  AArch64_FeatureReserveX22 = 143,
+  AArch64_FeatureReserveX23 = 144,
+  AArch64_FeatureReserveX24 = 145,
+  AArch64_FeatureReserveX25 = 146,
+  AArch64_FeatureReserveX26 = 147,
+  AArch64_FeatureReserveX27 = 148,
+  AArch64_FeatureReserveX28 = 149,
+  AArch64_FeatureReserveX30 = 150,
+  AArch64_FeatureSB = 151,
+  AArch64_FeatureSEL2 = 152,
+  AArch64_FeatureSHA2 = 153,
+  AArch64_FeatureSHA3 = 154,
+  AArch64_FeatureSM4 = 155,
+  AArch64_FeatureSME = 156,
+  AArch64_FeatureSME2 = 157,
+  AArch64_FeatureSME2p1 = 158,
+  AArch64_FeatureSMEF8F16 = 159,
+  AArch64_FeatureSMEF8F32 = 160,
+  AArch64_FeatureSMEF16F16 = 161,
+  AArch64_FeatureSMEF64F64 = 162,
+  AArch64_FeatureSMEFA64 = 163,
+  AArch64_FeatureSMEI16I64 = 164,
+  AArch64_FeatureSME_LUTv2 = 165,
+  AArch64_FeatureSPE = 166,
+  AArch64_FeatureSPECRES2 = 167,
+  AArch64_FeatureSPE_EEF = 168,
+  AArch64_FeatureSSBS = 169,
+  AArch64_FeatureSSVE_FP8DOT2 = 170,
+  AArch64_FeatureSSVE_FP8DOT4 = 171,
+  AArch64_FeatureSSVE_FP8FMA = 172,
+  AArch64_FeatureSVE = 173,
+  AArch64_FeatureSVE2 = 174,
+  AArch64_FeatureSVE2AES = 175,
+  AArch64_FeatureSVE2BitPerm = 176,
+  AArch64_FeatureSVE2SHA3 = 177,
+  AArch64_FeatureSVE2SM4 = 178,
+  AArch64_FeatureSVE2p1 = 179,
+  AArch64_FeatureSlowMisaligned128Store = 180,
+  AArch64_FeatureSlowPaired128 = 181,
+  AArch64_FeatureSlowSTRQro = 182,
+  AArch64_FeatureSpecRestrict = 183,
+  AArch64_FeatureStorePairSuppress = 184,
+  AArch64_FeatureStpAlignedOnly = 185,
+  AArch64_FeatureStrictAlign = 186,
+  AArch64_FeatureTHE = 187,
+  AArch64_FeatureTLBIW = 188,
+  AArch64_FeatureTLB_RMI = 189,
+  AArch64_FeatureTME = 190,
+  AArch64_FeatureTRACEV8_4 = 191,
+  AArch64_FeatureTRBE = 192,
+  AArch64_FeatureTaggedGlobals = 193,
+  AArch64_FeatureUseEL1ForTP = 194,
+  AArch64_FeatureUseEL2ForTP = 195,
+  AArch64_FeatureUseEL3ForTP = 196,
+  AArch64_FeatureUseROEL0ForTP = 197,
+  AArch64_FeatureUseRSqrt = 198,
+  AArch64_FeatureUseScalarIncVL = 199,
+  AArch64_FeatureVH = 200,
+  AArch64_FeatureWFxT = 201,
+  AArch64_FeatureXS = 202,
+  AArch64_FeatureZCRegMove = 203,
+  AArch64_FeatureZCZeroing = 204,
+  AArch64_FeatureZCZeroingFPWorkaround = 205,
+  AArch64_FeatureZCZeroingGP = 206,
+  AArch64_HasV8_0aOps = 207,
+  AArch64_HasV8_0rOps = 208,
+  AArch64_HasV8_1aOps = 209,
+  AArch64_HasV8_2aOps = 210,
+  AArch64_HasV8_3aOps = 211,
+  AArch64_HasV8_4aOps = 212,
+  AArch64_HasV8_5aOps = 213,
+  AArch64_HasV8_6aOps = 214,
+  AArch64_HasV8_7aOps = 215,
+  AArch64_HasV8_8aOps = 216,
+  AArch64_HasV8_9aOps = 217,
+  AArch64_HasV9_0aOps = 218,
+  AArch64_HasV9_1aOps = 219,
+  AArch64_HasV9_2aOps = 220,
+  AArch64_HasV9_3aOps = 221,
+  AArch64_HasV9_4aOps = 222,
+  AArch64_HasV9_5aOps = 223,
+  AArch64_TuneA35 = 224,
+  AArch64_TuneA53 = 225,
+  AArch64_TuneA55 = 226,
+  AArch64_TuneA57 = 227,
+  AArch64_TuneA64FX = 228,
+  AArch64_TuneA65 = 229,
+  AArch64_TuneA72 = 230,
+  AArch64_TuneA73 = 231,
+  AArch64_TuneA75 = 232,
+  AArch64_TuneA76 = 233,
+  AArch64_TuneA77 = 234,
+  AArch64_TuneA78 = 235,
+  AArch64_TuneA78C = 236,
+  AArch64_TuneA510 = 237,
+  AArch64_TuneA520 = 238,
+  AArch64_TuneA710 = 239,
+  AArch64_TuneA715 = 240,
+  AArch64_TuneA720 = 241,
+  AArch64_TuneAmpere1 = 242,
+  AArch64_TuneAmpere1A = 243,
+  AArch64_TuneAmpere1B = 244,
+  AArch64_TuneAppleA7 = 245,
+  AArch64_TuneAppleA10 = 246,
+  AArch64_TuneAppleA11 = 247,
+  AArch64_TuneAppleA12 = 248,
+  AArch64_TuneAppleA13 = 249,
+  AArch64_TuneAppleA14 = 250,
+  AArch64_TuneAppleA15 = 251,
+  AArch64_TuneAppleA16 = 252,
+  AArch64_TuneAppleA17 = 253,
+  AArch64_TuneCarmel = 254,
+  AArch64_TuneExynosM3 = 255,
+  AArch64_TuneExynosM4 = 256,
+  AArch64_TuneFalkor = 257,
+  AArch64_TuneKryo = 258,
+  AArch64_TuneNeoverse512TVB = 259,
+  AArch64_TuneNeoverseE1 = 260,
+  AArch64_TuneNeoverseN1 = 261,
+  AArch64_TuneNeoverseN2 = 262,
+  AArch64_TuneNeoverseV1 = 263,
+  AArch64_TuneNeoverseV2 = 264,
+  AArch64_TuneR82 = 265,
+  AArch64_TuneSaphira = 266,
+  AArch64_TuneTSV110 = 267,
+  AArch64_TuneThunderX = 268,
+  AArch64_TuneThunderX2T99 = 269,
+  AArch64_TuneThunderX3T110 = 270,
+  AArch64_TuneThunderXT81 = 271,
+  AArch64_TuneThunderXT83 = 272,
+  AArch64_TuneThunderXT88 = 273,
+  AArch64_TuneX1 = 274,
+  AArch64_TuneX2 = 275,
+  AArch64_TuneX3 = 276,
+  AArch64_TuneX4 = 277,
+  AArch64_NumSubtargetFeatures = 278
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

external/capstone/arch/AArch64/AArch64InstPrinter.h

@@ -0,0 +1,351 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an AArch64 MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
+#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "AArch64Mapping.h"
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInstPrinter.h"
+#include "../../SStream.h"
+#include "../../utils.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+#define CHAR(c) #c[0]
+
+void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
+void printRegName(SStream *OS, unsigned Reg);
+void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
+// Autogenerated by tblgen.
+const char *getRegName(unsigned Reg);
+bool printSysAlias(MCInst *MI, SStream *O);
+bool printSyspAlias(MCInst *MI, SStream *O);
+bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
+// Operand printers
+void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printImm(MCInst *MI, unsigned OpNo, SStream *O);
+void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
+#define DECLARE_printSImm(Size) \
+	void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
+DECLARE_printSImm(16);
+DECLARE_printSImm(8);
+
+#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
+DECLARE_printImmSVE(int16_t);
+DECLARE_printImmSVE(int8_t);
+DECLARE_printImmSVE(int64_t);
+DECLARE_printImmSVE(int32_t);
+DECLARE_printImmSVE(uint16_t);
+DECLARE_printImmSVE(uint8_t);
+DECLARE_printImmSVE(uint64_t);
+DECLARE_printImmSVE(uint32_t);
+
+void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
+#define DEFINE_printPostIncOperand(Amount) \
+	static inline void CONCAT(printPostIncOperand, Amount)( \
+		MCInst * MI, unsigned OpNo, SStream *O) \
+	{ \
+		AArch64_add_cs_detail_1(MI, \
+			      CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
+			      OpNo, Amount); \
+		printPostIncOperand(MI, OpNo, Amount, O); \
+	}
+DEFINE_printPostIncOperand(64);
+DEFINE_printPostIncOperand(32);
+DEFINE_printPostIncOperand(16);
+DEFINE_printPostIncOperand(8);
+DEFINE_printPostIncOperand(1);
+DEFINE_printPostIncOperand(4);
+DEFINE_printPostIncOperand(2);
+DEFINE_printPostIncOperand(48);
+DEFINE_printPostIncOperand(24);
+DEFINE_printPostIncOperand(3);
+DEFINE_printPostIncOperand(12);
+DEFINE_printPostIncOperand(6);
+
+void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printLogicalImm(T) \
+	void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
+					SStream *O);
+DECLARE_printLogicalImm(int64_t);
+DECLARE_printLogicalImm(int32_t);
+DECLARE_printLogicalImm(int8_t);
+DECLARE_printLogicalImm(int16_t);
+
+void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
+void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
+
+void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
+		    unsigned Width);
+void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
+		    unsigned Width);
+#define DEFINE_printMemExtend(SrcRegKind, Width) \
+	static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
+		MCInst * MI, unsigned OpNum, SStream *O) \
+	{ \
+		AArch64_add_cs_detail_2( \
+			MI, \
+			CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
+			       Width), \
+			OpNum, CHAR(SrcRegKind), Width); \
+		printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
+	}
+DEFINE_printMemExtend(w, 8);
+DEFINE_printMemExtend(x, 8);
+DEFINE_printMemExtend(w, 64);
+DEFINE_printMemExtend(x, 64);
+DEFINE_printMemExtend(w, 16);
+DEFINE_printMemExtend(x, 16);
+DEFINE_printMemExtend(w, 128);
+DEFINE_printMemExtend(x, 128);
+DEFINE_printMemExtend(w, 32);
+DEFINE_printMemExtend(x, 32);
+
+#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
+					Suffix) \
+	void CONCAT(printRegWithShiftExtend, \
+		    CONCAT(SignedExtend, \
+			   CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printRegWithShiftExtend(false, 8, x, d);
+DECLARE_printRegWithShiftExtend(true, 8, w, d);
+DECLARE_printRegWithShiftExtend(false, 8, w, d);
+DECLARE_printRegWithShiftExtend(false, 8, x, 0);
+DECLARE_printRegWithShiftExtend(true, 8, w, s);
+DECLARE_printRegWithShiftExtend(false, 8, w, s);
+DECLARE_printRegWithShiftExtend(false, 64, x, d);
+DECLARE_printRegWithShiftExtend(true, 64, w, d);
+DECLARE_printRegWithShiftExtend(false, 64, w, d);
+DECLARE_printRegWithShiftExtend(false, 64, x, 0);
+DECLARE_printRegWithShiftExtend(true, 64, w, s);
+DECLARE_printRegWithShiftExtend(false, 64, w, s);
+DECLARE_printRegWithShiftExtend(false, 16, x, d);
+DECLARE_printRegWithShiftExtend(true, 16, w, d);
+DECLARE_printRegWithShiftExtend(false, 16, w, d);
+DECLARE_printRegWithShiftExtend(false, 16, x, 0);
+DECLARE_printRegWithShiftExtend(true, 16, w, s);
+DECLARE_printRegWithShiftExtend(false, 16, w, s);
+DECLARE_printRegWithShiftExtend(false, 32, x, d);
+DECLARE_printRegWithShiftExtend(true, 32, w, d);
+DECLARE_printRegWithShiftExtend(false, 32, w, d);
+DECLARE_printRegWithShiftExtend(false, 32, x, 0);
+DECLARE_printRegWithShiftExtend(true, 32, w, s);
+DECLARE_printRegWithShiftExtend(false, 32, w, s);
+DECLARE_printRegWithShiftExtend(false, 8, x, s);
+DECLARE_printRegWithShiftExtend(false, 16, x, s);
+DECLARE_printRegWithShiftExtend(false, 32, x, s);
+DECLARE_printRegWithShiftExtend(false, 64, x, s);
+DECLARE_printRegWithShiftExtend(false, 128, x, 0);
+
+void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
+void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
+void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
+		       SStream *O);
+void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
+void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
+#define DEFINE_printUImm12Offset(Scale) \
+	static inline void CONCAT(printUImm12Offset, Scale)( \
+		MCInst * MI, unsigned OpNum, SStream *O) \
+	{ \
+		AArch64_add_cs_detail_1(MI, \
+			      CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
+			      OpNum, Scale); \
+		printUImm12Offset(MI, OpNum, Scale, O); \
+	}
+DEFINE_printUImm12Offset(1);
+DEFINE_printUImm12Offset(8);
+DEFINE_printUImm12Offset(2);
+DEFINE_printUImm12Offset(16);
+DEFINE_printUImm12Offset(4);
+
+void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printImmScale(Scale) \
+	void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
+					  SStream *O);
+DECLARE_printImmScale(8);
+DECLARE_printImmScale(2);
+DECLARE_printImmScale(4);
+DECLARE_printImmScale(16);
+DECLARE_printImmScale(32);
+DECLARE_printImmScale(3);
+
+#define DECLARE_printImmRangeScale(Scale, Offset) \
+	void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printImmRangeScale(2, 1);
+DECLARE_printImmRangeScale(4, 3);
+
+#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
+	void CONCAT(printPrefetchOp, \
+		    IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printPrefetchOp(true);
+DECLARE_printPrefetchOp(false);
+
+void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
+		     const char *LayoutSuffix);
+void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
+/// (i.e. attached to the instruction rather than the registers).
+/// Print a list of vector registers where the type suffix is implicit
+void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
+	void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printTypedVectorList(0, b);
+DECLARE_printTypedVectorList(0, d);
+DECLARE_printTypedVectorList(0, h);
+DECLARE_printTypedVectorList(0, s);
+DECLARE_printTypedVectorList(0, q);
+DECLARE_printTypedVectorList(16, b);
+DECLARE_printTypedVectorList(1, d);
+DECLARE_printTypedVectorList(2, d);
+DECLARE_printTypedVectorList(2, s);
+DECLARE_printTypedVectorList(4, h);
+DECLARE_printTypedVectorList(4, s);
+DECLARE_printTypedVectorList(8, b);
+DECLARE_printTypedVectorList(8, h);
+DECLARE_printTypedVectorList(0, 0);
+
+#define DECLARE_printVectorIndex(Scale) \
+	void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
+					     SStream *O);
+DECLARE_printVectorIndex(1);
+DECLARE_printVectorIndex(8);
+
+void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
+		       SStream *O);
+void printAppleSysBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
+void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printPredicateAsCounter(EltSize) \
+	void CONCAT(printPredicateAsCounter, \
+		    EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printPredicateAsCounter(8);
+DECLARE_printPredicateAsCounter(64);
+DECLARE_printPredicateAsCounter(16);
+DECLARE_printPredicateAsCounter(32);
+DECLARE_printPredicateAsCounter(0);
+
+#define DECLARE_printGPRSeqPairsClassOperand(size) \
+	void CONCAT(printGPRSeqPairsClassOperand, \
+		    size)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printGPRSeqPairsClassOperand(32);
+DECLARE_printGPRSeqPairsClassOperand(64);
+
+#define DECLARE_printImm8OptLsl(T) \
+	void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
+					SStream *O);
+DECLARE_printImm8OptLsl(int16_t);
+DECLARE_printImm8OptLsl(int8_t);
+DECLARE_printImm8OptLsl(int64_t);
+DECLARE_printImm8OptLsl(int32_t);
+DECLARE_printImm8OptLsl(uint16_t);
+DECLARE_printImm8OptLsl(uint8_t);
+DECLARE_printImm8OptLsl(uint64_t);
+DECLARE_printImm8OptLsl(uint32_t);
+
+#define DECLARE_printSVELogicalImm(T) \
+	void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
+					   SStream *O);
+DECLARE_printSVELogicalImm(int16_t);
+DECLARE_printSVELogicalImm(int32_t);
+DECLARE_printSVELogicalImm(int64_t);
+
+void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
+void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMatrixTileVector(IsVertical) \
+	void CONCAT(printMatrixTileVector, \
+		    IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printMatrixTileVector(0);
+DECLARE_printMatrixTileVector(1);
+
+void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMatrix(EltSize) \
+	void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
+					  SStream *O);
+DECLARE_printMatrix(64);
+DECLARE_printMatrix(32);
+DECLARE_printMatrix(16);
+DECLARE_printMatrix(0);
+
+void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printSVERegOp(char) \
+	void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
+					 SStream *O);
+DECLARE_printSVERegOp(b);
+DECLARE_printSVERegOp(d);
+DECLARE_printSVERegOp(h);
+DECLARE_printSVERegOp(s);
+DECLARE_printSVERegOp(0);
+DECLARE_printSVERegOp(q);
+
+void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
+void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
+void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printZPRasFPR(Width) \
+	void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
+					  SStream *O);
+DECLARE_printZPRasFPR(8);
+DECLARE_printZPRasFPR(64);
+DECLARE_printZPRasFPR(16);
+DECLARE_printZPRasFPR(32);
+DECLARE_printZPRasFPR(128);
+
+#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
+	void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
+DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
+DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
+
+#define DECLARE_printMatrixIndex(Scale) \
+	void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
+					     SStream *O);
+DECLARE_printMatrixIndex(8);
+DECLARE_printMatrixIndex(0);
+DECLARE_printMatrixIndex(1);
+
+// end namespace llvm
+
+#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H

external/capstone/arch/AArch64/AArch64Linkage.h

@@ -0,0 +1,23 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org> 2022-2023 */
+
+#ifndef CS_AARCH64_LINKAGE_H
+#define CS_AARCH64_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+					 size_t ByteLen, MCInst *MI,
+					 uint16_t *Size, uint64_t Address,
+					 void *Info);
+const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O,
+				   void * /* MCRegisterInfo* */ info);
+
+#endif // CS_AARCH64_LINKAGE_H

external/capstone/arch/AArch64/AArch64Mapping.h

@@ -0,0 +1,90 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_AARCH64_MAP_H
+#define CS_AARCH64_MAP_H
+
+#include "capstone/capstone.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+typedef enum {
+#include "AArch64GenCSOpGroup.inc"
+} aarch64_op_group;
+
+/// Components of an SME matrix.
+/// Used when an sme operand is set to signal which part should be set.
+typedef enum {
+	AARCH64_SME_MATRIX_TILE,
+	AARCH64_SME_MATRIX_TILE_LIST,
+	AARCH64_SME_MATRIX_SLICE_REG,
+	AARCH64_SME_MATRIX_SLICE_OFF,
+	AARCH64_SME_MATRIX_SLICE_OFF_RANGE,
+} aarch64_sme_op_part;
+
+// return name of register in friendly string
+const char *AArch64_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *AArch64_insn_name(csh handle, unsigned int id);
+
+const char *AArch64_group_name(csh handle, unsigned int id);
+
+void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count);
+
+void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group,
+				  unsigned OpNum);
+void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group,
+				     unsigned OpNum, uint64_t temp_arg_0);
+void AArch64_add_cs_detail_2(MCInst *MI, aarch64_op_group op_group,
+				     unsigned OpNum, uint64_t temp_arg_0,
+				     uint64_t temp_arg_1);
+void AArch64_add_cs_detail_4(MCInst *MI, aarch64_op_group op_group,
+				     unsigned OpNum, uint64_t temp_arg_0,
+				     uint64_t temp_arg_1, uint64_t temp_arg_2,
+				     uint64_t temp_arg_3);
+
+void AArch64_init_mri(MCRegisterInfo *MRI);
+
+void AArch64_init_cs_detail(MCInst *MI);
+
+void AArch64_set_instr_map_data(MCInst *MI);
+
+bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			    MCInst *instr, uint16_t *size, uint64_t address,
+			    void *info);
+
+void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
+
+void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
+void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+			       aarch64_op_type ImmType, int64_t Imm);
+void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
+				     uint32_t FirstImm, uint32_t offset);
+void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
+void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
+void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
+				  bool DoShift, unsigned ExtWidth,
+				  char SrcRegKind);
+void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
+void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op,
+			       aarch64_op_type type);
+void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
+			       aarch64_sme_op_part part,
+			       AArch64Layout_VectorLayout vas, ...);
+void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum);
+void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index,
+				     aarch64_reg Reg, cs_ac_type access);
+void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val,
+				       cs_ac_type access);
+void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm);
+void AArch64_insert_detail_op_sys(MCInst *MI, unsigned index, aarch64_sysop sys_op,
+			       aarch64_op_type type);
+void AArch64_insert_detail_op_sme(MCInst *MI, unsigned index, aarch64_op_sme sme_op);
+void AArch64_add_vas(MCInst *MI, const SStream *OS);
+
+#endif

external/capstone/arch/AArch64/AArch64Module.c

@@ -0,0 +1,46 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_AARCH64
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "AArch64InstPrinter.h"
+#include "AArch64Mapping.h"
+#include "AArch64Module.h"
+
+cs_err AArch64_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	AArch64_init_mri(mri);
+	ud->printer = AArch64_printer;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = AArch64_getInstruction;
+	ud->reg_name = AArch64_reg_name;
+	ud->insn_id = AArch64_get_insn_id;
+	ud->insn_name = AArch64_insn_name;
+	ud->group_name = AArch64_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = AArch64_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax |= (int)value;
+
+	if (type == CS_OPT_MODE) {
+		handle->mode |= (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

external/capstone/arch/AArch64/AArch64Module.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_AARCH64_MODULE_H
+#define CS_AARCH64_MODULE_H
+
+#include "../../utils.h"
+
+cs_err AArch64_global_init(cs_struct *ud);
+cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif