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external/capstone/arch/ARC/ARCInstPrinter.c
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210
external/capstone/arch/ARC/ARCInstPrinter.c
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifdef CAPSTONE_HAS_ARC
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../SStream.h"
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#include "../../MCInst.h"
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#include "../../MCInstPrinter.h"
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#include "ARCInfo.h"
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#include "ARCInstPrinter.h"
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#include "ARCLinkage.h"
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#include "ARCMapping.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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#define DEBUG_TYPE "asm-printer"
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#include "ARCGenAsmWriter.inc"
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static const char *ARCBRCondCodeToString(ARCCC_BRCondCode BRCC)
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{
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switch (BRCC) {
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case ARCCC_BREQ:
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return "eq";
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case ARCCC_BRNE:
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return "ne";
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case ARCCC_BRLT:
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return "lt";
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case ARCCC_BRGE:
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return "ge";
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case ARCCC_BRLO:
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return "lo";
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case ARCCC_BRHS:
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return "hs";
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}
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// CS_ASSERT(0 && "Unknown condition code passed");
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return "";
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}
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static const char *ARCCondCodeToString(ARCCC_CondCode CC)
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{
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switch (CC) {
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case ARCCC_EQ:
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return "eq";
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case ARCCC_NE:
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return "ne";
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case ARCCC_P:
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return "p";
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case ARCCC_N:
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return "n";
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case ARCCC_HS:
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return "hs";
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case ARCCC_LO:
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return "lo";
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case ARCCC_GT:
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return "gt";
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case ARCCC_GE:
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return "ge";
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case ARCCC_VS:
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return "vs";
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case ARCCC_VC:
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return "vc";
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case ARCCC_LT:
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return "lt";
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case ARCCC_LE:
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return "le";
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case ARCCC_HI:
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return "hi";
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case ARCCC_LS:
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return "ls";
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case ARCCC_PNZ:
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return "pnz";
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case ARCCC_AL:
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return "al";
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case ARCCC_NZ:
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return "nz";
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case ARCCC_Z:
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return "z";
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}
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// CS_ASSERT(0 && "Unknown condition code passed");
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return "";
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}
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static void printRegName(SStream *OS, MCRegister Reg)
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{
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SStream_concat0(OS, getRegisterName(Reg));
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}
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static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
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{
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printInstruction(MI, Address, O);
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}
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static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, ARC_OP_GROUP_Operand, OpNum);
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MCOperand *Op = MCInst_getOperand(MI, (OpNum));
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if (MCOperand_isReg(Op)) {
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printRegName(O, MCOperand_getReg(Op));
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} else if (MCOperand_isImm(Op)) {
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SStream_concat(O, "%" PRId64, MCOperand_getImm(Op));
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} else if (MCOperand_isExpr(Op)) {
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printExpr(O, MCOperand_getExpr(Op));
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}
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}
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static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
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{
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printOperand(MI, OpNum, O);
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}
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static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, ARC_OP_GROUP_MemOperandRI, OpNum);
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MCOperand *base = MCInst_getOperand(MI, (OpNum));
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MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1));
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CS_ASSERT((MCOperand_isReg(base) && "Base should be register."));
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CS_ASSERT((MCOperand_isImm(offset) && "Offset should be immediate."));
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printRegName(O, MCOperand_getReg(base));
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SStream_concat(O, "%s", ",");
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printInt64(O, MCOperand_getImm(offset));
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}
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static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, ARC_OP_GROUP_PredicateOperand, OpNum);
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MCOperand *Op = MCInst_getOperand(MI, (OpNum));
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CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
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SStream_concat0(
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O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(Op)));
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}
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static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
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{
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add_cs_detail(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum);
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MCOperand *Op = MCInst_getOperand(MI, (OpNum));
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CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
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SStream_concat0(O, ARCBRCondCodeToString(
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(ARCCC_BRCondCode)MCOperand_getImm(Op)));
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}
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static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, ARC_OP_GROUP_CCOperand, OpNum);
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SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(
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MCInst_getOperand(MI, (OpNum)))));
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}
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static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, (OpNum));
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if (MCOperand_isImm(MO)) {
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unsigned Value = MCOperand_getImm(MO);
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unsigned Value2 = Value >> ShiftBy;
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if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
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CS_ASSERT((false && "instruction has wrong format"));
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}
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}
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printOperand(MI, OpNum, O);
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}
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static void printU6(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, ARC_OP_GROUP_U6, OpNum);
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printU6ShiftedBy(0, MI, OpNum, O);
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}
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void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
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SStream *O)
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{
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printInst(MI, Address, Annot, O);
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}
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const char *ARC_LLVM_getRegisterName(unsigned RegNo)
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{
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return getRegisterName(RegNo);
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}
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#endif
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