Fuck git

external/capstone/arch/Sparc/SparcDisassembler.c

@@ -0,0 +1,342 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the Sparc Disassembler.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCDisassembler.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "SparcDisassemblerExtension.h"
+#include "SparcLinkage.h"
+#include "SparcMapping.h"
+#include "SparcMCTargetDesc.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "sparc-disassembler"
+
+static const unsigned IntRegDecoderTable[] = {
+	Sparc_G0, Sparc_G1, Sparc_G2, Sparc_G3, Sparc_G4, Sparc_G5, Sparc_G6, Sparc_G7,
+	Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, Sparc_O6, Sparc_O7,
+	Sparc_L0, Sparc_L1, Sparc_L2, Sparc_L3, Sparc_L4, Sparc_L5, Sparc_L6, Sparc_L7,
+	Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, Sparc_I6, Sparc_I7
+};
+
+static const unsigned FPRegDecoderTable[] = {
+	Sparc_F0,	Sparc_F1,	Sparc_F2,	Sparc_F3,	Sparc_F4,	Sparc_F5,	Sparc_F6,	Sparc_F7,
+	Sparc_F8,	Sparc_F9,	Sparc_F10, Sparc_F11, Sparc_F12, Sparc_F13, Sparc_F14, Sparc_F15,
+	Sparc_F16, Sparc_F17, Sparc_F18, Sparc_F19, Sparc_F20, Sparc_F21, Sparc_F22, Sparc_F23,
+	Sparc_F24, Sparc_F25, Sparc_F26, Sparc_F27, Sparc_F28, Sparc_F29, Sparc_F30, Sparc_F31
+};
+
+static const unsigned DFPRegDecoderTable[] = {
+	Sparc_D0,	Sparc_D16, Sparc_D1,	Sparc_D17, Sparc_D2,	Sparc_D18, Sparc_D3,	Sparc_D19,
+	Sparc_D4,	Sparc_D20, Sparc_D5,	Sparc_D21, Sparc_D6,	Sparc_D22, Sparc_D7,	Sparc_D23,
+	Sparc_D8,	Sparc_D24, Sparc_D9,	Sparc_D25, Sparc_D10, Sparc_D26, Sparc_D11, Sparc_D27,
+	Sparc_D12, Sparc_D28, Sparc_D13, Sparc_D29, Sparc_D14, Sparc_D30, Sparc_D15, Sparc_D31
+};
+
+static const unsigned QFPRegDecoderTable[] = {
+	Sparc_Q0, Sparc_Q8,  ~0U, ~0U, Sparc_Q1, Sparc_Q9,	~0U, ~0U,
+	Sparc_Q2, Sparc_Q10, ~0U, ~0U, Sparc_Q3, Sparc_Q11, ~0U, ~0U,
+	Sparc_Q4, Sparc_Q12, ~0U, ~0U, Sparc_Q5, Sparc_Q13, ~0U, ~0U,
+	Sparc_Q6, Sparc_Q14, ~0U, ~0U, Sparc_Q7, Sparc_Q15, ~0U, ~0U
+};
+
+static const unsigned FCCRegDecoderTable[] = { Sparc_FCC0, Sparc_FCC1, Sparc_FCC2,
+					       Sparc_FCC3 };
+
+static const unsigned ASRRegDecoderTable[] = {
+	Sparc_Y,	  Sparc_ASR1,  Sparc_ASR2,  Sparc_ASR3,	Sparc_ASR4,  Sparc_ASR5,  Sparc_ASR6,
+	Sparc_ASR7,  Sparc_ASR8,  Sparc_ASR9,  Sparc_ASR10, Sparc_ASR11, Sparc_ASR12, Sparc_ASR13,
+	Sparc_ASR14, Sparc_ASR15, Sparc_ASR16, Sparc_ASR17, Sparc_ASR18, Sparc_ASR19, Sparc_ASR20,
+	Sparc_ASR21, Sparc_ASR22, Sparc_ASR23, Sparc_ASR24, Sparc_ASR25, Sparc_ASR26, Sparc_ASR27,
+	Sparc_ASR28, Sparc_ASR29, Sparc_ASR30, Sparc_ASR31
+};
+
+static const unsigned PRRegDecoderTable[] = {
+	Sparc_TPC,	    Sparc_TNPC,	   Sparc_TSTATE,	Sparc_TT,	     Sparc_TICK,
+	Sparc_TBA,	    Sparc_PSTATE,	   Sparc_TL,	Sparc_PIL,	     Sparc_CWP,
+	Sparc_CANSAVE, Sparc_CANRESTORE, Sparc_CLEANWIN, Sparc_OTHERWIN, Sparc_WSTATE
+};
+
+static const uint16_t IntPairDecoderTable[] = {
+	Sparc_G0_G1, Sparc_G2_G3, Sparc_G4_G5, Sparc_G6_G7, Sparc_O0_O1, Sparc_O2_O3,
+	Sparc_O4_O5, Sparc_O6_O7, Sparc_L0_L1, Sparc_L2_L3, Sparc_L4_L5, Sparc_L6_L7,
+	Sparc_I0_I1, Sparc_I2_I3, Sparc_I4_I5, Sparc_I6_I7,
+};
+
+static const unsigned CPRegDecoderTable[] = {
+	Sparc_C0,	Sparc_C1,	Sparc_C2,	Sparc_C3,	Sparc_C4,	Sparc_C5,	Sparc_C6,	Sparc_C7,
+	Sparc_C8,	Sparc_C9,	Sparc_C10, Sparc_C11, Sparc_C12, Sparc_C13, Sparc_C14, Sparc_C15,
+	Sparc_C16, Sparc_C17, Sparc_C18, Sparc_C19, Sparc_C20, Sparc_C21, Sparc_C22, Sparc_C23,
+	Sparc_C24, Sparc_C25, Sparc_C26, Sparc_C27, Sparc_C28, Sparc_C29, Sparc_C30, Sparc_C31
+};
+
+static const uint16_t CPPairDecoderTable[] = {
+	Sparc_C0_C1,   Sparc_C2_C3,	Sparc_C4_C5,   Sparc_C6_C7,	Sparc_C8_C9,   Sparc_C10_C11,
+	Sparc_C12_C13, Sparc_C14_C15, Sparc_C16_C17, Sparc_C18_C19, Sparc_C20_C21, Sparc_C22_C23,
+	Sparc_C24_C25, Sparc_C26_C27, Sparc_C28_C29, Sparc_C30_C31
+};
+
+static DecodeStatus DecodeDisp19(MCInst *Inst, uint32_t ImmVal,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	int64_t BranchTarget = Address + (SignExtend64(ImmVal, 19) * 4);
+	MCOperand_CreateImm0(Inst, BranchTarget);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDisp16(MCInst *Inst, uint32_t ImmVal,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	int64_t BranchTarget = Address + (SignExtend64(ImmVal, 16) * 4);
+	MCOperand_CreateImm0(Inst, BranchTarget);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDisp22(MCInst *Inst, uint32_t ImmVal,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	int64_t BranchTarget = Address + (SignExtend64(ImmVal, 22) * 4);
+	MCOperand_CreateImm0(Inst, BranchTarget);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+	unsigned Reg = IntRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
+// depending on SparcRegisterInfo::getPointerRegClass.
+static DecodeStatus DecodePointerLikeRegClass0(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+	unsigned Reg = FPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+	unsigned Reg = DFPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Reg = QFPRegDecoderTable[RegNo];
+	if (Reg == ~0U)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCoprocRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+						  uint64_t Address,
+						  const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+	unsigned Reg = CPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo > 3)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (FCCRegDecoderTable[RegNo]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeASRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (ASRRegDecoderTable[RegNo]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(PRRegDecoderTable))
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (PRRegDecoderTable[RegNo]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeIntPairRegisterClass(MCInst *Inst, unsigned RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	if ((RegNo & 1))
+		S = MCDisassembler_SoftFail;
+
+	unsigned RegisterPair = IntPairDecoderTable[RegNo / 2];
+	MCOperand_CreateReg0(Inst, (RegisterPair));
+	return S;
+}
+
+static DecodeStatus DecodeCoprocPairRegisterClass(MCInst *Inst, unsigned RegNo,
+						  uint64_t Address,
+						  const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned RegisterPair = CPPairDecoderTable[RegNo / 2];
+	MCOperand_CreateReg0(Inst, (RegisterPair));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, uint64_t Address,
+			       const void *Decoder);
+static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, uint64_t Address,
+				 const void *Decoder);
+
+#include "SparcGenDisassemblerTables.inc"
+
+static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
+			    size_t BytesLen, uint64_t Address, SStream *CStream)
+{
+	if (BytesLen < 4) {
+		return MCDisassembler_Fail;
+	}
+	uint32_t Insn = readBytes32(Instr, Bytes);
+
+	DecodeStatus Result = MCDisassembler_Fail;
+	// Calling the auto-generated decoder function.
+	if (Sparc_getFeatureBits(Instr->csh->mode, Sparc_FeatureV9)) {
+		Result = decodeInstruction_4(DecoderTableSparcV932, Instr, Insn,
+					     Address, NULL);
+	} else {
+		Result = decodeInstruction_4(DecoderTableSparcV832, Instr, Insn,
+					     Address, NULL);
+	}
+	if (Result != MCDisassembler_Fail) {
+		*Size = 4;
+		return Result;
+	}
+
+	Result = decodeInstruction_4(DecoderTableSparc32, Instr, Insn, Address,
+				     NULL);
+
+	if (Result != MCDisassembler_Fail) {
+		*Size = 4;
+		return Result;
+	}
+
+	return MCDisassembler_Fail;
+}
+
+static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
+				     uint64_t Address, uint64_t Offset,
+				     uint64_t Width, MCInst *MI,
+				     const void *Decoder)
+{
+	// Capstone doesn't support symbols.
+	return false;
+}
+
+static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, uint64_t Address,
+			       const void *Decoder)
+{
+	unsigned Offset = fieldFromInstruction_4(insn, 0, 30);
+	int64_t CallTarget = Address + (SignExtend64(Offset, 30) * 4);
+	if (!tryAddingSymbolicOperand(CallTarget, false, Address, 0, 30, MI,
+				      Decoder))
+		MCOperand_CreateImm0(MI, CallTarget);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, uint64_t Address,
+				 const void *Decoder)
+{
+	CS_ASSERT(isUIntN(13, insn));
+	MCOperand_CreateImm0(MI, (SignExtend64((insn), 13)));
+	return MCDisassembler_Success;
+}
+
+DecodeStatus Sparc_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				     size_t ByteLen, MCInst *MI, uint16_t *Size,
+				     uint64_t Address, void *Info) {
+	uint64_t s = 0;
+	DecodeStatus status = getInstruction(MI, &s, Bytes, ByteLen, Address, NULL);
+	*Size = (uint16_t) s;
+	return status;
+}

external/capstone/arch/Sparc/SparcDisassemblerExtension.c

@@ -0,0 +1,13 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org>, 2025 */
+
+#include "SparcDisassemblerExtension.h"
+#include "SparcMCTargetDesc.h"
+
+bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	if (feature == Sparc_FeatureV9) {
+		return mode & CS_MODE_V9;
+	}
+	return true;
+}

external/capstone/arch/Sparc/SparcDisassemblerExtension.h

@@ -0,0 +1,11 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org>, 2025 */
+
+#ifndef CS_SPARC_DISASSEMBLER_EXTENSION_H
+#define CS_SPARC_DISASSEMBLER_EXTENSION_H
+
+#include <capstone/capstone.h>
+
+bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif // CS_SPARC_DISASSEMBLER_EXTENSION_H

external/capstone/arch/Sparc/SparcGenCSAliasMnemMap.inc

@@ -0,0 +1,394 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ SPARC_INS_ALIAS_MOVA, "mova" },
+	{ SPARC_INS_ALIAS_FMOVSA, "fmovsa" },
+	{ SPARC_INS_ALIAS_FMOVDA, "fmovda" },
+	{ SPARC_INS_ALIAS_MOVRZ, "movrz" },
+	{ SPARC_INS_ALIAS_FMOVRSZ, "fmovrsz" },
+	{ SPARC_INS_ALIAS_FMOVRDZ, "fmovrdz" },
+	{ SPARC_INS_ALIAS_FMOVRQZ, "fmovrqz" },
+	{ SPARC_INS_ALIAS_BA, "ba" },
+	{ SPARC_INS_ALIAS_BA_A, "ba_a" },
+	{ SPARC_INS_ALIAS_BA_PT, "ba_pt" },
+	{ SPARC_INS_ALIAS_BA_A_PT, "ba_a_pt" },
+	{ SPARC_INS_ALIAS_BA_PN, "ba_pn" },
+	{ SPARC_INS_ALIAS_BA_A_PN, "ba_a_pn" },
+	{ SPARC_INS_ALIAS_FMOVQA, "fmovqa" },
+	{ SPARC_INS_ALIAS_TA, "ta" },
+	{ SPARC_INS_ALIAS_FBA, "fba" },
+	{ SPARC_INS_ALIAS_FBA_PT, "fba_pt" },
+	{ SPARC_INS_ALIAS_FBA_A, "fba_a" },
+	{ SPARC_INS_ALIAS_FBA_A_PT, "fba_a_pt" },
+	{ SPARC_INS_ALIAS_FBA_PN, "fba_pn" },
+	{ SPARC_INS_ALIAS_FBA_A_PN, "fba_a_pn" },
+	{ SPARC_INS_ALIAS_BRZ, "brz" },
+	{ SPARC_INS_ALIAS_BRZ_PT, "brz_pt" },
+	{ SPARC_INS_ALIAS_BRZ_PN, "brz_pn" },
+	{ SPARC_INS_ALIAS_BRZ_A, "brz_a" },
+	{ SPARC_INS_ALIAS_BRZ_A_PT, "brz_a_pt" },
+	{ SPARC_INS_ALIAS_BRZ_A_PN, "brz_a_pn" },
+	{ SPARC_INS_ALIAS_BN, "bn" },
+	{ SPARC_INS_ALIAS_BN_A, "bn_a" },
+	{ SPARC_INS_ALIAS_BN_PT, "bn_pt" },
+	{ SPARC_INS_ALIAS_BN_A_PT, "bn_a_pt" },
+	{ SPARC_INS_ALIAS_BN_PN, "bn_pn" },
+	{ SPARC_INS_ALIAS_BN_A_PN, "bn_a_pn" },
+	{ SPARC_INS_ALIAS_MOVN, "movn" },
+	{ SPARC_INS_ALIAS_FMOVSN, "fmovsn" },
+	{ SPARC_INS_ALIAS_FMOVDN, "fmovdn" },
+	{ SPARC_INS_ALIAS_FMOVQN, "fmovqn" },
+	{ SPARC_INS_ALIAS_TN, "tn" },
+	{ SPARC_INS_ALIAS_BNE, "bne" },
+	{ SPARC_INS_ALIAS_BNE_A, "bne_a" },
+	{ SPARC_INS_ALIAS_BNE_PT, "bne_pt" },
+	{ SPARC_INS_ALIAS_BNE_A_PT, "bne_a_pt" },
+	{ SPARC_INS_ALIAS_BNE_PN, "bne_pn" },
+	{ SPARC_INS_ALIAS_BNE_A_PN, "bne_a_pn" },
+	{ SPARC_INS_ALIAS_MOVNE, "movne" },
+	{ SPARC_INS_ALIAS_FMOVSNE, "fmovsne" },
+	{ SPARC_INS_ALIAS_FMOVDNE, "fmovdne" },
+	{ SPARC_INS_ALIAS_FMOVQNE, "fmovqne" },
+	{ SPARC_INS_ALIAS_TNE, "tne" },
+	{ SPARC_INS_ALIAS_BE, "be" },
+	{ SPARC_INS_ALIAS_BE_A, "be_a" },
+	{ SPARC_INS_ALIAS_BE_PT, "be_pt" },
+	{ SPARC_INS_ALIAS_BE_A_PT, "be_a_pt" },
+	{ SPARC_INS_ALIAS_BE_PN, "be_pn" },
+	{ SPARC_INS_ALIAS_BE_A_PN, "be_a_pn" },
+	{ SPARC_INS_ALIAS_MOVE, "move" },
+	{ SPARC_INS_ALIAS_FMOVSE, "fmovse" },
+	{ SPARC_INS_ALIAS_FMOVDE, "fmovde" },
+	{ SPARC_INS_ALIAS_FMOVQE, "fmovqe" },
+	{ SPARC_INS_ALIAS_TE, "te" },
+	{ SPARC_INS_ALIAS_BG, "bg" },
+	{ SPARC_INS_ALIAS_BG_A, "bg_a" },
+	{ SPARC_INS_ALIAS_BG_PT, "bg_pt" },
+	{ SPARC_INS_ALIAS_BG_A_PT, "bg_a_pt" },
+	{ SPARC_INS_ALIAS_BG_PN, "bg_pn" },
+	{ SPARC_INS_ALIAS_BG_A_PN, "bg_a_pn" },
+	{ SPARC_INS_ALIAS_MOVG, "movg" },
+	{ SPARC_INS_ALIAS_FMOVSG, "fmovsg" },
+	{ SPARC_INS_ALIAS_FMOVDG, "fmovdg" },
+	{ SPARC_INS_ALIAS_FMOVQG, "fmovqg" },
+	{ SPARC_INS_ALIAS_TG, "tg" },
+	{ SPARC_INS_ALIAS_BLE, "ble" },
+	{ SPARC_INS_ALIAS_BLE_A, "ble_a" },
+	{ SPARC_INS_ALIAS_BLE_PT, "ble_pt" },
+	{ SPARC_INS_ALIAS_BLE_A_PT, "ble_a_pt" },
+	{ SPARC_INS_ALIAS_BLE_PN, "ble_pn" },
+	{ SPARC_INS_ALIAS_BLE_A_PN, "ble_a_pn" },
+	{ SPARC_INS_ALIAS_MOVLE, "movle" },
+	{ SPARC_INS_ALIAS_FMOVSLE, "fmovsle" },
+	{ SPARC_INS_ALIAS_FMOVDLE, "fmovdle" },
+	{ SPARC_INS_ALIAS_FMOVQLE, "fmovqle" },
+	{ SPARC_INS_ALIAS_TLE, "tle" },
+	{ SPARC_INS_ALIAS_BGE, "bge" },
+	{ SPARC_INS_ALIAS_BGE_A, "bge_a" },
+	{ SPARC_INS_ALIAS_BGE_PT, "bge_pt" },
+	{ SPARC_INS_ALIAS_BGE_A_PT, "bge_a_pt" },
+	{ SPARC_INS_ALIAS_BGE_PN, "bge_pn" },
+	{ SPARC_INS_ALIAS_BGE_A_PN, "bge_a_pn" },
+	{ SPARC_INS_ALIAS_MOVGE, "movge" },
+	{ SPARC_INS_ALIAS_FMOVSGE, "fmovsge" },
+	{ SPARC_INS_ALIAS_FMOVDGE, "fmovdge" },
+	{ SPARC_INS_ALIAS_FMOVQGE, "fmovqge" },
+	{ SPARC_INS_ALIAS_TGE, "tge" },
+	{ SPARC_INS_ALIAS_BL, "bl" },
+	{ SPARC_INS_ALIAS_BL_A, "bl_a" },
+	{ SPARC_INS_ALIAS_BL_PT, "bl_pt" },
+	{ SPARC_INS_ALIAS_BL_A_PT, "bl_a_pt" },
+	{ SPARC_INS_ALIAS_BL_PN, "bl_pn" },
+	{ SPARC_INS_ALIAS_BL_A_PN, "bl_a_pn" },
+	{ SPARC_INS_ALIAS_MOVL, "movl" },
+	{ SPARC_INS_ALIAS_FMOVSL, "fmovsl" },
+	{ SPARC_INS_ALIAS_FMOVDL, "fmovdl" },
+	{ SPARC_INS_ALIAS_FMOVQL, "fmovql" },
+	{ SPARC_INS_ALIAS_TL, "tl" },
+	{ SPARC_INS_ALIAS_BGU, "bgu" },
+	{ SPARC_INS_ALIAS_BGU_A, "bgu_a" },
+	{ SPARC_INS_ALIAS_BGU_PT, "bgu_pt" },
+	{ SPARC_INS_ALIAS_BGU_A_PT, "bgu_a_pt" },
+	{ SPARC_INS_ALIAS_BGU_PN, "bgu_pn" },
+	{ SPARC_INS_ALIAS_BGU_A_PN, "bgu_a_pn" },
+	{ SPARC_INS_ALIAS_MOVGU, "movgu" },
+	{ SPARC_INS_ALIAS_FMOVSGU, "fmovsgu" },
+	{ SPARC_INS_ALIAS_FMOVDGU, "fmovdgu" },
+	{ SPARC_INS_ALIAS_FMOVQGU, "fmovqgu" },
+	{ SPARC_INS_ALIAS_TGU, "tgu" },
+	{ SPARC_INS_ALIAS_BLEU, "bleu" },
+	{ SPARC_INS_ALIAS_BLEU_A, "bleu_a" },
+	{ SPARC_INS_ALIAS_BLEU_PT, "bleu_pt" },
+	{ SPARC_INS_ALIAS_BLEU_A_PT, "bleu_a_pt" },
+	{ SPARC_INS_ALIAS_BLEU_PN, "bleu_pn" },
+	{ SPARC_INS_ALIAS_BLEU_A_PN, "bleu_a_pn" },
+	{ SPARC_INS_ALIAS_MOVLEU, "movleu" },
+	{ SPARC_INS_ALIAS_FMOVSLEU, "fmovsleu" },
+	{ SPARC_INS_ALIAS_FMOVDLEU, "fmovdleu" },
+	{ SPARC_INS_ALIAS_FMOVQLEU, "fmovqleu" },
+	{ SPARC_INS_ALIAS_TLEU, "tleu" },
+	{ SPARC_INS_ALIAS_BCC, "bcc" },
+	{ SPARC_INS_ALIAS_BCC_A, "bcc_a" },
+	{ SPARC_INS_ALIAS_BCC_PT, "bcc_pt" },
+	{ SPARC_INS_ALIAS_BCC_A_PT, "bcc_a_pt" },
+	{ SPARC_INS_ALIAS_BCC_PN, "bcc_pn" },
+	{ SPARC_INS_ALIAS_BCC_A_PN, "bcc_a_pn" },
+	{ SPARC_INS_ALIAS_MOVCC, "movcc" },
+	{ SPARC_INS_ALIAS_FMOVSCC, "fmovscc" },
+	{ SPARC_INS_ALIAS_FMOVDCC, "fmovdcc" },
+	{ SPARC_INS_ALIAS_FMOVQCC, "fmovqcc" },
+	{ SPARC_INS_ALIAS_TCC, "tcc" },
+	{ SPARC_INS_ALIAS_BCS, "bcs" },
+	{ SPARC_INS_ALIAS_BCS_A, "bcs_a" },
+	{ SPARC_INS_ALIAS_BCS_PT, "bcs_pt" },
+	{ SPARC_INS_ALIAS_BCS_A_PT, "bcs_a_pt" },
+	{ SPARC_INS_ALIAS_BCS_PN, "bcs_pn" },
+	{ SPARC_INS_ALIAS_BCS_A_PN, "bcs_a_pn" },
+	{ SPARC_INS_ALIAS_MOVCS, "movcs" },
+	{ SPARC_INS_ALIAS_FMOVSCS, "fmovscs" },
+	{ SPARC_INS_ALIAS_FMOVDCS, "fmovdcs" },
+	{ SPARC_INS_ALIAS_FMOVQCS, "fmovqcs" },
+	{ SPARC_INS_ALIAS_TCS, "tcs" },
+	{ SPARC_INS_ALIAS_BPOS, "bpos" },
+	{ SPARC_INS_ALIAS_BPOS_A, "bpos_a" },
+	{ SPARC_INS_ALIAS_BPOS_PT, "bpos_pt" },
+	{ SPARC_INS_ALIAS_BPOS_A_PT, "bpos_a_pt" },
+	{ SPARC_INS_ALIAS_BPOS_PN, "bpos_pn" },
+	{ SPARC_INS_ALIAS_BPOS_A_PN, "bpos_a_pn" },
+	{ SPARC_INS_ALIAS_MOVPOS, "movpos" },
+	{ SPARC_INS_ALIAS_FMOVSPOS, "fmovspos" },
+	{ SPARC_INS_ALIAS_FMOVDPOS, "fmovdpos" },
+	{ SPARC_INS_ALIAS_FMOVQPOS, "fmovqpos" },
+	{ SPARC_INS_ALIAS_TPOS, "tpos" },
+	{ SPARC_INS_ALIAS_BNEG, "bneg" },
+	{ SPARC_INS_ALIAS_BNEG_A, "bneg_a" },
+	{ SPARC_INS_ALIAS_BNEG_PT, "bneg_pt" },
+	{ SPARC_INS_ALIAS_BNEG_A_PT, "bneg_a_pt" },
+	{ SPARC_INS_ALIAS_BNEG_PN, "bneg_pn" },
+	{ SPARC_INS_ALIAS_BNEG_A_PN, "bneg_a_pn" },
+	{ SPARC_INS_ALIAS_MOVNEG, "movneg" },
+	{ SPARC_INS_ALIAS_FMOVSNEG, "fmovsneg" },
+	{ SPARC_INS_ALIAS_FMOVDNEG, "fmovdneg" },
+	{ SPARC_INS_ALIAS_FMOVQNEG, "fmovqneg" },
+	{ SPARC_INS_ALIAS_TNEG, "tneg" },
+	{ SPARC_INS_ALIAS_BVC, "bvc" },
+	{ SPARC_INS_ALIAS_BVC_A, "bvc_a" },
+	{ SPARC_INS_ALIAS_BVC_PT, "bvc_pt" },
+	{ SPARC_INS_ALIAS_BVC_A_PT, "bvc_a_pt" },
+	{ SPARC_INS_ALIAS_BVC_PN, "bvc_pn" },
+	{ SPARC_INS_ALIAS_BVC_A_PN, "bvc_a_pn" },
+	{ SPARC_INS_ALIAS_MOVVC, "movvc" },
+	{ SPARC_INS_ALIAS_FMOVSVC, "fmovsvc" },
+	{ SPARC_INS_ALIAS_FMOVDVC, "fmovdvc" },
+	{ SPARC_INS_ALIAS_FMOVQVC, "fmovqvc" },
+	{ SPARC_INS_ALIAS_TVC, "tvc" },
+	{ SPARC_INS_ALIAS_BVS, "bvs" },
+	{ SPARC_INS_ALIAS_BVS_A, "bvs_a" },
+	{ SPARC_INS_ALIAS_BVS_PT, "bvs_pt" },
+	{ SPARC_INS_ALIAS_BVS_A_PT, "bvs_a_pt" },
+	{ SPARC_INS_ALIAS_BVS_PN, "bvs_pn" },
+	{ SPARC_INS_ALIAS_BVS_A_PN, "bvs_a_pn" },
+	{ SPARC_INS_ALIAS_MOVVS, "movvs" },
+	{ SPARC_INS_ALIAS_FMOVSVS, "fmovsvs" },
+	{ SPARC_INS_ALIAS_FMOVDVS, "fmovdvs" },
+	{ SPARC_INS_ALIAS_FMOVQVS, "fmovqvs" },
+	{ SPARC_INS_ALIAS_TVS, "tvs" },
+	{ SPARC_INS_ALIAS_FBN, "fbn" },
+	{ SPARC_INS_ALIAS_FBN_PT, "fbn_pt" },
+	{ SPARC_INS_ALIAS_FBN_A, "fbn_a" },
+	{ SPARC_INS_ALIAS_FBN_A_PT, "fbn_a_pt" },
+	{ SPARC_INS_ALIAS_FBN_PN, "fbn_pn" },
+	{ SPARC_INS_ALIAS_FBN_A_PN, "fbn_a_pn" },
+	{ SPARC_INS_ALIAS_FBU, "fbu" },
+	{ SPARC_INS_ALIAS_FBU_PT, "fbu_pt" },
+	{ SPARC_INS_ALIAS_FBU_A, "fbu_a" },
+	{ SPARC_INS_ALIAS_FBU_A_PT, "fbu_a_pt" },
+	{ SPARC_INS_ALIAS_FBU_PN, "fbu_pn" },
+	{ SPARC_INS_ALIAS_FBU_A_PN, "fbu_a_pn" },
+	{ SPARC_INS_ALIAS_MOVU, "movu" },
+	{ SPARC_INS_ALIAS_FMOVSU, "fmovsu" },
+	{ SPARC_INS_ALIAS_FMOVDU, "fmovdu" },
+	{ SPARC_INS_ALIAS_FMOVQU, "fmovqu" },
+	{ SPARC_INS_ALIAS_FBG, "fbg" },
+	{ SPARC_INS_ALIAS_FBG_PT, "fbg_pt" },
+	{ SPARC_INS_ALIAS_FBG_A, "fbg_a" },
+	{ SPARC_INS_ALIAS_FBG_A_PT, "fbg_a_pt" },
+	{ SPARC_INS_ALIAS_FBG_PN, "fbg_pn" },
+	{ SPARC_INS_ALIAS_FBG_A_PN, "fbg_a_pn" },
+	{ SPARC_INS_ALIAS_FBUG, "fbug" },
+	{ SPARC_INS_ALIAS_FBUG_PT, "fbug_pt" },
+	{ SPARC_INS_ALIAS_FBUG_A, "fbug_a" },
+	{ SPARC_INS_ALIAS_FBUG_A_PT, "fbug_a_pt" },
+	{ SPARC_INS_ALIAS_FBUG_PN, "fbug_pn" },
+	{ SPARC_INS_ALIAS_FBUG_A_PN, "fbug_a_pn" },
+	{ SPARC_INS_ALIAS_MOVUG, "movug" },
+	{ SPARC_INS_ALIAS_FMOVSUG, "fmovsug" },
+	{ SPARC_INS_ALIAS_FMOVDUG, "fmovdug" },
+	{ SPARC_INS_ALIAS_FMOVQUG, "fmovqug" },
+	{ SPARC_INS_ALIAS_FBL, "fbl" },
+	{ SPARC_INS_ALIAS_FBL_PT, "fbl_pt" },
+	{ SPARC_INS_ALIAS_FBL_A, "fbl_a" },
+	{ SPARC_INS_ALIAS_FBL_A_PT, "fbl_a_pt" },
+	{ SPARC_INS_ALIAS_FBL_PN, "fbl_pn" },
+	{ SPARC_INS_ALIAS_FBL_A_PN, "fbl_a_pn" },
+	{ SPARC_INS_ALIAS_FBUL, "fbul" },
+	{ SPARC_INS_ALIAS_FBUL_PT, "fbul_pt" },
+	{ SPARC_INS_ALIAS_FBUL_A, "fbul_a" },
+	{ SPARC_INS_ALIAS_FBUL_A_PT, "fbul_a_pt" },
+	{ SPARC_INS_ALIAS_FBUL_PN, "fbul_pn" },
+	{ SPARC_INS_ALIAS_FBUL_A_PN, "fbul_a_pn" },
+	{ SPARC_INS_ALIAS_MOVUL, "movul" },
+	{ SPARC_INS_ALIAS_FMOVSUL, "fmovsul" },
+	{ SPARC_INS_ALIAS_FMOVDUL, "fmovdul" },
+	{ SPARC_INS_ALIAS_FMOVQUL, "fmovqul" },
+	{ SPARC_INS_ALIAS_FBLG, "fblg" },
+	{ SPARC_INS_ALIAS_FBLG_PT, "fblg_pt" },
+	{ SPARC_INS_ALIAS_FBLG_A, "fblg_a" },
+	{ SPARC_INS_ALIAS_FBLG_A_PT, "fblg_a_pt" },
+	{ SPARC_INS_ALIAS_FBLG_PN, "fblg_pn" },
+	{ SPARC_INS_ALIAS_FBLG_A_PN, "fblg_a_pn" },
+	{ SPARC_INS_ALIAS_MOVLG, "movlg" },
+	{ SPARC_INS_ALIAS_FMOVSLG, "fmovslg" },
+	{ SPARC_INS_ALIAS_FMOVDLG, "fmovdlg" },
+	{ SPARC_INS_ALIAS_FMOVQLG, "fmovqlg" },
+	{ SPARC_INS_ALIAS_FBNE, "fbne" },
+	{ SPARC_INS_ALIAS_FBNE_PT, "fbne_pt" },
+	{ SPARC_INS_ALIAS_FBNE_A, "fbne_a" },
+	{ SPARC_INS_ALIAS_FBNE_A_PT, "fbne_a_pt" },
+	{ SPARC_INS_ALIAS_FBNE_PN, "fbne_pn" },
+	{ SPARC_INS_ALIAS_FBNE_A_PN, "fbne_a_pn" },
+	{ SPARC_INS_ALIAS_FBE, "fbe" },
+	{ SPARC_INS_ALIAS_FBE_PT, "fbe_pt" },
+	{ SPARC_INS_ALIAS_FBE_A, "fbe_a" },
+	{ SPARC_INS_ALIAS_FBE_A_PT, "fbe_a_pt" },
+	{ SPARC_INS_ALIAS_FBE_PN, "fbe_pn" },
+	{ SPARC_INS_ALIAS_FBE_A_PN, "fbe_a_pn" },
+	{ SPARC_INS_ALIAS_FBUE, "fbue" },
+	{ SPARC_INS_ALIAS_FBUE_PT, "fbue_pt" },
+	{ SPARC_INS_ALIAS_FBUE_A, "fbue_a" },
+	{ SPARC_INS_ALIAS_FBUE_A_PT, "fbue_a_pt" },
+	{ SPARC_INS_ALIAS_FBUE_PN, "fbue_pn" },
+	{ SPARC_INS_ALIAS_FBUE_A_PN, "fbue_a_pn" },
+	{ SPARC_INS_ALIAS_MOVUE, "movue" },
+	{ SPARC_INS_ALIAS_FMOVSUE, "fmovsue" },
+	{ SPARC_INS_ALIAS_FMOVDUE, "fmovdue" },
+	{ SPARC_INS_ALIAS_FMOVQUE, "fmovque" },
+	{ SPARC_INS_ALIAS_FBGE, "fbge" },
+	{ SPARC_INS_ALIAS_FBGE_PT, "fbge_pt" },
+	{ SPARC_INS_ALIAS_FBGE_A, "fbge_a" },
+	{ SPARC_INS_ALIAS_FBGE_A_PT, "fbge_a_pt" },
+	{ SPARC_INS_ALIAS_FBGE_PN, "fbge_pn" },
+	{ SPARC_INS_ALIAS_FBGE_A_PN, "fbge_a_pn" },
+	{ SPARC_INS_ALIAS_FBUGE, "fbuge" },
+	{ SPARC_INS_ALIAS_FBUGE_PT, "fbuge_pt" },
+	{ SPARC_INS_ALIAS_FBUGE_A, "fbuge_a" },
+	{ SPARC_INS_ALIAS_FBUGE_A_PT, "fbuge_a_pt" },
+	{ SPARC_INS_ALIAS_FBUGE_PN, "fbuge_pn" },
+	{ SPARC_INS_ALIAS_FBUGE_A_PN, "fbuge_a_pn" },
+	{ SPARC_INS_ALIAS_MOVUGE, "movuge" },
+	{ SPARC_INS_ALIAS_FMOVSUGE, "fmovsuge" },
+	{ SPARC_INS_ALIAS_FMOVDUGE, "fmovduge" },
+	{ SPARC_INS_ALIAS_FMOVQUGE, "fmovquge" },
+	{ SPARC_INS_ALIAS_FBLE, "fble" },
+	{ SPARC_INS_ALIAS_FBLE_PT, "fble_pt" },
+	{ SPARC_INS_ALIAS_FBLE_A, "fble_a" },
+	{ SPARC_INS_ALIAS_FBLE_A_PT, "fble_a_pt" },
+	{ SPARC_INS_ALIAS_FBLE_PN, "fble_pn" },
+	{ SPARC_INS_ALIAS_FBLE_A_PN, "fble_a_pn" },
+	{ SPARC_INS_ALIAS_FBULE, "fbule" },
+	{ SPARC_INS_ALIAS_FBULE_PT, "fbule_pt" },
+	{ SPARC_INS_ALIAS_FBULE_A, "fbule_a" },
+	{ SPARC_INS_ALIAS_FBULE_A_PT, "fbule_a_pt" },
+	{ SPARC_INS_ALIAS_FBULE_PN, "fbule_pn" },
+	{ SPARC_INS_ALIAS_FBULE_A_PN, "fbule_a_pn" },
+	{ SPARC_INS_ALIAS_MOVULE, "movule" },
+	{ SPARC_INS_ALIAS_FMOVSULE, "fmovsule" },
+	{ SPARC_INS_ALIAS_FMOVDULE, "fmovdule" },
+	{ SPARC_INS_ALIAS_FMOVQULE, "fmovqule" },
+	{ SPARC_INS_ALIAS_FBO, "fbo" },
+	{ SPARC_INS_ALIAS_FBO_PT, "fbo_pt" },
+	{ SPARC_INS_ALIAS_FBO_A, "fbo_a" },
+	{ SPARC_INS_ALIAS_FBO_A_PT, "fbo_a_pt" },
+	{ SPARC_INS_ALIAS_FBO_PN, "fbo_pn" },
+	{ SPARC_INS_ALIAS_FBO_A_PN, "fbo_a_pn" },
+	{ SPARC_INS_ALIAS_MOVO, "movo" },
+	{ SPARC_INS_ALIAS_FMOVSO, "fmovso" },
+	{ SPARC_INS_ALIAS_FMOVDO, "fmovdo" },
+	{ SPARC_INS_ALIAS_FMOVQO, "fmovqo" },
+	{ SPARC_INS_ALIAS_BRLEZ, "brlez" },
+	{ SPARC_INS_ALIAS_BRLEZ_PT, "brlez_pt" },
+	{ SPARC_INS_ALIAS_BRLEZ_PN, "brlez_pn" },
+	{ SPARC_INS_ALIAS_BRLEZ_A, "brlez_a" },
+	{ SPARC_INS_ALIAS_BRLEZ_A_PT, "brlez_a_pt" },
+	{ SPARC_INS_ALIAS_BRLEZ_A_PN, "brlez_a_pn" },
+	{ SPARC_INS_ALIAS_MOVRLEZ, "movrlez" },
+	{ SPARC_INS_ALIAS_FMOVRSLEZ, "fmovrslez" },
+	{ SPARC_INS_ALIAS_FMOVRDLEZ, "fmovrdlez" },
+	{ SPARC_INS_ALIAS_FMOVRQLEZ, "fmovrqlez" },
+	{ SPARC_INS_ALIAS_BRLZ, "brlz" },
+	{ SPARC_INS_ALIAS_BRLZ_PT, "brlz_pt" },
+	{ SPARC_INS_ALIAS_BRLZ_PN, "brlz_pn" },
+	{ SPARC_INS_ALIAS_BRLZ_A, "brlz_a" },
+	{ SPARC_INS_ALIAS_BRLZ_A_PT, "brlz_a_pt" },
+	{ SPARC_INS_ALIAS_BRLZ_A_PN, "brlz_a_pn" },
+	{ SPARC_INS_ALIAS_MOVRLZ, "movrlz" },
+	{ SPARC_INS_ALIAS_FMOVRSLZ, "fmovrslz" },
+	{ SPARC_INS_ALIAS_FMOVRDLZ, "fmovrdlz" },
+	{ SPARC_INS_ALIAS_FMOVRQLZ, "fmovrqlz" },
+	{ SPARC_INS_ALIAS_BRNZ, "brnz" },
+	{ SPARC_INS_ALIAS_BRNZ_PT, "brnz_pt" },
+	{ SPARC_INS_ALIAS_BRNZ_PN, "brnz_pn" },
+	{ SPARC_INS_ALIAS_BRNZ_A, "brnz_a" },
+	{ SPARC_INS_ALIAS_BRNZ_A_PT, "brnz_a_pt" },
+	{ SPARC_INS_ALIAS_BRNZ_A_PN, "brnz_a_pn" },
+	{ SPARC_INS_ALIAS_MOVRNZ, "movrnz" },
+	{ SPARC_INS_ALIAS_FMOVRSNZ, "fmovrsnz" },
+	{ SPARC_INS_ALIAS_FMOVRDNZ, "fmovrdnz" },
+	{ SPARC_INS_ALIAS_FMOVRQNZ, "fmovrqnz" },
+	{ SPARC_INS_ALIAS_BRGZ, "brgz" },
+	{ SPARC_INS_ALIAS_BRGZ_PT, "brgz_pt" },
+	{ SPARC_INS_ALIAS_BRGZ_PN, "brgz_pn" },
+	{ SPARC_INS_ALIAS_BRGZ_A, "brgz_a" },
+	{ SPARC_INS_ALIAS_BRGZ_A_PT, "brgz_a_pt" },
+	{ SPARC_INS_ALIAS_BRGZ_A_PN, "brgz_a_pn" },
+	{ SPARC_INS_ALIAS_MOVRGZ, "movrgz" },
+	{ SPARC_INS_ALIAS_FMOVRSGZ, "fmovrsgz" },
+	{ SPARC_INS_ALIAS_FMOVRDGZ, "fmovrdgz" },
+	{ SPARC_INS_ALIAS_FMOVRQGZ, "fmovrqgz" },
+	{ SPARC_INS_ALIAS_BRGEZ, "brgez" },
+	{ SPARC_INS_ALIAS_BRGEZ_PT, "brgez_pt" },
+	{ SPARC_INS_ALIAS_BRGEZ_PN, "brgez_pn" },
+	{ SPARC_INS_ALIAS_BRGEZ_A, "brgez_a" },
+	{ SPARC_INS_ALIAS_BRGEZ_A_PT, "brgez_a_pt" },
+	{ SPARC_INS_ALIAS_BRGEZ_A_PN, "brgez_a_pn" },
+	{ SPARC_INS_ALIAS_MOVRGEZ, "movrgez" },
+	{ SPARC_INS_ALIAS_FMOVRSGEZ, "fmovrsgez" },
+	{ SPARC_INS_ALIAS_FMOVRDGEZ, "fmovrdgez" },
+	{ SPARC_INS_ALIAS_FMOVRQGEZ, "fmovrqgez" },
+	{ SPARC_INS_ALIAS_CMP, "cmp" },
+	{ SPARC_INS_ALIAS_TST, "tst" },
+	{ SPARC_INS_ALIAS_RET, "ret" },
+	{ SPARC_INS_ALIAS_RETL, "retl" },
+	{ SPARC_INS_ALIAS_RESTORE, "restore" },
+	{ SPARC_INS_ALIAS_SAVE, "save" },
+	{ SPARC_INS_ALIAS_CAS, "cas" },
+	{ SPARC_INS_ALIAS_CASL, "casl" },
+	{ SPARC_INS_ALIAS_CASX, "casx" },
+	{ SPARC_INS_ALIAS_CASXL, "casxl" },
+	{ SPARC_INS_ALIAS_MOV, "mov" },
+	{ SPARC_INS_ALIAS_FCMPS, "fcmps" },
+	{ SPARC_INS_ALIAS_FCMPD, "fcmpd" },
+	{ SPARC_INS_ALIAS_FCMPQ, "fcmpq" },
+	{ SPARC_INS_ALIAS_FCMPES, "fcmpes" },
+	{ SPARC_INS_ALIAS_FCMPED, "fcmped" },
+	{ SPARC_INS_ALIAS_FCMPEQ, "fcmpeq" },

external/capstone/arch/Sparc/SparcGenCSFeatureName.inc

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ SPARC_FEATURE_IS64BIT, "Is64Bit" },
+{ SPARC_FEATURE_USESOFTMULDIV, "UseSoftMulDiv" },
+{ SPARC_FEATURE_HASV9, "HasV9" },
+{ SPARC_FEATURE_HASVIS, "HasVIS" },
+{ SPARC_FEATURE_HASVIS2, "HasVIS2" },
+{ SPARC_FEATURE_HASVIS3, "HasVIS3" },
+{ SPARC_FEATURE_HASCASA, "HasCASA" },
+{ SPARC_FEATURE_HASPWRPSR, "HasPWRPSR" },

external/capstone/arch/Sparc/SparcGenCSMappingInsnName.inc

@@ -0,0 +1,298 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // SPARC_INS_INVALID
+  "set", // SPARC_INS_SET
+  "setx", // SPARC_INS_SETX
+  "addcc", // SPARC_INS_ADDCC
+  "addx", // SPARC_INS_ADDX
+  "addxcc", // SPARC_INS_ADDXCC
+  "addxc", // SPARC_INS_ADDXC
+  "addxccc", // SPARC_INS_ADDXCCC
+  "add", // SPARC_INS_ADD
+  "alignaddr", // SPARC_INS_ALIGNADDR
+  "alignaddrl", // SPARC_INS_ALIGNADDRL
+  "andcc", // SPARC_INS_ANDCC
+  "andncc", // SPARC_INS_ANDNCC
+  "andn", // SPARC_INS_ANDN
+  "and", // SPARC_INS_AND
+  "array16", // SPARC_INS_ARRAY16
+  "array32", // SPARC_INS_ARRAY32
+  "array8", // SPARC_INS_ARRAY8
+  "b", // SPARC_INS_B
+  "bmask", // SPARC_INS_BMASK
+  "fb", // SPARC_INS_FB
+  "br", // SPARC_INS_BR
+  "bshuffle", // SPARC_INS_BSHUFFLE
+  "call", // SPARC_INS_CALL
+  "casa", // SPARC_INS_CASA
+  "casxa", // SPARC_INS_CASXA
+  "cb", // SPARC_INS_CB
+  "cmask16", // SPARC_INS_CMASK16
+  "cmask32", // SPARC_INS_CMASK32
+  "cmask8", // SPARC_INS_CMASK8
+  "done", // SPARC_INS_DONE
+  "edge16", // SPARC_INS_EDGE16
+  "edge16l", // SPARC_INS_EDGE16L
+  "edge16ln", // SPARC_INS_EDGE16LN
+  "edge16n", // SPARC_INS_EDGE16N
+  "edge32", // SPARC_INS_EDGE32
+  "edge32l", // SPARC_INS_EDGE32L
+  "edge32ln", // SPARC_INS_EDGE32LN
+  "edge32n", // SPARC_INS_EDGE32N
+  "edge8", // SPARC_INS_EDGE8
+  "edge8l", // SPARC_INS_EDGE8L
+  "edge8ln", // SPARC_INS_EDGE8LN
+  "edge8n", // SPARC_INS_EDGE8N
+  "fabsd", // SPARC_INS_FABSD
+  "fabsq", // SPARC_INS_FABSQ
+  "fabss", // SPARC_INS_FABSS
+  "faddd", // SPARC_INS_FADDD
+  "faddq", // SPARC_INS_FADDQ
+  "fadds", // SPARC_INS_FADDS
+  "faligndata", // SPARC_INS_FALIGNDATA
+  "fand", // SPARC_INS_FAND
+  "fandnot1", // SPARC_INS_FANDNOT1
+  "fandnot1s", // SPARC_INS_FANDNOT1S
+  "fandnot2", // SPARC_INS_FANDNOT2
+  "fandnot2s", // SPARC_INS_FANDNOT2S
+  "fands", // SPARC_INS_FANDS
+  "fchksm16", // SPARC_INS_FCHKSM16
+  "fcmpeq16", // SPARC_INS_FCMPEQ16
+  "fcmpeq32", // SPARC_INS_FCMPEQ32
+  "fcmpgt16", // SPARC_INS_FCMPGT16
+  "fcmpgt32", // SPARC_INS_FCMPGT32
+  "fcmple16", // SPARC_INS_FCMPLE16
+  "fcmple32", // SPARC_INS_FCMPLE32
+  "fcmpne16", // SPARC_INS_FCMPNE16
+  "fcmpne32", // SPARC_INS_FCMPNE32
+  "fdivd", // SPARC_INS_FDIVD
+  "fdivq", // SPARC_INS_FDIVQ
+  "fdivs", // SPARC_INS_FDIVS
+  "fdmulq", // SPARC_INS_FDMULQ
+  "fdtoi", // SPARC_INS_FDTOI
+  "fdtoq", // SPARC_INS_FDTOQ
+  "fdtos", // SPARC_INS_FDTOS
+  "fdtox", // SPARC_INS_FDTOX
+  "fexpand", // SPARC_INS_FEXPAND
+  "fhaddd", // SPARC_INS_FHADDD
+  "fhadds", // SPARC_INS_FHADDS
+  "fhsubd", // SPARC_INS_FHSUBD
+  "fhsubs", // SPARC_INS_FHSUBS
+  "fitod", // SPARC_INS_FITOD
+  "fitoq", // SPARC_INS_FITOQ
+  "fitos", // SPARC_INS_FITOS
+  "flcmpd", // SPARC_INS_FLCMPD
+  "flcmps", // SPARC_INS_FLCMPS
+  "flush", // SPARC_INS_FLUSH
+  "flushw", // SPARC_INS_FLUSHW
+  "fmean16", // SPARC_INS_FMEAN16
+  "fmovd", // SPARC_INS_FMOVD
+  "fmovq", // SPARC_INS_FMOVQ
+  "fmovrd", // SPARC_INS_FMOVRD
+  "fmovrq", // SPARC_INS_FMOVRQ
+  "fmovrs", // SPARC_INS_FMOVRS
+  "fmovs", // SPARC_INS_FMOVS
+  "fmul8sux16", // SPARC_INS_FMUL8SUX16
+  "fmul8ulx16", // SPARC_INS_FMUL8ULX16
+  "fmul8x16", // SPARC_INS_FMUL8X16
+  "fmul8x16al", // SPARC_INS_FMUL8X16AL
+  "fmul8x16au", // SPARC_INS_FMUL8X16AU
+  "fmuld", // SPARC_INS_FMULD
+  "fmuld8sux16", // SPARC_INS_FMULD8SUX16
+  "fmuld8ulx16", // SPARC_INS_FMULD8ULX16
+  "fmulq", // SPARC_INS_FMULQ
+  "fmuls", // SPARC_INS_FMULS
+  "fnaddd", // SPARC_INS_FNADDD
+  "fnadds", // SPARC_INS_FNADDS
+  "fnand", // SPARC_INS_FNAND
+  "fnands", // SPARC_INS_FNANDS
+  "fnegd", // SPARC_INS_FNEGD
+  "fnegq", // SPARC_INS_FNEGQ
+  "fnegs", // SPARC_INS_FNEGS
+  "fnhaddd", // SPARC_INS_FNHADDD
+  "fnhadds", // SPARC_INS_FNHADDS
+  "fnor", // SPARC_INS_FNOR
+  "fnors", // SPARC_INS_FNORS
+  "fnot1", // SPARC_INS_FNOT1
+  "fnot1s", // SPARC_INS_FNOT1S
+  "fnot2", // SPARC_INS_FNOT2
+  "fnot2s", // SPARC_INS_FNOT2S
+  "fone", // SPARC_INS_FONE
+  "fones", // SPARC_INS_FONES
+  "for", // SPARC_INS_FOR
+  "fornot1", // SPARC_INS_FORNOT1
+  "fornot1s", // SPARC_INS_FORNOT1S
+  "fornot2", // SPARC_INS_FORNOT2
+  "fornot2s", // SPARC_INS_FORNOT2S
+  "fors", // SPARC_INS_FORS
+  "fpack16", // SPARC_INS_FPACK16
+  "fpack32", // SPARC_INS_FPACK32
+  "fpackfix", // SPARC_INS_FPACKFIX
+  "fpadd16", // SPARC_INS_FPADD16
+  "fpadd16s", // SPARC_INS_FPADD16S
+  "fpadd32", // SPARC_INS_FPADD32
+  "fpadd32s", // SPARC_INS_FPADD32S
+  "fpadd64", // SPARC_INS_FPADD64
+  "fpmerge", // SPARC_INS_FPMERGE
+  "fpsub16", // SPARC_INS_FPSUB16
+  "fpsub16S", // SPARC_INS_FPSUB16S
+  "fpsub32", // SPARC_INS_FPSUB32
+  "fpsub32S", // SPARC_INS_FPSUB32S
+  "fqtod", // SPARC_INS_FQTOD
+  "fqtoi", // SPARC_INS_FQTOI
+  "fqtos", // SPARC_INS_FQTOS
+  "fqtox", // SPARC_INS_FQTOX
+  "fslas16", // SPARC_INS_FSLAS16
+  "fslas32", // SPARC_INS_FSLAS32
+  "fsll16", // SPARC_INS_FSLL16
+  "fsll32", // SPARC_INS_FSLL32
+  "fsmuld", // SPARC_INS_FSMULD
+  "fsqrtd", // SPARC_INS_FSQRTD
+  "fsqrtq", // SPARC_INS_FSQRTQ
+  "fsqrts", // SPARC_INS_FSQRTS
+  "fsra16", // SPARC_INS_FSRA16
+  "fsra32", // SPARC_INS_FSRA32
+  "fsrc1", // SPARC_INS_FSRC1
+  "fsrc1s", // SPARC_INS_FSRC1S
+  "fsrc2", // SPARC_INS_FSRC2
+  "fsrc2s", // SPARC_INS_FSRC2S
+  "fsrl16", // SPARC_INS_FSRL16
+  "fsrl32", // SPARC_INS_FSRL32
+  "fstod", // SPARC_INS_FSTOD
+  "fstoi", // SPARC_INS_FSTOI
+  "fstoq", // SPARC_INS_FSTOQ
+  "fstox", // SPARC_INS_FSTOX
+  "fsubd", // SPARC_INS_FSUBD
+  "fsubq", // SPARC_INS_FSUBQ
+  "fsubs", // SPARC_INS_FSUBS
+  "fxnor", // SPARC_INS_FXNOR
+  "fxnors", // SPARC_INS_FXNORS
+  "fxor", // SPARC_INS_FXOR
+  "fxors", // SPARC_INS_FXORS
+  "fxtod", // SPARC_INS_FXTOD
+  "fxtoq", // SPARC_INS_FXTOQ
+  "fxtos", // SPARC_INS_FXTOS
+  "fzero", // SPARC_INS_FZERO
+  "fzeros", // SPARC_INS_FZEROS
+  "ldx", // SPARC_INS_LDX
+  "ld", // SPARC_INS_LD
+  "jmpl", // SPARC_INS_JMPL
+  "lda", // SPARC_INS_LDA
+  "ldda", // SPARC_INS_LDDA
+  "ldd", // SPARC_INS_LDD
+  "ldqa", // SPARC_INS_LDQA
+  "ldq", // SPARC_INS_LDQ
+  "ldsba", // SPARC_INS_LDSBA
+  "ldsb", // SPARC_INS_LDSB
+  "ldsha", // SPARC_INS_LDSHA
+  "ldsh", // SPARC_INS_LDSH
+  "ldstuba", // SPARC_INS_LDSTUBA
+  "ldstub", // SPARC_INS_LDSTUB
+  "ldswa", // SPARC_INS_LDSWA
+  "ldsw", // SPARC_INS_LDSW
+  "lduba", // SPARC_INS_LDUBA
+  "ldub", // SPARC_INS_LDUB
+  "lduha", // SPARC_INS_LDUHA
+  "lduh", // SPARC_INS_LDUH
+  "ldxa", // SPARC_INS_LDXA
+  "lzcnt", // SPARC_INS_LZCNT
+  "membar", // SPARC_INS_MEMBAR
+  "movdtox", // SPARC_INS_MOVDTOX
+  "mov", // SPARC_INS_MOV
+  "movr", // SPARC_INS_MOVR
+  "movstosw", // SPARC_INS_MOVSTOSW
+  "movstouw", // SPARC_INS_MOVSTOUW
+  "mulscc", // SPARC_INS_MULSCC
+  "mulx", // SPARC_INS_MULX
+  "nop", // SPARC_INS_NOP
+  "orcc", // SPARC_INS_ORCC
+  "orncc", // SPARC_INS_ORNCC
+  "orn", // SPARC_INS_ORN
+  "or", // SPARC_INS_OR
+  "pdist", // SPARC_INS_PDIST
+  "pdistn", // SPARC_INS_PDISTN
+  "popc", // SPARC_INS_POPC
+  "prefetch", // SPARC_INS_PREFETCH
+  "pwr", // SPARC_INS_PWR
+  "rd", // SPARC_INS_RD
+  "rdpr", // SPARC_INS_RDPR
+  "restored", // SPARC_INS_RESTORED
+  "restore", // SPARC_INS_RESTORE
+  "retry", // SPARC_INS_RETRY
+  "rett", // SPARC_INS_RETT
+  "saved", // SPARC_INS_SAVED
+  "save", // SPARC_INS_SAVE
+  "sdivcc", // SPARC_INS_SDIVCC
+  "sdivx", // SPARC_INS_SDIVX
+  "sdiv", // SPARC_INS_SDIV
+  "sethi", // SPARC_INS_SETHI
+  "shutdown", // SPARC_INS_SHUTDOWN
+  "siam", // SPARC_INS_SIAM
+  "sir", // SPARC_INS_SIR
+  "sllx", // SPARC_INS_SLLX
+  "sll", // SPARC_INS_SLL
+  "smac", // SPARC_INS_SMAC
+  "smulcc", // SPARC_INS_SMULCC
+  "smul", // SPARC_INS_SMUL
+  "srax", // SPARC_INS_SRAX
+  "sra", // SPARC_INS_SRA
+  "srlx", // SPARC_INS_SRLX
+  "srl", // SPARC_INS_SRL
+  "sta", // SPARC_INS_STA
+  "stbar", // SPARC_INS_STBAR
+  "stba", // SPARC_INS_STBA
+  "stb", // SPARC_INS_STB
+  "st", // SPARC_INS_ST
+  "stda", // SPARC_INS_STDA
+  "std", // SPARC_INS_STD
+  "stha", // SPARC_INS_STHA
+  "sth", // SPARC_INS_STH
+  "stqa", // SPARC_INS_STQA
+  "stq", // SPARC_INS_STQ
+  "stxa", // SPARC_INS_STXA
+  "stx", // SPARC_INS_STX
+  "subcc", // SPARC_INS_SUBCC
+  "subx", // SPARC_INS_SUBX
+  "subxcc", // SPARC_INS_SUBXCC
+  "sub", // SPARC_INS_SUB
+  "swapa", // SPARC_INS_SWAPA
+  "swap", // SPARC_INS_SWAP
+  "ta", // SPARC_INS_TA
+  "taddcctv", // SPARC_INS_TADDCCTV
+  "taddcc", // SPARC_INS_TADDCC
+  "t", // SPARC_INS_T
+  "tsubcctv", // SPARC_INS_TSUBCCTV
+  "tsubcc", // SPARC_INS_TSUBCC
+  "udivcc", // SPARC_INS_UDIVCC
+  "udivx", // SPARC_INS_UDIVX
+  "udiv", // SPARC_INS_UDIV
+  "umac", // SPARC_INS_UMAC
+  "umulcc", // SPARC_INS_UMULCC
+  "umulxhi", // SPARC_INS_UMULXHI
+  "umul", // SPARC_INS_UMUL
+  "unimp", // SPARC_INS_UNIMP
+  "fcmpd", // SPARC_INS_FCMPD
+  "fcmped", // SPARC_INS_FCMPED
+  "fcmpeq", // SPARC_INS_FCMPEQ
+  "fcmpes", // SPARC_INS_FCMPES
+  "fcmpq", // SPARC_INS_FCMPQ
+  "fcmps", // SPARC_INS_FCMPS
+  "wr", // SPARC_INS_WR
+  "wrpr", // SPARC_INS_WRPR
+  "xmulx", // SPARC_INS_XMULX
+  "xmulxhi", // SPARC_INS_XMULXHI
+  "xnorcc", // SPARC_INS_XNORCC
+  "xnor", // SPARC_INS_XNOR
+  "xorcc", // SPARC_INS_XORCC
+  "xor", // SPARC_INS_XOR

external/capstone/arch/Sparc/SparcGenCSOpGroup.inc

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  Sparc_OP_GROUP_Operand = 0,
+  Sparc_OP_GROUP_GetPCX = 1,
+  Sparc_OP_GROUP_CCOperand = 2,
+  Sparc_OP_GROUP_MemOperand = 3,
+  Sparc_OP_GROUP_ASITag = 4,
+  Sparc_OP_GROUP_MembarTag = 5,

external/capstone/arch/Sparc/SparcGenSubtargetInfo.inc

@@ -0,0 +1,70 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  Sparc_DetectRoundChange = 0,
+  Sparc_FeatureHardQuad = 1,
+  Sparc_FeatureLeon = 2,
+  Sparc_FeatureNoFMULS = 3,
+  Sparc_FeatureNoFSMULD = 4,
+  Sparc_FeaturePWRPSR = 5,
+  Sparc_FeatureReserveG1 = 6,
+  Sparc_FeatureReserveG2 = 7,
+  Sparc_FeatureReserveG3 = 8,
+  Sparc_FeatureReserveG4 = 9,
+  Sparc_FeatureReserveG5 = 10,
+  Sparc_FeatureReserveG6 = 11,
+  Sparc_FeatureReserveG7 = 12,
+  Sparc_FeatureReserveI0 = 13,
+  Sparc_FeatureReserveI1 = 14,
+  Sparc_FeatureReserveI2 = 15,
+  Sparc_FeatureReserveI3 = 16,
+  Sparc_FeatureReserveI4 = 17,
+  Sparc_FeatureReserveI5 = 18,
+  Sparc_FeatureReserveL0 = 19,
+  Sparc_FeatureReserveL1 = 20,
+  Sparc_FeatureReserveL2 = 21,
+  Sparc_FeatureReserveL3 = 22,
+  Sparc_FeatureReserveL4 = 23,
+  Sparc_FeatureReserveL5 = 24,
+  Sparc_FeatureReserveL6 = 25,
+  Sparc_FeatureReserveL7 = 26,
+  Sparc_FeatureReserveO0 = 27,
+  Sparc_FeatureReserveO1 = 28,
+  Sparc_FeatureReserveO2 = 29,
+  Sparc_FeatureReserveO3 = 30,
+  Sparc_FeatureReserveO4 = 31,
+  Sparc_FeatureReserveO5 = 32,
+  Sparc_FeatureSoftFloat = 33,
+  Sparc_FeatureSoftMulDiv = 34,
+  Sparc_FeatureV8Deprecated = 35,
+  Sparc_FeatureV9 = 36,
+  Sparc_FeatureVIS = 37,
+  Sparc_FeatureVIS2 = 38,
+  Sparc_FeatureVIS3 = 39,
+  Sparc_FixAllFDIVSQRT = 40,
+  Sparc_InsertNOPLoad = 41,
+  Sparc_LeonCASA = 42,
+  Sparc_LeonCycleCounter = 43,
+  Sparc_TuneSlowRDPC = 44,
+  Sparc_UMACSMACSupport = 45,
+  Sparc_UsePopc = 46,
+  Sparc_NumSubtargetFeatures = 47
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

external/capstone/arch/Sparc/SparcGenSystemOperands.inc

@@ -0,0 +1,119 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_ASITAG_DECL
+#endif
+
+#ifdef GET_ASITAG_DECL
+const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByName(const char * Name);
+const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByAltName(const char * AltName);
+const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByEncoding(uint8_t Encoding);
+#endif
+
+#ifdef GET_ASITAG_IMPL
+static const Sparc_ASITag_ASITag ASITagsList[] = {
+  { "ASI_AIUP", { .raw_val = SPARC_ASITAG_ASI_AIUP }, "ASI_AS_IF_USER_PRIMARY", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_PRIMARY }, 0x10 }, // 0
+  { "ASI_AIUP_L", { .raw_val = SPARC_ASITAG_ASI_AIUP_L }, "ASI_AS_IF_USER_PRIMARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_PRIMARY_LITTLE }, 0x18 }, // 1
+  { "ASI_AIUS", { .raw_val = SPARC_ASITAG_ASI_AIUS }, "ASI_AS_IF_USER_SECONDARY", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_SECONDARY }, 0x11 }, // 2
+  { "ASI_AIUS_L", { .raw_val = SPARC_ASITAG_ASI_AIUS_L }, "ASI_AS_IF_USER_SECONDARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_SECONDARY_LITTLE }, 0x19 }, // 3
+  { "ASI_N", { .raw_val = SPARC_ASITAG_ASI_N }, "ASI_NUCLEUS", { .raw_val = SPARC_ASITAG_ASI_NUCLEUS }, 0x4 }, // 4
+  { "ASI_N_L", { .raw_val = SPARC_ASITAG_ASI_N_L }, "ASI_NUCLEUS_LITTLE", { .raw_val = SPARC_ASITAG_ASI_NUCLEUS_LITTLE }, 0xC }, // 5
+  { "ASI_P", { .raw_val = SPARC_ASITAG_ASI_P }, "ASI_PRIMARY", { .raw_val = SPARC_ASITAG_ASI_PRIMARY }, 0x80 }, // 6
+  { "ASI_PNF", { .raw_val = SPARC_ASITAG_ASI_PNF }, "ASI_PRIMARY_NOFAULT", { .raw_val = SPARC_ASITAG_ASI_PRIMARY_NOFAULT }, 0x82 }, // 7
+  { "ASI_PNF_L", { .raw_val = SPARC_ASITAG_ASI_PNF_L }, "ASI_PRIMARY_NOFAULT_LITTLE", { .raw_val = SPARC_ASITAG_ASI_PRIMARY_NOFAULT_LITTLE }, 0x8A }, // 8
+  { "ASI_P_L", { .raw_val = SPARC_ASITAG_ASI_P_L }, "ASI_PRIMARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_PRIMARY_LITTLE }, 0x88 }, // 9
+  { "ASI_S", { .raw_val = SPARC_ASITAG_ASI_S }, "ASI_SECONDARY", { .raw_val = SPARC_ASITAG_ASI_SECONDARY }, 0x81 }, // 10
+  { "ASI_SNF", { .raw_val = SPARC_ASITAG_ASI_SNF }, "ASI_SECONDARY_NOFAULT", { .raw_val = SPARC_ASITAG_ASI_SECONDARY_NOFAULT }, 0x83 }, // 11
+  { "ASI_SNF_L", { .raw_val = SPARC_ASITAG_ASI_SNF_L }, "ASI_SECONDARY_NOFAULT_LITTLE", { .raw_val = SPARC_ASITAG_ASI_SECONDARY_NOFAULT_LITTLE }, 0x8B }, // 12
+  { "ASI_S_L", { .raw_val = SPARC_ASITAG_ASI_S_L }, "ASI_SECONDARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_SECONDARY_LITTLE }, 0x89 }, // 13
+  };
+
+const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByName(const char * Name) {
+  static const struct IndexTypeStr Index[] = {
+    { "ASI_AIUP", 0 },
+    { "ASI_AIUP_L", 1 },
+    { "ASI_AIUS", 2 },
+    { "ASI_AIUS_L", 3 },
+    { "ASI_N", 4 },
+    { "ASI_N_L", 5 },
+    { "ASI_P", 6 },
+    { "ASI_PNF", 7 },
+    { "ASI_PNF_L", 8 },
+    { "ASI_P_L", 9 },
+    { "ASI_S", 10 },
+    { "ASI_SNF", 11 },
+    { "ASI_SNF_L", 12 },
+    { "ASI_S_L", 13 },
+  };
+
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   if (i == -1)
+      return NULL;
+   else
+      return &ASITagsList[Index[i].index];
+}
+
+const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByAltName(const char * AltName) {
+  static const struct IndexTypeStr Index[] = {
+    { "ASI_AS_IF_USER_PRIMARY", 0 },
+    { "ASI_AS_IF_USER_PRIMARY_LITTLE", 1 },
+    { "ASI_AS_IF_USER_SECONDARY", 2 },
+    { "ASI_AS_IF_USER_SECONDARY_LITTLE", 3 },
+    { "ASI_NUCLEUS", 4 },
+    { "ASI_NUCLEUS_LITTLE", 5 },
+    { "ASI_PRIMARY", 6 },
+    { "ASI_PRIMARY_LITTLE", 9 },
+    { "ASI_PRIMARY_NOFAULT", 7 },
+    { "ASI_PRIMARY_NOFAULT_LITTLE", 8 },
+    { "ASI_SECONDARY", 10 },
+    { "ASI_SECONDARY_LITTLE", 13 },
+    { "ASI_SECONDARY_NOFAULT", 11 },
+    { "ASI_SECONDARY_NOFAULT_LITTLE", 12 },
+  };
+
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), AltName);
+   if (i == -1)
+      return NULL;
+   else
+      return &ASITagsList[Index[i].index];
+}
+
+const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByEncoding(uint8_t Encoding) {
+  static const struct IndexType Index[] = {
+    { 0x4, 4 },
+    { 0xC, 5 },
+    { 0x10, 0 },
+    { 0x11, 2 },
+    { 0x18, 1 },
+    { 0x19, 3 },
+    { 0x80, 6 },
+    { 0x81, 10 },
+    { 0x82, 7 },
+    { 0x83, 11 },
+    { 0x88, 9 },
+    { 0x89, 13 },
+    { 0x8A, 8 },
+    { 0x8B, 12 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   if (i == -1)
+      return NULL;
+   else
+      return &ASITagsList[Index[i].index];
+}
+
+#endif
+
+#undef GET_ASITAG_DECL
+#undef GET_ASITAG_IMPL

external/capstone/arch/Sparc/SparcInstPrinter.c

@@ -0,0 +1,340 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Sparc MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInstPrinter.h"
+#include "../../Mapping.h"
+#include "SparcInstPrinter.h"
+#include "SparcLinkage.h"
+#include "SparcMCTargetDesc.h"
+#include "SparcMapping.h"
+#include "SparcDisassemblerExtension.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "asm-printer"
+
+static void printCustomAliasOperand(
+         MCInst *MI, uint64_t Address, unsigned OpIdx,
+         unsigned PrintMethodIdx,
+         SStream *OS);
+static void printOperand(MCInst *MI, int opNum, SStream *O);
+
+#define GET_INSTRUCTION_NAME
+#define PRINT_ALIAS_INSTR
+#include "SparcGenAsmWriter.inc"
+
+static void printRegName(SStream *OS, MCRegister Reg)
+{
+	SStream_concat1(OS, '%');
+	SStream_concat0(OS, getRegisterName(Reg, Sparc_NoRegAltName));
+}
+
+static void printRegNameAlt(SStream *OS, MCRegister Reg, unsigned AltIdx)
+{
+	SStream_concat1(OS, '%');
+	SStream_concat0(OS, getRegisterName(Reg, AltIdx));
+}
+
+static void printInst(MCInst *MI, uint64_t Address, SStream *O)
+{
+	bool isAlias = false;
+	bool useAliasDetails = map_use_alias_details(MI);
+	map_set_fill_detail_ops(MI, useAliasDetails);
+
+	if (!printAliasInstr(MI, Address, O) &&
+		!printSparcAliasInstr(MI, O)) {
+		MCInst_setIsAlias(MI, false);
+	} else {
+		isAlias = true;
+		MCInst_setIsAlias(MI, isAlias);
+		if (useAliasDetails) {
+			return;
+		}
+	}
+
+	if (!isAlias || !useAliasDetails) {
+		map_set_fill_detail_ops(MI, !(isAlias && useAliasDetails));
+		if (isAlias)
+			SStream_Close(O);
+		printInstruction(MI, Address, O);
+		if (isAlias)
+			SStream_Open(O);
+	}
+}
+
+bool printSparcAliasInstr(MCInst *MI, SStream *O)
+{
+	switch (MCInst_getOpcode(MI)) {
+	default:
+		return false;
+	case Sparc_JMPLrr:
+	case Sparc_JMPLri: {
+		if (MCInst_getNumOperands(MI) != 3)
+			return false;
+		if (!MCOperand_isReg(MCInst_getOperand(MI, (0))))
+			return false;
+		switch (MCOperand_getReg(MCInst_getOperand(MI, (0)))) {
+		default:
+			return false;
+		case Sparc_G0: // jmp $addr | ret | retl
+			if (MCOperand_isImm(MCInst_getOperand(MI, (2))) &&
+			    MCOperand_getImm(MCInst_getOperand(MI, (2))) == 8) {
+				switch (MCOperand_getReg(
+					MCInst_getOperand(MI, (1)))) {
+				default:
+					break;
+				case Sparc_I7:
+					SStream_concat0(O, "\tret");
+					return true;
+				case Sparc_O7:
+					SStream_concat0(O, "\tretl");
+					return true;
+				}
+			}
+			SStream_concat0(O, "\tjmp ");
+			printMemOperand(MI, 1, O);
+			return true;
+		case Sparc_O7: // call $addr
+			SStream_concat0(O, "\tcall ");
+			printMemOperand(MI, 1, O);
+			return true;
+		}
+	}
+	case Sparc_V9FCMPS:
+	case Sparc_V9FCMPD:
+	case Sparc_V9FCMPQ:
+	case Sparc_V9FCMPES:
+	case Sparc_V9FCMPED:
+	case Sparc_V9FCMPEQ: {
+		if (Sparc_getFeatureBits(MI->csh->mode, Sparc_FeatureV9) || (MCInst_getNumOperands(MI) != 3) ||
+		    (!MCOperand_isReg(MCInst_getOperand(MI, (0)))) ||
+		    (MCOperand_getReg(MCInst_getOperand(MI, (0))) != Sparc_FCC0))
+			return false;
+		// if V8, skip printing %fcc0.
+		switch (MCInst_getOpcode(MI)) {
+		default:
+		case Sparc_V9FCMPS:
+			SStream_concat0(O, "\tfcmps ");
+			break;
+		case Sparc_V9FCMPD:
+			SStream_concat0(O, "\tfcmpd ");
+			break;
+		case Sparc_V9FCMPQ:
+			SStream_concat0(O, "\tfcmpq ");
+			break;
+		case Sparc_V9FCMPES:
+			SStream_concat0(O, "\tfcmpes ");
+			break;
+		case Sparc_V9FCMPED:
+			SStream_concat0(O, "\tfcmped ");
+			break;
+		case Sparc_V9FCMPEQ:
+			SStream_concat0(O, "\tfcmpeq ");
+			break;
+		}
+		printOperand(MI, 1, O);
+		SStream_concat0(O, ", ");
+		printOperand(MI, 2, O);
+		return true;
+	}
+	}
+}
+
+static void printOperand(MCInst *MI, int opNum, SStream *O)
+{
+	Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_Operand, opNum);
+	MCOperand *MO = MCInst_getOperand(MI, (opNum));
+
+	if (MCOperand_isReg(MO)) {
+		unsigned Reg = MCOperand_getReg(MO);
+		if (Sparc_getFeatureBits(MI->csh->mode, Sparc_FeatureV9))
+			printRegNameAlt(O, Reg, Sparc_RegNamesStateReg);
+		else
+			printRegName(O, Reg);
+		return;
+	}
+
+	if (MCOperand_isImm(MO)) {
+		switch (MCInst_getOpcode(MI)) {
+		default:
+			printInt32(O, (int)MCOperand_getImm(MO));
+			return;
+
+		case Sparc_TICCri: // Fall through
+		case Sparc_TICCrr: // Fall through
+		case Sparc_TRAPri: // Fall through
+		case Sparc_TRAPrr: // Fall through
+		case Sparc_TXCCri: // Fall through
+		case Sparc_TXCCrr: // Fall through
+			// Only seven-bit values up to 127.
+			printInt8(O, ((int)MCOperand_getImm(MO) & 0x7f));
+			return;
+		}
+	}
+
+	CS_ASSERT(MCOperand_isExpr(MO) &&
+		  "Unknown operand kind in printOperand");
+}
+
+void printMemOperand(MCInst *MI, int opNum, SStream *O)
+{
+	Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_MemOperand, opNum);
+	MCOperand *Op1 = MCInst_getOperand(MI, (opNum));
+	MCOperand *Op2 = MCInst_getOperand(MI, (opNum + 1));
+
+	bool PrintedFirstOperand = false;
+	if (MCOperand_isReg(Op1) && MCOperand_getReg(Op1) != Sparc_G0) {
+		printOperand(MI, opNum, O);
+		PrintedFirstOperand = true;
+	}
+
+	// Skip the second operand iff it adds nothing (literal 0 or %g0) and we've
+	// already printed the first one
+	const bool SkipSecondOperand =
+		PrintedFirstOperand &&
+		((MCOperand_isReg(Op2) && MCOperand_getReg(Op2) == Sparc_G0) ||
+		 (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0));
+
+	if (!SkipSecondOperand) {
+		if (PrintedFirstOperand)
+			SStream_concat0(O, "+");
+
+		printOperand(MI, opNum + 1, O);
+	}
+}
+
+void printCCOperand(MCInst *MI, int opNum, SStream *O)
+{
+	Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_CCOperand, opNum);
+	int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, (opNum)));
+	switch (MCInst_getOpcode(MI)) {
+	default:
+		break;
+	case Sparc_FBCOND:
+	case Sparc_FBCONDA:
+	case Sparc_FBCOND_V9:
+	case Sparc_FBCONDA_V9:
+	case Sparc_BPFCC:
+	case Sparc_BPFCCA:
+	case Sparc_BPFCCNT:
+	case Sparc_BPFCCANT:
+	case Sparc_MOVFCCrr:
+	case Sparc_V9MOVFCCrr:
+	case Sparc_MOVFCCri:
+	case Sparc_V9MOVFCCri:
+	case Sparc_FMOVS_FCC:
+	case Sparc_V9FMOVS_FCC:
+	case Sparc_FMOVD_FCC:
+	case Sparc_V9FMOVD_FCC:
+	case Sparc_FMOVQ_FCC:
+	case Sparc_V9FMOVQ_FCC:
+		// Make sure CC is a fp conditional flag.
+		CC = (CC < SPARC_CC_FCC_BEGIN) ? (CC + SPARC_CC_FCC_BEGIN) : CC;
+		break;
+	case Sparc_CBCOND:
+	case Sparc_CBCONDA:
+		// Make sure CC is a cp conditional flag.
+		CC = (CC < SPARC_CC_CPCC_BEGIN) ? (CC + SPARC_CC_CPCC_BEGIN) : CC;
+		break;
+	case Sparc_BPR:
+	case Sparc_BPRA:
+	case Sparc_BPRNT:
+	case Sparc_BPRANT:
+	case Sparc_MOVRri:
+	case Sparc_MOVRrr:
+	case Sparc_FMOVRS:
+	case Sparc_FMOVRD:
+	case Sparc_FMOVRQ:
+		// Make sure CC is a register conditional flag.
+		CC = (CC < SPARC_CC_REG_BEGIN) ? (CC + SPARC_CC_REG_BEGIN) : CC;
+		break;
+	}
+	SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
+}
+
+bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O)
+{
+	printf("FIXME: Implement SparcInstPrinter::printGetPCX.");
+	return true;
+}
+
+void printMembarTag(MCInst *MI, int opNum, SStream *O)
+{
+	Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_MembarTag, opNum);
+	static const char *const TagNames[] = { "#LoadLoad",  "#StoreLoad",
+						"#LoadStore", "#StoreStore",
+						"#Lookaside", "#MemIssue",
+						"#Sync" };
+
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (opNum)));
+
+	if (Imm > 127) {
+		printUInt32(O, Imm);
+		return;
+	}
+
+	bool First = true;
+	for (unsigned i = 0; i < sizeof(TagNames); i++) {
+		if (Imm & (1ull << i)) {
+			SStream_concat(O, "%s", (First ? "" : " | "));
+			SStream_concat0(O, TagNames[i]);
+			First = false;
+		}
+	}
+}
+
+#define GET_ASITAG_IMPL
+#include "SparcGenSystemOperands.inc"
+
+void printASITag(MCInst *MI, int opNum, SStream *O)
+{
+	Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_ASITag, opNum);
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (opNum)));
+	const Sparc_ASITag_ASITag *ASITag = Sparc_ASITag_lookupASITagByEncoding(Imm);
+	if (Sparc_getFeatureBits(MI->csh->mode, Sparc_FeatureV9) && ASITag) {
+		SStream_concat1(O, '#');
+		SStream_concat0(O, ASITag->Name);
+	} else
+		printUInt32(O, Imm);
+}
+
+
+void Sparc_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O)
+{
+	printInst(MI, Address, O);
+}
+
+const char *Sparc_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx)
+{
+	return getRegisterName(RegNo, AltIdx);
+}

external/capstone/arch/Sparc/SparcInstPrinter.h

@@ -0,0 +1,49 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- SparcInstPrinter.h - Convert Sparc MCInst to assembly syntax ------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Sparc MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCINSTPRINTER_H
+#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCINSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "SparcMCTargetDesc.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+bool printSparcAliasInstr(MCInst *MI, SStream *OS);
+void printMemOperand(MCInst *MI, int opNum, SStream *OS);
+void printCCOperand(MCInst *MI, int opNum, SStream *OS);
+bool printGetPCX(MCInst *MI, unsigned OpNo, SStream *OS);
+void printMembarTag(MCInst *MI, int opNum, SStream *O);
+void printASITag(MCInst *MI, int opNum, SStream *O);
+;
+// end namespace llvm
+
+#endif

external/capstone/arch/Sparc/SparcLinkage.h

@@ -0,0 +1,19 @@
+#ifndef CS_SPARC_LINKAGE_H
+#define CS_SPARC_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+DecodeStatus Sparc_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				     size_t ByteLen, MCInst *MI, uint16_t *Size,
+				     uint64_t Address, void *Info);
+const char *Sparc_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void Sparc_LLVM_printInstruction(MCInst *MI, SStream *O,
+			       void * /* MCRegisterInfo* */ info);
+void Sparc_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O);
+
+#endif // CS_SPARC_LINKAGE_H

external/capstone/arch/Sparc/SparcMCTargetDesc.h

@@ -0,0 +1,83 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides Sparc specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
+#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../LEB128.h"
+#include "../../MathExtras.h"
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+// Defines symbolic names for Sparc v9 ASI tag names.
+// CS namespace begin: SparcASITag
+
+typedef union sparc_sys_imm {
+	sparc_asi asi;
+	unsigned raw_val;
+} sparc_sys_imm;
+
+typedef struct {
+	const char *Name;
+	sparc_sys_imm imm;
+	const char *AltName;
+	sparc_sys_imm alt_imm;
+	unsigned Encoding;
+} Sparc_ASITag_ASITag;
+
+#define GET_ASITAG_DECL
+#include "SparcGenSystemOperands.inc"
+
+// CS namespace end: SparcASITag
+
+// end namespace SparcASITag
+// End llvm namespace
+
+// Defines symbolic names for Sparc registers.  This defines a mapping from
+// register name to register number.
+//
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "SparcGenRegisterInfo.inc"
+
+// Defines symbolic names for the Sparc instructions.
+//
+#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_MC_HELPER_DECLS
+#include "SparcGenInstrInfo.inc"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "SparcGenSubtargetInfo.inc"
+
+#endif

external/capstone/arch/Sparc/SparcMapping.c

@@ -0,0 +1,494 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../Mapping.h"
+#include "../../utils.h"
+#include "../../cs_simple_types.h"
+
+#include "SparcMapping.h"
+
+void Sparc_init_cs_detail(MCInst *MI)
+{
+	if (!detail_is_set(MI)) {
+		return;
+	}
+	memset(get_detail(MI), 0, offsetof(cs_detail, sparc) + sizeof(cs_sparc));
+	Sparc_get_detail(MI)->cc = SPARC_CC_UNDEF;
+	Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_NONE;
+}
+
+const insn_map sparc_insns[] = {
+#include "SparcGenCSMappingInsn.inc"
+};
+
+void Sparc_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, sparc_insns, ARR_SIZE(sparc_insns));
+	map_implicit_reads(MI, sparc_insns);
+	map_implicit_writes(MI, sparc_insns);
+	map_groups(MI, sparc_insns);
+	const sparc_suppl_info *suppl_info =
+		map_get_suppl_info(MI, sparc_insns);
+	if (suppl_info) {
+		Sparc_get_detail(MI)->format = suppl_info->form;
+	}
+}
+
+/// Adds details which are not defined consistently as LLVM operands like
+/// condition codes for alias instructions or branch hint bits.
+static void Sparc_add_bit_details(MCInst *MI, const uint8_t *Bytes,
+				  size_t BytesLen)
+{
+	if (!Bytes || BytesLen < 4 || !detail_is_set(MI)) {
+		return;
+	}
+	uint32_t insn = readBytes32(MI, Bytes);
+
+	// CC field
+	cs_sparc *detail = Sparc_get_detail(MI);
+	switch (detail->format) {
+	default:
+		break;
+	case SPARC_INSN_FORM_F2_2: {
+		// This format is used either by B or FB instructions.
+		// The op2 == 6 for the FB and 2 for B.
+		// This is the only indicator we have here to determine which CC field is used
+		// if we don't want big switch cases.
+		//
+		// See: Opcode Maps - Table 39 - Sparc V9 ISA
+		size_t op2 = get_insn_field_r(insn, 22, 24);
+		detail->cc_field = op2 == 6 ? SPARC_CC_FIELD_FCC0 : SPARC_CC_FIELD_ICC;
+		break;
+	}
+	case SPARC_INSN_FORM_F2_3:
+		detail->cc_field = 0x4 | get_insn_field_r(insn, 20, 21);
+		break;
+	case SPARC_INSN_FORM_TRAPSP:
+		detail->cc_field = 0x4 | get_insn_field_r(insn, 11, 12);
+		break;
+	case SPARC_INSN_FORM_F4_1:
+	case SPARC_INSN_FORM_F4_2:
+		detail->cc_field = get_insn_field_r(insn, 11, 12);
+		detail->cc_field |= get_insn_field_r(insn, 18, 18) << 2;
+		break;
+	case SPARC_INSN_FORM_F4_3:
+		detail->cc_field = get_insn_field_r(insn, 11, 13);
+		break;
+	}
+
+	// Condition codes
+	switch (detail->format) {
+	default:
+		break;
+	case SPARC_INSN_FORM_F2_1:
+	case SPARC_INSN_FORM_F2_2:
+	case SPARC_INSN_FORM_F2_3:
+	case SPARC_INSN_FORM_TRAPSP: {
+		// cond
+		// Alias instructions don't define the conditions as operands.
+		// We need to add them here to the details again.
+		sparc_cc cc = get_insn_field_r(insn, 25, 28);
+		if (MCInst_getOpcode(MI) == Sparc_CBCOND ||
+		    MCInst_getOpcode(MI) == Sparc_CBCONDA) {
+			cc += SPARC_CC_CPCC_BEGIN;
+		}
+		detail->cc = cc;
+		break;
+	}
+	case SPARC_INSN_FORM_F4_1:
+	case SPARC_INSN_FORM_F4_2:
+	case SPARC_INSN_FORM_F4_3: {
+		sparc_cc cc = get_insn_field_r(insn, 14, 17);
+		detail->cc = cc;
+		break;
+	}
+	case SPARC_INSN_FORM_F2_4: {
+		// cond
+		// Alias instructions don't define the conditions as operands.
+		// We need to add them here to the details again.
+		sparc_cc rcc = get_insn_field_r(insn, 25, 27);
+		detail->cc = rcc + SPARC_CC_REG_BEGIN;
+		break;
+	}
+	case SPARC_INSN_FORM_F4_4R:
+	case SPARC_INSN_FORM_F4_4I: {
+		sparc_cc rcc = get_insn_field_r(insn, 10, 12);
+		detail->cc = rcc + SPARC_CC_REG_BEGIN;
+		break;
+	}
+	}
+	switch (detail->cc_field) {
+	default:
+	case SPARC_CC_FIELD_ICC:
+	case SPARC_CC_FIELD_XCC:
+		break;
+	case SPARC_CC_FIELD_FCC0:
+	case SPARC_CC_FIELD_FCC1:
+	case SPARC_CC_FIELD_FCC2:
+	case SPARC_CC_FIELD_FCC3:
+		detail->cc += SPARC_CC_FCC_BEGIN;
+		break;
+	}
+
+	// Hints
+	switch (detail->format) {
+	default:
+		break;
+	case SPARC_INSN_FORM_F2_2:
+		detail->hint = get_insn_field_r(insn, 29, 29);
+		break;
+	case SPARC_INSN_FORM_F2_3:
+	case SPARC_INSN_FORM_F2_4:
+		detail->hint = get_insn_field_r(insn, 29, 29);
+		detail->hint |=
+			get_insn_field_r(insn, 19, 19) == 0 ? SPARC_HINT_PN :
+							      SPARC_HINT_PT;
+		break;
+	}
+}
+
+bool Sparc_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			  MCInst *instr, uint16_t *size, uint64_t address,
+			  void *info)
+{
+	Sparc_init_cs_detail(instr);
+	bool Result = Sparc_LLVM_getInstruction(handle, code, code_len, instr,
+						size, address,
+						info) != MCDisassembler_Fail;
+	Sparc_set_instr_map_data(instr);
+
+	Sparc_add_bit_details(instr, code, code_len);
+	return Result;
+}
+
+void Sparc_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(
+		MRI, SparcRegDesc, sizeof(SparcRegDesc), 0, 0,
+		SparcMCRegisterClasses, ARR_SIZE(SparcMCRegisterClasses), 0, 0,
+		SparcRegDiffLists, 0, SparcSubRegIdxLists,
+		ARR_SIZE(SparcSubRegIdxLists), 0);
+}
+
+const char *Sparc_reg_name(csh handle, unsigned int reg)
+{
+	int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
+
+	if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
+		return Sparc_LLVM_getRegisterName(reg, Sparc_NoRegAltName);
+	}
+	return Sparc_LLVM_getRegisterName(reg, Sparc_RegNamesStateReg);
+}
+
+void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used by Sparc. Information is set after disassembly.
+}
+
+static const char *const insn_name_maps[] = {
+#include "SparcGenCSMappingInsnName.inc"
+};
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_alias_mnem_map[] = {
+#include "SparcGenCSAliasMnemMap.inc"
+	{ SPARC_INS_ALIAS_CALL, "call" },
+	{ SPARC_INS_ALIAS_END, NULL },
+};
+#endif
+
+static void insert_op(MCInst *MI, unsigned index, cs_sparc_op op)
+{
+	if (!detail_is_set(MI)) {
+		return;
+	}
+	Sparc_check_safe_inc(MI);
+
+	cs_sparc_op *ops = Sparc_get_detail(MI)->operands;
+	int i = Sparc_get_detail(MI)->op_count;
+	if (index == -1) {
+		ops[i] = op;
+		Sparc_inc_op_count(MI);
+		return;
+	}
+	for (; i > 0 && i > index; --i) {
+		ops[i] = ops[i - 1];
+	}
+	ops[index] = op;
+	Sparc_inc_op_count(MI);
+}
+
+/// Inserts a register to the detail operands at @index.
+/// Already present operands are moved.
+/// If @index is -1 the operand is appended.
+static void Sparc_insert_detail_op_reg_at(MCInst *MI, unsigned index, sparc_reg Reg,
+				 cs_ac_type access)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	cs_sparc_op op = { 0 };
+	op.type = SPARC_OP_REG;
+	op.reg = Reg;
+	op.access = access;
+	insert_op(MI, index, op);
+}
+
+static void Sparc_correct_details(MCInst *MI)
+{
+	if (!detail_is_set(MI)) {
+		return;
+	}
+	switch (MCInst_getOpcode(MI)) {
+	default:
+		return;
+	case Sparc_LDSTUBri:
+	case Sparc_LDSTUBrr:
+	case Sparc_LDSTUBAri:
+	case Sparc_LDSTUBArr:
+		// The memory gets written back with ones
+		// but there is not write back memory operand defined
+		// (if even possible).
+		Sparc_get_detail(MI)->operands[0].access = CS_AC_READ_WRITE;
+		break;
+	case Sparc_RDPSR:
+		Sparc_insert_detail_op_reg_at(MI, 0, SPARC_REG_PSR, CS_AC_READ);
+		break;
+	case Sparc_PWRPSRri:
+	case Sparc_PWRPSRrr:
+	case Sparc_WRPSRri:
+	case Sparc_WRPSRrr:
+		Sparc_insert_detail_op_reg_at(MI, -1, SPARC_REG_PSR, CS_AC_WRITE);
+		break;
+	case Sparc_RDWIM:
+		Sparc_insert_detail_op_reg_at(MI, 0, SPARC_REG_WIM, CS_AC_READ);
+		break;
+	case Sparc_WRWIMri:
+	case Sparc_WRWIMrr:
+		Sparc_insert_detail_op_reg_at(MI, -1, SPARC_REG_WIM, CS_AC_WRITE);
+		break;
+	case Sparc_RDTBR:
+		Sparc_insert_detail_op_reg_at(MI, 0, SPARC_REG_TBR, CS_AC_READ);
+		break;
+	case Sparc_WRTBRri:
+	case Sparc_WRTBRrr:
+		Sparc_insert_detail_op_reg_at(MI, -1, SPARC_REG_TBR, CS_AC_WRITE);
+		break;
+	}
+}
+
+void Sparc_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
+{
+	MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+	MI->MRI = MRI;
+	MI->flat_insn->usesAliasDetails = map_use_alias_details(MI);
+	Sparc_LLVM_printInst(MI, MI->address, "", O);
+
+#ifndef CAPSTONE_DIET
+	map_set_alias_id(MI, O, insn_alias_mnem_map,
+			 ARR_SIZE(insn_alias_mnem_map));
+	Sparc_correct_details(MI);
+#endif
+}
+
+const char *Sparc_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id < SPARC_INS_ALIAS_END && id > SPARC_INS_ALIAS_BEGIN) {
+		if (id - SPARC_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
+			return NULL;
+
+		return insn_alias_mnem_map[id - SPARC_INS_ALIAS_BEGIN - 1].name;
+	}
+	if (id >= SPARC_INS_ENDING)
+		return NULL;
+
+	if (id < ARR_SIZE(insn_name_maps))
+		return insn_name_maps[id];
+	// not found
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ SPARC_GRP_INVALID, NULL },
+
+	{ SPARC_GRP_JUMP, "jump" },
+	{ SPARC_GRP_CALL, "call" },
+	{ SPARC_GRP_RET, "return" },
+	{ SPARC_GRP_INT, "int" },
+	{ SPARC_GRP_IRET, "iret" },
+	{ SPARC_GRP_PRIVILEGE, "privilege" },
+	{ SPARC_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+// architecture-specific groups
+#include "SparcGenCSFeatureName.inc"
+};
+#endif
+
+const char *Sparc_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+static const map_insn_ops insn_operands[] = {
+#include "SparcGenCSMappingInsnOp.inc"
+};
+
+void Sparc_set_detail_op_imm(MCInst *MI, unsigned OpNum, sparc_op_type ImmType,
+			     int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	CS_ASSERT_RET((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
+	CS_ASSERT_RET(ImmType == SPARC_OP_IMM);
+
+	Sparc_get_detail_op(MI, 0)->type = ImmType;
+	Sparc_get_detail_op(MI, 0)->imm = Imm;
+	Sparc_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	Sparc_inc_op_count(MI);
+}
+
+void Sparc_set_detail_op_reg(MCInst *MI, unsigned OpNum, sparc_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	CS_ASSERT_RET((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+
+	switch (Reg) {
+	default:
+		Sparc_get_detail_op(MI, 0)->type = SPARC_OP_REG;
+		Sparc_get_detail_op(MI, 0)->reg = Reg;
+		Sparc_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+		Sparc_inc_op_count(MI);
+		return;
+	// The LLVM definition is inconsistent with the cc fields.
+	// Sometimes they are encoded as register, sometimes not at all.
+	// For Capstone they are always saved in the cc_field field for now.
+	case SPARC_REG_ICC:
+		Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_ICC;
+		break;
+	case SPARC_REG_FCC0:
+		Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC0;
+		break;
+	case SPARC_REG_FCC1:
+		Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC1;
+		break;
+	case SPARC_REG_FCC2:
+		Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC2;
+		break;
+	case SPARC_REG_FCC3:
+		Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC3;
+		break;
+	}
+}
+
+static inline bool is_single_reg_mem_case(MCInst *MI, unsigned OpNo)
+{
+	if (map_get_op_type(MI, OpNo) != CS_OP_MEM_REG) {
+		return false;
+	}
+	if (MI->size == 1) {
+		return true;
+	} else if (MI->size > OpNo + 1 && Sparc_get_detail(MI)->operands[0].type != SPARC_OP_MEM) {
+		// Next operand is not a memory operand (disponent or index reg).
+		return !(map_get_op_type(MI, OpNo + 1) & SPARC_OP_MEM);
+	}
+	return false;
+}
+
+void Sparc_add_cs_detail_0(MCInst *MI, sparc_op_group op_group, unsigned OpNo)
+{
+	if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
+		return;
+
+	cs_op_type op_type = map_get_op_type(MI, OpNo);
+
+	switch (op_group) {
+	default:
+	case Sparc_OP_GROUP_GetPCX:
+		printf("Operand group %d not handled!\n", op_group);
+		return;
+	case Sparc_OP_GROUP_Operand:
+		if (op_type & CS_OP_MEM) {
+			if (is_single_reg_mem_case(MI, OpNo)) {
+				Sparc_get_detail_op(MI, 0)->type = SPARC_OP_MEM;
+				Sparc_get_detail_op(MI, 0)->mem.base =
+					MCInst_getOpVal(MI, OpNo);
+				Sparc_get_detail_op(MI, 0)->access =
+					map_get_op_access(MI, OpNo);
+				Sparc_inc_op_count(MI);
+			}
+			break;
+		}
+		if (op_type == CS_OP_IMM) {
+			Sparc_set_detail_op_imm(MI, OpNo, SPARC_OP_IMM,
+						MCInst_getOpVal(MI, OpNo));
+		} else if (op_type == CS_OP_REG) {
+			Sparc_set_detail_op_reg(MI, OpNo,
+						MCInst_getOpVal(MI, OpNo));
+		} else {
+			CS_ASSERT_RET(0 && "Op type not handled.");
+		}
+		Sparc_get_detail_op(MI, 0)->access =
+			map_get_op_access(MI, OpNo);
+		break;
+	case Sparc_OP_GROUP_CCOperand: {
+		// Handled in Sparc_add_bit_details().
+		break;
+	}
+	case Sparc_OP_GROUP_MemOperand: {
+		MCOperand *Op1 = MCInst_getOperand(MI, (OpNo));
+		MCOperand *Op2 = MCInst_getOperand(MI, (OpNo + 1));
+		if (!MCOperand_isReg(Op1) ||
+		    MCOperand_getReg(Op1) == Sparc_G0) {
+			// Ignored
+			return;
+		}
+		Sparc_get_detail_op(MI, 0)->type = SPARC_OP_MEM;
+		Sparc_get_detail_op(MI, 0)->access =
+			map_get_op_access(MI, OpNo);
+		Sparc_get_detail_op(MI, 0)->mem.base = MCOperand_getReg(Op1);
+
+		if (MCOperand_isReg(Op2) && MCOperand_getReg(Op2) != Sparc_G0) {
+			Sparc_get_detail_op(MI, 0)->mem.index =
+				MCOperand_getReg(Op2);
+		} else if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) != 0) {
+			Sparc_get_detail_op(MI, 0)->mem.disp =
+				MCOperand_getImm(Op2);
+		}
+		Sparc_inc_op_count(MI);
+		break;
+	}
+	case Sparc_OP_GROUP_ASITag:
+		Sparc_get_detail_op(MI, 0)->type = SPARC_OP_ASI;
+		Sparc_get_detail_op(MI, 0)->access =
+			map_get_op_access(MI, OpNo);
+		Sparc_get_detail_op(MI, 0)->asi =
+			MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+		Sparc_inc_op_count(MI);
+		break;
+	case Sparc_OP_GROUP_MembarTag:
+		Sparc_get_detail_op(MI, 0)->type = SPARC_OP_MEMBAR_TAG;
+		Sparc_get_detail_op(MI, 0)->access =
+			map_get_op_access(MI, OpNo);
+		Sparc_get_detail_op(MI, 0)->membar_tag =
+			MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+		Sparc_inc_op_count(MI);
+		break;
+	}
+}
+
+#endif

external/capstone/arch/Sparc/SparcMapping.h

@@ -0,0 +1,40 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SPARC_MAP_H
+#define CS_SPARC_MAP_H
+
+#include "../../utils.h"
+#include "SparcMCTargetDesc.h"
+#include "SparcLinkage.h"
+#include <capstone/capstone.h>
+
+typedef enum {
+#include "SparcGenCSOpGroup.inc"
+} sparc_op_group;
+
+void Sparc_add_cs_detail_0(MCInst *MI, sparc_op_group op_group, unsigned OpNo);
+
+// return name of register in friendly string
+const char *Sparc_reg_name(csh handle, unsigned int reg);
+
+void Sparc_init_mri(MCRegisterInfo *MRI);
+void Sparc_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info);
+bool Sparc_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info);
+// given internal insn id, return public instruction info
+void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *Sparc_insn_name(csh handle, unsigned int id);
+
+const char *Sparc_group_name(csh handle, unsigned int id);
+void Sparc_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 sparc_op_type ImmType, int64_t Imm);
+void Sparc_set_detail_op_reg(MCInst *MI, unsigned OpNum, sparc_reg Reg);
+void Sparc_add_cs_detail_0(MCInst *MI, sparc_op_group op_group, unsigned OpNo);
+void Sparc_set_instr_map_data(MCInst *MI);
+
+#endif
+

external/capstone/arch/Sparc/SparcModule.c

@@ -0,0 +1,47 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "SparcMapping.h"
+#include "SparcModule.h"
+
+cs_err Sparc_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	Sparc_init_mri(mri);
+	ud->printer = Sparc_printer;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = Sparc_getInstruction;
+	ud->post_printer = NULL;
+
+	ud->reg_name = Sparc_reg_name;
+	ud->insn_id = Sparc_get_insn_id;
+	ud->insn_name = Sparc_insn_name;
+	ud->group_name = Sparc_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int) value;
+
+	if (type == CS_OPT_MODE) {
+		handle->mode |= (cs_mode)value;
+		if (value & CS_MODE_V9 || value & CS_MODE_64) {
+			// V9 implies 64bit.
+			handle->mode |= (CS_MODE_64 | CS_MODE_V9);
+		}
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

external/capstone/arch/Sparc/SparcModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_SPARC_MODULE_H
+#define CS_SPARC_MODULE_H
+
+#include "../../utils.h"
+
+cs_err Sparc_global_init(cs_struct *ud);
+cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif