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2026-03-23 12:11:07 +01:00
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/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#ifndef XTENSA_DISASSEMBLER_H
#define XTENSA_DISASSEMBLER_H
#include "../../MCDisassembler.h"
DecodeStatus Xtensa_LLVM_getInstruction(MCInst *MI, uint16_t *Size,
const uint8_t *Bytes,
unsigned BytesSize, uint64_t Address);
#endif

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ XTENSA_FEATURE_HASDENSITY, "HasDensity" },
{ XTENSA_FEATURE_HASSINGLEFLOAT, "HasSingleFloat" },
{ XTENSA_FEATURE_HASWINDOWED, "HasWindowed" },
{ XTENSA_FEATURE_HASBOOLEAN, "HasBoolean" },
{ XTENSA_FEATURE_HASLOOP, "HasLoop" },
{ XTENSA_FEATURE_HASSEXT, "HasSEXT" },
{ XTENSA_FEATURE_HASCLAMPS, "HasCLAMPS" },
{ XTENSA_FEATURE_HASNSA, "HasNSA" },
{ XTENSA_FEATURE_HASMINMAX, "HasMINMAX" },
{ XTENSA_FEATURE_HASMUL16, "HasMul16" },
{ XTENSA_FEATURE_HASMUL32, "HasMul32" },
{ XTENSA_FEATURE_HASMUL32HIGH, "HasMul32High" },
{ XTENSA_FEATURE_HASDIV32, "HasDiv32" },
{ XTENSA_FEATURE_HASMAC16, "HasMAC16" },
{ XTENSA_FEATURE_HASDFPACCEL, "HasDFPAccel" },
{ XTENSA_FEATURE_HASS32C1I, "HasS32C1I" },
{ XTENSA_FEATURE_HASTHREADPTR, "HasTHREADPTR" },
{ XTENSA_FEATURE_HASEXTENDEDL32R, "HasExtendedL32R" },
{ XTENSA_FEATURE_HASATOMCTL, "HasATOMCTL" },
{ XTENSA_FEATURE_HASMEMCTL, "HasMEMCTL" },
{ XTENSA_FEATURE_HASDEBUG, "HasDebug" },
{ XTENSA_FEATURE_HASEXCEPTION, "HasException" },
{ XTENSA_FEATURE_HASHIGHPRIINTERRUPTS, "HasHighPriInterrupts" },
{ XTENSA_FEATURE_HASCOPROCESSOR, "HasCoprocessor" },
{ XTENSA_FEATURE_HASINTERRUPT, "HasInterrupt" },
{ XTENSA_FEATURE_HASRELOCATABLEVECTOR, "HasRelocatableVector" },
{ XTENSA_FEATURE_HASTIMERINT, "HasTimerInt" },
{ XTENSA_FEATURE_HASPRID, "HasPRID" },
{ XTENSA_FEATURE_HASREGIONPROTECTION, "HasRegionProtection" },
{ XTENSA_FEATURE_HASMISCSR, "HasMiscSR" },
{ XTENSA_FEATURE_HASESP32S2OPS, "HasESP32S2Ops" },
{ XTENSA_FEATURE_HASESP32S3OPS, "HasESP32S3Ops" },
{ XTENSA_FEATURE_HASHIFI3, "HasHIFI3" },
{ XTENSA_FEATURE_HASFORCEDATOMICS, "HasForcedAtomics" },

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
Xtensa_OP_GROUP_Operand = 0,
Xtensa_OP_GROUP_BranchTarget = 1,
Xtensa_OP_GROUP_Imm8_AsmOperand = 2,
Xtensa_OP_GROUP_Select_4_AsmOperand = 3,
Xtensa_OP_GROUP_Select_2_AsmOperand = 4,
Xtensa_OP_GROUP_Select_8_AsmOperand = 5,
Xtensa_OP_GROUP_Offset_16_16_AsmOperand = 6,
Xtensa_OP_GROUP_Offset_256_8_AsmOperand = 7,
Xtensa_OP_GROUP_Offset_256_16_AsmOperand = 8,
Xtensa_OP_GROUP_Offset_256_4_AsmOperand = 9,
Xtensa_OP_GROUP_Select_16_AsmOperand = 10,
Xtensa_OP_GROUP_Offset_128_2_AsmOperand = 11,
Xtensa_OP_GROUP_Offset_128_1_AsmOperand = 12,
Xtensa_OP_GROUP_Offset_64_16_AsmOperand = 13,
Xtensa_OP_GROUP_MemOperand = 14,
Xtensa_OP_GROUP_Imm1n_15_AsmOperand = 15,
Xtensa_OP_GROUP_Imm8_sh8_AsmOperand = 16,
Xtensa_OP_GROUP_Imm1_16_AsmOperand = 17,
Xtensa_OP_GROUP_ImmOperand_minus16_14_2 = 18,
Xtensa_OP_GROUP_ImmOperand_minus32_28_4 = 19,
Xtensa_OP_GROUP_ImmOperand_minus64_56_8 = 20,
Xtensa_OP_GROUP_ImmOperand_0_56_8 = 21,
Xtensa_OP_GROUP_ImmOperand_minus16_47_1 = 22,
Xtensa_OP_GROUP_ImmOperand_0_3_1 = 23,
Xtensa_OP_GROUP_Uimm4_AsmOperand = 24,
Xtensa_OP_GROUP_Imm7_22_AsmOperand = 25,
Xtensa_OP_GROUP_Uimm5_AsmOperand = 26,
Xtensa_OP_GROUP_ImmOperand_0_63_1 = 27,
Xtensa_OP_GROUP_B4const_AsmOperand = 28,
Xtensa_OP_GROUP_B4constu_AsmOperand = 29,
Xtensa_OP_GROUP_CallOperand = 30,
Xtensa_OP_GROUP_Select_256_AsmOperand = 31,
Xtensa_OP_GROUP_Entry_Imm12_AsmOperand = 32,
Xtensa_OP_GROUP_JumpTarget = 33,
Xtensa_OP_GROUP_Imm64n_4n_AsmOperand = 34,
Xtensa_OP_GROUP_L32RTarget = 35,
Xtensa_OP_GROUP_LoopTarget = 36,
Xtensa_OP_GROUP_Offset8m32_AsmOperand = 37,
Xtensa_OP_GROUP_Imm12m_AsmOperand = 38,
Xtensa_OP_GROUP_Imm32n_95_AsmOperand = 39,
Xtensa_OP_GROUP_Imm8n_7_AsmOperand = 40,
Xtensa_OP_GROUP_Shimm0_31_AsmOperand = 41,
Xtensa_OP_GROUP_Imm12_AsmOperand = 42,
Xtensa_OP_GROUP_Shimm1_31_AsmOperand = 43,

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#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
Xtensa_NoRegister,
Xtensa_ACCHI = 1,
Xtensa_ACCLO = 2,
Xtensa_ACCX = 3,
Xtensa_ATOMCTL = 4,
Xtensa_BREG = 5,
Xtensa_CCOUNT = 6,
Xtensa_CPENABLE = 7,
Xtensa_DDR = 8,
Xtensa_DEBUGCAUSE = 9,
Xtensa_DEPC = 10,
Xtensa_EXCCAUSE = 11,
Xtensa_EXCVADDR = 12,
Xtensa_EXPSTATE = 13,
Xtensa_FCR = 14,
Xtensa_FFT_BIT_WIDTH = 15,
Xtensa_FSR = 16,
Xtensa_GPIO_OUT = 17,
Xtensa_IBREAKENABLE = 18,
Xtensa_ICOUNT = 19,
Xtensa_ICOUNTLEVEL = 20,
Xtensa_INTCLEAR = 21,
Xtensa_INTENABLE = 22,
Xtensa_INTERRUPT = 23,
Xtensa_LBEG = 24,
Xtensa_LCOUNT = 25,
Xtensa_LEND = 26,
Xtensa_LITBASE = 27,
Xtensa_MEMCTL = 28,
Xtensa_PRID = 29,
Xtensa_PS = 30,
Xtensa_QACC = 31,
Xtensa_SAR = 32,
Xtensa_SAR_BYTE = 33,
Xtensa_SP = 34,
Xtensa_THREADPTR = 35,
Xtensa_UA_STATE = 36,
Xtensa_VECBASE = 37,
Xtensa_WINDOWBASE = 38,
Xtensa_WINDOWSTART = 39,
Xtensa_A0 = 40,
Xtensa_A2 = 41,
Xtensa_A3 = 42,
Xtensa_A4 = 43,
Xtensa_A5 = 44,
Xtensa_A6 = 45,
Xtensa_A7 = 46,
Xtensa_A8 = 47,
Xtensa_A9 = 48,
Xtensa_A10 = 49,
Xtensa_A11 = 50,
Xtensa_A12 = 51,
Xtensa_A13 = 52,
Xtensa_A14 = 53,
Xtensa_A15 = 54,
Xtensa_AED0 = 55,
Xtensa_AED1 = 56,
Xtensa_AED2 = 57,
Xtensa_AED3 = 58,
Xtensa_AED4 = 59,
Xtensa_AED5 = 60,
Xtensa_AED6 = 61,
Xtensa_AED7 = 62,
Xtensa_AED8 = 63,
Xtensa_AED9 = 64,
Xtensa_AED10 = 65,
Xtensa_AED11 = 66,
Xtensa_AED12 = 67,
Xtensa_AED13 = 68,
Xtensa_AED14 = 69,
Xtensa_AED15 = 70,
Xtensa_B0 = 71,
Xtensa_B1 = 72,
Xtensa_B2 = 73,
Xtensa_B3 = 74,
Xtensa_B4 = 75,
Xtensa_B5 = 76,
Xtensa_B6 = 77,
Xtensa_B7 = 78,
Xtensa_B8 = 79,
Xtensa_B9 = 80,
Xtensa_B10 = 81,
Xtensa_B11 = 82,
Xtensa_B12 = 83,
Xtensa_B13 = 84,
Xtensa_B14 = 85,
Xtensa_B15 = 86,
Xtensa_CCOMPARE0 = 87,
Xtensa_CCOMPARE1 = 88,
Xtensa_CCOMPARE2 = 89,
Xtensa_CONFIGID0 = 90,
Xtensa_CONFIGID1 = 91,
Xtensa_DBREAKA0 = 92,
Xtensa_DBREAKA1 = 93,
Xtensa_DBREAKC0 = 94,
Xtensa_DBREAKC1 = 95,
Xtensa_EPC1 = 96,
Xtensa_EPC2 = 97,
Xtensa_EPC3 = 98,
Xtensa_EPC4 = 99,
Xtensa_EPC5 = 100,
Xtensa_EPC6 = 101,
Xtensa_EPC7 = 102,
Xtensa_EPS2 = 103,
Xtensa_EPS3 = 104,
Xtensa_EPS4 = 105,
Xtensa_EPS5 = 106,
Xtensa_EPS6 = 107,
Xtensa_EPS7 = 108,
Xtensa_EXCSAVE1 = 109,
Xtensa_EXCSAVE2 = 110,
Xtensa_EXCSAVE3 = 111,
Xtensa_EXCSAVE4 = 112,
Xtensa_EXCSAVE5 = 113,
Xtensa_EXCSAVE6 = 114,
Xtensa_EXCSAVE7 = 115,
Xtensa_F0 = 116,
Xtensa_F1 = 117,
Xtensa_F2 = 118,
Xtensa_F3 = 119,
Xtensa_F4 = 120,
Xtensa_F5 = 121,
Xtensa_F6 = 122,
Xtensa_F7 = 123,
Xtensa_F8 = 124,
Xtensa_F9 = 125,
Xtensa_F10 = 126,
Xtensa_F11 = 127,
Xtensa_F12 = 128,
Xtensa_F13 = 129,
Xtensa_F14 = 130,
Xtensa_F15 = 131,
Xtensa_IBREAKA0 = 132,
Xtensa_IBREAKA1 = 133,
Xtensa_M0 = 134,
Xtensa_M1 = 135,
Xtensa_M2 = 136,
Xtensa_M3 = 137,
Xtensa_MISC0 = 138,
Xtensa_MISC1 = 139,
Xtensa_MISC2 = 140,
Xtensa_MISC3 = 141,
Xtensa_Q0 = 142,
Xtensa_Q1 = 143,
Xtensa_Q2 = 144,
Xtensa_Q3 = 145,
Xtensa_Q4 = 146,
Xtensa_Q5 = 147,
Xtensa_Q6 = 148,
Xtensa_Q7 = 149,
Xtensa_SCOMPARE1 = 150,
Xtensa_U0 = 151,
Xtensa_U1 = 152,
Xtensa_U2 = 153,
Xtensa_U3 = 154,
Xtensa_F64R_HI = 155,
Xtensa_F64R_LO = 156,
Xtensa_F64S = 157,
Xtensa_B0_B1 = 158,
Xtensa_B2_B3 = 159,
Xtensa_B4_B5 = 160,
Xtensa_B6_B7 = 161,
Xtensa_B8_B9 = 162,
Xtensa_B10_B11 = 163,
Xtensa_B12_B13 = 164,
Xtensa_B14_B15 = 165,
Xtensa_B0_B1_B2_B3 = 166,
Xtensa_B4_B5_B6_B7 = 167,
Xtensa_B8_B9_B10_B11 = 168,
Xtensa_B12_B13_B14_B15 = 169,
NUM_TARGET_REGS // 170
};
// Register classes
enum {
Xtensa_BRRegClassID = 0,
Xtensa_BR2RegClassID = 1,
Xtensa_BR4RegClassID = 2,
Xtensa_SRRegClassID = 3,
Xtensa_ARRegClassID = 4,
Xtensa_FPRRegClassID = 5,
Xtensa_URRegClassID = 6,
Xtensa_MRRegClassID = 7,
Xtensa_MR01RegClassID = 8,
Xtensa_MR23RegClassID = 9,
Xtensa_AE_DRRegClassID = 10,
Xtensa_AE_VALIGNRegClassID = 11,
Xtensa_QRRegClassID = 12,
};
// Subregister indices
enum {
Xtensa_NoSubRegister,
Xtensa_bsub0, // 1
Xtensa_bsub1, // 2
Xtensa_bsub2, // 3
Xtensa_bsub3, // 4
Xtensa_NUM_TARGET_SUBREGS
};
#endif // GET_REGINFO_ENUM
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg XtensaRegDiffLists[] = {
/* 0 */ -87, 1, 0,
/* 3 */ -86, 1, 0,
/* 6 */ -85, 1, 0,
/* 9 */ -84, 1, 0,
/* 12 */ -83, 1, 0,
/* 15 */ -82, 1, 0,
/* 18 */ -81, 1, 0,
/* 21 */ -80, 1, 0,
/* 24 */ -95, 1, 1, 1, 0,
/* 29 */ -92, 1, 1, 1, 0,
/* 34 */ -89, 1, 1, 1, 0,
/* 39 */ -86, 1, 1, 1, 0,
/* 44 */ 79, 4, 0,
/* 47 */ 80, 4, 0,
/* 50 */ 80, 5, 0,
/* 53 */ 81, 5, 0,
/* 56 */ 82, 5, 0,
/* 59 */ 82, 6, 0,
/* 62 */ 83, 6, 0,
/* 65 */ 84, 6, 0,
/* 68 */ 84, 7, 0,
/* 71 */ 85, 7, 0,
/* 74 */ 86, 7, 0,
/* 77 */ 86, 8, 0,
/* 80 */ 87, 8, 0,
};
static const uint16_t XtensaSubRegIdxLists[] = {
/* 0 */ 1, 2, 0,
/* 3 */ 1, 2, 3, 4, 0,
};
static const MCRegisterDesc XtensaRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 759, 2, 2, 2, 8192, 8 },
{ 800, 2, 2, 2, 8193, 8 },
{ 917, 2, 2, 2, 8194, 8 },
{ 792, 2, 2, 2, 8195, 8 },
{ 740, 2, 2, 2, 8196, 8 },
{ 865, 2, 2, 2, 8197, 8 },
{ 642, 2, 2, 2, 8198, 8 },
{ 839, 2, 2, 2, 8199, 8 },
{ 697, 2, 2, 2, 8200, 8 },
{ 614, 2, 2, 2, 8201, 8 },
{ 688, 2, 2, 2, 8202, 8 },
{ 834, 2, 2, 2, 8203, 8 },
{ 708, 2, 2, 2, 8204, 8 },
{ 830, 2, 2, 2, 8205, 8 },
{ 745, 2, 2, 2, 8206, 8 },
{ 843, 2, 2, 2, 8207, 8 },
{ 908, 2, 2, 2, 8208, 8 },
{ 629, 2, 2, 2, 8209, 8 },
{ 872, 2, 2, 2, 8210, 8 },
{ 773, 2, 2, 2, 8211, 8 },
{ 817, 2, 2, 2, 8212, 8 },
{ 651, 2, 2, 2, 8213, 8 },
{ 886, 2, 2, 2, 8214, 8 },
{ 735, 2, 2, 2, 8215, 8 },
{ 879, 2, 2, 2, 8216, 8 },
{ 624, 2, 2, 2, 8217, 8 },
{ 669, 2, 2, 2, 8218, 8 },
{ 785, 2, 2, 2, 8219, 8 },
{ 619, 2, 2, 2, 8220, 8 },
{ 862, 2, 2, 2, 8221, 8 },
{ 609, 2, 2, 2, 8222, 8 },
{ 826, 2, 2, 2, 8223, 8 },
{ 726, 2, 2, 2, 8224, 8 },
{ 814, 2, 2, 2, 8225, 8 },
{ 847, 2, 2, 2, 8226, 8 },
{ 717, 2, 2, 2, 8227, 8 },
{ 661, 2, 2, 2, 8228, 8 },
{ 677, 2, 2, 2, 8229, 8 },
{ 896, 2, 2, 2, 8230, 8 },
{ 24, 2, 2, 2, 8231, 8 },
{ 237, 2, 2, 2, 8232, 8 },
{ 317, 2, 2, 2, 8233, 8 },
{ 392, 2, 2, 2, 8234, 8 },
{ 458, 2, 2, 2, 8235, 8 },
{ 497, 2, 2, 2, 8236, 8 },
{ 533, 2, 2, 2, 8237, 8 },
{ 578, 2, 2, 2, 8238, 8 },
{ 592, 2, 2, 2, 8239, 8 },
{ 0, 2, 2, 2, 8240, 8 },
{ 91, 2, 2, 2, 8241, 8 },
{ 219, 2, 2, 2, 8242, 8 },
{ 295, 2, 2, 2, 8243, 8 },
{ 374, 2, 2, 2, 8244, 8 },
{ 428, 2, 2, 2, 8245, 8 },
{ 54, 2, 2, 2, 8246, 8 },
{ 163, 2, 2, 2, 8247, 8 },
{ 254, 2, 2, 2, 8248, 8 },
{ 343, 2, 2, 2, 8249, 8 },
{ 403, 2, 2, 2, 8250, 8 },
{ 472, 2, 2, 2, 8251, 8 },
{ 508, 2, 2, 2, 8252, 8 },
{ 553, 2, 2, 2, 8253, 8 },
{ 584, 2, 2, 2, 8254, 8 },
{ 601, 2, 2, 2, 8255, 8 },
{ 8, 2, 2, 2, 8256, 8 },
{ 109, 2, 2, 2, 8257, 8 },
{ 227, 2, 2, 2, 8258, 8 },
{ 307, 2, 2, 2, 8259, 8 },
{ 382, 2, 2, 2, 8260, 8 },
{ 448, 2, 2, 2, 8261, 8 },
{ 36, 2, 80, 2, 8262, 8 },
{ 140, 2, 77, 2, 8263, 8 },
{ 240, 2, 74, 2, 8264, 8 },
{ 329, 2, 71, 2, 8265, 8 },
{ 395, 2, 71, 2, 8266, 8 },
{ 464, 2, 68, 2, 8267, 8 },
{ 500, 2, 65, 2, 8268, 8 },
{ 545, 2, 62, 2, 8269, 8 },
{ 581, 2, 62, 2, 8270, 8 },
{ 598, 2, 59, 2, 8271, 8 },
{ 4, 2, 56, 2, 8272, 8 },
{ 105, 2, 53, 2, 8273, 8 },
{ 223, 2, 53, 2, 8274, 8 },
{ 303, 2, 50, 2, 8275, 8 },
{ 378, 2, 47, 2, 8276, 8 },
{ 444, 2, 44, 2, 8277, 8 },
{ 69, 2, 2, 2, 8278, 8 },
{ 178, 2, 2, 2, 8279, 8 },
{ 259, 2, 2, 2, 8280, 8 },
{ 59, 2, 2, 2, 8281, 8 },
{ 168, 2, 2, 2, 8282, 8 },
{ 18, 2, 2, 2, 8283, 8 },
{ 119, 2, 2, 2, 8284, 8 },
{ 39, 2, 2, 2, 8285, 8 },
{ 143, 2, 2, 2, 8286, 8 },
{ 152, 2, 2, 2, 8287, 8 },
{ 243, 2, 2, 2, 8288, 8 },
{ 332, 2, 2, 2, 8289, 8 },
{ 398, 2, 2, 2, 8290, 8 },
{ 467, 2, 2, 2, 8291, 8 },
{ 503, 2, 2, 2, 8292, 8 },
{ 548, 2, 2, 2, 8293, 8 },
{ 287, 2, 2, 2, 8294, 8 },
{ 366, 2, 2, 2, 8295, 8 },
{ 423, 2, 2, 2, 8296, 8 },
{ 492, 2, 2, 2, 8297, 8 },
{ 528, 2, 2, 2, 8298, 8 },
{ 573, 2, 2, 2, 8299, 8 },
{ 198, 2, 2, 2, 8300, 8 },
{ 269, 2, 2, 2, 8301, 8 },
{ 348, 2, 2, 2, 8302, 8 },
{ 408, 2, 2, 2, 8303, 8 },
{ 477, 2, 2, 2, 8304, 8 },
{ 513, 2, 2, 2, 8305, 8 },
{ 558, 2, 2, 2, 8306, 8 },
{ 79, 2, 2, 2, 8307, 8 },
{ 207, 2, 2, 2, 8308, 8 },
{ 278, 2, 2, 2, 8309, 8 },
{ 357, 2, 2, 2, 8310, 8 },
{ 417, 2, 2, 2, 8311, 8 },
{ 486, 2, 2, 2, 8312, 8 },
{ 522, 2, 2, 2, 8313, 8 },
{ 567, 2, 2, 2, 8314, 8 },
{ 589, 2, 2, 2, 8315, 8 },
{ 606, 2, 2, 2, 8316, 8 },
{ 14, 2, 2, 2, 8317, 8 },
{ 115, 2, 2, 2, 8318, 8 },
{ 233, 2, 2, 2, 8319, 8 },
{ 313, 2, 2, 2, 8320, 8 },
{ 388, 2, 2, 2, 8321, 8 },
{ 454, 2, 2, 2, 8322, 8 },
{ 27, 2, 2, 2, 8323, 8 },
{ 128, 2, 2, 2, 8324, 8 },
{ 82, 2, 2, 2, 8325, 8 },
{ 210, 2, 2, 2, 8326, 8 },
{ 281, 2, 2, 2, 8327, 8 },
{ 360, 2, 2, 2, 8328, 8 },
{ 48, 2, 2, 2, 8329, 8 },
{ 157, 2, 2, 2, 8330, 8 },
{ 248, 2, 2, 2, 8331, 8 },
{ 337, 2, 2, 2, 8332, 8 },
{ 85, 2, 2, 2, 8333, 8 },
{ 213, 2, 2, 2, 8334, 8 },
{ 284, 2, 2, 2, 8335, 8 },
{ 363, 2, 2, 2, 8336, 8 },
{ 420, 2, 2, 2, 8337, 8 },
{ 489, 2, 2, 2, 8338, 8 },
{ 525, 2, 2, 2, 8339, 8 },
{ 570, 2, 2, 2, 8340, 8 },
{ 188, 2, 2, 2, 8341, 8 },
{ 88, 2, 2, 2, 8342, 8 },
{ 216, 2, 2, 2, 8343, 8 },
{ 292, 2, 2, 2, 8344, 8 },
{ 371, 2, 2, 2, 8345, 8 },
{ 765, 2, 2, 2, 8346, 8 },
{ 806, 2, 2, 2, 8347, 8 },
{ 857, 2, 2, 2, 8348, 8 },
{ 137, 0, 2, 0, 4166, 0 },
{ 326, 3, 2, 0, 4168, 0 },
{ 461, 6, 2, 0, 4170, 0 },
{ 542, 9, 2, 0, 4172, 0 },
{ 595, 12, 2, 0, 4174, 0 },
{ 101, 15, 2, 0, 4176, 0 },
{ 299, 18, 2, 0, 4178, 0 },
{ 440, 21, 2, 0, 4180, 0 },
{ 320, 24, 2, 3, 102470, 3 },
{ 536, 29, 2, 3, 102474, 3 },
{ 95, 34, 2, 3, 102478, 3 },
{ 432, 39, 2, 3, 102482, 3 },
};
// BR Register Class...
static const MCPhysReg BR[] = {
Xtensa_B0, Xtensa_B1, Xtensa_B2, Xtensa_B3, Xtensa_B4, Xtensa_B5, Xtensa_B6, Xtensa_B7, Xtensa_B8, Xtensa_B9, Xtensa_B10, Xtensa_B11, Xtensa_B12, Xtensa_B13, Xtensa_B14, Xtensa_B15,
};
// BR Bit set.
static const uint8_t BRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// BR2 Register Class...
static const MCPhysReg BR2[] = {
Xtensa_B0_B1, Xtensa_B2_B3, Xtensa_B4_B5, Xtensa_B6_B7, Xtensa_B8_B9, Xtensa_B10_B11, Xtensa_B12_B13, Xtensa_B14_B15,
};
// BR2 Bit set.
static const uint8_t BR2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
};
// BR4 Register Class...
static const MCPhysReg BR4[] = {
Xtensa_B0_B1_B2_B3, Xtensa_B4_B5_B6_B7, Xtensa_B8_B9_B10_B11, Xtensa_B12_B13_B14_B15,
};
// BR4 Bit set.
static const uint8_t BR4Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
};
// SR Register Class...
static const MCPhysReg SR[] = {
Xtensa_LBEG, Xtensa_LEND, Xtensa_LCOUNT, Xtensa_SAR, Xtensa_BREG, Xtensa_LITBASE, Xtensa_SCOMPARE1, Xtensa_ACCLO, Xtensa_ACCHI, Xtensa_M0, Xtensa_M1, Xtensa_M2, Xtensa_M3, Xtensa_WINDOWBASE, Xtensa_WINDOWSTART, Xtensa_IBREAKENABLE, Xtensa_MEMCTL, Xtensa_ATOMCTL, Xtensa_DDR, Xtensa_IBREAKA0, Xtensa_IBREAKA1, Xtensa_DBREAKA0, Xtensa_DBREAKA1, Xtensa_DBREAKC0, Xtensa_DBREAKC1, Xtensa_CONFIGID0, Xtensa_EPC1, Xtensa_EPC2, Xtensa_EPC3, Xtensa_EPC4, Xtensa_EPC5, Xtensa_EPC6, Xtensa_EPC7, Xtensa_DEPC, Xtensa_EPS2, Xtensa_EPS3, Xtensa_EPS4, Xtensa_EPS5, Xtensa_EPS6, Xtensa_EPS7, Xtensa_CONFIGID1, Xtensa_EXCSAVE1, Xtensa_EXCSAVE2, Xtensa_EXCSAVE3, Xtensa_EXCSAVE4, Xtensa_EXCSAVE5, Xtensa_EXCSAVE6, Xtensa_EXCSAVE7, Xtensa_CPENABLE, Xtensa_INTERRUPT, Xtensa_INTCLEAR, Xtensa_INTENABLE, Xtensa_PS, Xtensa_VECBASE, Xtensa_EXCCAUSE, Xtensa_DEBUGCAUSE, Xtensa_CCOUNT, Xtensa_PRID, Xtensa_ICOUNT, Xtensa_ICOUNTLEVEL, Xtensa_EXCVADDR, Xtensa_CCOMPARE0, Xtensa_CCOMPARE1, Xtensa_CCOMPARE2, Xtensa_MISC0, Xtensa_MISC1, Xtensa_MISC2, Xtensa_MISC3,
};
// SR Bit set.
static const uint8_t SRBits[] = {
0xf6, 0x1f, 0xfc, 0x7f, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0x3f, 0x40,
};
// AR Register Class...
static const MCPhysReg AR[] = {
Xtensa_A8, Xtensa_A9, Xtensa_A10, Xtensa_A11, Xtensa_A12, Xtensa_A13, Xtensa_A14, Xtensa_A15, Xtensa_A7, Xtensa_A6, Xtensa_A5, Xtensa_A4, Xtensa_A3, Xtensa_A2, Xtensa_A0, Xtensa_SP,
};
// AR Bit set.
static const uint8_t ARBits[] = {
0x00, 0x00, 0x00, 0x00, 0x04, 0xff, 0x7f,
};
// FPR Register Class...
static const MCPhysReg FPR[] = {
Xtensa_F8, Xtensa_F9, Xtensa_F10, Xtensa_F11, Xtensa_F12, Xtensa_F13, Xtensa_F14, Xtensa_F15, Xtensa_F7, Xtensa_F6, Xtensa_F5, Xtensa_F4, Xtensa_F3, Xtensa_F2, Xtensa_F1, Xtensa_F0,
};
// FPR Bit set.
static const uint8_t FPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
};
// UR Register Class...
static const MCPhysReg UR[] = {
Xtensa_GPIO_OUT, Xtensa_EXPSTATE, Xtensa_THREADPTR, Xtensa_FCR, Xtensa_FSR, Xtensa_F64R_LO, Xtensa_F64R_HI, Xtensa_F64S, Xtensa_ACCX, Xtensa_QACC, Xtensa_FFT_BIT_WIDTH, Xtensa_SAR_BYTE, Xtensa_UA_STATE,
};
// UR Bit set.
static const uint8_t URBits[] = {
0x08, 0xe0, 0x03, 0x80, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
};
// MR Register Class...
static const MCPhysReg MR[] = {
Xtensa_M0, Xtensa_M1, Xtensa_M2, Xtensa_M3,
};
// MR Bit set.
static const uint8_t MRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
};
// MR01 Register Class...
static const MCPhysReg MR01[] = {
Xtensa_M0, Xtensa_M1,
};
// MR01 Bit set.
static const uint8_t MR01Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
};
// MR23 Register Class...
static const MCPhysReg MR23[] = {
Xtensa_M2, Xtensa_M3,
};
// MR23 Bit set.
static const uint8_t MR23Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
};
// AE_DR Register Class...
static const MCPhysReg AE_DR[] = {
Xtensa_AED0, Xtensa_AED1, Xtensa_AED2, Xtensa_AED3, Xtensa_AED4, Xtensa_AED5, Xtensa_AED6, Xtensa_AED7, Xtensa_AED8, Xtensa_AED9, Xtensa_AED10, Xtensa_AED11, Xtensa_AED12, Xtensa_AED13, Xtensa_AED14, Xtensa_AED15,
};
// AE_DR Bit set.
static const uint8_t AE_DRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// AE_VALIGN Register Class...
static const MCPhysReg AE_VALIGN[] = {
Xtensa_U0, Xtensa_U1, Xtensa_U2, Xtensa_U3,
};
// AE_VALIGN Bit set.
static const uint8_t AE_VALIGNBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
};
// QR Register Class...
static const MCPhysReg QR[] = {
Xtensa_Q0, Xtensa_Q1, Xtensa_Q2, Xtensa_Q3, Xtensa_Q4, Xtensa_Q5, Xtensa_Q6, Xtensa_Q7,
};
// QR Bit set.
static const uint8_t QRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
};
static const MCRegisterClass XtensaMCRegisterClasses[] = {
{ BR, BRBits, sizeof(BRBits) },
{ BR2, BR2Bits, sizeof(BR2Bits) },
{ BR4, BR4Bits, sizeof(BR4Bits) },
{ SR, SRBits, sizeof(SRBits) },
{ AR, ARBits, sizeof(ARBits) },
{ FPR, FPRBits, sizeof(FPRBits) },
{ UR, URBits, sizeof(URBits) },
{ MR, MRBits, sizeof(MRBits) },
{ MR01, MR01Bits, sizeof(MR01Bits) },
{ MR23, MR23Bits, sizeof(MR23Bits) },
{ AE_DR, AE_DRBits, sizeof(AE_DRBits) },
{ AE_VALIGN, AE_VALIGNBits, sizeof(AE_VALIGNBits) },
{ QR, QRBits, sizeof(QRBits) },
};
static const uint16_t XtensaRegEncodingTable[] = {
0,
17,
16,
237,
99,
4,
234,
224,
104,
233,
192,
232,
238,
230,
232,
239,
233,
0,
96,
236,
237,
227,
228,
226,
0,
2,
1,
5,
97,
235,
230,
238,
3,
240,
1,
231,
241,
231,
72,
73,
0,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
240,
241,
242,
176,
208,
144,
145,
160,
161,
177,
178,
179,
180,
181,
182,
183,
194,
195,
196,
197,
198,
199,
209,
210,
211,
212,
213,
214,
215,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
128,
129,
32,
33,
34,
35,
244,
245,
246,
247,
0,
1,
2,
3,
4,
5,
6,
7,
12,
0,
1,
2,
3,
235,
234,
236,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
};
#endif // GET_REGINFO_MC_DESC

57
external/capstone/arch/Xtensa/XtensaGenSubtargetInfo.inc vendored Normal file
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@@ -0,0 +1,57 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
Xtensa_FeatureATOMCTL = 0,
Xtensa_FeatureBoolean = 1,
Xtensa_FeatureCLAMPS = 2,
Xtensa_FeatureCoprocessor = 3,
Xtensa_FeatureDFPAccel = 4,
Xtensa_FeatureDebug = 5,
Xtensa_FeatureDensity = 6,
Xtensa_FeatureDiv32 = 7,
Xtensa_FeatureESP32S2Ops = 8,
Xtensa_FeatureESP32S3Ops = 9,
Xtensa_FeatureException = 10,
Xtensa_FeatureExtendedL32R = 11,
Xtensa_FeatureForcedAtomics = 12,
Xtensa_FeatureHIFI3 = 13,
Xtensa_FeatureHighPriInterrupts = 14,
Xtensa_FeatureInterrupt = 15,
Xtensa_FeatureLoop = 16,
Xtensa_FeatureMAC16 = 17,
Xtensa_FeatureMEMCTL = 18,
Xtensa_FeatureMINMAX = 19,
Xtensa_FeatureMiscSR = 20,
Xtensa_FeatureMul16 = 21,
Xtensa_FeatureMul32 = 22,
Xtensa_FeatureMul32High = 23,
Xtensa_FeatureNSA = 24,
Xtensa_FeaturePRID = 25,
Xtensa_FeatureRegionProtection = 26,
Xtensa_FeatureRelocatableVector = 27,
Xtensa_FeatureS32C1I = 28,
Xtensa_FeatureSEXT = 29,
Xtensa_FeatureSingleFloat = 30,
Xtensa_FeatureTHREADPTR = 31,
Xtensa_FeatureTimerInt = 32,
Xtensa_FeatureWindowed = 33,
Xtensa_NumSubtargetFeatures = 34
};
#endif // GET_SUBTARGETINFO_ENUM

700
external/capstone/arch/Xtensa/XtensaInstPrinter.c vendored Normal file
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@@ -0,0 +1,700 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- XtensaInstPrinter.cpp - Convert Xtensa MCInst to asm syntax --------===//
//
// The LLVM Compiler Infrastructure
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an Xtensa MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInstPrinter.h"
#include "../../SStream.h"
#include "./priv.h"
#include "../../Mapping.h"
#include "XtensaMapping.h"
#include "../../MathExtras.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O);
static const char *getRegisterName(unsigned RegNo);
typedef MCRegister Register;
static void printRegName(SStream *O, MCRegister Reg)
{
SStream_concat0(O, getRegisterName(Reg));
}
static void printOp(MCInst *MI, MCOperand *MC, SStream *O)
{
if (MCOperand_isReg(MC))
SStream_concat0(O, getRegisterName(MCOperand_getReg(MC)));
else if (MCOperand_isImm(MC))
printInt64(O, MCOperand_getImm(MC));
else if (MCOperand_isExpr(MC))
printExpr(MCOperand_getExpr(MC), O);
else
CS_ASSERT("Invalid operand");
}
static void printOperand(MCInst *MI, const int op_num, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Operand, op_num);
printOp(MI, MCInst_getOperand(MI, op_num), O);
}
static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_MemOperand, OpNum);
SStream_concat0(OS, getRegisterName(MCOperand_getReg(
MCInst_getOperand(MI, (OpNum)))));
SStream_concat0(OS, ", ");
printOp(MI, MCInst_getOperand(MI, OpNum + 1), OS);
}
static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_BranchTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printLoopTarget(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_LoopTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_JumpTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
;
}
static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_CallOperand, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_L32RTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
SStream_concat0(O, ". ");
printInt64(O, Xtensa_L32R_Value(MI, OpNum));
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
isIntN(8, Value) &&
"Invalid argument, value must be in ranges [-128,127]");
printInt64(O, Value);
} else {
printOperand(MI, OpNum, O);
}
}
static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_sh8_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(isIntN(16, Value) && ((Value & 0xFF) == 0)) &&
"Invalid argument, value must be multiples of 256 in range "
"[-32768,32512]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm12_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -2048 && Value <= 2047) &&
"Invalid argument, value must be in ranges [-2048,2047]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12m_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -2048 && Value <= 2047) &&
"Invalid argument, value must be in ranges [-2048,2047]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm4_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 15) && "Invalid argument");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm5_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 31) && "Invalid argument");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm1_31_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 1 && Value <= 31) &&
"Invalid argument, value must be in range [1,31]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printShimm0_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm0_31_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 31) &&
"Invalid argument, value must be in range [0,31]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1_16_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 1 && Value <= 16) &&
"Invalid argument, value must be in range [1,16]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm1n_15_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1n_15_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -1 && (Value != 0) && Value <= 15) &&
"Invalid argument, value must be in ranges <-1,-1> or <1,15>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm32n_95_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm32n_95_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= -32 && Value <= 95) &&
"Invalid argument, value must be in ranges <-32,95>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm8n_7_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8n_7_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= -8 && Value <= 7) &&
"Invalid argument, value must be in ranges <-8,7>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm64n_4n_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm64n_4n_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= -64 && Value <= -4) &
((Value & 0x3) == 0) &&
"Invalid argument, value must be in ranges <-64,-4>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset8m32_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset8m32_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= 0 && Value <= 1020 && ((Value & 0x3) == 0)) &&
"Invalid argument, value must be multiples of four in range [0,1020]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printEntry_Imm12_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Entry_Imm12_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= 0 && Value <= 32760) &&
"Invalid argument, value must be multiples of eight in range "
"<0,32760>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4const_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
switch (Value) {
case -1:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 10:
case 12:
case 16:
case 32:
case 64:
case 128:
case 256:
break;
default:
CS_ASSERT((0) && "Invalid B4const argument");
}
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4constu_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
switch (Value) {
case 32768:
case 65536:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 10:
case 12:
case 16:
case 32:
case 64:
case 128:
case 256:
break;
default:
CS_ASSERT((0) && "Invalid B4constu argument");
}
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm7_22_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm7_22_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 7 && Value <= 22) &&
"Invalid argument, value must be in range <7,22>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_2_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_2_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 1) &&
"Invalid argument, value must be in range [0,1]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_4_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 3) &&
"Invalid argument, value must be in range [0,3]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_8_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 7) &&
"Invalid argument, value must be in range [0,7]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_16_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 15) &&
"Invalid argument, value must be in range [0,15]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_256_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_256_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 255) &&
"Invalid argument, value must be in range [0,255]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_16_16_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_16_16_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -128 && Value <= 112 && (Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-128,112], first 4 bits "
"should be zero");
printInt64(O, Value);
} else {
printOperand(MI, OpNum, O);
}
}
static inline void printOffset_256_8_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_8_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -1024 && Value <= 1016 &&
(Value & 0x7) == 0) &&
"Invalid argument, value must be in range [-1024,1016], first 3 "
"bits should be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_256_16_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_16_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -2048 && Value <= 2032 &&
(Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-2048,2032], first 4 "
"bits should be zero");
printInt64(O, Value);
} else {
printOperand(MI, OpNum, O);
}
}
static inline void printOffset_256_4_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_4_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -512 && Value <= 508 && (Value & 0x3) == 0) &&
"Invalid argument, value must be in range [-512,508], first 2 bits "
"should be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_128_2_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_2_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= 0 && Value <= 254 && (Value & 0x1) == 0) &&
"Invalid argument, value must be in range [0,254], first bit should "
"be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_128_1_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_1_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 127) &&
"Invalid argument, value must be in range [0,127]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_64_16_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_64_16_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -512 && Value <= 496 && (Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-512,496], first 4 bits "
"should be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
#define IMPL_printImmOperand(N, L, H, S) \
static void printImmOperand_##N(MCInst *MI, int OpNum, SStream *O) \
{ \
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_ImmOperand_##N, \
OpNum); \
MCOperand *MC = MCInst_getOperand(MI, (OpNum)); \
if (MCOperand_isImm(MC)) { \
int64_t Value = MCOperand_getImm(MC); \
CS_ASSERT((Value >= L && Value <= H && \
((Value % S) == 0)) && \
"Invalid argument"); \
printInt64(O, Value); \
} else { \
printOperand(MI, OpNum, O); \
} \
}
IMPL_printImmOperand(minus64_56_8, -64, 56, 8);
IMPL_printImmOperand(minus32_28_4, -32, 28, 4);
IMPL_printImmOperand(minus16_47_1, -16, 47, 1);
IMPL_printImmOperand(minus16_14_2, -16, 14, 2);
IMPL_printImmOperand(0_56_8, 0, 56, 8);
IMPL_printImmOperand(0_3_1, 0, 3, 1);
IMPL_printImmOperand(0_63_1, 0, 63, 1);
#include "XtensaGenAsmWriter.inc"
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
unsigned Opcode = MCInst_getOpcode(MI);
switch (Opcode) {
case Xtensa_WSR: {
// INTERRUPT mnemonic is read-only, so use INTSET mnemonic instead
Register SR = MCOperand_getReg(MCInst_getOperand(MI, (0)));
if (SR == Xtensa_INTERRUPT) {
Register Reg =
MCOperand_getReg(MCInst_getOperand(MI, (1)));
SStream_concat1(O, '\t');
SStream_concat(O, "%s", "wsr");
SStream_concat0(O, "\t");
printRegName(O, Reg);
SStream_concat(O, "%s", ", ");
SStream_concat0(O, "intset");
;
return;
}
}
}
printInstruction(MI, Address, O);
}
void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O)
{
printInst(MI, Address, NULL, O);
}
const char *Xtensa_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}

45
external/capstone/arch/Xtensa/XtensaInstPrinter.h vendored Normal file
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- XtensaInstPrinter.h - Convert Xtensa MCInst to asm syntax -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an Xtensa MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H
#define LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#include "priv.h"
const char *Xtensa_LLVM_getRegisterName(unsigned RegNo);
void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O);
#endif /* LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H */

273
external/capstone/arch/Xtensa/XtensaMapping.c vendored Normal file
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/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#include <capstone/xtensa.h>
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../Mapping.h"
#include "../../utils.h"
#include "../../cs_simple_types.h"
#include "XtensaDisassembler.h"
#include "XtensaInstPrinter.h"
#include "priv.h"
#include "XtensaMapping.h"
#ifndef CAPSTONE_DIET
static const char *const insn_name_maps[] = {
#include "XtensaGenCSMappingInsnName.inc"
};
static const name_map group_name_maps[] = {
#include "XtensaGenCSFeatureName.inc"
};
static const insn_map mapping_insns[] = {
#include "XtensaGenCSMappingInsn.inc"
};
static const map_insn_ops insn_operands[] = {
#include "XtensaGenCSMappingInsnOp.inc"
};
#endif
#define GET_REGINFO_MC_DESC
#include "XtensaGenRegisterInfo.inc"
#include "../../MathExtras.h"
void Xtensa_init_mri(MCRegisterInfo *mri)
{
MCRegisterInfo_InitMCRegisterInfo(
mri, XtensaRegDesc, ARR_SIZE(XtensaRegDesc), 0, 0,
XtensaMCRegisterClasses, ARR_SIZE(XtensaMCRegisterClasses), 0,
0, XtensaRegDiffLists, NULL, XtensaSubRegIdxLists,
ARR_SIZE(XtensaSubRegIdxLists), XtensaRegEncodingTable);
}
void Xtensa_printer(MCInst *MI, SStream *OS, void *info)
{
Xtensa_LLVM_printInstruction(MI, MI->address, OS);
}
static void set_instr_map_data(MCInst *MI)
{
#ifndef CAPSTONE_DIET
map_cs_id(MI, mapping_insns, ARR_SIZE(mapping_insns));
map_implicit_reads(MI, mapping_insns);
map_implicit_writes(MI, mapping_insns);
map_groups(MI, mapping_insns);
const xtensa_suppl_info *suppl_info =
map_get_suppl_info(MI, mapping_insns);
if (suppl_info) {
Xtensa_get_detail(MI)->format = suppl_info->form;
}
#endif
}
bool Xtensa_disasm(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info)
{
DecodeStatus res = Xtensa_LLVM_getInstruction(instr, size, code,
code_len, address);
if (res != MCDisassembler_Fail) {
set_instr_map_data(instr);
}
if (res == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return res != MCDisassembler_Fail;
}
const char *Xtensa_reg_name(csh handle, unsigned int id)
{
return Xtensa_LLVM_getRegisterName(id);
}
void Xtensa_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Done in Xtensa_disasm
}
const char *Xtensa_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id >= ARR_SIZE(insn_name_maps)) {
return NULL;
}
return insn_name_maps[id];
#else
return NULL;
#endif
}
const char *Xtensa_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_xtensa *detail = &(insn->detail->xtensa);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < detail->op_count; i++) {
cs_xtensa_op *op = &(detail->operands[i]);
switch (op->type) {
case XTENSA_OP_REG:
if ((op->access & CS_AC_READ) &&
!arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) &&
!arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
case XTENSA_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != XTENSA_REG_INVALID) &&
!arr_exist(regs_read, read_count, op->mem.base)) {
regs_read[read_count] = (uint16_t)op->mem.base;
read_count++;
}
if ((insn->detail->writeback) &&
(op->mem.base != XTENSA_REG_INVALID) &&
!arr_exist(regs_write, write_count, op->mem.base)) {
regs_write[write_count] =
(uint16_t)op->mem.base;
write_count++;
}
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
#endif
int64_t Xtensa_L32R_Value(MCInst *MI, int op_num)
{
int64_t InstrOff = MCOperand_getImm(MCInst_getOperand(MI, (op_num)));
CS_ASSERT((InstrOff >= -262144 && InstrOff <= -4) &&
"Invalid argument, value must be in ranges [-262144,-4]");
int64_t Value = 0;
if (MI->csh->LITBASE & 0x1) {
Value = (MI->csh->LITBASE & 0xfffff000) + InstrOff;
} else {
Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff;
}
return Value;
}
void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num)
{
if (!detail_is_set(MI)) {
return;
}
cs_xtensa_op *xop = Xtensa_get_detail_op(MI, 0);
switch (op_group) {
case Xtensa_OP_GROUP_Operand: {
const MCOperand *MC = MCInst_getOperand(MI, op_num);
if (MCOperand_isReg(MC)) {
xop->type = XTENSA_OP_REG;
xop->reg = MC->RegVal;
} else if (MCOperand_isImm(MC)) {
xop->type = XTENSA_OP_IMM;
xop->imm = MC->ImmVal;
}
} break;
case Xtensa_OP_GROUP_Imm1_16_AsmOperand:
case Xtensa_OP_GROUP_Imm1n_15_AsmOperand:
case Xtensa_OP_GROUP_Imm7_22_AsmOperand:
case Xtensa_OP_GROUP_Imm8_AsmOperand:
case Xtensa_OP_GROUP_Imm8_sh8_AsmOperand:
case Xtensa_OP_GROUP_Imm8n_7_AsmOperand:
case Xtensa_OP_GROUP_Imm12_AsmOperand:
case Xtensa_OP_GROUP_Imm12m_AsmOperand:
case Xtensa_OP_GROUP_Imm32n_95_AsmOperand:
case Xtensa_OP_GROUP_Imm64n_4n_AsmOperand:
case Xtensa_OP_GROUP_ImmOperand_minus32_28_4:
case Xtensa_OP_GROUP_Uimm5_AsmOperand:
case Xtensa_OP_GROUP_Uimm4_AsmOperand:
case Xtensa_OP_GROUP_Shimm0_31_AsmOperand:
case Xtensa_OP_GROUP_Shimm1_31_AsmOperand:
case Xtensa_OP_GROUP_B4const_AsmOperand:
case Xtensa_OP_GROUP_B4constu_AsmOperand:
case Xtensa_OP_GROUP_ImmOperand_minus16_14_2:
case Xtensa_OP_GROUP_ImmOperand_minus64_56_8:
case Xtensa_OP_GROUP_ImmOperand_0_56_8:
case Xtensa_OP_GROUP_ImmOperand_minus16_47_1:
case Xtensa_OP_GROUP_ImmOperand_0_3_1:
case Xtensa_OP_GROUP_ImmOperand_0_63_1:
case Xtensa_OP_GROUP_Entry_Imm12_AsmOperand:
case Xtensa_OP_GROUP_Offset8m32_AsmOperand:
case Xtensa_OP_GROUP_Select_4_AsmOperand:
case Xtensa_OP_GROUP_Select_2_AsmOperand:
case Xtensa_OP_GROUP_Select_8_AsmOperand:
case Xtensa_OP_GROUP_Offset_16_16_AsmOperand:
case Xtensa_OP_GROUP_Offset_256_8_AsmOperand:
case Xtensa_OP_GROUP_Offset_256_16_AsmOperand:
case Xtensa_OP_GROUP_Offset_256_4_AsmOperand:
case Xtensa_OP_GROUP_Select_16_AsmOperand:
case Xtensa_OP_GROUP_Offset_128_2_AsmOperand:
case Xtensa_OP_GROUP_Offset_128_1_AsmOperand:
case Xtensa_OP_GROUP_Offset_64_16_AsmOperand:
case Xtensa_OP_GROUP_Select_256_AsmOperand: {
int64_t val = MCOperand_getImm(MCInst_getOperand(MI, op_num));
xop->type = XTENSA_OP_IMM;
xop->imm = (int32_t)val;
} break;
case Xtensa_OP_GROUP_BranchTarget:
case Xtensa_OP_GROUP_JumpTarget:
case Xtensa_OP_GROUP_CallOperand:
case Xtensa_OP_GROUP_LoopTarget: {
int64_t val =
MCOperand_getImm(MCInst_getOperand(MI, op_num)) + 4;
xop->type = XTENSA_OP_IMM;
xop->imm = (int32_t)val;
} break;
case Xtensa_OP_GROUP_L32RTarget: {
xop->type = XTENSA_OP_L32R;
xop->imm = (int32_t)Xtensa_L32R_Value(MI, op_num);
} break;
case Xtensa_OP_GROUP_MemOperand: {
unsigned reg =
MCOperand_getReg(MCInst_getOperand(MI, (op_num)));
int64_t imm8 =
MCOperand_getImm(MCInst_getOperand(MI, op_num + 1));
xop->type = XTENSA_OP_MEM;
xop->mem.base = reg;
xop->mem.disp = (int32_t)imm8;
} break;
}
xop->access = map_get_op_access(MI, op_num);
Xtensa_inc_op_count(MI);
}

31
external/capstone/arch/Xtensa/XtensaMapping.h vendored Normal file
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/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#ifndef XTENSA_MAPPING_H
#define XTENSA_MAPPING_H
#include "../../Mapping.h"
typedef enum {
#include "XtensaGenCSOpGroup.inc"
} xtensa_op_group;
int64_t Xtensa_L32R_Value(MCInst *MI, int op_num);
void Xtensa_init_mri(MCRegisterInfo *mri);
void Xtensa_printer(MCInst *MI, SStream *OS, void *info);
bool Xtensa_disasm(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
const char *Xtensa_reg_name(csh handle, unsigned int id);
void Xtensa_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *Xtensa_insn_name(csh handle, unsigned int id);
const char *Xtensa_group_name(csh handle, unsigned int id);
#ifndef CAPSTONE_DIET
void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
#endif
void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num);
#endif

47
external/capstone/arch/Xtensa/XtensaModule.c vendored Normal file
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/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "XtensaInstPrinter.h"
#include "XtensaMapping.h"
#include "XtensaModule.h"
cs_err Xtensa_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_calloc(1, sizeof(*mri));
Xtensa_init_mri(mri);
ud->printer = Xtensa_printer;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = Xtensa_disasm;
ud->reg_name = Xtensa_reg_name;
ud->insn_id = Xtensa_insn_id;
ud->insn_name = Xtensa_insn_name;
ud->group_name = Xtensa_group_name;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = Xtensa_reg_access;
#endif
return CS_ERR_OK;
}
cs_err Xtensa_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX) {
handle->syntax |= (int)value;
}
if (type == CS_OPT_MODE) {
handle->mode |= (cs_mode)value;
}
if (type == CS_OPT_LITBASE) {
handle->LITBASE = (uint32_t)value;
}
return CS_ERR_OK;
}

10
external/capstone/arch/Xtensa/XtensaModule.h vendored Normal file
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/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#ifndef CS_XTENSA_MODULE_H
#define CS_XTENSA_MODULE_H
cs_err Xtensa_global_init(cs_struct *ud);
cs_err Xtensa_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif

20
external/capstone/arch/Xtensa/priv.h vendored Normal file
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/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#ifndef CAPSTONE_PRIV_H
#define CAPSTONE_PRIV_H
#define llvm_unreachable(x) assert(0 && x)
#define printExpr(E, O) assert(0 && "unimplemented expr")
#define MCExpr_print(E, OS, MAI, InParens) assert(0 && "unimplemented expr")
#define GET_REGINFO_ENUM
#include "XtensaGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "XtensaGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "XtensaGenSubtargetInfo.inc"
#endif //CAPSTONE_PRIV_H