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#include <Core.hpp>
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#include <log.hpp>
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namespace n64 {
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RSP::RSP() { Reset(); }
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void RSP::Reset() {
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lastSuccessfulSPAddr.raw = 0;
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lastSuccessfulDRAMAddr.raw = 0;
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spStatus.raw = 0;
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spStatus.halt = true;
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oldPC = 0;
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pc = 0;
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nextPC = 4;
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spDMASPAddr.raw = 0;
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spDMADRAMAddr.raw = 0;
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spDMALen.raw = 0;
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dmem = {};
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imem = {};
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memset(vpr, 0, 32 * sizeof(VPR));
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memset(gpr, 0, 32 * sizeof(u32));
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memset(&vce, 0, sizeof(VPR));
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memset(&acc, 0, 3 * sizeof(VPR));
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memset(&vcc, 0, 2 * sizeof(VPR));
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memset(&vco, 0, 2 * sizeof(VPR));
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semaphore = false;
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divIn = 0;
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divOut = 0;
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divInLoaded = false;
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steps = 0;
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}
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/*
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FORCE_INLINE void logRSP(const RSP& rsp, const u32 instr) {
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debug("{:04X} {:08X} ", rsp.oldPC, instr);
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for (auto gpr : rsp.gpr) {
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debug("{:08X} ", gpr);
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}
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for (auto vpr : rsp.vpr) {
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for (int i = 0; i < 8; i++) {
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debug("{:04X}", vpr.element[i]);
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}
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debug(" ");
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}
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for (int i = 0; i < 8; i++) {
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debug("{:04X}", rsp.acc.h.element[i]);
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}
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debug(" ");
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for (int i = 0; i < 8; i++) {
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debug("{:04X}", rsp.acc.m.element[i]);
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}
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debug(" ");
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for (int i = 0; i < 8; i++) {
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debug("{:04X}", rsp.acc.l.element[i]);
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}
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debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
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debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
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}
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*/
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auto RSP::Read(const u32 addr) -> u32 {
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switch (addr) {
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case 0x04040000:
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return lastSuccessfulSPAddr.raw & 0x1FF8;
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case 0x04040004:
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return lastSuccessfulDRAMAddr.raw & 0xFFFFF8;
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case 0x04040008:
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case 0x0404000C:
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return spDMALen.raw;
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case 0x04040010:
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return spStatus.raw;
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case 0x04040014:
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return spStatus.dmaFull;
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case 0x04040018:
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return 0;
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case 0x0404001C:
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return AcquireSemaphore();
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case 0x04080000:
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return pc & 0xFFC;
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default:
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panic("Unimplemented SP register read {:08X}", addr);
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}
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}
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void RSP::WriteStatus(const u32 value) {
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Mem& mem = Core::GetMem();
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Registers& regs = Core::GetRegs();
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MI &mi = mem.mmio.mi;
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const auto write = SPStatusWrite{.raw = value};
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if (write.clearHalt && !write.setHalt) {
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spStatus.halt = false;
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}
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if (write.setHalt && !write.clearHalt) {
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regs.steps = 0;
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spStatus.halt = true;
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}
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if (write.clearBroke)
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spStatus.broke = false;
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if (write.clearIntr && !write.setIntr)
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mi.InterruptLower(MI::Interrupt::SP);
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if (write.setIntr && !write.clearIntr)
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mi.InterruptRaise(MI::Interrupt::SP);
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#define CLEAR_SET(val, clear, set) \
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do { \
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if ((clear) && !(set)) \
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(val) = 0; \
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if ((set) && !(clear)) \
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(val) = 1; \
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} \
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while (0)
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CLEAR_SET(spStatus.singleStep, write.clearSstep, write.setSstep);
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CLEAR_SET(spStatus.interruptOnBreak, write.clearIntrOnBreak, write.setIntrOnBreak);
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CLEAR_SET(spStatus.signal0, write.clearSignal0, write.setSignal0);
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CLEAR_SET(spStatus.signal1, write.clearSignal1, write.setSignal1);
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CLEAR_SET(spStatus.signal2, write.clearSignal2, write.setSignal2);
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CLEAR_SET(spStatus.signal3, write.clearSignal3, write.setSignal3);
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CLEAR_SET(spStatus.signal4, write.clearSignal4, write.setSignal4);
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CLEAR_SET(spStatus.signal5, write.clearSignal5, write.setSignal5);
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CLEAR_SET(spStatus.signal6, write.clearSignal6, write.setSignal6);
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CLEAR_SET(spStatus.signal7, write.clearSignal7, write.setSignal7);
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#undef CLEAR_SET
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}
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template <>
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void RSP::DMA<true>() {
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Mem& mem = Core::GetMem();
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u32 length = spDMALen.len + 1;
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length = (length + 0x7) & ~0x7;
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const auto &src = spDMASPAddr.bank ? imem : dmem;
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u32 mem_address = spDMASPAddr.address & 0xFF8;
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u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
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trace("SP DMA from RSP to RDRAM (size: {} B, {:08X} to {:08X})", length, mem_address, dram_address);
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for (u32 i = 0; i < spDMALen.count + 1; i++) {
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for (u32 j = 0; j < length; j++) {
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mem.mmio.rdp.WriteRDRAM<u8>(BYTE_ADDRESS(dram_address + j), src[(mem_address + j) & DMEM_DSIZE]);
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}
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const int skip = i == spDMALen.count ? 0 : spDMALen.skip;
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dram_address += (length + skip);
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dram_address &= 0xFFFFF8;
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mem_address += length;
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mem_address &= 0xFF8;
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}
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trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
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lastSuccessfulSPAddr.address = mem_address;
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lastSuccessfulSPAddr.bank = spDMASPAddr.bank;
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lastSuccessfulDRAMAddr.address = dram_address;
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spDMALen.raw = 0xFF8 | (spDMALen.skip << 20);
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}
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template <>
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void RSP::DMA<false>() {
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Mem& mem = Core::GetMem();
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u32 length = spDMALen.len + 1;
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length = (length + 0x7) & ~0x7;
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auto &dst = spDMASPAddr.bank ? imem : dmem;
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u32 mem_address = spDMASPAddr.address & 0xFF8;
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u32 dram_address = spDMADRAMAddr.address & 0xFFFFF8;
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trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
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for (u32 i = 0; i < spDMALen.count + 1; i++) {
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for (u32 j = 0; j < length; j++) {
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dst[(mem_address + j) & DMEM_DSIZE] = mem.mmio.rdp.ReadRDRAM<u8>(BYTE_ADDRESS(dram_address + j));
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}
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const int skip = i == spDMALen.count ? 0 : spDMALen.skip;
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dram_address += (length + skip);
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dram_address &= 0xFFFFF8;
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mem_address += length;
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mem_address &= 0xFF8;
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}
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trace("Addresses after: RSP: 0x{:08X}, Dram: 0x{:08X}", mem_address, dram_address);
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lastSuccessfulSPAddr.address = mem_address;
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lastSuccessfulSPAddr.bank = spDMASPAddr.bank;
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lastSuccessfulDRAMAddr.address = dram_address;
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spDMALen.raw = 0xFF8 | (spDMALen.skip << 20);
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}
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void RSP::Write(const u32 addr, const u32 val) {
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switch (addr) {
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case 0x04040000:
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spDMASPAddr.raw = val & 0x1FF8;
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break;
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case 0x04040004:
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spDMADRAMAddr.raw = val & 0xFFFFF8;
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break;
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case 0x04040008:
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spDMALen.raw = val;
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DMA<false>();
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break;
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case 0x0404000C:
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spDMALen.raw = val;
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DMA<true>();
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break;
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case 0x04040010:
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WriteStatus(val);
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break;
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case 0x0404001C:
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ReleaseSemaphore();
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break;
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case 0x04080000:
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if (spStatus.halt) {
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SetPC(val);
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}
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break;
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default:
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panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, val);
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}
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}
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} // namespace n64
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