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@@ -0,0 +1,4 @@
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file(GLOB_RECURSE SOURCES *.cpp)
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file(GLOB_RECURSE HEADERS *.hpp)
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add_library(jit ${SOURCES} ${HEADERS})
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@@ -0,0 +1,465 @@
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#include <JIT.hpp>
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#include <Instruction.hpp>
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namespace n64 {
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void JIT::special(const Instruction instr) {
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// 00rr_rccc
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switch (instr.special()) {
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case Instruction::SLL:
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if (instr != 0) {
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sll(instr);
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}
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break;
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case Instruction::SRL:
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srl(instr);
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break;
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case Instruction::SRA:
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sra(instr);
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break;
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case Instruction::SLLV:
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sllv(instr);
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break;
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case Instruction::SRLV:
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srlv(instr);
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break;
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case Instruction::SRAV:
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srav(instr);
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break;
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case Instruction::JR:
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jr(instr);
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break;
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case Instruction::JALR:
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jalr(instr);
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break;
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case Instruction::SYSCALL:
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regs.cop0.FireException(ExceptionCode::Syscall, 0, regs.oldPC);
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break;
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case Instruction::BREAK:
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regs.cop0.FireException(ExceptionCode::Breakpoint, 0, regs.oldPC);
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break;
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case Instruction::SYNC:
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break; // SYNC
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case Instruction::MFHI:
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mfhi(instr);
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break;
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case Instruction::MTHI:
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mthi(instr);
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break;
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case Instruction::MFLO:
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mflo(instr);
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break;
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case Instruction::MTLO:
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mtlo(instr);
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break;
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case Instruction::DSLLV:
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dsllv(instr);
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break;
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case Instruction::DSRLV:
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dsrlv(instr);
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break;
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case Instruction::DSRAV:
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dsrav(instr);
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break;
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case Instruction::MULT:
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mult(instr);
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break;
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case Instruction::MULTU:
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multu(instr);
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break;
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case Instruction::DIV:
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div(instr);
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break;
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case Instruction::DIVU:
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divu(instr);
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break;
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case Instruction::DMULT:
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dmult(instr);
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break;
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case Instruction::DMULTU:
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dmultu(instr);
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break;
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case Instruction::DDIV:
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ddiv(instr);
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break;
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case Instruction::DDIVU:
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ddivu(instr);
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break;
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case Instruction::ADD:
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add(instr);
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break;
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case Instruction::ADDU:
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addu(instr);
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break;
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case Instruction::SUB:
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sub(instr);
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break;
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case Instruction::SUBU:
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subu(instr);
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break;
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case Instruction::AND:
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and_(instr);
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break;
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case Instruction::OR:
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or_(instr);
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break;
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case Instruction::XOR:
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xor_(instr);
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break;
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case Instruction::NOR:
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nor(instr);
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break;
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case Instruction::SLT:
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slt(instr);
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break;
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case Instruction::SLTU:
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sltu(instr);
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break;
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case Instruction::DADD:
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dadd(instr);
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break;
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case Instruction::DADDU:
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daddu(instr);
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break;
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case Instruction::DSUB:
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dsub(instr);
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break;
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case Instruction::DSUBU:
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dsubu(instr);
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break;
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case Instruction::TGE:
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trap(regs.Read<s64>(instr.rs()) >= regs.Read<s64>(instr.rt()));
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break;
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case Instruction::TGEU:
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trap(regs.Read<u64>(instr.rs()) >= regs.Read<u64>(instr.rt()));
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break;
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case Instruction::TLT:
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trap(regs.Read<s64>(instr.rs()) < regs.Read<s64>(instr.rt()));
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break;
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case Instruction::TLTU:
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trap(regs.Read<u64>(instr.rs()) < regs.Read<u64>(instr.rt()));
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break;
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case Instruction::TEQ:
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trap(regs.Read<s64>(instr.rs()) == regs.Read<s64>(instr.rt()));
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break;
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case Instruction::TNE:
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trap(regs.Read<s64>(instr.rs()) != regs.Read<s64>(instr.rt()));
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break;
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case Instruction::DSLL:
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dsll(instr);
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break;
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case Instruction::DSRL:
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dsrl(instr);
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break;
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case Instruction::DSRA:
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dsra(instr);
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break;
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case Instruction::DSLL32:
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dsll32(instr);
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break;
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case Instruction::DSRL32:
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dsrl32(instr);
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break;
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case Instruction::DSRA32:
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dsra32(instr);
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break;
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default:
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panic("Unimplemented special {} ({:08X}) (pc: {:016X})", instr.special(), u32(instr),
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static_cast<u64>(regs.oldPC));
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}
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}
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void JIT::regimm(const Instruction instr) {
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// 000r_rccc
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switch (instr.regimm()) {
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case Instruction::BLTZ:
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bltz(instr);
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break;
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case Instruction::BGEZ:
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bgez(instr);
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break;
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case Instruction::BLTZL:
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bltzl(instr);
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break;
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case Instruction::BGEZL:
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bgezl(instr);
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break;
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case Instruction::TGEI:
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trap(regs.Read<s64>(instr.rs()) >= static_cast<s64>(static_cast<s16>(instr)));
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break;
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case Instruction::TGEIU:
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trap(regs.Read<u64>(instr.rs()) >= static_cast<u64>(static_cast<s64>(static_cast<s16>(instr))));
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break;
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case Instruction::TLTI:
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trap(regs.Read<s64>(instr.rs()) < static_cast<s64>(static_cast<s16>(instr)));
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break;
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case Instruction::TLTIU:
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trap(regs.Read<u64>(instr.rs()) < static_cast<u64>(static_cast<s64>(static_cast<s16>(instr))));
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break;
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case Instruction::TEQI:
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trap(regs.Read<s64>(instr.rs()) == static_cast<s64>(static_cast<s16>(instr)));
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break;
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case Instruction::TNEI:
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trap(regs.Read<s64>(instr.rs()) != static_cast<s64>(static_cast<s16>(instr)));
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break;
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case Instruction::BLTZAL:
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bltzal(instr);
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break;
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case Instruction::BGEZAL:
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bgezal(instr);
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break;
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case Instruction::BLTZALL:
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bltzall(instr);
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break;
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case Instruction::BGEZALL:
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bgezall(instr);
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break;
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default:
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panic("Unimplemented regimm {} ({:08X}) (pc: {:016X})", instr.regimm(), u32(instr),
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static_cast<u64>(regs.oldPC));
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}
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}
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void JIT::Emit(const Instruction instr) {
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switch (instr.opcode()) {
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case Instruction::SPECIAL:
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special(instr);
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break;
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case Instruction::REGIMM:
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regimm(instr);
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break;
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case Instruction::J:
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j(instr);
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break;
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case Instruction::JAL:
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jal(instr);
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break;
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case Instruction::BEQ:
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beq(instr);
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break;
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case Instruction::BNE:
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bne(instr);
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break;
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case Instruction::BLEZ:
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blez(instr);
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break;
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case Instruction::BGTZ:
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bgtz(instr);
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break;
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case Instruction::ADDI:
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addi(instr);
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break;
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case Instruction::ADDIU:
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addiu(instr);
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break;
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case Instruction::SLTI:
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slti(instr);
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break;
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case Instruction::SLTIU:
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sltiu(instr);
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break;
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case Instruction::ANDI:
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andi(instr);
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break;
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case Instruction::ORI:
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ori(instr);
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break;
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case Instruction::XORI:
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xori(instr);
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break;
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case Instruction::LUI:
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lui(instr);
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break;
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case Instruction::COP0:
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switch (instr.cop_rs()) {
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case 0x00:
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code.mov(code.ARG2, instr);
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emitMemberFunctionCall(&Cop0::mfc0, ®s.cop0);
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break;
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case 0x01:
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code.mov(code.ARG2, instr);
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emitMemberFunctionCall(&Cop0::dmfc0, ®s.cop0);
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break;
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case 0x04:
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code.mov(code.ARG2, instr);
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emitMemberFunctionCall(&Cop0::mtc0, ®s.cop0);
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break;
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case 0x05:
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code.mov(code.ARG2, instr);
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emitMemberFunctionCall(&Cop0::dmtc0, ®s.cop0);
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break;
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case 0x10 ... 0x1F:
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switch (instr.cop_funct()) {
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case 0x01:
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emitMemberFunctionCall(&Cop0::tlbr, ®s.cop0);
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break;
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case 0x02:
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code.mov(code.ARG2, COP0_REG_INDEX);
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emitMemberFunctionCall(&Cop0::GetReg32, ®s.cop0);
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code.mov(code.ARG2, code.rax);
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code.and_(code.ARG2, 0x3F);
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emitMemberFunctionCall(&Cop0::tlbw, ®s.cop0);
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break;
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case 0x06:
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emitMemberFunctionCall(&Cop0::GetRandom, ®s.cop0);
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code.mov(code.ARG2, code.rax);
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emitMemberFunctionCall(&Cop0::tlbw, ®s.cop0);
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break;
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case 0x08:
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emitMemberFunctionCall(&Cop0::tlbp, ®s.cop0);
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break;
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case 0x18:
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emitMemberFunctionCall(&Cop0::eret, ®s.cop0);
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break;
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default:
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panic("Unimplemented COP0 function {} ({:08X}) ({:016X})", instr.cop_funct(), u32(instr),
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regs.oldPC);
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}
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break;
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default:
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panic("Unimplemented COP0 instruction {}", instr.cop_rs());
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}
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break;
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case Instruction::COP1:
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{
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if (instr.cop_rs() == 0x08) {
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switch (instr.cop_rt()) {
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case 0:
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// if (!regs.cop1.CheckFPUUsable())
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// return;
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bfc0(instr);
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break;
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case 1:
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// if (!regs.cop1.CheckFPUUsable())
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// return;
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bfc1(instr);
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break;
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case 2:
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// if (!regs.cop1.CheckFPUUsable())
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// return;
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blfc0(instr);
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break;
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case 3:
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// if (!regs.cop1.CheckFPUUsable())
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// return;
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blfc1(instr);
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break;
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default:
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panic("Undefined BC COP1 {:02X}", instr.cop_rt());
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}
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break;
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}
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regs.cop1.decode(instr);
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}
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break;
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case Instruction::COP2:
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break;
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case Instruction::BEQL:
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beql(instr);
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break;
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case Instruction::BNEL:
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bnel(instr);
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break;
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case Instruction::BLEZL:
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blezl(instr);
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break;
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case Instruction::BGTZL:
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bgtzl(instr);
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break;
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case Instruction::DADDI:
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daddi(instr);
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break;
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case Instruction::DADDIU:
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daddiu(instr);
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break;
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case Instruction::LDL:
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ldl(instr);
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break;
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case Instruction::LDR:
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ldr(instr);
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break;
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case 0x1F:
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regs.cop0.FireException(ExceptionCode::ReservedInstruction, 0, regs.oldPC);
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break;
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case Instruction::LB:
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lb(instr);
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break;
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case Instruction::LH:
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lh(instr);
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break;
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case Instruction::LWL:
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lwl(instr);
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break;
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case Instruction::LW:
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lw(instr);
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break;
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case Instruction::LBU:
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lbu(instr);
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break;
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case Instruction::LHU:
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lhu(instr);
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break;
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case Instruction::LWR:
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lwr(instr);
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break;
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case Instruction::LWU:
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lwu(instr);
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||||
break;
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case Instruction::SB:
|
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sb(instr);
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break;
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case Instruction::SH:
|
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sh(instr);
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break;
|
||||
case Instruction::SWL:
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swl(instr);
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||||
break;
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||||
case Instruction::SW:
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sw(instr);
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||||
break;
|
||||
case Instruction::SDL:
|
||||
sdl(instr);
|
||||
break;
|
||||
case Instruction::SDR:
|
||||
sdr(instr);
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||||
break;
|
||||
case Instruction::SWR:
|
||||
swr(instr);
|
||||
break;
|
||||
case Instruction::CACHE:
|
||||
break; // CACHE
|
||||
case Instruction::LL:
|
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ll(instr);
|
||||
break;
|
||||
case Instruction::LWC1:
|
||||
lwc1(instr);
|
||||
break;
|
||||
case Instruction::LLD:
|
||||
lld(instr);
|
||||
break;
|
||||
case Instruction::LDC1:
|
||||
ldc1(instr);
|
||||
break;
|
||||
case Instruction::LD:
|
||||
ld(instr);
|
||||
break;
|
||||
case Instruction::SC:
|
||||
sc(instr);
|
||||
break;
|
||||
case Instruction::SWC1:
|
||||
swc1(instr);
|
||||
break;
|
||||
case Instruction::SCD:
|
||||
scd(instr);
|
||||
break;
|
||||
case Instruction::SDC1:
|
||||
sdc1(instr);
|
||||
break;
|
||||
case Instruction::SD:
|
||||
sd(instr);
|
||||
break;
|
||||
default:
|
||||
DumpBlockCacheToDisk();
|
||||
panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})", instr.opcode(), u32(instr), static_cast<u64>(regs.oldPC));
|
||||
}
|
||||
}
|
||||
} // namespace n64
|
||||
@@ -0,0 +1,102 @@
|
||||
#pragma once
|
||||
#include <Instruction.hpp>
|
||||
|
||||
namespace n64 {
|
||||
static bool SpecialEndsBlock(const Instruction instr) {
|
||||
switch (instr.special()) {
|
||||
case Instruction::JR:
|
||||
case Instruction::JALR:
|
||||
case Instruction::SYSCALL:
|
||||
case Instruction::BREAK:
|
||||
case Instruction::TGE:
|
||||
case Instruction::TGEU:
|
||||
case Instruction::TLT:
|
||||
case Instruction::TLTU:
|
||||
case Instruction::TEQ:
|
||||
case Instruction::TNE:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool InstrEndsBlock(const Instruction instr) {
|
||||
switch (instr.opcode()) {
|
||||
case Instruction::SPECIAL:
|
||||
return SpecialEndsBlock(instr);
|
||||
case Instruction::REGIMM:
|
||||
case Instruction::J:
|
||||
case Instruction::JAL:
|
||||
case Instruction::BEQ:
|
||||
case Instruction::BNE:
|
||||
case Instruction::BLEZ:
|
||||
case Instruction::BGTZ:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool IsBranchLikely(const Instruction instr) {
|
||||
switch (instr.opcode()) {
|
||||
case Instruction::BEQL:
|
||||
case Instruction::BNEL:
|
||||
case Instruction::BLEZL:
|
||||
case Instruction::BGTZL:
|
||||
return true;
|
||||
case Instruction::REGIMM:
|
||||
switch (instr.regimm()) {
|
||||
case Instruction::BLTZL:
|
||||
case Instruction::BGEZL:
|
||||
case Instruction::BLTZALL:
|
||||
case Instruction::BGEZALL:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
case Instruction::COP1:
|
||||
{
|
||||
if (instr.cop_rs() == 0x08) {
|
||||
if (instr.cop_rt() == 2 || instr.cop_rt() == 3)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef _WIN32
|
||||
#define ARG1 rcx
|
||||
#define ARG2 rdx
|
||||
#define ARG3 r8
|
||||
#define ARG4 r9
|
||||
#define SCR1 rax
|
||||
#define SCR2 rcx
|
||||
#define SCR3 rdx
|
||||
#define SCR4 r8
|
||||
#define SCR5 r9
|
||||
#define SCR6 r10
|
||||
#define SCR7 r11
|
||||
#else
|
||||
#define ARG1 rdi
|
||||
#define ARG2 rsi
|
||||
#define ARG3 rdx
|
||||
#define ARG4 rcx
|
||||
#define ARG5 r8
|
||||
#define ARG6 r9
|
||||
#define SCR1 rax
|
||||
#define SCR2 rdi
|
||||
#define SCR3 rsi
|
||||
#define SCR4 rdx
|
||||
#define SCR5 rcx
|
||||
#define SCR6 r8
|
||||
#define SCR7 r9
|
||||
#define SCR8 r10
|
||||
#define SCR9 r11
|
||||
#endif
|
||||
} // namespace n64
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user