TLBWR + Scheduler (SI DMA delay)

src/n64/Scheduler.cpp

@@ -0,0 +1,23 @@
+#include <Scheduler.hpp>
+#include <Mem.hpp>
+#include <Registers.hpp>
+
+Scheduler scheduler;
+
+Scheduler::Scheduler() {
+  events.push({UINT64_MAX, [](n64::Mem&, n64::Registers&){
+    util::panic("How the fuck did we get here?!\n");
+  }});
+}
+
+void Scheduler::enqueue(const Event& event) {
+  events.push({event.time + ticks, event.event_cb});
+}
+
+void Scheduler::tick(u64 t, n64::Mem& mem, n64::Registers& regs) {
+  ticks += t;
+  while(ticks >= events.top().time) {
+    events.top().event_cb(mem, regs);
+    events.pop();
+  }
+}