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Use virtual class for different cpu types rather than that hot mess with pointers and shiz

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This commit is contained in:
CocoSimone
2023-02-19 22:14:59 +01:00
parent 24eac65357
commit f113db7059
26 changed files with 700 additions and 536 deletions
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48
src/backend/core/interpreter/decode.cpp
View File

@@ -107,7 +107,7 @@ void Interpreter::cop2Decode(u32 instr) {
}
}
void Interpreter::Exec(Mem& mem, u32 instr) {
void Interpreter::Exec(u32 instr) {
u8 mask = (instr >> 26) & 0x3f;
// 00rr_rccc
switch(mask) { // TODO: named constants for clearer code
@@ -139,35 +139,35 @@ void Interpreter::Exec(Mem& mem, u32 instr) {
case 0x17: bl(instr, regs.gpr[RS(instr)] > 0); break;
case 0x18: daddi(instr); break;
case 0x19: daddiu(instr); break;
case 0x1A: ldl(mem, instr); break;
case 0x1B: ldr(mem, instr); break;
case 0x1A: ldl(instr); break;
case 0x1B: ldr(instr); break;
case 0x1F: FireException(regs, ExceptionCode::ReservedInstruction, 0, true); break;
case 0x20: lb(mem, instr); break;
case 0x21: lh(mem, instr); break;
case 0x22: lwl(mem, instr); break;
case 0x23: lw(mem, instr); break;
case 0x24: lbu(mem, instr); break;
case 0x25: lhu(mem, instr); break;
case 0x26: lwr(mem, instr); break;
case 0x27: lwu(mem, instr); break;
case 0x28: sb(mem, instr); break;
case 0x29: sh(mem, instr); break;
case 0x2A: swl(mem, instr); break;
case 0x2B: sw(mem, instr); break;
case 0x2C: sdl(mem, instr); break;
case 0x2D: sdr(mem, instr); break;
case 0x2E: swr(mem, instr); break;
case 0x20: lb(instr); break;
case 0x21: lh(instr); break;
case 0x22: lwl(instr); break;
case 0x23: lw(instr); break;
case 0x24: lbu(instr); break;
case 0x25: lhu(instr); break;
case 0x26: lwr(instr); break;
case 0x27: lwu(instr); break;
case 0x28: sb(instr); break;
case 0x29: sh(instr); break;
case 0x2A: swl(instr); break;
case 0x2B: sw(instr); break;
case 0x2C: sdl(instr); break;
case 0x2D: sdr(instr); break;
case 0x2E: swr(instr); break;
case 0x2F: break; // CACHE
case 0x30: ll(mem, instr); break;
case 0x30: ll(instr); break;
case 0x31: regs.cop1.lwc1(regs, mem, instr); break;
case 0x34: lld(mem, instr); break;
case 0x34: lld(instr); break;
case 0x35: regs.cop1.ldc1(regs, mem, instr); break;
case 0x37: ld(mem, instr); break;
case 0x38: sc(mem, instr); break;
case 0x37: ld(instr); break;
case 0x38: sc(instr); break;
case 0x39: regs.cop1.swc1(regs, mem, instr); break;
case 0x3C: scd(mem, instr); break;
case 0x3C: scd(instr); break;
case 0x3D: regs.cop1.sdc1(regs, mem, instr); break;
case 0x3F: sd(mem, instr); break;
case 0x3F: sd(instr); break;
default:
Util::panic("Unimplemented instruction {:02X} ({:08X}) (pc: {:016X})\n", mask, instr, (u64)regs.oldPC);
}

46
src/backend/core/interpreter/instructions.cpp
View File

@@ -203,7 +203,7 @@ void Interpreter::lui(u32 instr) {
regs.gpr[RT(instr)] = val;
}
void Interpreter::lb(Mem& mem, u32 instr) {
void Interpreter::lb(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) {
@@ -214,7 +214,7 @@ void Interpreter::lb(Mem& mem, u32 instr) {
}
}
void Interpreter::lh(Mem& mem, u32 instr) {
void Interpreter::lh(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b1) > 0) {
HandleTLBException(regs, address);
@@ -231,7 +231,7 @@ void Interpreter::lh(Mem& mem, u32 instr) {
}
}
void Interpreter::lw(Mem& mem, u32 instr) {
void Interpreter::lw(u32 instr) {
s16 offset = instr;
u64 address = regs.gpr[RS(instr)] + offset;
if (check_address_error(0b11, address)) {
@@ -249,7 +249,7 @@ void Interpreter::lw(Mem& mem, u32 instr) {
}
}
void Interpreter::ll(Mem& mem, u32 instr) {
void Interpreter::ll(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 physical;
if (!MapVAddr(regs, LOAD, address, physical)) {
@@ -268,7 +268,7 @@ void Interpreter::ll(Mem& mem, u32 instr) {
regs.cop0.LLAddr = physical >> 4;
}
void Interpreter::lwl(Mem& mem, u32 instr) {
void Interpreter::lwl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) {
@@ -283,7 +283,7 @@ void Interpreter::lwl(Mem& mem, u32 instr) {
}
}
void Interpreter::lwr(Mem& mem, u32 instr) {
void Interpreter::lwr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) {
@@ -298,7 +298,7 @@ void Interpreter::lwr(Mem& mem, u32 instr) {
}
}
void Interpreter::ld(Mem& mem, u32 instr) {
void Interpreter::ld(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(0b111, address)) {
HandleTLBException(regs, address);
@@ -316,7 +316,7 @@ void Interpreter::ld(Mem& mem, u32 instr) {
}
}
void Interpreter::lld(Mem& mem, u32 instr) {
void Interpreter::lld(u32 instr) {
if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
FireException(regs, ExceptionCode::ReservedInstruction, 0, true);
return;
@@ -338,7 +338,7 @@ void Interpreter::lld(Mem& mem, u32 instr) {
}
}
void Interpreter::ldl(Mem& mem, u32 instr) {
void Interpreter::ldl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0;
if (!MapVAddr(regs, LOAD, address, paddr)) {
@@ -353,7 +353,7 @@ void Interpreter::ldl(Mem& mem, u32 instr) {
}
}
void Interpreter::ldr(Mem& mem, u32 instr) {
void Interpreter::ldr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, LOAD, address, paddr)) {
@@ -368,7 +368,7 @@ void Interpreter::ldr(Mem& mem, u32 instr) {
}
}
void Interpreter::lbu(Mem& mem, u32 instr) {
void Interpreter::lbu(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, LOAD, address, paddr)) {
@@ -380,7 +380,7 @@ void Interpreter::lbu(Mem& mem, u32 instr) {
}
}
void Interpreter::lhu(Mem& mem, u32 instr) {
void Interpreter::lhu(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b1) > 0) {
HandleTLBException(regs, address);
@@ -397,7 +397,7 @@ void Interpreter::lhu(Mem& mem, u32 instr) {
}
}
void Interpreter::lwu(Mem& mem, u32 instr) {
void Interpreter::lwu(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b11) > 0) {
HandleTLBException(regs, address);
@@ -415,7 +415,7 @@ void Interpreter::lwu(Mem& mem, u32 instr) {
}
}
void Interpreter::sb(Mem& mem, u32 instr) {
void Interpreter::sb(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -426,7 +426,7 @@ void Interpreter::sb(Mem& mem, u32 instr) {
}
}
void Interpreter::sc(Mem& mem, u32 instr) {
void Interpreter::sc(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b11) > 0) {
@@ -449,7 +449,7 @@ void Interpreter::sc(Mem& mem, u32 instr) {
}
}
void Interpreter::scd(Mem& mem, u32 instr) {
void Interpreter::scd(u32 instr) {
if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
FireException(regs, ExceptionCode::ReservedInstruction, 0, true);
return;
@@ -477,7 +477,7 @@ void Interpreter::scd(Mem& mem, u32 instr) {
}
}
void Interpreter::sh(Mem& mem, u32 instr) {
void Interpreter::sh(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 physical;
@@ -489,7 +489,7 @@ void Interpreter::sh(Mem& mem, u32 instr) {
}
}
void Interpreter::sw(Mem& mem, u32 instr) {
void Interpreter::sw(u32 instr) {
s16 offset = instr;
u64 address = regs.gpr[RS(instr)] + offset;
if (check_address_error(0b11, address)) {
@@ -507,7 +507,7 @@ void Interpreter::sw(Mem& mem, u32 instr) {
}
}
void Interpreter::sd(Mem& mem, u32 instr) {
void Interpreter::sd(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(0b111, address)) {
HandleTLBException(regs, address);
@@ -524,7 +524,7 @@ void Interpreter::sd(Mem& mem, u32 instr) {
}
}
void Interpreter::sdl(Mem& mem, u32 instr) {
void Interpreter::sdl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -539,7 +539,7 @@ void Interpreter::sdl(Mem& mem, u32 instr) {
}
}
void Interpreter::sdr(Mem& mem, u32 instr) {
void Interpreter::sdr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -554,7 +554,7 @@ void Interpreter::sdr(Mem& mem, u32 instr) {
}
}
void Interpreter::swl(Mem& mem, u32 instr) {
void Interpreter::swl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -569,7 +569,7 @@ void Interpreter::swl(Mem& mem, u32 instr) {
}
}
void Interpreter::swr(Mem& mem, u32 instr) {
void Interpreter::swr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) {