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stub jit instructions for linking

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This commit is contained in:
SimoneN64
2023-08-12 15:41:21 +02:00
parent 9266308c63
commit f4c58a4b1d
1 changed files with 104 additions and 105 deletions
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209
src/backend/core/JIT/instructions.cpp
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@@ -1,11 +1,11 @@
#include <core/Interpreter.hpp> #include <core/JIT.hpp>
#define check_address_error(mask, vaddr) (((!regs.cop0.is_64bit_addressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0)) #define check_address_error(mask, vaddr) (((!regs.cop0.is_64bit_addressing) && (s32)(vaddr) != (vaddr)) || (((vaddr) & (mask)) != 0))
#define check_signed_overflow(op1, op2, res) (((~((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1) #define check_signed_overflow(op1, op2, res) (((~((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
#define check_signed_underflow(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1) #define check_signed_underflow(op1, op2, res) (((((op1) ^ (op2)) & ((op1) ^ (res))) >> ((sizeof(res) * 8) - 1)) & 1)
namespace n64 { namespace n64 {
void Interpreter::add(u32 instr) { void JIT::add(u32 instr) {
u32 rs = (s32)regs.gpr[RS(instr)]; u32 rs = (s32)regs.gpr[RS(instr)];
u32 rt = (s32)regs.gpr[RT(instr)]; u32 rt = (s32)regs.gpr[RT(instr)];
u32 result = rs + rt; u32 result = rs + rt;
@@ -18,7 +18,7 @@ void Interpreter::add(u32 instr) {
} }
} }
void Interpreter::addu(u32 instr) { void JIT::addu(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s32 rs = (s32)regs.gpr[RS(instr)]; s32 rs = (s32)regs.gpr[RS(instr)];
s32 rt = (s32)regs.gpr[RT(instr)]; s32 rt = (s32)regs.gpr[RT(instr)];
@@ -27,7 +27,7 @@ void Interpreter::addu(u32 instr) {
} }
} }
void Interpreter::addi(u32 instr) { void JIT::addi(u32 instr) {
u32 rs = regs.gpr[RS(instr)]; u32 rs = regs.gpr[RS(instr)];
u32 imm = s32(s16(instr)); u32 imm = s32(s16(instr));
u32 result = rs + imm; u32 result = rs + imm;
@@ -38,14 +38,14 @@ void Interpreter::addi(u32 instr) {
} }
} }
void Interpreter::addiu(u32 instr) { void JIT::addiu(u32 instr) {
s32 rs = (s32)regs.gpr[RS(instr)]; s32 rs = (s32)regs.gpr[RS(instr)];
s16 imm = (s16)(instr); s16 imm = (s16)(instr);
s32 result = rs + imm; s32 result = rs + imm;
regs.gpr[RT(instr)] = result; regs.gpr[RT(instr)] = result;
} }
void Interpreter::dadd(u32 instr) { void JIT::dadd(u32 instr) {
u64 rs = regs.gpr[RS(instr)]; u64 rs = regs.gpr[RS(instr)];
u64 rt = regs.gpr[RT(instr)]; u64 rt = regs.gpr[RT(instr)];
u64 result = rt + rs; u64 result = rt + rs;
@@ -58,7 +58,7 @@ void Interpreter::dadd(u32 instr) {
} }
} }
void Interpreter::daddu(u32 instr) { void JIT::daddu(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 rs = regs.gpr[RS(instr)]; s64 rs = regs.gpr[RS(instr)];
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
@@ -66,7 +66,7 @@ void Interpreter::daddu(u32 instr) {
} }
} }
void Interpreter::daddi(u32 instr) { void JIT::daddi(u32 instr) {
u64 imm = s64(s16(instr)); u64 imm = s64(s16(instr));
u64 rs = regs.gpr[RS(instr)]; u64 rs = regs.gpr[RS(instr)];
u64 result = imm + rs; u64 result = imm + rs;
@@ -77,13 +77,13 @@ void Interpreter::daddi(u32 instr) {
} }
} }
void Interpreter::daddiu(u32 instr) { void JIT::daddiu(u32 instr) {
s16 imm = (s16)(instr); s16 imm = (s16)(instr);
s64 rs = regs.gpr[RS(instr)]; s64 rs = regs.gpr[RS(instr)];
regs.gpr[RT(instr)] = rs + imm; regs.gpr[RT(instr)] = rs + imm;
} }
void Interpreter::div(u32 instr) { void JIT::div(u32 instr) {
s64 dividend = (s32)regs.gpr[RS(instr)]; s64 dividend = (s32)regs.gpr[RS(instr)];
s64 divisor = (s32)regs.gpr[RT(instr)]; s64 divisor = (s32)regs.gpr[RT(instr)];
@@ -102,7 +102,7 @@ void Interpreter::div(u32 instr) {
} }
} }
void Interpreter::divu(u32 instr) { void JIT::divu(u32 instr) {
u32 dividend = regs.gpr[RS(instr)]; u32 dividend = regs.gpr[RS(instr)];
u32 divisor = regs.gpr[RT(instr)]; u32 divisor = regs.gpr[RT(instr)];
if(divisor == 0) { if(divisor == 0) {
@@ -116,7 +116,7 @@ void Interpreter::divu(u32 instr) {
} }
} }
void Interpreter::ddiv(u32 instr) { void JIT::ddiv(u32 instr) {
s64 dividend = regs.gpr[RS(instr)]; s64 dividend = regs.gpr[RS(instr)];
s64 divisor = regs.gpr[RT(instr)]; s64 divisor = regs.gpr[RT(instr)];
if (dividend == 0x8000000000000000 && divisor == 0xFFFFFFFFFFFFFFFF) { if (dividend == 0x8000000000000000 && divisor == 0xFFFFFFFFFFFFFFFF) {
@@ -137,7 +137,7 @@ void Interpreter::ddiv(u32 instr) {
} }
} }
void Interpreter::ddivu(u32 instr) { void JIT::ddivu(u32 instr) {
u64 dividend = regs.gpr[RS(instr)]; u64 dividend = regs.gpr[RS(instr)];
u64 divisor = regs.gpr[RT(instr)]; u64 divisor = regs.gpr[RT(instr)];
if(divisor == 0) { if(divisor == 0) {
@@ -151,14 +151,14 @@ void Interpreter::ddivu(u32 instr) {
} }
} }
void Interpreter::branch(bool cond, s64 address) { void JIT::branch(bool cond, s64 address) {
regs.delaySlot = true; regs.delaySlot = true;
if (cond) { if (cond) {
regs.nextPC = address; regs.nextPC = address;
} }
} }
void Interpreter::branch_likely(bool cond, s64 address) { void JIT::branch_likely(bool cond, s64 address) {
if (cond) { if (cond) {
regs.delaySlot = true; regs.delaySlot = true;
regs.nextPC = address; regs.nextPC = address;
@@ -167,14 +167,14 @@ void Interpreter::branch_likely(bool cond, s64 address) {
} }
} }
void Interpreter::b(u32 instr, bool cond) { void JIT::b(u32 instr, bool cond) {
s16 imm = instr; s16 imm = instr;
s64 offset = u64((s64)imm) << 2; s64 offset = u64((s64)imm) << 2;
s64 address = regs.pc + offset; s64 address = regs.pc + offset;
branch(cond, address); branch(cond, address);
} }
void Interpreter::blink(u32 instr, bool cond) { void JIT::blink(u32 instr, bool cond) {
regs.gpr[31] = regs.nextPC; regs.gpr[31] = regs.nextPC;
s16 imm = instr; s16 imm = instr;
s64 offset = u64((s64)imm) << 2; s64 offset = u64((s64)imm) << 2;
@@ -182,14 +182,14 @@ void Interpreter::blink(u32 instr, bool cond) {
branch(cond, address); branch(cond, address);
} }
void Interpreter::bl(u32 instr, bool cond) { void JIT::bl(u32 instr, bool cond) {
s16 imm = instr; s16 imm = instr;
s64 offset = u64((s64)imm) << 2; s64 offset = u64((s64)imm) << 2;
s64 address = regs.pc + offset; s64 address = regs.pc + offset;
branch_likely(cond, address); branch_likely(cond, address);
} }
void Interpreter::bllink(u32 instr, bool cond) { void JIT::bllink(u32 instr, bool cond) {
regs.gpr[31] = regs.nextPC; regs.gpr[31] = regs.nextPC;
s16 imm = instr; s16 imm = instr;
s64 offset = u64((s64)imm) << 2; s64 offset = u64((s64)imm) << 2;
@@ -197,13 +197,13 @@ void Interpreter::bllink(u32 instr, bool cond) {
branch_likely(cond, address); branch_likely(cond, address);
} }
void Interpreter::lui(u32 instr) { void JIT::lui(u32 instr) {
u64 val = s64((s16)instr); u64 val = s64((s16)instr);
val <<= 16; val <<= 16;
regs.gpr[RT(instr)] = val; regs.gpr[RT(instr)] = val;
} }
void Interpreter::lb(u32 instr) { void JIT::lb(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0; u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) { if(!MapVAddr(regs, LOAD, address, paddr)) {
@@ -214,7 +214,7 @@ void Interpreter::lb(u32 instr) {
} }
} }
void Interpreter::lh(u32 instr) { void JIT::lh(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b1) > 0) { if ((address & 0b1) > 0) {
HandleTLBException(regs, address); HandleTLBException(regs, address);
@@ -231,7 +231,7 @@ void Interpreter::lh(u32 instr) {
} }
} }
void Interpreter::lw(u32 instr) { void JIT::lw(u32 instr) {
s16 offset = instr; s16 offset = instr;
u64 address = regs.gpr[RS(instr)] + offset; u64 address = regs.gpr[RS(instr)] + offset;
if (check_address_error(0b11, address)) { if (check_address_error(0b11, address)) {
@@ -249,7 +249,7 @@ void Interpreter::lw(u32 instr) {
} }
} }
void Interpreter::ll(u32 instr) { void JIT::ll(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 physical; u32 physical;
if (!MapVAddr(regs, LOAD, address, physical)) { if (!MapVAddr(regs, LOAD, address, physical)) {
@@ -268,7 +268,7 @@ void Interpreter::ll(u32 instr) {
regs.cop0.LLAddr = physical >> 4; regs.cop0.LLAddr = physical >> 4;
} }
void Interpreter::lwl(u32 instr) { void JIT::lwl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0; u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) { if(!MapVAddr(regs, LOAD, address, paddr)) {
@@ -283,7 +283,7 @@ void Interpreter::lwl(u32 instr) {
} }
} }
void Interpreter::lwr(u32 instr) { void JIT::lwr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0; u32 paddr = 0;
if(!MapVAddr(regs, LOAD, address, paddr)) { if(!MapVAddr(regs, LOAD, address, paddr)) {
@@ -298,7 +298,7 @@ void Interpreter::lwr(u32 instr) {
} }
} }
void Interpreter::ld(u32 instr) { void JIT::ld(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr; s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(0b111, address)) { if (check_address_error(0b111, address)) {
HandleTLBException(regs, address); HandleTLBException(regs, address);
@@ -316,7 +316,7 @@ void Interpreter::ld(u32 instr) {
} }
} }
void Interpreter::lld(u32 instr) { void JIT::lld(u32 instr) {
if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) { if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
FireException(regs, ExceptionCode::ReservedInstruction, 0, true); FireException(regs, ExceptionCode::ReservedInstruction, 0, true);
return; return;
@@ -338,7 +338,7 @@ void Interpreter::lld(u32 instr) {
} }
} }
void Interpreter::ldl(u32 instr) { void JIT::ldl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr = 0; u32 paddr = 0;
if (!MapVAddr(regs, LOAD, address, paddr)) { if (!MapVAddr(regs, LOAD, address, paddr)) {
@@ -353,7 +353,7 @@ void Interpreter::ldl(u32 instr) {
} }
} }
void Interpreter::ldr(u32 instr) { void JIT::ldr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, LOAD, address, paddr)) { if (!MapVAddr(regs, LOAD, address, paddr)) {
@@ -368,7 +368,7 @@ void Interpreter::ldr(u32 instr) {
} }
} }
void Interpreter::lbu(u32 instr) { void JIT::lbu(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, LOAD, address, paddr)) { if (!MapVAddr(regs, LOAD, address, paddr)) {
@@ -380,7 +380,7 @@ void Interpreter::lbu(u32 instr) {
} }
} }
void Interpreter::lhu(u32 instr) { void JIT::lhu(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr; s64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b1) > 0) { if ((address & 0b1) > 0) {
HandleTLBException(regs, address); HandleTLBException(regs, address);
@@ -397,7 +397,7 @@ void Interpreter::lhu(u32 instr) {
} }
} }
void Interpreter::lwu(u32 instr) { void JIT::lwu(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr; s64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b11) > 0) { if ((address & 0b11) > 0) {
HandleTLBException(regs, address); HandleTLBException(regs, address);
@@ -415,7 +415,7 @@ void Interpreter::lwu(u32 instr) {
} }
} }
void Interpreter::sb(u32 instr) { void JIT::sb(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) { if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -426,7 +426,7 @@ void Interpreter::sb(u32 instr) {
} }
} }
void Interpreter::sc(u32 instr) { void JIT::sc(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
if ((address & 0b11) > 0) { if ((address & 0b11) > 0) {
@@ -449,7 +449,7 @@ void Interpreter::sc(u32 instr) {
} }
} }
void Interpreter::scd(u32 instr) { void JIT::scd(u32 instr) {
if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) { if (!regs.cop0.is_64bit_addressing && !regs.cop0.kernel_mode) {
FireException(regs, ExceptionCode::ReservedInstruction, 0, true); FireException(regs, ExceptionCode::ReservedInstruction, 0, true);
return; return;
@@ -477,7 +477,7 @@ void Interpreter::scd(u32 instr) {
} }
} }
void Interpreter::sh(u32 instr) { void JIT::sh(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr; s64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 physical; u32 physical;
@@ -489,7 +489,7 @@ void Interpreter::sh(u32 instr) {
} }
} }
void Interpreter::sw(u32 instr) { void JIT::sw(u32 instr) {
s16 offset = instr; s16 offset = instr;
u64 address = regs.gpr[RS(instr)] + offset; u64 address = regs.gpr[RS(instr)] + offset;
if (check_address_error(0b11, address)) { if (check_address_error(0b11, address)) {
@@ -507,7 +507,7 @@ void Interpreter::sw(u32 instr) {
} }
} }
void Interpreter::sd(u32 instr) { void JIT::sd(u32 instr) {
s64 address = regs.gpr[RS(instr)] + (s16)instr; s64 address = regs.gpr[RS(instr)] + (s16)instr;
if (check_address_error(0b111, address)) { if (check_address_error(0b111, address)) {
HandleTLBException(regs, address); HandleTLBException(regs, address);
@@ -524,7 +524,7 @@ void Interpreter::sd(u32 instr) {
} }
} }
void Interpreter::sdl(u32 instr) { void JIT::sdl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) { if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -539,7 +539,7 @@ void Interpreter::sdl(u32 instr) {
} }
} }
void Interpreter::sdr(u32 instr) { void JIT::sdr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) { if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -554,7 +554,7 @@ void Interpreter::sdr(u32 instr) {
} }
} }
void Interpreter::swl(u32 instr) { void JIT::swl(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) { if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -569,7 +569,7 @@ void Interpreter::swl(u32 instr) {
} }
} }
void Interpreter::swr(u32 instr) { void JIT::swr(u32 instr) {
u64 address = regs.gpr[RS(instr)] + (s16)instr; u64 address = regs.gpr[RS(instr)] + (s16)instr;
u32 paddr; u32 paddr;
if (!MapVAddr(regs, STORE, address, paddr)) { if (!MapVAddr(regs, STORE, address, paddr)) {
@@ -584,88 +584,88 @@ void Interpreter::swr(u32 instr) {
} }
} }
void Interpreter::ori(u32 instr) { void JIT::ori(u32 instr) {
s64 imm = (u16)instr; s64 imm = (u16)instr;
s64 result = imm | regs.gpr[RS(instr)]; s64 result = imm | regs.gpr[RS(instr)];
regs.gpr[RT(instr)] = result; regs.gpr[RT(instr)] = result;
} }
void Interpreter::or_(u32 instr) { void JIT::or_(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.gpr[RS(instr)] | regs.gpr[RT(instr)]; regs.gpr[RD(instr)] = regs.gpr[RS(instr)] | regs.gpr[RT(instr)];
} }
} }
void Interpreter::nor(u32 instr) { void JIT::nor(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = ~(regs.gpr[RS(instr)] | regs.gpr[RT(instr)]); regs.gpr[RD(instr)] = ~(regs.gpr[RS(instr)] | regs.gpr[RT(instr)]);
} }
} }
void Interpreter::j(u32 instr) { void JIT::j(u32 instr) {
s32 target = (instr & 0x3ffffff) << 2; s32 target = (instr & 0x3ffffff) << 2;
s64 address = (regs.oldPC & ~0xfffffff) | target; s64 address = (regs.oldPC & ~0xfffffff) | target;
branch(true, address); branch(true, address);
} }
void Interpreter::jal(u32 instr) { void JIT::jal(u32 instr) {
regs.gpr[31] = regs.nextPC; regs.gpr[31] = regs.nextPC;
j(instr); j(instr);
} }
void Interpreter::jalr(u32 instr) { void JIT::jalr(u32 instr) {
branch(true, regs.gpr[RS(instr)]); branch(true, regs.gpr[RS(instr)]);
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.pc + 4; regs.gpr[RD(instr)] = regs.pc + 4;
} }
} }
void Interpreter::slti(u32 instr) { void JIT::slti(u32 instr) {
s16 imm = instr; s16 imm = instr;
regs.gpr[RT(instr)] = regs.gpr[RS(instr)] < imm; regs.gpr[RT(instr)] = regs.gpr[RS(instr)] < imm;
} }
void Interpreter::sltiu(u32 instr) { void JIT::sltiu(u32 instr) {
s16 imm = instr; s16 imm = instr;
regs.gpr[RT(instr)] = (u64)regs.gpr[RS(instr)] < imm; regs.gpr[RT(instr)] = (u64)regs.gpr[RS(instr)] < imm;
} }
void Interpreter::slt(u32 instr) { void JIT::slt(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.gpr[RS(instr)] < regs.gpr[RT(instr)]; regs.gpr[RD(instr)] = regs.gpr[RS(instr)] < regs.gpr[RT(instr)];
} }
} }
void Interpreter::sltu(u32 instr) { void JIT::sltu(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = (u64) regs.gpr[RS(instr)] < (u64) regs.gpr[RT(instr)]; regs.gpr[RD(instr)] = (u64) regs.gpr[RS(instr)] < (u64) regs.gpr[RT(instr)];
} }
} }
void Interpreter::xori(u32 instr) { void JIT::xori(u32 instr) {
s64 imm = (u16)instr; s64 imm = (u16)instr;
regs.gpr[RT(instr)] = regs.gpr[RS(instr)] ^ imm; regs.gpr[RT(instr)] = regs.gpr[RS(instr)] ^ imm;
} }
void Interpreter::xor_(u32 instr) { void JIT::xor_(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.gpr[RT(instr)] ^ regs.gpr[RS(instr)]; regs.gpr[RD(instr)] = regs.gpr[RT(instr)] ^ regs.gpr[RS(instr)];
} }
} }
void Interpreter::andi(u32 instr) { void JIT::andi(u32 instr) {
s64 imm = (u16)instr; s64 imm = (u16)instr;
regs.gpr[RT(instr)] = regs.gpr[RS(instr)] & imm; regs.gpr[RT(instr)] = regs.gpr[RS(instr)] & imm;
} }
void Interpreter::and_(u32 instr) { void JIT::and_(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.gpr[RS(instr)] & regs.gpr[RT(instr)]; regs.gpr[RD(instr)] = regs.gpr[RS(instr)] & regs.gpr[RT(instr)];
} }
} }
void Interpreter::sll(u32 instr) { void JIT::sll(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
s32 result = regs.gpr[RT(instr)] << sa; s32 result = regs.gpr[RT(instr)] << sa;
@@ -673,7 +673,7 @@ void Interpreter::sll(u32 instr) {
} }
} }
void Interpreter::sllv(u32 instr) { void JIT::sllv(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u8 sa = (regs.gpr[RS(instr)]) & 0x1F; u8 sa = (regs.gpr[RS(instr)]) & 0x1F;
u32 rt = regs.gpr[RT(instr)]; u32 rt = regs.gpr[RT(instr)];
@@ -682,7 +682,7 @@ void Interpreter::sllv(u32 instr) {
} }
} }
void Interpreter::dsll32(u32 instr) { void JIT::dsll32(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
s64 result = regs.gpr[RT(instr)] << (sa + 32); s64 result = regs.gpr[RT(instr)] << (sa + 32);
@@ -690,7 +690,7 @@ void Interpreter::dsll32(u32 instr) {
} }
} }
void Interpreter::dsll(u32 instr) { void JIT::dsll(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
s64 result = regs.gpr[RT(instr)] << sa; s64 result = regs.gpr[RT(instr)] << sa;
@@ -698,7 +698,7 @@ void Interpreter::dsll(u32 instr) {
} }
} }
void Interpreter::dsllv(u32 instr) { void JIT::dsllv(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 sa = regs.gpr[RS(instr)] & 63; s64 sa = regs.gpr[RS(instr)] & 63;
s64 result = regs.gpr[RT(instr)] << sa; s64 result = regs.gpr[RT(instr)] << sa;
@@ -706,7 +706,7 @@ void Interpreter::dsllv(u32 instr) {
} }
} }
void Interpreter::srl(u32 instr) { void JIT::srl(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u32 rt = regs.gpr[RT(instr)]; u32 rt = regs.gpr[RT(instr)];
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
@@ -715,7 +715,7 @@ void Interpreter::srl(u32 instr) {
} }
} }
void Interpreter::srlv(u32 instr) { void JIT::srlv(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u8 sa = (regs.gpr[RS(instr)] & 0x1F); u8 sa = (regs.gpr[RS(instr)] & 0x1F);
u32 rt = regs.gpr[RT(instr)]; u32 rt = regs.gpr[RT(instr)];
@@ -724,7 +724,7 @@ void Interpreter::srlv(u32 instr) {
} }
} }
void Interpreter::dsrl(u32 instr) { void JIT::dsrl(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u64 rt = regs.gpr[RT(instr)]; u64 rt = regs.gpr[RT(instr)];
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
@@ -733,7 +733,7 @@ void Interpreter::dsrl(u32 instr) {
} }
} }
void Interpreter::dsrlv(u32 instr) { void JIT::dsrlv(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u8 amount = (regs.gpr[RS(instr)] & 63); u8 amount = (regs.gpr[RS(instr)] & 63);
u64 rt = regs.gpr[RT(instr)]; u64 rt = regs.gpr[RT(instr)];
@@ -742,7 +742,7 @@ void Interpreter::dsrlv(u32 instr) {
} }
} }
void Interpreter::dsrl32(u32 instr) { void JIT::dsrl32(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u64 rt = regs.gpr[RT(instr)]; u64 rt = regs.gpr[RT(instr)];
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
@@ -751,7 +751,7 @@ void Interpreter::dsrl32(u32 instr) {
} }
} }
void Interpreter::sra(u32 instr) { void JIT::sra(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
@@ -760,7 +760,7 @@ void Interpreter::sra(u32 instr) {
} }
} }
void Interpreter::srav(u32 instr) { void JIT::srav(u32 instr) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 rs = regs.gpr[RS(instr)]; s64 rs = regs.gpr[RS(instr)];
@@ -770,7 +770,7 @@ void Interpreter::srav(u32 instr) {
} }
} }
void Interpreter::dsra(u32 instr) { void JIT::dsra(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
@@ -779,7 +779,7 @@ void Interpreter::dsra(u32 instr) {
} }
} }
void Interpreter::dsrav(u32 instr) { void JIT::dsrav(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
s64 rs = regs.gpr[RS(instr)]; s64 rs = regs.gpr[RS(instr)];
@@ -789,7 +789,7 @@ void Interpreter::dsrav(u32 instr) {
} }
} }
void Interpreter::dsra32(u32 instr) { void JIT::dsra32(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
u8 sa = ((instr >> 6) & 0x1f); u8 sa = ((instr >> 6) & 0x1f);
@@ -798,12 +798,12 @@ void Interpreter::dsra32(u32 instr) {
} }
} }
void Interpreter::jr(u32 instr) { void JIT::jr(u32 instr) {
s64 address = regs.gpr[RS(instr)]; s64 address = regs.gpr[RS(instr)];
branch(true, address); branch(true, address);
} }
void Interpreter::dsub(u32 instr) { void JIT::dsub(u32 instr) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
s64 rs = regs.gpr[RS(instr)]; s64 rs = regs.gpr[RS(instr)];
s64 result = rs - rt; s64 result = rs - rt;
@@ -816,7 +816,7 @@ void Interpreter::dsub(u32 instr) {
} }
} }
void Interpreter::dsubu(u32 instr) { void JIT::dsubu(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u64 rt = regs.gpr[RT(instr)]; u64 rt = regs.gpr[RT(instr)];
u64 rs = regs.gpr[RS(instr)]; u64 rs = regs.gpr[RS(instr)];
@@ -825,7 +825,7 @@ void Interpreter::dsubu(u32 instr) {
} }
} }
void Interpreter::sub(u32 instr) { void JIT::sub(u32 instr) {
s32 rt = regs.gpr[RT(instr)]; s32 rt = regs.gpr[RT(instr)];
s32 rs = regs.gpr[RS(instr)]; s32 rs = regs.gpr[RS(instr)];
s32 result = rs - rt; s32 result = rs - rt;
@@ -838,7 +838,7 @@ void Interpreter::sub(u32 instr) {
} }
} }
void Interpreter::subu(u32 instr) { void JIT::subu(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
u32 rt = regs.gpr[RT(instr)]; u32 rt = regs.gpr[RT(instr)];
u32 rs = regs.gpr[RS(instr)]; u32 rs = regs.gpr[RS(instr)];
@@ -847,7 +847,7 @@ void Interpreter::subu(u32 instr) {
} }
} }
void Interpreter::dmultu(u32 instr) { void JIT::dmultu(u32 instr) {
u64 rt = regs.gpr[RT(instr)]; u64 rt = regs.gpr[RT(instr)];
u64 rs = regs.gpr[RS(instr)]; u64 rs = regs.gpr[RS(instr)];
u128 result = (u128)rt * (u128)rs; u128 result = (u128)rt * (u128)rs;
@@ -855,7 +855,7 @@ void Interpreter::dmultu(u32 instr) {
regs.hi = (s64)(result >> 64); regs.hi = (s64)(result >> 64);
} }
void Interpreter::dmult(u32 instr) { void JIT::dmult(u32 instr) {
s64 rt = regs.gpr[RT(instr)]; s64 rt = regs.gpr[RT(instr)];
s64 rs = regs.gpr[RS(instr)]; s64 rs = regs.gpr[RS(instr)];
s128 result = (s128)rt * (s128)rs; s128 result = (s128)rt * (s128)rs;
@@ -863,7 +863,7 @@ void Interpreter::dmult(u32 instr) {
regs.hi = result >> 64; regs.hi = result >> 64;
} }
void Interpreter::multu(u32 instr) { void JIT::multu(u32 instr) {
u32 rt = regs.gpr[RT(instr)]; u32 rt = regs.gpr[RT(instr)];
u32 rs = regs.gpr[RS(instr)]; u32 rs = regs.gpr[RS(instr)];
u64 result = (u64)rt * (u64)rs; u64 result = (u64)rt * (u64)rs;
@@ -871,7 +871,7 @@ void Interpreter::multu(u32 instr) {
regs.hi = (s64)((s32)(result >> 32)); regs.hi = (s64)((s32)(result >> 32));
} }
void Interpreter::mult(u32 instr) { void JIT::mult(u32 instr) {
s32 rt = regs.gpr[RT(instr)]; s32 rt = regs.gpr[RT(instr)];
s32 rs = regs.gpr[RS(instr)]; s32 rs = regs.gpr[RS(instr)];
s64 result = (s64)rt * (s64)rs; s64 result = (s64)rt * (s64)rs;
@@ -879,54 +879,53 @@ void Interpreter::mult(u32 instr) {
regs.hi = (s64)((s32)(result >> 32)); regs.hi = (s64)((s32)(result >> 32));
} }
void Interpreter::mflo(u32 instr) { void JIT::mflo(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.lo; regs.gpr[RD(instr)] = regs.lo;
} }
} }
void Interpreter::mfhi(u32 instr) { void JIT::mfhi(u32 instr) {
if(likely(RD(instr) != 0)) { if(likely(RD(instr) != 0)) {
regs.gpr[RD(instr)] = regs.hi; regs.gpr[RD(instr)] = regs.hi;
} }
} }
void Interpreter::mtlo(u32 instr) { void JIT::mtlo(u32 instr) {
regs.lo = regs.gpr[RS(instr)]; regs.lo = regs.gpr[RS(instr)];
} }
void Interpreter::mthi(u32 instr) { void JIT::mthi(u32 instr) {
regs.hi = regs.gpr[RS(instr)]; regs.hi = regs.gpr[RS(instr)];
} }
void Interpreter::trap(bool cond) { void JIT::trap(bool cond) {
if(cond) { if(cond) {
FireException(regs, ExceptionCode::Trap, 0, true); FireException(regs, ExceptionCode::Trap, 0, true);
} }
} }
void Interpreter::mtc2(u32 instr) { void JIT::mtc2(u32 instr) {
cop2Latch = regs.gpr[RT(instr)];
}
void Interpreter::mfc2(u32 instr) {
s32 value = cop2Latch;
regs.gpr[RT(instr)] = value;
}
void Interpreter::dmtc2(u32 instr) {
cop2Latch = regs.gpr[RT(instr)];
}
void Interpreter::dmfc2(u32 instr) {
regs.gpr[RT(instr)] = cop2Latch;
}
void Interpreter::ctc2(u32) {
} }
void Interpreter::cfc2(u32) { void JIT::mfc2(u32 instr) {
}
void JIT::dmtc2(u32 instr) {
}
void JIT::dmfc2(u32 instr) {
}
void JIT::ctc2(u32) {
}
void JIT::cfc2(u32) {
} }