34895 lines
1.2 MiB
34895 lines
1.2 MiB
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#include <capstone/platform.h>
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#include "../../cs_priv.h"
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/// getMnemonic - This method is automatically generated by tablegen
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/// from the instruction set description.
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static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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#ifndef CAPSTONE_DIET
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static const char AsmStrs[] = {
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/* 0 */ "sha1su0\t\0"
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/* 9 */ "sha512su0\t\0"
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/* 20 */ "sha256su0\t\0"
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/* 31 */ "st64bv0\t\0"
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/* 40 */ "ld1\t\0"
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/* 45 */ "stl1\t\0"
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/* 51 */ "trn1\t\0"
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/* 57 */ "ldap1\t\0"
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/* 64 */ "zip1\t\0"
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/* 70 */ "uzp1\t\0"
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/* 76 */ "zipq1\t\0"
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/* 83 */ "uzpq1\t\0"
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/* 90 */ "dcps1\t\0"
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/* 97 */ "sm3ss1\t\0"
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/* 105 */ "gcsss1\t\0"
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/* 113 */ "st1\t\0"
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/* 118 */ "sha1su1\t\0"
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/* 127 */ "sha512su1\t\0"
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/* 138 */ "sha256su1\t\0"
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/* 149 */ "sm3partw1\t\0"
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/* 160 */ "rax1\t\0"
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/* 166 */ "fma32\t\0"
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/* 173 */ "fms32\t\0"
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/* 180 */ "rev32\t\0"
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/* 187 */ "ld2\t\0"
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/* 192 */ "sha512h2\t\0"
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/* 202 */ "sha256h2\t\0"
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/* 212 */ "luti2\t\0"
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/* 219 */ "sabal2\t\0"
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/* 227 */ "uabal2\t\0"
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/* 235 */ "sqdmlal2\t\0"
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/* 245 */ "fmlal2\t\0"
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/* 253 */ "smlal2\t\0"
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/* 261 */ "umlal2\t\0"
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/* 269 */ "ssubl2\t\0"
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/* 277 */ "usubl2\t\0"
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/* 285 */ "sabdl2\t\0"
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/* 293 */ "uabdl2\t\0"
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/* 301 */ "saddl2\t\0"
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/* 309 */ "uaddl2\t\0"
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/* 317 */ "sshll2\t\0"
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/* 325 */ "ushll2\t\0"
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/* 333 */ "sqdmull2\t\0"
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/* 343 */ "pmull2\t\0"
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/* 351 */ "smull2\t\0"
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/* 359 */ "umull2\t\0"
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/* 367 */ "sqdmlsl2\t\0"
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/* 377 */ "fmlsl2\t\0"
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/* 385 */ "smlsl2\t\0"
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/* 393 */ "umlsl2\t\0"
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/* 401 */ "bf1cvtl2\t\0"
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/* 411 */ "bf2cvtl2\t\0"
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/* 421 */ "fcvtl2\t\0"
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/* 429 */ "rsubhn2\t\0"
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/* 438 */ "raddhn2\t\0"
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/* 447 */ "sqshrn2\t\0"
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/* 456 */ "uqshrn2\t\0"
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/* 465 */ "sqrshrn2\t\0"
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/* 475 */ "uqrshrn2\t\0"
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/* 485 */ "trn2\t\0"
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/* 491 */ "bfcvtn2\t\0"
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/* 500 */ "sqxtn2\t\0"
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/* 508 */ "uqxtn2\t\0"
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/* 516 */ "sqshrun2\t\0"
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/* 526 */ "sqrshrun2\t\0"
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/* 537 */ "sqxtun2\t\0"
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/* 546 */ "fcvtxn2\t\0"
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/* 555 */ "zip2\t\0"
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/* 561 */ "uzp2\t\0"
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/* 567 */ "zipq2\t\0"
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/* 574 */ "uzpq2\t\0"
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/* 581 */ "dcps2\t\0"
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/* 588 */ "gcsss2\t\0"
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/* 596 */ "st2\t\0"
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/* 601 */ "ssubw2\t\0"
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/* 609 */ "usubw2\t\0"
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/* 617 */ "saddw2\t\0"
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/* 625 */ "uaddw2\t\0"
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/* 633 */ "sm3partw2\t\0"
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/* 644 */ "ld3\t\0"
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/* 649 */ "eor3\t\0"
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/* 655 */ "dcps3\t\0"
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/* 662 */ "st3\t\0"
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/* 667 */ "fma64\t\0"
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/* 674 */ "fms64\t\0"
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/* 681 */ "rev64\t\0"
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/* 688 */ "ld4\t\0"
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/* 693 */ "luti4\t\0"
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/* 700 */ "st4\t\0"
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/* 705 */ "fma16\t\0"
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/* 712 */ "mac16\t\0"
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/* 719 */ "setf16\t\0"
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/* 727 */ "fms16\t\0"
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/* 734 */ "rev16\t\0"
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/* 741 */ "setf8\t\0"
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/* 748 */ "sm3tt1a\t\0"
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/* 757 */ "sm3tt2a\t\0"
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/* 766 */ "braa\t\0"
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/* 772 */ "ldraa\t\0"
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/* 779 */ "blraa\t\0"
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/* 786 */ "saba\t\0"
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/* 792 */ "uaba\t\0"
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/* 798 */ "pacda\t\0"
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/* 805 */ "ldadda\t\0"
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/* 813 */ "fadda\t\0"
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/* 820 */ "autda\t\0"
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/* 827 */ "pacga\t\0"
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/* 834 */ "addha\t\0"
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/* 841 */ "pacia\t\0"
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/* 848 */ "autia\t\0"
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/* 855 */ "brka\t\0"
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/* 861 */ "fcmla\t\0"
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/* 868 */ "bfmla\t\0"
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/* 875 */ "bfmmla\t\0"
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/* 883 */ "usmmla\t\0"
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/* 891 */ "ummla\t\0"
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/* 898 */ "fnmla\t\0"
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/* 905 */ "ldsmina\t\0"
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/* 914 */ "ldumina\t\0"
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/* 923 */ "brkpa\t\0"
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/* 930 */ "bmopa\t\0"
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/* 937 */ "bfmopa\t\0"
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/* 945 */ "usmopa\t\0"
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/* 953 */ "sumopa\t\0"
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/* 961 */ "rcwsswppa\t\0"
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/* 972 */ "rcwswppa\t\0"
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/* 982 */ "ldclrpa\t\0"
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/* 991 */ "rcwsclrpa\t\0"
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/* 1002 */ "rcwclrpa\t\0"
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/* 1012 */ "rcwscaspa\t\0"
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/* 1023 */ "rcwcaspa\t\0"
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/* 1033 */ "ldsetpa\t\0"
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/* 1042 */ "rcwssetpa\t\0"
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/* 1053 */ "rcwsetpa\t\0"
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/* 1063 */ "rcwsswpa\t\0"
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/* 1073 */ "rcwswpa\t\0"
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/* 1082 */ "fexpa\t\0"
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/* 1089 */ "ldclra\t\0"
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/* 1097 */ "rcwsclra\t\0"
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/* 1107 */ "rcwclra\t\0"
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/* 1116 */ "ldeora\t\0"
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/* 1124 */ "srsra\t\0"
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/* 1131 */ "ursra\t\0"
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/* 1138 */ "ssra\t\0"
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/* 1144 */ "usra\t\0"
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/* 1150 */ "rcwscasa\t\0"
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/* 1160 */ "rcwcasa\t\0"
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/* 1169 */ "ldseta\t\0"
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/* 1177 */ "rcwsseta\t\0"
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/* 1187 */ "rcwseta\t\0"
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/* 1196 */ "frinta\t\0"
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/* 1204 */ "clasta\t\0"
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/* 1212 */ "addva\t\0"
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/* 1219 */ "mova\t\0"
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/* 1225 */ "ldsmaxa\t\0"
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/* 1234 */ "ldumaxa\t\0"
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/* 1243 */ "pacdza\t\0"
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/* 1251 */ "autdza\t\0"
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/* 1259 */ "paciza\t\0"
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/* 1267 */ "autiza\t\0"
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/* 1275 */ "ld1b\t\0"
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/* 1281 */ "ldff1b\t\0"
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/* 1289 */ "ldnf1b\t\0"
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/* 1297 */ "ldnt1b\t\0"
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/* 1305 */ "stnt1b\t\0"
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/* 1313 */ "st1b\t\0"
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/* 1319 */ "sm3tt1b\t\0"
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/* 1328 */ "crc32b\t\0"
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/* 1336 */ "ld2b\t\0"
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/* 1342 */ "st2b\t\0"
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/* 1348 */ "sm3tt2b\t\0"
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/* 1357 */ "ld3b\t\0"
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/* 1363 */ "st3b\t\0"
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/* 1369 */ "ld64b\t\0"
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/* 1376 */ "st64b\t\0"
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/* 1383 */ "ld4b\t\0"
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/* 1389 */ "st4b\t\0"
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/* 1395 */ "ldaddab\t\0"
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/* 1404 */ "ldsminab\t\0"
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/* 1414 */ "lduminab\t\0"
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/* 1424 */ "swpab\t\0"
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/* 1431 */ "brab\t\0"
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/* 1437 */ "ldrab\t\0"
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/* 1444 */ "blrab\t\0"
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/* 1451 */ "ldclrab\t\0"
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/* 1460 */ "ldeorab\t\0"
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/* 1469 */ "casab\t\0"
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/* 1476 */ "ldsetab\t\0"
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/* 1485 */ "ldsmaxab\t\0"
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/* 1495 */ "ldumaxab\t\0"
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/* 1505 */ "fmlallbb\t\0"
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/* 1515 */ "crc32cb\t\0"
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/* 1524 */ "sqdecb\t\0"
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/* 1532 */ "uqdecb\t\0"
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/* 1540 */ "sqincb\t\0"
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/* 1548 */ "uqincb\t\0"
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/* 1556 */ "pacdb\t\0"
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/* 1563 */ "ldaddb\t\0"
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/* 1571 */ "autdb\t\0"
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/* 1578 */ "prfb\t\0"
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/* 1584 */ "flogb\t\0"
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/* 1591 */ "pacib\t\0"
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/* 1598 */ "autib\t\0"
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/* 1605 */ "brkb\t\0"
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/* 1611 */ "sabalb\t\0"
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/* 1619 */ "uabalb\t\0"
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/* 1627 */ "ldaddalb\t\0"
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/* 1637 */ "sqdmlalb\t\0"
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/* 1647 */ "bfmlalb\t\0"
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/* 1656 */ "smlalb\t\0"
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/* 1664 */ "umlalb\t\0"
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/* 1672 */ "ldsminalb\t\0"
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/* 1683 */ "lduminalb\t\0"
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/* 1694 */ "swpalb\t\0"
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/* 1702 */ "ldclralb\t\0"
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/* 1712 */ "ldeoralb\t\0"
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/* 1722 */ "casalb\t\0"
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/* 1730 */ "ldsetalb\t\0"
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/* 1740 */ "ldsmaxalb\t\0"
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/* 1751 */ "ldumaxalb\t\0"
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/* 1762 */ "ssublb\t\0"
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/* 1770 */ "usublb\t\0"
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/* 1778 */ "sbclb\t\0"
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/* 1785 */ "adclb\t\0"
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/* 1792 */ "sabdlb\t\0"
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/* 1800 */ "uabdlb\t\0"
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/* 1808 */ "ldaddlb\t\0"
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/* 1817 */ "saddlb\t\0"
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/* 1825 */ "uaddlb\t\0"
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/* 1833 */ "sshllb\t\0"
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/* 1841 */ "ushllb\t\0"
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/* 1849 */ "sqdmullb\t\0"
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/* 1859 */ "pmullb\t\0"
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/* 1867 */ "smullb\t\0"
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/* 1875 */ "umullb\t\0"
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/* 1883 */ "ldsminlb\t\0"
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/* 1893 */ "lduminlb\t\0"
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/* 1903 */ "swplb\t\0"
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/* 1910 */ "ldclrlb\t\0"
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/* 1919 */ "ldeorlb\t\0"
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/* 1928 */ "caslb\t\0"
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/* 1935 */ "sqdmlslb\t\0"
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/* 1945 */ "bfmlslb\t\0"
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/* 1954 */ "smlslb\t\0"
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/* 1962 */ "umlslb\t\0"
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/* 1970 */ "ldsetlb\t\0"
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/* 1979 */ "ldsmaxlb\t\0"
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/* 1989 */ "ldumaxlb\t\0"
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/* 1999 */ "dmb\t\0"
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/* 2004 */ "rsubhnb\t\0"
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/* 2013 */ "raddhnb\t\0"
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/* 2022 */ "ldsminb\t\0"
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/* 2031 */ "lduminb\t\0"
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/* 2040 */ "sqshrnb\t\0"
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/* 2049 */ "uqshrnb\t\0"
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/* 2058 */ "sqrshrnb\t\0"
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/* 2068 */ "uqrshrnb\t\0"
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/* 2078 */ "fcvtnb\t\0"
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/* 2086 */ "sqxtnb\t\0"
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/* 2094 */ "uqxtnb\t\0"
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/* 2102 */ "sqshrunb\t\0"
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/* 2112 */ "sqrshrunb\t\0"
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/* 2123 */ "sqxtunb\t\0"
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/* 2132 */ "ld1rob\t\0"
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/* 2140 */ "brkpb\t\0"
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/* 2147 */ "swpb\t\0"
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/* 2153 */ "ld1rqb\t\0"
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/* 2161 */ "ld1rb\t\0"
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/* 2168 */ "ldarb\t\0"
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/* 2175 */ "ldlarb\t\0"
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/* 2183 */ "ldrb\t\0"
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/* 2189 */ "ldclrb\t\0"
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/* 2197 */ "stllrb\t\0"
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/* 2205 */ "stlrb\t\0"
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/* 2212 */ "ldeorb\t\0"
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/* 2220 */ "ldaprb\t\0"
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/* 2228 */ "ldtrb\t\0"
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/* 2235 */ "strb\t\0"
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/* 2241 */ "sttrb\t\0"
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/* 2248 */ "ldurb\t\0"
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/* 2255 */ "stlurb\t\0"
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/* 2263 */ "ldapurb\t\0"
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/* 2272 */ "sturb\t\0"
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/* 2279 */ "ldaxrb\t\0"
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/* 2287 */ "ldxrb\t\0"
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/* 2294 */ "stlxrb\t\0"
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/* 2302 */ "stxrb\t\0"
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/* 2309 */ "ld1sb\t\0"
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/* 2316 */ "ldff1sb\t\0"
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/* 2325 */ "ldnf1sb\t\0"
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/* 2334 */ "ldnt1sb\t\0"
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/* 2343 */ "casb\t\0"
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/* 2349 */ "sdsb\t\0"
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/* 2355 */ "isb\t\0"
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/* 2360 */ "fmsb\t\0"
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/* 2366 */ "fnmsb\t\0"
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/* 2373 */ "ld1rsb\t\0"
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/* 2381 */ "ldrsb\t\0"
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/* 2388 */ "ldtrsb\t\0"
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/* 2396 */ "ldursb\t\0"
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/* 2404 */ "ldapursb\t\0"
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/* 2414 */ "tsb\t\0"
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/* 2419 */ "ldsetb\t\0"
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/* 2427 */ "ssubltb\t\0"
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/* 2436 */ "fmlalltb\t\0"
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/* 2446 */ "cntb\t\0"
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/* 2452 */ "fvdotb\t\0"
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/* 2460 */ "eortb\t\0"
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/* 2467 */ "clastb\t\0"
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/* 2475 */ "sxtb\t\0"
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/* 2481 */ "uxtb\t\0"
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/* 2487 */ "bfsub\t\0"
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/* 2494 */ "shsub\t\0"
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/* 2501 */ "uhsub\t\0"
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/* 2508 */ "fmsub\t\0"
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/* 2515 */ "fnmsub\t\0"
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/* 2523 */ "sqsub\t\0"
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/* 2530 */ "uqsub\t\0"
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/* 2537 */ "revb\t\0"
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/* 2543 */ "ssubwb\t\0"
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/* 2551 */ "usubwb\t\0"
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/* 2559 */ "saddwb\t\0"
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/* 2567 */ "uaddwb\t\0"
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/* 2575 */ "ldsmaxb\t\0"
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/* 2584 */ "ldumaxb\t\0"
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/* 2593 */ "pacdzb\t\0"
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/* 2601 */ "autdzb\t\0"
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/* 2609 */ "pacizb\t\0"
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/* 2617 */ "autizb\t\0"
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/* 2625 */ "sha1c\t\0"
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/* 2632 */ "sbc\t\0"
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/* 2637 */ "adc\t\0"
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/* 2642 */ "bic\t\0"
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/* 2647 */ "wkdmc\t\0"
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/* 2654 */ "aesimc\t\0"
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/* 2662 */ "aesmc\t\0"
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/* 2669 */ "csinc\t\0"
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/* 2676 */ "retaasppc\t\0"
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/* 2687 */ "autiasppc\t\0"
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/* 2698 */ "retabsppc\t\0"
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/* 2709 */ "autibsppc\t\0"
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/* 2720 */ "hvc\t\0"
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/* 2725 */ "svc\t\0"
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/* 2730 */ "ld1d\t\0"
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/* 2736 */ "ldff1d\t\0"
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/* 2744 */ "ldnf1d\t\0"
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/* 2752 */ "ldnt1d\t\0"
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/* 2760 */ "stnt1d\t\0"
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/* 2768 */ "st1d\t\0"
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/* 2774 */ "mul53hi.2d\t\0"
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/* 2786 */ "mul53lo.2d\t\0"
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/* 2798 */ "ld2d\t\0"
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/* 2804 */ "st2d\t\0"
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/* 2810 */ "ld3d\t\0"
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/* 2816 */ "st3d\t\0"
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/* 2822 */ "ld4d\t\0"
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/* 2828 */ "st4d\t\0"
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/* 2834 */ "fmad\t\0"
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/* 2840 */ "fnmad\t\0"
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/* 2847 */ "ftmad\t\0"
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/* 2854 */ "fabd\t\0"
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/* 2860 */ "sabd\t\0"
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/* 2866 */ "uabd\t\0"
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/* 2872 */ "xpacd\t\0"
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/* 2879 */ "sqdecd\t\0"
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/* 2887 */ "uqdecd\t\0"
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/* 2895 */ "sqincd\t\0"
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/* 2903 */ "uqincd\t\0"
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/* 2911 */ "fcadd\t\0"
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/* 2918 */ "sqcadd\t\0"
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/* 2926 */ "ldadd\t\0"
|
|
/* 2933 */ "bfadd\t\0"
|
|
/* 2940 */ "srhadd\t\0"
|
|
/* 2948 */ "urhadd\t\0"
|
|
/* 2956 */ "shadd\t\0"
|
|
/* 2963 */ "uhadd\t\0"
|
|
/* 2970 */ "fmadd\t\0"
|
|
/* 2977 */ "fnmadd\t\0"
|
|
/* 2985 */ "usqadd\t\0"
|
|
/* 2993 */ "suqadd\t\0"
|
|
/* 3001 */ "prfd\t\0"
|
|
/* 3007 */ "wkdmd\t\0"
|
|
/* 3014 */ "nand\t\0"
|
|
/* 3020 */ "ld1rod\t\0"
|
|
/* 3028 */ "ld1rqd\t\0"
|
|
/* 3036 */ "ld1rd\t\0"
|
|
/* 3043 */ "asrd\t\0"
|
|
/* 3049 */ "aesd\t\0"
|
|
/* 3055 */ "cntd\t\0"
|
|
/* 3061 */ "revd\t\0"
|
|
/* 3067 */ "sm4e\t\0"
|
|
/* 3073 */ "splice\t\0"
|
|
/* 3081 */ "facge\t\0"
|
|
/* 3088 */ "whilege\t\0"
|
|
/* 3097 */ "fcmge\t\0"
|
|
/* 3104 */ "cmpge\t\0"
|
|
/* 3111 */ "fscale\t\0"
|
|
/* 3119 */ "whilele\t\0"
|
|
/* 3128 */ "fcmle\t\0"
|
|
/* 3135 */ "cmple\t\0"
|
|
/* 3142 */ "fcmne\t\0"
|
|
/* 3149 */ "ctermne\t\0"
|
|
/* 3158 */ "cmpne\t\0"
|
|
/* 3165 */ "frecpe\t\0"
|
|
/* 3173 */ "urecpe\t\0"
|
|
/* 3181 */ "fccmpe\t\0"
|
|
/* 3189 */ "fcmpe\t\0"
|
|
/* 3196 */ "aese\t\0"
|
|
/* 3202 */ "pfalse\t\0"
|
|
/* 3210 */ "frsqrte\t\0"
|
|
/* 3219 */ "ursqrte\t\0"
|
|
/* 3228 */ "ptrue\t\0"
|
|
/* 3235 */ "udf\t\0"
|
|
/* 3240 */ "bif\t\0"
|
|
/* 3245 */ "rmif\t\0"
|
|
/* 3251 */ "scvtf\t\0"
|
|
/* 3258 */ "ucvtf\t\0"
|
|
/* 3265 */ "st2g\t\0"
|
|
/* 3271 */ "stz2g\t\0"
|
|
/* 3278 */ "subg\t\0"
|
|
/* 3284 */ "addg\t\0"
|
|
/* 3290 */ "ldg\t\0"
|
|
/* 3295 */ "fneg\t\0"
|
|
/* 3301 */ "sqneg\t\0"
|
|
/* 3308 */ "csneg\t\0"
|
|
/* 3315 */ "histseg\t\0"
|
|
/* 3324 */ "irg\t\0"
|
|
/* 3329 */ "stg\t\0"
|
|
/* 3334 */ "stzg\t\0"
|
|
/* 3340 */ "sha1h\t\0"
|
|
/* 3347 */ "ld1h\t\0"
|
|
/* 3353 */ "ldff1h\t\0"
|
|
/* 3361 */ "ldnf1h\t\0"
|
|
/* 3369 */ "ldnt1h\t\0"
|
|
/* 3377 */ "stnt1h\t\0"
|
|
/* 3385 */ "st1h\t\0"
|
|
/* 3391 */ "sha512h\t\0"
|
|
/* 3400 */ "crc32h\t\0"
|
|
/* 3408 */ "ld2h\t\0"
|
|
/* 3414 */ "st2h\t\0"
|
|
/* 3420 */ "ld3h\t\0"
|
|
/* 3426 */ "st3h\t\0"
|
|
/* 3432 */ "ld4h\t\0"
|
|
/* 3438 */ "st4h\t\0"
|
|
/* 3444 */ "sha256h\t\0"
|
|
/* 3453 */ "ldaddah\t\0"
|
|
/* 3462 */ "sqrdcmlah\t\0"
|
|
/* 3473 */ "sqrdmlah\t\0"
|
|
/* 3483 */ "ldsminah\t\0"
|
|
/* 3493 */ "lduminah\t\0"
|
|
/* 3503 */ "swpah\t\0"
|
|
/* 3510 */ "ldclrah\t\0"
|
|
/* 3519 */ "ldeorah\t\0"
|
|
/* 3528 */ "casah\t\0"
|
|
/* 3535 */ "ldsetah\t\0"
|
|
/* 3544 */ "ldsmaxah\t\0"
|
|
/* 3554 */ "ldumaxah\t\0"
|
|
/* 3564 */ "crc32ch\t\0"
|
|
/* 3573 */ "sqdech\t\0"
|
|
/* 3581 */ "uqdech\t\0"
|
|
/* 3589 */ "sqinch\t\0"
|
|
/* 3597 */ "uqinch\t\0"
|
|
/* 3605 */ "nmatch\t\0"
|
|
/* 3613 */ "ldaddh\t\0"
|
|
/* 3621 */ "prfh\t\0"
|
|
/* 3627 */ "ldaddalh\t\0"
|
|
/* 3637 */ "ldsminalh\t\0"
|
|
/* 3648 */ "lduminalh\t\0"
|
|
/* 3659 */ "swpalh\t\0"
|
|
/* 3667 */ "ldclralh\t\0"
|
|
/* 3677 */ "ldeoralh\t\0"
|
|
/* 3687 */ "casalh\t\0"
|
|
/* 3695 */ "ldsetalh\t\0"
|
|
/* 3705 */ "ldsmaxalh\t\0"
|
|
/* 3716 */ "ldumaxalh\t\0"
|
|
/* 3727 */ "ldaddlh\t\0"
|
|
/* 3736 */ "ldsminlh\t\0"
|
|
/* 3746 */ "lduminlh\t\0"
|
|
/* 3756 */ "swplh\t\0"
|
|
/* 3763 */ "ldclrlh\t\0"
|
|
/* 3772 */ "ldeorlh\t\0"
|
|
/* 3781 */ "caslh\t\0"
|
|
/* 3788 */ "ldsetlh\t\0"
|
|
/* 3797 */ "sqdmulh\t\0"
|
|
/* 3806 */ "sqrdmulh\t\0"
|
|
/* 3816 */ "smulh\t\0"
|
|
/* 3823 */ "umulh\t\0"
|
|
/* 3830 */ "ldsmaxlh\t\0"
|
|
/* 3840 */ "ldumaxlh\t\0"
|
|
/* 3850 */ "ldsminh\t\0"
|
|
/* 3859 */ "lduminh\t\0"
|
|
/* 3868 */ "ld1roh\t\0"
|
|
/* 3876 */ "swph\t\0"
|
|
/* 3882 */ "ld1rqh\t\0"
|
|
/* 3890 */ "ld1rh\t\0"
|
|
/* 3897 */ "ldarh\t\0"
|
|
/* 3904 */ "ldlarh\t\0"
|
|
/* 3912 */ "ldrh\t\0"
|
|
/* 3918 */ "ldclrh\t\0"
|
|
/* 3926 */ "stllrh\t\0"
|
|
/* 3934 */ "stlrh\t\0"
|
|
/* 3941 */ "ldeorh\t\0"
|
|
/* 3949 */ "ldaprh\t\0"
|
|
/* 3957 */ "ldtrh\t\0"
|
|
/* 3964 */ "strh\t\0"
|
|
/* 3970 */ "sttrh\t\0"
|
|
/* 3977 */ "ldurh\t\0"
|
|
/* 3984 */ "stlurh\t\0"
|
|
/* 3992 */ "ldapurh\t\0"
|
|
/* 4001 */ "sturh\t\0"
|
|
/* 4008 */ "ldaxrh\t\0"
|
|
/* 4016 */ "ldxrh\t\0"
|
|
/* 4023 */ "stlxrh\t\0"
|
|
/* 4031 */ "stxrh\t\0"
|
|
/* 4038 */ "ld1sh\t\0"
|
|
/* 4045 */ "ldff1sh\t\0"
|
|
/* 4054 */ "ldnf1sh\t\0"
|
|
/* 4063 */ "ldnt1sh\t\0"
|
|
/* 4072 */ "cash\t\0"
|
|
/* 4078 */ "sqrdmlsh\t\0"
|
|
/* 4088 */ "ld1rsh\t\0"
|
|
/* 4096 */ "ldrsh\t\0"
|
|
/* 4103 */ "ldtrsh\t\0"
|
|
/* 4111 */ "ldursh\t\0"
|
|
/* 4119 */ "ldapursh\t\0"
|
|
/* 4129 */ "ldseth\t\0"
|
|
/* 4137 */ "cnth\t\0"
|
|
/* 4143 */ "sxth\t\0"
|
|
/* 4149 */ "uxth\t\0"
|
|
/* 4155 */ "revh\t\0"
|
|
/* 4161 */ "ldsmaxh\t\0"
|
|
/* 4170 */ "ldumaxh\t\0"
|
|
/* 4179 */ "xpaci\t\0"
|
|
/* 4186 */ "whilehi\t\0"
|
|
/* 4195 */ "punpkhi\t\0"
|
|
/* 4204 */ "sunpkhi\t\0"
|
|
/* 4213 */ "uunpkhi\t\0"
|
|
/* 4222 */ "cmhi\t\0"
|
|
/* 4228 */ "cmphi\t\0"
|
|
/* 4235 */ "sli\t\0"
|
|
/* 4240 */ "gmi\t\0"
|
|
/* 4245 */ "mvni\t\0"
|
|
/* 4251 */ "sri\t\0"
|
|
/* 4256 */ "frinti\t\0"
|
|
/* 4264 */ "movi\t\0"
|
|
/* 4270 */ "ldzi\t\0"
|
|
/* 4276 */ "stzi\t\0"
|
|
/* 4282 */ "sunpk\t\0"
|
|
/* 4289 */ "uunpk\t\0"
|
|
/* 4296 */ "brk\t\0"
|
|
/* 4301 */ "movk\t\0"
|
|
/* 4307 */ "sabal\t\0"
|
|
/* 4314 */ "uabal\t\0"
|
|
/* 4321 */ "ldaddal\t\0"
|
|
/* 4330 */ "sqdmlal\t\0"
|
|
/* 4339 */ "bfmlal\t\0"
|
|
/* 4347 */ "smlal\t\0"
|
|
/* 4354 */ "umlal\t\0"
|
|
/* 4361 */ "ldsminal\t\0"
|
|
/* 4371 */ "lduminal\t\0"
|
|
/* 4381 */ "rcwsswppal\t\0"
|
|
/* 4393 */ "rcwswppal\t\0"
|
|
/* 4404 */ "ldclrpal\t\0"
|
|
/* 4414 */ "rcwsclrpal\t\0"
|
|
/* 4426 */ "rcwclrpal\t\0"
|
|
/* 4437 */ "rcwscaspal\t\0"
|
|
/* 4449 */ "rcwcaspal\t\0"
|
|
/* 4460 */ "ldsetpal\t\0"
|
|
/* 4470 */ "rcwssetpal\t\0"
|
|
/* 4482 */ "rcwsetpal\t\0"
|
|
/* 4493 */ "rcwsswpal\t\0"
|
|
/* 4504 */ "rcwswpal\t\0"
|
|
/* 4514 */ "ldclral\t\0"
|
|
/* 4523 */ "rcwsclral\t\0"
|
|
/* 4534 */ "rcwclral\t\0"
|
|
/* 4544 */ "ldeoral\t\0"
|
|
/* 4553 */ "rcwscasal\t\0"
|
|
/* 4564 */ "rcwcasal\t\0"
|
|
/* 4574 */ "ldsetal\t\0"
|
|
/* 4583 */ "rcwssetal\t\0"
|
|
/* 4594 */ "rcwsetal\t\0"
|
|
/* 4604 */ "ldsmaxal\t\0"
|
|
/* 4614 */ "ldumaxal\t\0"
|
|
/* 4624 */ "tbl\t\0"
|
|
/* 4629 */ "smsubl\t\0"
|
|
/* 4637 */ "umsubl\t\0"
|
|
/* 4645 */ "ssubl\t\0"
|
|
/* 4652 */ "usubl\t\0"
|
|
/* 4659 */ "sabdl\t\0"
|
|
/* 4666 */ "uabdl\t\0"
|
|
/* 4673 */ "ldaddl\t\0"
|
|
/* 4681 */ "smaddl\t\0"
|
|
/* 4689 */ "umaddl\t\0"
|
|
/* 4697 */ "saddl\t\0"
|
|
/* 4704 */ "uaddl\t\0"
|
|
/* 4711 */ "tcancel\t\0"
|
|
/* 4720 */ "fcsel\t\0"
|
|
/* 4727 */ "psel\t\0"
|
|
/* 4733 */ "ftssel\t\0"
|
|
/* 4741 */ "sqshl\t\0"
|
|
/* 4748 */ "uqshl\t\0"
|
|
/* 4755 */ "sqrshl\t\0"
|
|
/* 4763 */ "uqrshl\t\0"
|
|
/* 4771 */ "srshl\t\0"
|
|
/* 4778 */ "urshl\t\0"
|
|
/* 4785 */ "sshl\t\0"
|
|
/* 4791 */ "ushl\t\0"
|
|
/* 4797 */ "fmlall\t\0"
|
|
/* 4805 */ "usmlall\t\0"
|
|
/* 4814 */ "sumlall\t\0"
|
|
/* 4823 */ "sshll\t\0"
|
|
/* 4830 */ "ushll\t\0"
|
|
/* 4837 */ "smlsll\t\0"
|
|
/* 4845 */ "umlsll\t\0"
|
|
/* 4853 */ "sqdmull\t\0"
|
|
/* 4862 */ "pmull\t\0"
|
|
/* 4869 */ "smull\t\0"
|
|
/* 4876 */ "umull\t\0"
|
|
/* 4883 */ "ldsminl\t\0"
|
|
/* 4892 */ "lduminl\t\0"
|
|
/* 4901 */ "addpl\t\0"
|
|
/* 4908 */ "rcwsswppl\t\0"
|
|
/* 4919 */ "rcwswppl\t\0"
|
|
/* 4929 */ "ldclrpl\t\0"
|
|
/* 4938 */ "rcwsclrpl\t\0"
|
|
/* 4949 */ "rcwclrpl\t\0"
|
|
/* 4959 */ "rcwscaspl\t\0"
|
|
/* 4970 */ "rcwcaspl\t\0"
|
|
/* 4980 */ "addspl\t\0"
|
|
/* 4988 */ "ldsetpl\t\0"
|
|
/* 4997 */ "rcwssetpl\t\0"
|
|
/* 5008 */ "rcwsetpl\t\0"
|
|
/* 5018 */ "rcwsswpl\t\0"
|
|
/* 5028 */ "rcwswpl\t\0"
|
|
/* 5037 */ "ldclrl\t\0"
|
|
/* 5045 */ "rcwsclrl\t\0"
|
|
/* 5055 */ "rcwclrl\t\0"
|
|
/* 5064 */ "ldeorl\t\0"
|
|
/* 5072 */ "rcwscasl\t\0"
|
|
/* 5082 */ "rcwcasl\t\0"
|
|
/* 5091 */ "nbsl\t\0"
|
|
/* 5097 */ "sqdmlsl\t\0"
|
|
/* 5106 */ "bfmlsl\t\0"
|
|
/* 5114 */ "smlsl\t\0"
|
|
/* 5121 */ "umlsl\t\0"
|
|
/* 5128 */ "sysl\t\0"
|
|
/* 5134 */ "ldsetl\t\0"
|
|
/* 5142 */ "rcwssetl\t\0"
|
|
/* 5152 */ "rcwsetl\t\0"
|
|
/* 5161 */ "bf1cvtl\t\0"
|
|
/* 5170 */ "bf2cvtl\t\0"
|
|
/* 5179 */ "fcvtl\t\0"
|
|
/* 5186 */ "bfmul\t\0"
|
|
/* 5193 */ "fnmul\t\0"
|
|
/* 5200 */ "pmul\t\0"
|
|
/* 5206 */ "ftsmul\t\0"
|
|
/* 5214 */ "addvl\t\0"
|
|
/* 5221 */ "rdvl\t\0"
|
|
/* 5227 */ "addsvl\t\0"
|
|
/* 5235 */ "rdsvl\t\0"
|
|
/* 5242 */ "ldsmaxl\t\0"
|
|
/* 5251 */ "ldumaxl\t\0"
|
|
/* 5260 */ "sha1m\t\0"
|
|
/* 5267 */ "sbfm\t\0"
|
|
/* 5273 */ "ubfm\t\0"
|
|
/* 5279 */ "rprfm\t\0"
|
|
/* 5286 */ "ldgm\t\0"
|
|
/* 5292 */ "stgm\t\0"
|
|
/* 5298 */ "stzgm\t\0"
|
|
/* 5305 */ "gcspushm\t\0"
|
|
/* 5315 */ "bfminnm\t\0"
|
|
/* 5324 */ "bfmaxnm\t\0"
|
|
/* 5333 */ "gcspopm\t\0"
|
|
/* 5342 */ "dupm\t\0"
|
|
/* 5348 */ "frintm\t\0"
|
|
/* 5356 */ "prfum\t\0"
|
|
/* 5363 */ "bsl1n\t\0"
|
|
/* 5370 */ "bsl2n\t\0"
|
|
/* 5377 */ "rsubhn\t\0"
|
|
/* 5385 */ "raddhn\t\0"
|
|
/* 5393 */ "famin\t\0"
|
|
/* 5400 */ "bfmin\t\0"
|
|
/* 5407 */ "ldsmin\t\0"
|
|
/* 5415 */ "ldumin\t\0"
|
|
/* 5423 */ "brkn\t\0"
|
|
/* 5429 */ "ccmn\t\0"
|
|
/* 5435 */ "eon\t\0"
|
|
/* 5440 */ "sqshrn\t\0"
|
|
/* 5448 */ "uqshrn\t\0"
|
|
/* 5456 */ "sqrshrn\t\0"
|
|
/* 5465 */ "uqrshrn\t\0"
|
|
/* 5474 */ "orn\t\0"
|
|
/* 5479 */ "frintn\t\0"
|
|
/* 5487 */ "bfcvtn\t\0"
|
|
/* 5495 */ "sqcvtn\t\0"
|
|
/* 5503 */ "uqcvtn\t\0"
|
|
/* 5511 */ "sqxtn\t\0"
|
|
/* 5518 */ "uqxtn\t\0"
|
|
/* 5525 */ "sqshrun\t\0"
|
|
/* 5534 */ "sqrshrun\t\0"
|
|
/* 5544 */ "sqcvtun\t\0"
|
|
/* 5553 */ "sqxtun\t\0"
|
|
/* 5561 */ "movn\t\0"
|
|
/* 5567 */ "fcvtxn\t\0"
|
|
/* 5575 */ "whilelo\t\0"
|
|
/* 5584 */ "punpklo\t\0"
|
|
/* 5593 */ "sunpklo\t\0"
|
|
/* 5602 */ "uunpklo\t\0"
|
|
/* 5611 */ "cmplo\t\0"
|
|
/* 5618 */ "zero\t\0"
|
|
/* 5624 */ "fcmuo\t\0"
|
|
/* 5631 */ "sha1p\t\0"
|
|
/* 5638 */ "subp\t\0"
|
|
/* 5644 */ "sqdecp\t\0"
|
|
/* 5652 */ "uqdecp\t\0"
|
|
/* 5660 */ "sqincp\t\0"
|
|
/* 5668 */ "uqincp\t\0"
|
|
/* 5676 */ "faddp\t\0"
|
|
/* 5683 */ "ldp\t\0"
|
|
/* 5688 */ "bdep\t\0"
|
|
/* 5694 */ "vecfp\t\0"
|
|
/* 5701 */ "matfp\t\0"
|
|
/* 5708 */ "stgp\t\0"
|
|
/* 5714 */ "zip\t\0"
|
|
/* 5719 */ "sadalp\t\0"
|
|
/* 5727 */ "uadalp\t\0"
|
|
/* 5735 */ "saddlp\t\0"
|
|
/* 5743 */ "uaddlp\t\0"
|
|
/* 5751 */ "stilp\t\0"
|
|
/* 5758 */ "bfclamp\t\0"
|
|
/* 5767 */ "sclamp\t\0"
|
|
/* 5775 */ "uclamp\t\0"
|
|
/* 5783 */ "fccmp\t\0"
|
|
/* 5790 */ "fcmp\t\0"
|
|
/* 5796 */ "fminnmp\t\0"
|
|
/* 5805 */ "fmaxnmp\t\0"
|
|
/* 5814 */ "ldnp\t\0"
|
|
/* 5820 */ "fminp\t\0"
|
|
/* 5827 */ "sminp\t\0"
|
|
/* 5834 */ "uminp\t\0"
|
|
/* 5841 */ "stnp\t\0"
|
|
/* 5847 */ "ldiapp\t\0"
|
|
/* 5855 */ "rcwsswpp\t\0"
|
|
/* 5865 */ "rcwswpp\t\0"
|
|
/* 5874 */ "adrp\t\0"
|
|
/* 5880 */ "bgrp\t\0"
|
|
/* 5886 */ "ldclrp\t\0"
|
|
/* 5894 */ "rcwsclrp\t\0"
|
|
/* 5904 */ "rcwclrp\t\0"
|
|
/* 5913 */ "rcwscasp\t\0"
|
|
/* 5923 */ "rcwcasp\t\0"
|
|
/* 5932 */ "sysp\t\0"
|
|
/* 5938 */ "ldsetp\t\0"
|
|
/* 5946 */ "rcwssetp\t\0"
|
|
/* 5956 */ "rcwsetp\t\0"
|
|
/* 5965 */ "cntp\t\0"
|
|
/* 5971 */ "frintp\t\0"
|
|
/* 5979 */ "stp\t\0"
|
|
/* 5984 */ "fdup\t\0"
|
|
/* 5990 */ "rcwsswp\t\0"
|
|
/* 5999 */ "rcwswp\t\0"
|
|
/* 6007 */ "ldaxp\t\0"
|
|
/* 6014 */ "fmaxp\t\0"
|
|
/* 6021 */ "smaxp\t\0"
|
|
/* 6028 */ "umaxp\t\0"
|
|
/* 6035 */ "ldxp\t\0"
|
|
/* 6041 */ "stlxp\t\0"
|
|
/* 6048 */ "stxp\t\0"
|
|
/* 6054 */ "uzp\t\0"
|
|
/* 6059 */ "ld1q\t\0"
|
|
/* 6065 */ "st1q\t\0"
|
|
/* 6071 */ "ld2q\t\0"
|
|
/* 6077 */ "st2q\t\0"
|
|
/* 6083 */ "ld3q\t\0"
|
|
/* 6089 */ "st3q\t\0"
|
|
/* 6095 */ "ld4q\t\0"
|
|
/* 6101 */ "st4q\t\0"
|
|
/* 6107 */ "fcmeq\t\0"
|
|
/* 6114 */ "ctermeq\t\0"
|
|
/* 6123 */ "cmpeq\t\0"
|
|
/* 6130 */ "tblq\t\0"
|
|
/* 6136 */ "dupq\t\0"
|
|
/* 6142 */ "extq\t\0"
|
|
/* 6148 */ "tbxq\t\0"
|
|
/* 6154 */ "ld1r\t\0"
|
|
/* 6160 */ "ld2r\t\0"
|
|
/* 6166 */ "ld3r\t\0"
|
|
/* 6172 */ "ld4r\t\0"
|
|
/* 6178 */ "ldar\t\0"
|
|
/* 6184 */ "ldlar\t\0"
|
|
/* 6191 */ "xar\t\0"
|
|
/* 6196 */ "fsubr\t\0"
|
|
/* 6203 */ "shsubr\t\0"
|
|
/* 6211 */ "uhsubr\t\0"
|
|
/* 6219 */ "sqsubr\t\0"
|
|
/* 6227 */ "uqsubr\t\0"
|
|
/* 6235 */ "adr\t\0"
|
|
/* 6240 */ "ldr\t\0"
|
|
/* 6245 */ "genter\t\0"
|
|
/* 6253 */ "rdffr\t\0"
|
|
/* 6260 */ "wrffr\t\0"
|
|
/* 6267 */ "sqrshr\t\0"
|
|
/* 6275 */ "uqrshr\t\0"
|
|
/* 6283 */ "srshr\t\0"
|
|
/* 6290 */ "urshr\t\0"
|
|
/* 6297 */ "sshr\t\0"
|
|
/* 6303 */ "ushr\t\0"
|
|
/* 6309 */ "blr\t\0"
|
|
/* 6314 */ "ldclr\t\0"
|
|
/* 6321 */ "rcwsclr\t\0"
|
|
/* 6330 */ "rcwclr\t\0"
|
|
/* 6338 */ "sqshlr\t\0"
|
|
/* 6346 */ "uqshlr\t\0"
|
|
/* 6354 */ "sqrshlr\t\0"
|
|
/* 6363 */ "uqrshlr\t\0"
|
|
/* 6372 */ "srshlr\t\0"
|
|
/* 6380 */ "urshlr\t\0"
|
|
/* 6388 */ "stllr\t\0"
|
|
/* 6395 */ "lslr\t\0"
|
|
/* 6401 */ "stlr\t\0"
|
|
/* 6407 */ "ldeor\t\0"
|
|
/* 6414 */ "nor\t\0"
|
|
/* 6419 */ "ror\t\0"
|
|
/* 6424 */ "ldapr\t\0"
|
|
/* 6431 */ "orr\t\0"
|
|
/* 6436 */ "asrr\t\0"
|
|
/* 6442 */ "lsrr\t\0"
|
|
/* 6448 */ "msrr\t\0"
|
|
/* 6454 */ "asr\t\0"
|
|
/* 6459 */ "lsr\t\0"
|
|
/* 6464 */ "msr\t\0"
|
|
/* 6469 */ "insr\t\0"
|
|
/* 6475 */ "ldtr\t\0"
|
|
/* 6481 */ "gcsstr\t\0"
|
|
/* 6489 */ "gcssttr\t\0"
|
|
/* 6498 */ "extr\t\0"
|
|
/* 6504 */ "ldur\t\0"
|
|
/* 6510 */ "stlur\t\0"
|
|
/* 6517 */ "ldapur\t\0"
|
|
/* 6525 */ "stur\t\0"
|
|
/* 6531 */ "fdivr\t\0"
|
|
/* 6538 */ "sdivr\t\0"
|
|
/* 6545 */ "udivr\t\0"
|
|
/* 6552 */ "whilewr\t\0"
|
|
/* 6561 */ "ldaxr\t\0"
|
|
/* 6568 */ "ldxr\t\0"
|
|
/* 6574 */ "stlxr\t\0"
|
|
/* 6581 */ "stxr\t\0"
|
|
/* 6587 */ "rcwscas\t\0"
|
|
/* 6596 */ "rcwcas\t\0"
|
|
/* 6604 */ "brkas\t\0"
|
|
/* 6611 */ "brkpas\t\0"
|
|
/* 6619 */ "fcvtas\t\0"
|
|
/* 6627 */ "fabs\t\0"
|
|
/* 6633 */ "sqabs\t\0"
|
|
/* 6640 */ "brkbs\t\0"
|
|
/* 6647 */ "brkpbs\t\0"
|
|
/* 6655 */ "subs\t\0"
|
|
/* 6661 */ "sbcs\t\0"
|
|
/* 6667 */ "adcs\t\0"
|
|
/* 6673 */ "bics\t\0"
|
|
/* 6679 */ "adds\t\0"
|
|
/* 6685 */ "nands\t\0"
|
|
/* 6692 */ "ptrues\t\0"
|
|
/* 6700 */ "whilehs\t\0"
|
|
/* 6709 */ "cmhs\t\0"
|
|
/* 6715 */ "cmphs\t\0"
|
|
/* 6722 */ "cls\t\0"
|
|
/* 6727 */ "whilels\t\0"
|
|
/* 6736 */ "bfmls\t\0"
|
|
/* 6743 */ "fnmls\t\0"
|
|
/* 6750 */ "cmpls\t\0"
|
|
/* 6757 */ "fcvtms\t\0"
|
|
/* 6765 */ "ins\t\0"
|
|
/* 6770 */ "brkns\t\0"
|
|
/* 6777 */ "orns\t\0"
|
|
/* 6783 */ "fcvtns\t\0"
|
|
/* 6791 */ "subps\t\0"
|
|
/* 6798 */ "frecps\t\0"
|
|
/* 6806 */ "bmops\t\0"
|
|
/* 6813 */ "bfmops\t\0"
|
|
/* 6821 */ "usmops\t\0"
|
|
/* 6829 */ "sumops\t\0"
|
|
/* 6837 */ "fcvtps\t\0"
|
|
/* 6845 */ "rdffrs\t\0"
|
|
/* 6853 */ "mrs\t\0"
|
|
/* 6858 */ "eors\t\0"
|
|
/* 6864 */ "nors\t\0"
|
|
/* 6870 */ "mrrs\t\0"
|
|
/* 6876 */ "orrs\t\0"
|
|
/* 6882 */ "frsqrts\t\0"
|
|
/* 6891 */ "sys\t\0"
|
|
/* 6896 */ "fcvtzs\t\0"
|
|
/* 6904 */ "fjcvtzs\t\0"
|
|
/* 6913 */ "sqdmlalbt\t\0"
|
|
/* 6924 */ "ssublbt\t\0"
|
|
/* 6933 */ "saddlbt\t\0"
|
|
/* 6942 */ "fmlallbt\t\0"
|
|
/* 6952 */ "sqdmlslbt\t\0"
|
|
/* 6963 */ "eorbt\t\0"
|
|
/* 6970 */ "compact\t\0"
|
|
/* 6979 */ "wfet\t\0"
|
|
/* 6985 */ "ret\t\0"
|
|
/* 6990 */ "ldset\t\0"
|
|
/* 6997 */ "rcwsset\t\0"
|
|
/* 7006 */ "rcwset\t\0"
|
|
/* 7014 */ "facgt\t\0"
|
|
/* 7021 */ "whilegt\t\0"
|
|
/* 7030 */ "fcmgt\t\0"
|
|
/* 7037 */ "cmpgt\t\0"
|
|
/* 7044 */ "rbit\t\0"
|
|
/* 7050 */ "trcit\t\0"
|
|
/* 7057 */ "wfit\t\0"
|
|
/* 7063 */ "sabalt\t\0"
|
|
/* 7071 */ "uabalt\t\0"
|
|
/* 7079 */ "sqdmlalt\t\0"
|
|
/* 7089 */ "bfmlalt\t\0"
|
|
/* 7098 */ "smlalt\t\0"
|
|
/* 7106 */ "umlalt\t\0"
|
|
/* 7114 */ "ssublt\t\0"
|
|
/* 7122 */ "usublt\t\0"
|
|
/* 7130 */ "sbclt\t\0"
|
|
/* 7137 */ "adclt\t\0"
|
|
/* 7144 */ "sabdlt\t\0"
|
|
/* 7152 */ "uabdlt\t\0"
|
|
/* 7160 */ "saddlt\t\0"
|
|
/* 7168 */ "uaddlt\t\0"
|
|
/* 7176 */ "whilelt\t\0"
|
|
/* 7185 */ "hlt\t\0"
|
|
/* 7190 */ "sshllt\t\0"
|
|
/* 7198 */ "ushllt\t\0"
|
|
/* 7206 */ "sqdmullt\t\0"
|
|
/* 7216 */ "pmullt\t\0"
|
|
/* 7224 */ "smullt\t\0"
|
|
/* 7232 */ "umullt\t\0"
|
|
/* 7240 */ "fcmlt\t\0"
|
|
/* 7247 */ "cmplt\t\0"
|
|
/* 7254 */ "sqdmlslt\t\0"
|
|
/* 7264 */ "bfmlslt\t\0"
|
|
/* 7273 */ "smlslt\t\0"
|
|
/* 7281 */ "umlslt\t\0"
|
|
/* 7289 */ "bf1cvtlt\t\0"
|
|
/* 7299 */ "bf2cvtlt\t\0"
|
|
/* 7309 */ "fcvtlt\t\0"
|
|
/* 7317 */ "histcnt\t\0"
|
|
/* 7326 */ "rsubhnt\t\0"
|
|
/* 7335 */ "raddhnt\t\0"
|
|
/* 7344 */ "vecint\t\0"
|
|
/* 7352 */ "hint\t\0"
|
|
/* 7358 */ "matint\t\0"
|
|
/* 7366 */ "sqshrnt\t\0"
|
|
/* 7375 */ "uqshrnt\t\0"
|
|
/* 7384 */ "sqrshrnt\t\0"
|
|
/* 7394 */ "uqrshrnt\t\0"
|
|
/* 7404 */ "bfcvtnt\t\0"
|
|
/* 7413 */ "sqxtnt\t\0"
|
|
/* 7421 */ "uqxtnt\t\0"
|
|
/* 7429 */ "sqshrunt\t\0"
|
|
/* 7439 */ "sqrshrunt\t\0"
|
|
/* 7450 */ "sqxtunt\t\0"
|
|
/* 7459 */ "fcvtxnt\t\0"
|
|
/* 7468 */ "cdot\t\0"
|
|
/* 7474 */ "bfdot\t\0"
|
|
/* 7481 */ "usdot\t\0"
|
|
/* 7488 */ "sudot\t\0"
|
|
/* 7495 */ "bfvdot\t\0"
|
|
/* 7503 */ "usvdot\t\0"
|
|
/* 7511 */ "suvdot\t\0"
|
|
/* 7519 */ "cnot\t\0"
|
|
/* 7525 */ "mlapt\t\0"
|
|
/* 7532 */ "msubpt\t\0"
|
|
/* 7540 */ "madpt\t\0"
|
|
/* 7547 */ "maddpt\t\0"
|
|
/* 7555 */ "tstart\t\0"
|
|
/* 7563 */ "fsqrt\t\0"
|
|
/* 7570 */ "ptest\t\0"
|
|
/* 7577 */ "ttest\t\0"
|
|
/* 7584 */ "pfirst\t\0"
|
|
/* 7592 */ "cmtst\t\0"
|
|
/* 7599 */ "fmlalltt\t\0"
|
|
/* 7609 */ "fvdott\t\0"
|
|
/* 7617 */ "genlut\t\0"
|
|
/* 7625 */ "bf1cvt\t\0"
|
|
/* 7633 */ "bf2cvt\t\0"
|
|
/* 7641 */ "bfcvt\t\0"
|
|
/* 7648 */ "sqcvt\t\0"
|
|
/* 7655 */ "uqcvt\t\0"
|
|
/* 7662 */ "movt\t\0"
|
|
/* 7668 */ "ssubwt\t\0"
|
|
/* 7676 */ "usubwt\t\0"
|
|
/* 7684 */ "saddwt\t\0"
|
|
/* 7692 */ "uaddwt\t\0"
|
|
/* 7700 */ "bext\t\0"
|
|
/* 7706 */ "pnext\t\0"
|
|
/* 7713 */ "pext\t\0"
|
|
/* 7719 */ "fcvtau\t\0"
|
|
/* 7727 */ "sqshlu\t\0"
|
|
/* 7735 */ "fcvtmu\t\0"
|
|
/* 7743 */ "fcvtnu\t\0"
|
|
/* 7751 */ "fcvtpu\t\0"
|
|
/* 7759 */ "sqrshru\t\0"
|
|
/* 7768 */ "sqcvtu\t\0"
|
|
/* 7776 */ "fcvtzu\t\0"
|
|
/* 7784 */ "st64bv\t\0"
|
|
/* 7792 */ "faddv\t\0"
|
|
/* 7799 */ "saddv\t\0"
|
|
/* 7806 */ "uaddv\t\0"
|
|
/* 7813 */ "andv\t\0"
|
|
/* 7819 */ "rev\t\0"
|
|
/* 7824 */ "fdiv\t\0"
|
|
/* 7830 */ "sdiv\t\0"
|
|
/* 7836 */ "udiv\t\0"
|
|
/* 7842 */ "saddlv\t\0"
|
|
/* 7850 */ "uaddlv\t\0"
|
|
/* 7858 */ "fminnmv\t\0"
|
|
/* 7867 */ "fmaxnmv\t\0"
|
|
/* 7876 */ "fminv\t\0"
|
|
/* 7883 */ "sminv\t\0"
|
|
/* 7890 */ "uminv\t\0"
|
|
/* 7897 */ "csinv\t\0"
|
|
/* 7904 */ "fmov\t\0"
|
|
/* 7910 */ "pmov\t\0"
|
|
/* 7916 */ "smov\t\0"
|
|
/* 7922 */ "umov\t\0"
|
|
/* 7928 */ "faddqv\t\0"
|
|
/* 7936 */ "andqv\t\0"
|
|
/* 7943 */ "fminnmqv\t\0"
|
|
/* 7953 */ "fmaxnmqv\t\0"
|
|
/* 7963 */ "fminqv\t\0"
|
|
/* 7971 */ "sminqv\t\0"
|
|
/* 7979 */ "uminqv\t\0"
|
|
/* 7987 */ "eorqv\t\0"
|
|
/* 7994 */ "fmaxqv\t\0"
|
|
/* 8002 */ "smaxqv\t\0"
|
|
/* 8010 */ "umaxqv\t\0"
|
|
/* 8018 */ "eorv\t\0"
|
|
/* 8024 */ "fmaxv\t\0"
|
|
/* 8031 */ "smaxv\t\0"
|
|
/* 8038 */ "umaxv\t\0"
|
|
/* 8045 */ "ld1w\t\0"
|
|
/* 8051 */ "ldff1w\t\0"
|
|
/* 8059 */ "ldnf1w\t\0"
|
|
/* 8067 */ "ldnt1w\t\0"
|
|
/* 8075 */ "stnt1w\t\0"
|
|
/* 8083 */ "st1w\t\0"
|
|
/* 8089 */ "crc32w\t\0"
|
|
/* 8097 */ "ld2w\t\0"
|
|
/* 8103 */ "st2w\t\0"
|
|
/* 8109 */ "ld3w\t\0"
|
|
/* 8115 */ "st3w\t\0"
|
|
/* 8121 */ "ld4w\t\0"
|
|
/* 8127 */ "st4w\t\0"
|
|
/* 8133 */ "ssubw\t\0"
|
|
/* 8140 */ "usubw\t\0"
|
|
/* 8147 */ "crc32cw\t\0"
|
|
/* 8156 */ "sqdecw\t\0"
|
|
/* 8164 */ "uqdecw\t\0"
|
|
/* 8172 */ "sqincw\t\0"
|
|
/* 8180 */ "uqincw\t\0"
|
|
/* 8188 */ "saddw\t\0"
|
|
/* 8195 */ "uaddw\t\0"
|
|
/* 8202 */ "prfw\t\0"
|
|
/* 8208 */ "ld1row\t\0"
|
|
/* 8216 */ "ld1rqw\t\0"
|
|
/* 8224 */ "ld1rw\t\0"
|
|
/* 8231 */ "whilerw\t\0"
|
|
/* 8240 */ "ld1sw\t\0"
|
|
/* 8247 */ "ldff1sw\t\0"
|
|
/* 8256 */ "ldnf1sw\t\0"
|
|
/* 8265 */ "ldnt1sw\t\0"
|
|
/* 8274 */ "ldpsw\t\0"
|
|
/* 8281 */ "ld1rsw\t\0"
|
|
/* 8289 */ "ldrsw\t\0"
|
|
/* 8296 */ "ldtrsw\t\0"
|
|
/* 8304 */ "ldursw\t\0"
|
|
/* 8312 */ "ldapursw\t\0"
|
|
/* 8322 */ "cntw\t\0"
|
|
/* 8328 */ "sxtw\t\0"
|
|
/* 8334 */ "uxtw\t\0"
|
|
/* 8340 */ "revw\t\0"
|
|
/* 8346 */ "crc32x\t\0"
|
|
/* 8354 */ "frint32x\t\0"
|
|
/* 8364 */ "frint64x\t\0"
|
|
/* 8374 */ "bcax\t\0"
|
|
/* 8380 */ "famax\t\0"
|
|
/* 8387 */ "bfmax\t\0"
|
|
/* 8394 */ "ldsmax\t\0"
|
|
/* 8402 */ "ldumax\t\0"
|
|
/* 8410 */ "tbx\t\0"
|
|
/* 8415 */ "crc32cx\t\0"
|
|
/* 8424 */ "ldx\t\0"
|
|
/* 8429 */ "index\t\0"
|
|
/* 8436 */ "clrex\t\0"
|
|
/* 8443 */ "movprfx\t\0"
|
|
/* 8452 */ "at_as1elx\t\0"
|
|
/* 8463 */ "fmulx\t\0"
|
|
/* 8470 */ "frecpx\t\0"
|
|
/* 8478 */ "extrx\t\0"
|
|
/* 8485 */ "frintx\t\0"
|
|
/* 8493 */ "stx\t\0"
|
|
/* 8498 */ "fcvtx\t\0"
|
|
/* 8505 */ "ldy\t\0"
|
|
/* 8510 */ "sm4ekey\t\0"
|
|
/* 8519 */ "fcpy\t\0"
|
|
/* 8525 */ "extry\t\0"
|
|
/* 8532 */ "sty\t\0"
|
|
/* 8537 */ "frint32z\t\0"
|
|
/* 8547 */ "frint64z\t\0"
|
|
/* 8557 */ "braaz\t\0"
|
|
/* 8564 */ "blraaz\t\0"
|
|
/* 8572 */ "movaz\t\0"
|
|
/* 8579 */ "brabz\t\0"
|
|
/* 8586 */ "blrabz\t\0"
|
|
/* 8594 */ "cbz\t\0"
|
|
/* 8599 */ "tbz\t\0"
|
|
/* 8604 */ "ldz\t\0"
|
|
/* 8609 */ "clz\t\0"
|
|
/* 8614 */ "cbnz\t\0"
|
|
/* 8620 */ "tbnz\t\0"
|
|
/* 8626 */ "ctz\t\0"
|
|
/* 8631 */ "frintz\t\0"
|
|
/* 8639 */ "stz\t\0"
|
|
/* 8644 */ "movz\t\0"
|
|
/* 8650 */ ".tlsdesccall \0"
|
|
/* 8664 */ "zero\t{ \0"
|
|
/* 8672 */ "# XRay Function Patchable RET.\0"
|
|
/* 8703 */ "b.\0"
|
|
/* 8706 */ "bc.\0"
|
|
/* 8710 */ "# XRay Typed Event Log.\0"
|
|
/* 8734 */ "# XRay Custom Event Log.\0"
|
|
/* 8759 */ "# XRay Function Enter.\0"
|
|
/* 8782 */ "# XRay Tail Call Exit.\0"
|
|
/* 8805 */ "# XRay Function Exit.\0"
|
|
/* 8827 */ "hint\t#10\0"
|
|
/* 8836 */ "hint\t#30\0"
|
|
/* 8845 */ "hint\t#40\0"
|
|
/* 8854 */ "hint\t#31\0"
|
|
/* 8863 */ "hint\t#12\0"
|
|
/* 8872 */ "hint\t#14\0"
|
|
/* 8881 */ "hint\t#24\0"
|
|
/* 8890 */ "pacia171615\0"
|
|
/* 8902 */ "autia171615\0"
|
|
/* 8914 */ "pacib171615\0"
|
|
/* 8926 */ "autib171615\0"
|
|
/* 8938 */ "hint\t#25\0"
|
|
/* 8947 */ "hint\t#26\0"
|
|
/* 8956 */ "hint\t#7\0"
|
|
/* 8964 */ "hint\t#27\0"
|
|
/* 8973 */ "hint\t#8\0"
|
|
/* 8981 */ "hint\t#28\0"
|
|
/* 8990 */ "hint\t#29\0"
|
|
/* 8999 */ "hint\t#39\0"
|
|
/* 9008 */ "LIFETIME_END\0"
|
|
/* 9021 */ "PSEUDO_PROBE\0"
|
|
/* 9034 */ "BUNDLE\0"
|
|
/* 9041 */ "DBG_VALUE\0"
|
|
/* 9051 */ "DBG_INSTR_REF\0"
|
|
/* 9065 */ "DBG_PHI\0"
|
|
/* 9073 */ "DBG_LABEL\0"
|
|
/* 9083 */ "LIFETIME_START\0"
|
|
/* 9098 */ "DBG_VALUE_LIST\0"
|
|
/* 9113 */ "cpyfe\t[\0"
|
|
/* 9121 */ "setge\t[\0"
|
|
/* 9129 */ "sete\t[\0"
|
|
/* 9136 */ "cpye\t[\0"
|
|
/* 9143 */ "cpyfm\t[\0"
|
|
/* 9151 */ "setgm\t[\0"
|
|
/* 9159 */ "setm\t[\0"
|
|
/* 9166 */ "cpym\t[\0"
|
|
/* 9173 */ "cpyfen\t[\0"
|
|
/* 9182 */ "setgen\t[\0"
|
|
/* 9191 */ "seten\t[\0"
|
|
/* 9199 */ "cpyen\t[\0"
|
|
/* 9207 */ "cpyfmn\t[\0"
|
|
/* 9216 */ "setgmn\t[\0"
|
|
/* 9225 */ "setmn\t[\0"
|
|
/* 9233 */ "cpymn\t[\0"
|
|
/* 9241 */ "cpyfpn\t[\0"
|
|
/* 9250 */ "setgpn\t[\0"
|
|
/* 9259 */ "setpn\t[\0"
|
|
/* 9267 */ "cpypn\t[\0"
|
|
/* 9275 */ "cpyfern\t[\0"
|
|
/* 9285 */ "cpyern\t[\0"
|
|
/* 9294 */ "cpyfmrn\t[\0"
|
|
/* 9304 */ "cpymrn\t[\0"
|
|
/* 9313 */ "cpyfprn\t[\0"
|
|
/* 9323 */ "cpyprn\t[\0"
|
|
/* 9332 */ "cpyfetrn\t[\0"
|
|
/* 9343 */ "cpyetrn\t[\0"
|
|
/* 9353 */ "cpyfmtrn\t[\0"
|
|
/* 9364 */ "cpymtrn\t[\0"
|
|
/* 9374 */ "cpyfptrn\t[\0"
|
|
/* 9385 */ "cpyptrn\t[\0"
|
|
/* 9395 */ "cpyfertrn\t[\0"
|
|
/* 9407 */ "cpyertrn\t[\0"
|
|
/* 9418 */ "cpyfmrtrn\t[\0"
|
|
/* 9430 */ "cpymrtrn\t[\0"
|
|
/* 9441 */ "cpyfprtrn\t[\0"
|
|
/* 9453 */ "cpyprtrn\t[\0"
|
|
/* 9464 */ "cpyfewtrn\t[\0"
|
|
/* 9476 */ "cpyewtrn\t[\0"
|
|
/* 9487 */ "cpyfmwtrn\t[\0"
|
|
/* 9499 */ "cpymwtrn\t[\0"
|
|
/* 9510 */ "cpyfpwtrn\t[\0"
|
|
/* 9522 */ "cpypwtrn\t[\0"
|
|
/* 9533 */ "cpyfetn\t[\0"
|
|
/* 9543 */ "setgetn\t[\0"
|
|
/* 9553 */ "setetn\t[\0"
|
|
/* 9562 */ "cpyetn\t[\0"
|
|
/* 9571 */ "cpyfmtn\t[\0"
|
|
/* 9581 */ "setgmtn\t[\0"
|
|
/* 9591 */ "setmtn\t[\0"
|
|
/* 9600 */ "cpymtn\t[\0"
|
|
/* 9609 */ "cpyfptn\t[\0"
|
|
/* 9619 */ "setgptn\t[\0"
|
|
/* 9629 */ "setptn\t[\0"
|
|
/* 9638 */ "cpyptn\t[\0"
|
|
/* 9647 */ "cpyfertn\t[\0"
|
|
/* 9658 */ "cpyertn\t[\0"
|
|
/* 9668 */ "cpyfmrtn\t[\0"
|
|
/* 9679 */ "cpymrtn\t[\0"
|
|
/* 9689 */ "cpyfprtn\t[\0"
|
|
/* 9700 */ "cpyprtn\t[\0"
|
|
/* 9710 */ "cpyfewtn\t[\0"
|
|
/* 9721 */ "cpyewtn\t[\0"
|
|
/* 9731 */ "cpyfmwtn\t[\0"
|
|
/* 9742 */ "cpymwtn\t[\0"
|
|
/* 9752 */ "cpyfpwtn\t[\0"
|
|
/* 9763 */ "cpypwtn\t[\0"
|
|
/* 9773 */ "cpyfewn\t[\0"
|
|
/* 9783 */ "cpyewn\t[\0"
|
|
/* 9792 */ "cpyfmwn\t[\0"
|
|
/* 9802 */ "cpymwn\t[\0"
|
|
/* 9811 */ "cpyfpwn\t[\0"
|
|
/* 9821 */ "cpypwn\t[\0"
|
|
/* 9830 */ "cpyfetwn\t[\0"
|
|
/* 9841 */ "cpyetwn\t[\0"
|
|
/* 9851 */ "cpyfmtwn\t[\0"
|
|
/* 9862 */ "cpymtwn\t[\0"
|
|
/* 9872 */ "cpyfptwn\t[\0"
|
|
/* 9883 */ "cpyptwn\t[\0"
|
|
/* 9893 */ "cpyfertwn\t[\0"
|
|
/* 9905 */ "cpyertwn\t[\0"
|
|
/* 9916 */ "cpyfmrtwn\t[\0"
|
|
/* 9928 */ "cpymrtwn\t[\0"
|
|
/* 9939 */ "cpyfprtwn\t[\0"
|
|
/* 9951 */ "cpyprtwn\t[\0"
|
|
/* 9962 */ "cpyfewtwn\t[\0"
|
|
/* 9974 */ "cpyewtwn\t[\0"
|
|
/* 9985 */ "cpyfmwtwn\t[\0"
|
|
/* 9997 */ "cpymwtwn\t[\0"
|
|
/* 10008 */ "cpyfpwtwn\t[\0"
|
|
/* 10020 */ "cpypwtwn\t[\0"
|
|
/* 10031 */ "cpyfp\t[\0"
|
|
/* 10039 */ "setgp\t[\0"
|
|
/* 10047 */ "setp\t[\0"
|
|
/* 10054 */ "cpyp\t[\0"
|
|
/* 10061 */ "cpyfet\t[\0"
|
|
/* 10070 */ "setget\t[\0"
|
|
/* 10079 */ "setet\t[\0"
|
|
/* 10087 */ "cpyet\t[\0"
|
|
/* 10095 */ "cpyfmt\t[\0"
|
|
/* 10104 */ "setgmt\t[\0"
|
|
/* 10113 */ "setmt\t[\0"
|
|
/* 10121 */ "cpymt\t[\0"
|
|
/* 10129 */ "cpyfpt\t[\0"
|
|
/* 10138 */ "setgpt\t[\0"
|
|
/* 10147 */ "setpt\t[\0"
|
|
/* 10155 */ "cpypt\t[\0"
|
|
/* 10163 */ "cpyfert\t[\0"
|
|
/* 10173 */ "cpyert\t[\0"
|
|
/* 10182 */ "cpyfmrt\t[\0"
|
|
/* 10192 */ "cpymrt\t[\0"
|
|
/* 10201 */ "cpyfprt\t[\0"
|
|
/* 10211 */ "cpyprt\t[\0"
|
|
/* 10220 */ "cpyfewt\t[\0"
|
|
/* 10230 */ "cpyewt\t[\0"
|
|
/* 10239 */ "cpyfmwt\t[\0"
|
|
/* 10249 */ "cpymwt\t[\0"
|
|
/* 10258 */ "cpyfpwt\t[\0"
|
|
/* 10268 */ "cpypwt\t[\0"
|
|
/* 10277 */ "eretaa\0"
|
|
/* 10284 */ "eretab\0"
|
|
/* 10291 */ "sb\0"
|
|
/* 10294 */ "pacnbiasppc\0"
|
|
/* 10306 */ "paciasppc\0"
|
|
/* 10316 */ "pacnbibsppc\0"
|
|
/* 10328 */ "pacibsppc\0"
|
|
/* 10338 */ "xaflag\0"
|
|
/* 10345 */ "axflag\0"
|
|
/* 10352 */ "brb\tinj\0"
|
|
/* 10360 */ "# FEntry call\0"
|
|
/* 10374 */ "brb\tiall\0"
|
|
/* 10383 */ "setffr\0"
|
|
/* 10390 */ "clr\0"
|
|
/* 10394 */ "drps\0"
|
|
/* 10399 */ "eret\0"
|
|
/* 10404 */ "set\0"
|
|
/* 10408 */ "tcommit\0"
|
|
/* 10416 */ "gexit\0"
|
|
/* 10422 */ "cfinv\0"
|
|
/* 10428 */ "gcspopcx\0"
|
|
/* 10437 */ "gcspushx\0"
|
|
/* 10446 */ "gcspopx\0"
|
|
/* 10454 */ "ld1b\t{\0"
|
|
/* 10461 */ "st1b\t{\0"
|
|
/* 10468 */ "ld1d\t{\0"
|
|
/* 10475 */ "st1d\t{\0"
|
|
/* 10482 */ "ld1h\t{\0"
|
|
/* 10489 */ "st1h\t{\0"
|
|
/* 10496 */ "ld1q\t{\0"
|
|
/* 10503 */ "st1q\t{\0"
|
|
/* 10510 */ "ld1w\t{\0"
|
|
/* 10517 */ "st1w\t{\0"
|
|
};
|
|
#endif // CAPSTONE_DIET
|
|
|
|
static const uint32_t OpInfo0[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
9042U, // DBG_VALUE
|
|
9099U, // DBG_VALUE_LIST
|
|
9052U, // DBG_INSTR_REF
|
|
9066U, // DBG_PHI
|
|
9074U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
9035U, // BUNDLE
|
|
9084U, // LIFETIME_START
|
|
9009U, // LIFETIME_END
|
|
9022U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
10361U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
8760U, // PATCHABLE_FUNCTION_ENTER
|
|
8673U, // PATCHABLE_RET
|
|
8806U, // PATCHABLE_FUNCTION_EXIT
|
|
8783U, // PATCHABLE_TAIL_CALL
|
|
8735U, // PATCHABLE_EVENT_CALL
|
|
8711U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ABS_ZPmZ_B_UNDEF
|
|
0U, // ABS_ZPmZ_D_UNDEF
|
|
0U, // ABS_ZPmZ_H_UNDEF
|
|
0U, // ABS_ZPmZ_S_UNDEF
|
|
0U, // ADDHA_MPPZ_D_PSEUDO_D
|
|
0U, // ADDHA_MPPZ_S_PSEUDO_S
|
|
0U, // ADDSWrr
|
|
0U, // ADDSXrr
|
|
0U, // ADDVA_MPPZ_D_PSEUDO_D
|
|
0U, // ADDVA_MPPZ_S_PSEUDO_S
|
|
0U, // ADDWrr
|
|
0U, // ADDXrr
|
|
0U, // ADD_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // ADD_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // ADD_VG2_M2ZZ_D_PSEUDO
|
|
0U, // ADD_VG2_M2ZZ_S_PSEUDO
|
|
0U, // ADD_VG2_M2Z_D_PSEUDO
|
|
0U, // ADD_VG2_M2Z_S_PSEUDO
|
|
0U, // ADD_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // ADD_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // ADD_VG4_M4ZZ_D_PSEUDO
|
|
0U, // ADD_VG4_M4ZZ_S_PSEUDO
|
|
0U, // ADD_VG4_M4Z_D_PSEUDO
|
|
0U, // ADD_VG4_M4Z_S_PSEUDO
|
|
0U, // ADD_ZPZZ_B_ZERO
|
|
0U, // ADD_ZPZZ_D_ZERO
|
|
0U, // ADD_ZPZZ_H_ZERO
|
|
0U, // ADD_ZPZZ_S_ZERO
|
|
0U, // ADDlowTLS
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // AESIMCrrTied
|
|
0U, // AESMCrrTied
|
|
0U, // ANDSWrr
|
|
0U, // ANDSXrr
|
|
0U, // ANDWrr
|
|
0U, // ANDXrr
|
|
0U, // AND_ZPZZ_B_ZERO
|
|
0U, // AND_ZPZZ_D_ZERO
|
|
0U, // AND_ZPZZ_H_ZERO
|
|
0U, // AND_ZPZZ_S_ZERO
|
|
0U, // ASRD_ZPZI_B_ZERO
|
|
0U, // ASRD_ZPZI_D_ZERO
|
|
0U, // ASRD_ZPZI_H_ZERO
|
|
0U, // ASRD_ZPZI_S_ZERO
|
|
0U, // ASR_ZPZI_B_UNDEF
|
|
0U, // ASR_ZPZI_B_ZERO
|
|
0U, // ASR_ZPZI_D_UNDEF
|
|
0U, // ASR_ZPZI_D_ZERO
|
|
0U, // ASR_ZPZI_H_UNDEF
|
|
0U, // ASR_ZPZI_H_ZERO
|
|
0U, // ASR_ZPZI_S_UNDEF
|
|
0U, // ASR_ZPZI_S_ZERO
|
|
0U, // ASR_ZPZZ_B_UNDEF
|
|
0U, // ASR_ZPZZ_B_ZERO
|
|
0U, // ASR_ZPZZ_D_UNDEF
|
|
0U, // ASR_ZPZZ_D_ZERO
|
|
0U, // ASR_ZPZZ_H_UNDEF
|
|
0U, // ASR_ZPZZ_H_ZERO
|
|
0U, // ASR_ZPZZ_S_UNDEF
|
|
0U, // ASR_ZPZZ_S_ZERO
|
|
0U, // BFADD_VG2_M2Z_H_PSEUDO
|
|
0U, // BFADD_VG4_M4Z_H_PSEUDO
|
|
0U, // BFADD_ZPZZ_UNDEF
|
|
0U, // BFADD_ZPZZ_ZERO
|
|
0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // BFMAXNM_ZPZZ_UNDEF
|
|
0U, // BFMAXNM_ZPZZ_ZERO
|
|
0U, // BFMAX_ZPZZ_UNDEF
|
|
0U, // BFMAX_ZPZZ_ZERO
|
|
0U, // BFMINNM_ZPZZ_UNDEF
|
|
0U, // BFMINNM_ZPZZ_ZERO
|
|
0U, // BFMIN_ZPZZ_UNDEF
|
|
0U, // BFMIN_ZPZZ_ZERO
|
|
0U, // BFMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // BFMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // BFMLA_VG2_M2Z2Z_PSEUDO
|
|
0U, // BFMLA_VG4_M4Z4Z_PSEUDO
|
|
0U, // BFMLA_ZPZZZ_UNDEF
|
|
0U, // BFMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // BFMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // BFMLS_VG2_M2Z2Z_PSEUDO
|
|
0U, // BFMLS_VG4_M4Z4Z_PSEUDO
|
|
0U, // BFMLS_ZPZZZ_UNDEF
|
|
0U, // BFMOPA_MPPZZ_PSEUDO
|
|
0U, // BFMOPS_MPPZZ_PSEUDO
|
|
0U, // BFMUL_ZPZZ_UNDEF
|
|
0U, // BFMUL_ZPZZ_ZERO
|
|
0U, // BFSUB_VG2_M2Z_H_PSEUDO
|
|
0U, // BFSUB_VG4_M4Z_H_PSEUDO
|
|
0U, // BFSUB_ZPZZ_UNDEF
|
|
0U, // BFSUB_ZPZZ_ZERO
|
|
0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BICSWrr
|
|
0U, // BICSXrr
|
|
0U, // BICWrr
|
|
0U, // BICXrr
|
|
0U, // BIC_ZPZZ_B_ZERO
|
|
0U, // BIC_ZPZZ_D_ZERO
|
|
0U, // BIC_ZPZZ_H_ZERO
|
|
0U, // BIC_ZPZZ_S_ZERO
|
|
0U, // BLRNoIP
|
|
0U, // BLR_BTI
|
|
0U, // BLR_RVMARKER
|
|
0U, // BLR_X16
|
|
0U, // BMOPA_MPPZZ_S_PSEUDO
|
|
0U, // BMOPS_MPPZZ_S_PSEUDO
|
|
0U, // BSPv16i8
|
|
0U, // BSPv8i8
|
|
0U, // CATCHRET
|
|
0U, // CLEANUPRET
|
|
0U, // CLS_ZPmZ_B_UNDEF
|
|
0U, // CLS_ZPmZ_D_UNDEF
|
|
0U, // CLS_ZPmZ_H_UNDEF
|
|
0U, // CLS_ZPmZ_S_UNDEF
|
|
0U, // CLZ_ZPmZ_B_UNDEF
|
|
0U, // CLZ_ZPmZ_D_UNDEF
|
|
0U, // CLZ_ZPmZ_H_UNDEF
|
|
0U, // CLZ_ZPmZ_S_UNDEF
|
|
0U, // CMP_SWAP_128
|
|
0U, // CMP_SWAP_128_ACQUIRE
|
|
0U, // CMP_SWAP_128_MONOTONIC
|
|
0U, // CMP_SWAP_128_RELEASE
|
|
0U, // CMP_SWAP_16
|
|
0U, // CMP_SWAP_32
|
|
0U, // CMP_SWAP_64
|
|
0U, // CMP_SWAP_8
|
|
0U, // CNOT_ZPmZ_B_UNDEF
|
|
0U, // CNOT_ZPmZ_D_UNDEF
|
|
0U, // CNOT_ZPmZ_H_UNDEF
|
|
0U, // CNOT_ZPmZ_S_UNDEF
|
|
0U, // CNT_ZPmZ_B_UNDEF
|
|
0U, // CNT_ZPmZ_D_UNDEF
|
|
0U, // CNT_ZPmZ_H_UNDEF
|
|
0U, // CNT_ZPmZ_S_UNDEF
|
|
0U, // COALESCER_BARRIER_FPR128
|
|
0U, // COALESCER_BARRIER_FPR16
|
|
0U, // COALESCER_BARRIER_FPR32
|
|
0U, // COALESCER_BARRIER_FPR64
|
|
0U, // EMITBKEY
|
|
0U, // EMITMTETAGGED
|
|
0U, // EONWrr
|
|
0U, // EONXrr
|
|
0U, // EORWrr
|
|
0U, // EORXrr
|
|
0U, // EOR_ZPZZ_B_ZERO
|
|
0U, // EOR_ZPZZ_D_ZERO
|
|
0U, // EOR_ZPZZ_H_ZERO
|
|
0U, // EOR_ZPZZ_S_ZERO
|
|
0U, // F128CSEL
|
|
0U, // FABD_ZPZZ_D_UNDEF
|
|
0U, // FABD_ZPZZ_D_ZERO
|
|
0U, // FABD_ZPZZ_H_UNDEF
|
|
0U, // FABD_ZPZZ_H_ZERO
|
|
0U, // FABD_ZPZZ_S_UNDEF
|
|
0U, // FABD_ZPZZ_S_ZERO
|
|
0U, // FABS_ZPmZ_D_UNDEF
|
|
0U, // FABS_ZPmZ_H_UNDEF
|
|
0U, // FABS_ZPmZ_S_UNDEF
|
|
0U, // FADD_VG2_M2Z_D_PSEUDO
|
|
0U, // FADD_VG2_M2Z_H_PSEUDO
|
|
0U, // FADD_VG2_M2Z_S_PSEUDO
|
|
0U, // FADD_VG4_M4Z_D_PSEUDO
|
|
0U, // FADD_VG4_M4Z_H_PSEUDO
|
|
0U, // FADD_VG4_M4Z_S_PSEUDO
|
|
0U, // FADD_ZPZI_D_UNDEF
|
|
0U, // FADD_ZPZI_D_ZERO
|
|
0U, // FADD_ZPZI_H_UNDEF
|
|
0U, // FADD_ZPZI_H_ZERO
|
|
0U, // FADD_ZPZI_S_UNDEF
|
|
0U, // FADD_ZPZI_S_ZERO
|
|
0U, // FADD_ZPZZ_D_UNDEF
|
|
0U, // FADD_ZPZZ_D_ZERO
|
|
0U, // FADD_ZPZZ_H_UNDEF
|
|
0U, // FADD_ZPZZ_H_ZERO
|
|
0U, // FADD_ZPZZ_S_UNDEF
|
|
0U, // FADD_ZPZZ_S_ZERO
|
|
0U, // FCVTZS_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoS_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoH_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_StoD_UNDEF
|
|
0U, // FCVT_ZPmZ_StoH_UNDEF
|
|
0U, // FDIVR_ZPZZ_D_ZERO
|
|
0U, // FDIVR_ZPZZ_H_ZERO
|
|
0U, // FDIVR_ZPZZ_S_ZERO
|
|
0U, // FDIV_ZPZZ_D_UNDEF
|
|
0U, // FDIV_ZPZZ_D_ZERO
|
|
0U, // FDIV_ZPZZ_H_UNDEF
|
|
0U, // FDIV_ZPZZ_H_ZERO
|
|
0U, // FDIV_ZPZZ_S_UNDEF
|
|
0U, // FDIV_ZPZZ_S_ZERO
|
|
0U, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO
|
|
0U, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO
|
|
0U, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // FLOGB_ZPZZ_D_ZERO
|
|
0U, // FLOGB_ZPZZ_H_ZERO
|
|
0U, // FLOGB_ZPZZ_S_ZERO
|
|
0U, // FMAXNM_ZPZI_D_UNDEF
|
|
0U, // FMAXNM_ZPZI_D_ZERO
|
|
0U, // FMAXNM_ZPZI_H_UNDEF
|
|
0U, // FMAXNM_ZPZI_H_ZERO
|
|
0U, // FMAXNM_ZPZI_S_UNDEF
|
|
0U, // FMAXNM_ZPZI_S_ZERO
|
|
0U, // FMAXNM_ZPZZ_D_UNDEF
|
|
0U, // FMAXNM_ZPZZ_D_ZERO
|
|
0U, // FMAXNM_ZPZZ_H_UNDEF
|
|
0U, // FMAXNM_ZPZZ_H_ZERO
|
|
0U, // FMAXNM_ZPZZ_S_UNDEF
|
|
0U, // FMAXNM_ZPZZ_S_ZERO
|
|
0U, // FMAX_ZPZI_D_UNDEF
|
|
0U, // FMAX_ZPZI_D_ZERO
|
|
0U, // FMAX_ZPZI_H_UNDEF
|
|
0U, // FMAX_ZPZI_H_ZERO
|
|
0U, // FMAX_ZPZI_S_UNDEF
|
|
0U, // FMAX_ZPZI_S_ZERO
|
|
0U, // FMAX_ZPZZ_D_UNDEF
|
|
0U, // FMAX_ZPZZ_D_ZERO
|
|
0U, // FMAX_ZPZZ_H_UNDEF
|
|
0U, // FMAX_ZPZZ_H_ZERO
|
|
0U, // FMAX_ZPZZ_S_UNDEF
|
|
0U, // FMAX_ZPZZ_S_ZERO
|
|
0U, // FMINNM_ZPZI_D_UNDEF
|
|
0U, // FMINNM_ZPZI_D_ZERO
|
|
0U, // FMINNM_ZPZI_H_UNDEF
|
|
0U, // FMINNM_ZPZI_H_ZERO
|
|
0U, // FMINNM_ZPZI_S_UNDEF
|
|
0U, // FMINNM_ZPZI_S_ZERO
|
|
0U, // FMINNM_ZPZZ_D_UNDEF
|
|
0U, // FMINNM_ZPZZ_D_ZERO
|
|
0U, // FMINNM_ZPZZ_H_UNDEF
|
|
0U, // FMINNM_ZPZZ_H_ZERO
|
|
0U, // FMINNM_ZPZZ_S_UNDEF
|
|
0U, // FMINNM_ZPZZ_S_ZERO
|
|
0U, // FMIN_ZPZI_D_UNDEF
|
|
0U, // FMIN_ZPZI_D_ZERO
|
|
0U, // FMIN_ZPZI_H_UNDEF
|
|
0U, // FMIN_ZPZI_H_ZERO
|
|
0U, // FMIN_ZPZI_S_UNDEF
|
|
0U, // FMIN_ZPZI_S_ZERO
|
|
0U, // FMIN_ZPZZ_D_UNDEF
|
|
0U, // FMIN_ZPZZ_D_ZERO
|
|
0U, // FMIN_ZPZZ_H_UNDEF
|
|
0U, // FMIN_ZPZZ_H_ZERO
|
|
0U, // FMIN_ZPZZ_S_UNDEF
|
|
0U, // FMIN_ZPZZ_S_ZERO
|
|
0U, // FMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // FMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // FMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // FMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO
|
|
0U, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO
|
|
0U, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO
|
|
0U, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO
|
|
0U, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // FMLA_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // FMLA_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // FMLA_VG2_M2Z4Z_H_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZI_D_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZI_S_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZ_D_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZ_S_PSEUDO
|
|
0U, // FMLA_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // FMLA_VG4_M4Z4Z_H_PSEUDO
|
|
0U, // FMLA_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZI_D_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZI_S_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZ_D_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZ_S_PSEUDO
|
|
0U, // FMLA_ZPZZZ_D_UNDEF
|
|
0U, // FMLA_ZPZZZ_H_UNDEF
|
|
0U, // FMLA_ZPZZZ_S_UNDEF
|
|
0U, // FMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // FMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // FMLS_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // FMLS_VG2_M2Z2Z_H_PSEUDO
|
|
0U, // FMLS_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZI_D_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZI_S_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZ_D_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZ_S_PSEUDO
|
|
0U, // FMLS_VG4_M4Z2Z_H_PSEUDO
|
|
0U, // FMLS_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // FMLS_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZI_D_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZI_S_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZ_D_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZ_S_PSEUDO
|
|
0U, // FMLS_ZPZZZ_D_UNDEF
|
|
0U, // FMLS_ZPZZZ_H_UNDEF
|
|
0U, // FMLS_ZPZZZ_S_UNDEF
|
|
0U, // FMOPAL_MPPZZ_PSEUDO
|
|
0U, // FMOPA_MPPZZ_BtoS_PSEUDO
|
|
0U, // FMOPA_MPPZZ_D_PSEUDO
|
|
0U, // FMOPA_MPPZZ_S_PSEUDO
|
|
0U, // FMOPSL_MPPZZ_PSEUDO
|
|
0U, // FMOPS_MPPZZ_D_PSEUDO
|
|
0U, // FMOPS_MPPZZ_S_PSEUDO
|
|
0U, // FMOVD0
|
|
0U, // FMOVH0
|
|
0U, // FMOVS0
|
|
0U, // FMULX_ZPZZ_D_UNDEF
|
|
0U, // FMULX_ZPZZ_D_ZERO
|
|
0U, // FMULX_ZPZZ_H_UNDEF
|
|
0U, // FMULX_ZPZZ_H_ZERO
|
|
0U, // FMULX_ZPZZ_S_UNDEF
|
|
0U, // FMULX_ZPZZ_S_ZERO
|
|
0U, // FMUL_ZPZI_D_UNDEF
|
|
0U, // FMUL_ZPZI_D_ZERO
|
|
0U, // FMUL_ZPZI_H_UNDEF
|
|
0U, // FMUL_ZPZI_H_ZERO
|
|
0U, // FMUL_ZPZI_S_UNDEF
|
|
0U, // FMUL_ZPZI_S_ZERO
|
|
0U, // FMUL_ZPZZ_D_UNDEF
|
|
0U, // FMUL_ZPZZ_D_ZERO
|
|
0U, // FMUL_ZPZZ_H_UNDEF
|
|
0U, // FMUL_ZPZZ_H_ZERO
|
|
0U, // FMUL_ZPZZ_S_UNDEF
|
|
0U, // FMUL_ZPZZ_S_ZERO
|
|
0U, // FNEG_ZPmZ_D_UNDEF
|
|
0U, // FNEG_ZPmZ_H_UNDEF
|
|
0U, // FNEG_ZPmZ_S_UNDEF
|
|
0U, // FNMLA_ZPZZZ_D_UNDEF
|
|
0U, // FNMLA_ZPZZZ_H_UNDEF
|
|
0U, // FNMLA_ZPZZZ_S_UNDEF
|
|
0U, // FNMLS_ZPZZZ_D_UNDEF
|
|
0U, // FNMLS_ZPZZZ_H_UNDEF
|
|
0U, // FNMLS_ZPZZZ_S_UNDEF
|
|
0U, // FRECPX_ZPmZ_D_UNDEF
|
|
0U, // FRECPX_ZPmZ_H_UNDEF
|
|
0U, // FRECPX_ZPmZ_S_UNDEF
|
|
0U, // FRINTA_ZPmZ_D_UNDEF
|
|
0U, // FRINTA_ZPmZ_H_UNDEF
|
|
0U, // FRINTA_ZPmZ_S_UNDEF
|
|
0U, // FRINTI_ZPmZ_D_UNDEF
|
|
0U, // FRINTI_ZPmZ_H_UNDEF
|
|
0U, // FRINTI_ZPmZ_S_UNDEF
|
|
0U, // FRINTM_ZPmZ_D_UNDEF
|
|
0U, // FRINTM_ZPmZ_H_UNDEF
|
|
0U, // FRINTM_ZPmZ_S_UNDEF
|
|
0U, // FRINTN_ZPmZ_D_UNDEF
|
|
0U, // FRINTN_ZPmZ_H_UNDEF
|
|
0U, // FRINTN_ZPmZ_S_UNDEF
|
|
0U, // FRINTP_ZPmZ_D_UNDEF
|
|
0U, // FRINTP_ZPmZ_H_UNDEF
|
|
0U, // FRINTP_ZPmZ_S_UNDEF
|
|
0U, // FRINTX_ZPmZ_D_UNDEF
|
|
0U, // FRINTX_ZPmZ_H_UNDEF
|
|
0U, // FRINTX_ZPmZ_S_UNDEF
|
|
0U, // FRINTZ_ZPmZ_D_UNDEF
|
|
0U, // FRINTZ_ZPmZ_H_UNDEF
|
|
0U, // FRINTZ_ZPmZ_S_UNDEF
|
|
0U, // FSQRT_ZPmZ_D_UNDEF
|
|
0U, // FSQRT_ZPmZ_H_UNDEF
|
|
0U, // FSQRT_ZPmZ_S_UNDEF
|
|
0U, // FSUBR_ZPZI_D_UNDEF
|
|
0U, // FSUBR_ZPZI_D_ZERO
|
|
0U, // FSUBR_ZPZI_H_UNDEF
|
|
0U, // FSUBR_ZPZI_H_ZERO
|
|
0U, // FSUBR_ZPZI_S_UNDEF
|
|
0U, // FSUBR_ZPZI_S_ZERO
|
|
0U, // FSUBR_ZPZZ_D_ZERO
|
|
0U, // FSUBR_ZPZZ_H_ZERO
|
|
0U, // FSUBR_ZPZZ_S_ZERO
|
|
0U, // FSUB_VG2_M2Z_D_PSEUDO
|
|
0U, // FSUB_VG2_M2Z_H_PSEUDO
|
|
0U, // FSUB_VG2_M2Z_S_PSEUDO
|
|
0U, // FSUB_VG4_M4Z_D_PSEUDO
|
|
0U, // FSUB_VG4_M4Z_H_PSEUDO
|
|
0U, // FSUB_VG4_M4Z_S_PSEUDO
|
|
0U, // FSUB_ZPZI_D_UNDEF
|
|
0U, // FSUB_ZPZI_D_ZERO
|
|
0U, // FSUB_ZPZI_H_UNDEF
|
|
0U, // FSUB_ZPZI_H_ZERO
|
|
0U, // FSUB_ZPZI_S_UNDEF
|
|
0U, // FSUB_ZPZI_S_ZERO
|
|
0U, // FSUB_ZPZZ_D_UNDEF
|
|
0U, // FSUB_ZPZZ_D_ZERO
|
|
0U, // FSUB_ZPZZ_H_UNDEF
|
|
0U, // FSUB_ZPZZ_H_ZERO
|
|
0U, // FSUB_ZPZZ_S_UNDEF
|
|
0U, // FSUB_ZPZZ_S_ZERO
|
|
0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // GLD1B_D
|
|
0U, // GLD1B_D_IMM
|
|
0U, // GLD1B_D_SXTW
|
|
0U, // GLD1B_D_UXTW
|
|
0U, // GLD1B_S_IMM
|
|
0U, // GLD1B_S_SXTW
|
|
0U, // GLD1B_S_UXTW
|
|
0U, // GLD1D
|
|
0U, // GLD1D_IMM
|
|
0U, // GLD1D_SCALED
|
|
0U, // GLD1D_SXTW
|
|
0U, // GLD1D_SXTW_SCALED
|
|
0U, // GLD1D_UXTW
|
|
0U, // GLD1D_UXTW_SCALED
|
|
0U, // GLD1H_D
|
|
0U, // GLD1H_D_IMM
|
|
0U, // GLD1H_D_SCALED
|
|
0U, // GLD1H_D_SXTW
|
|
0U, // GLD1H_D_SXTW_SCALED
|
|
0U, // GLD1H_D_UXTW
|
|
0U, // GLD1H_D_UXTW_SCALED
|
|
0U, // GLD1H_S_IMM
|
|
0U, // GLD1H_S_SXTW
|
|
0U, // GLD1H_S_SXTW_SCALED
|
|
0U, // GLD1H_S_UXTW
|
|
0U, // GLD1H_S_UXTW_SCALED
|
|
0U, // GLD1SB_D
|
|
0U, // GLD1SB_D_IMM
|
|
0U, // GLD1SB_D_SXTW
|
|
0U, // GLD1SB_D_UXTW
|
|
0U, // GLD1SB_S_IMM
|
|
0U, // GLD1SB_S_SXTW
|
|
0U, // GLD1SB_S_UXTW
|
|
0U, // GLD1SH_D
|
|
0U, // GLD1SH_D_IMM
|
|
0U, // GLD1SH_D_SCALED
|
|
0U, // GLD1SH_D_SXTW
|
|
0U, // GLD1SH_D_SXTW_SCALED
|
|
0U, // GLD1SH_D_UXTW
|
|
0U, // GLD1SH_D_UXTW_SCALED
|
|
0U, // GLD1SH_S_IMM
|
|
0U, // GLD1SH_S_SXTW
|
|
0U, // GLD1SH_S_SXTW_SCALED
|
|
0U, // GLD1SH_S_UXTW
|
|
0U, // GLD1SH_S_UXTW_SCALED
|
|
0U, // GLD1SW_D
|
|
0U, // GLD1SW_D_IMM
|
|
0U, // GLD1SW_D_SCALED
|
|
0U, // GLD1SW_D_SXTW
|
|
0U, // GLD1SW_D_SXTW_SCALED
|
|
0U, // GLD1SW_D_UXTW
|
|
0U, // GLD1SW_D_UXTW_SCALED
|
|
0U, // GLD1W_D
|
|
0U, // GLD1W_D_IMM
|
|
0U, // GLD1W_D_SCALED
|
|
0U, // GLD1W_D_SXTW
|
|
0U, // GLD1W_D_SXTW_SCALED
|
|
0U, // GLD1W_D_UXTW
|
|
0U, // GLD1W_D_UXTW_SCALED
|
|
0U, // GLD1W_IMM
|
|
0U, // GLD1W_SXTW
|
|
0U, // GLD1W_SXTW_SCALED
|
|
0U, // GLD1W_UXTW
|
|
0U, // GLD1W_UXTW_SCALED
|
|
0U, // GLDFF1B_D
|
|
0U, // GLDFF1B_D_IMM
|
|
0U, // GLDFF1B_D_SXTW
|
|
0U, // GLDFF1B_D_UXTW
|
|
0U, // GLDFF1B_S_IMM
|
|
0U, // GLDFF1B_S_SXTW
|
|
0U, // GLDFF1B_S_UXTW
|
|
0U, // GLDFF1D
|
|
0U, // GLDFF1D_IMM
|
|
0U, // GLDFF1D_SCALED
|
|
0U, // GLDFF1D_SXTW
|
|
0U, // GLDFF1D_SXTW_SCALED
|
|
0U, // GLDFF1D_UXTW
|
|
0U, // GLDFF1D_UXTW_SCALED
|
|
0U, // GLDFF1H_D
|
|
0U, // GLDFF1H_D_IMM
|
|
0U, // GLDFF1H_D_SCALED
|
|
0U, // GLDFF1H_D_SXTW
|
|
0U, // GLDFF1H_D_SXTW_SCALED
|
|
0U, // GLDFF1H_D_UXTW
|
|
0U, // GLDFF1H_D_UXTW_SCALED
|
|
0U, // GLDFF1H_S_IMM
|
|
0U, // GLDFF1H_S_SXTW
|
|
0U, // GLDFF1H_S_SXTW_SCALED
|
|
0U, // GLDFF1H_S_UXTW
|
|
0U, // GLDFF1H_S_UXTW_SCALED
|
|
0U, // GLDFF1SB_D
|
|
0U, // GLDFF1SB_D_IMM
|
|
0U, // GLDFF1SB_D_SXTW
|
|
0U, // GLDFF1SB_D_UXTW
|
|
0U, // GLDFF1SB_S_IMM
|
|
0U, // GLDFF1SB_S_SXTW
|
|
0U, // GLDFF1SB_S_UXTW
|
|
0U, // GLDFF1SH_D
|
|
0U, // GLDFF1SH_D_IMM
|
|
0U, // GLDFF1SH_D_SCALED
|
|
0U, // GLDFF1SH_D_SXTW
|
|
0U, // GLDFF1SH_D_SXTW_SCALED
|
|
0U, // GLDFF1SH_D_UXTW
|
|
0U, // GLDFF1SH_D_UXTW_SCALED
|
|
0U, // GLDFF1SH_S_IMM
|
|
0U, // GLDFF1SH_S_SXTW
|
|
0U, // GLDFF1SH_S_SXTW_SCALED
|
|
0U, // GLDFF1SH_S_UXTW
|
|
0U, // GLDFF1SH_S_UXTW_SCALED
|
|
0U, // GLDFF1SW_D
|
|
0U, // GLDFF1SW_D_IMM
|
|
0U, // GLDFF1SW_D_SCALED
|
|
0U, // GLDFF1SW_D_SXTW
|
|
0U, // GLDFF1SW_D_SXTW_SCALED
|
|
0U, // GLDFF1SW_D_UXTW
|
|
0U, // GLDFF1SW_D_UXTW_SCALED
|
|
0U, // GLDFF1W_D
|
|
0U, // GLDFF1W_D_IMM
|
|
0U, // GLDFF1W_D_SCALED
|
|
0U, // GLDFF1W_D_SXTW
|
|
0U, // GLDFF1W_D_SXTW_SCALED
|
|
0U, // GLDFF1W_D_UXTW
|
|
0U, // GLDFF1W_D_UXTW_SCALED
|
|
0U, // GLDFF1W_IMM
|
|
0U, // GLDFF1W_SXTW
|
|
0U, // GLDFF1W_SXTW_SCALED
|
|
0U, // GLDFF1W_UXTW
|
|
0U, // GLDFF1W_UXTW_SCALED
|
|
0U, // G_AARCH64_PREFETCH
|
|
0U, // G_ADD_LOW
|
|
0U, // G_BSP
|
|
0U, // G_DUP
|
|
0U, // G_DUPLANE16
|
|
0U, // G_DUPLANE32
|
|
0U, // G_DUPLANE64
|
|
0U, // G_DUPLANE8
|
|
0U, // G_EXT
|
|
0U, // G_FCMEQ
|
|
0U, // G_FCMEQZ
|
|
0U, // G_FCMGE
|
|
0U, // G_FCMGEZ
|
|
0U, // G_FCMGT
|
|
0U, // G_FCMGTZ
|
|
0U, // G_FCMLEZ
|
|
0U, // G_FCMLTZ
|
|
0U, // G_REV16
|
|
0U, // G_REV32
|
|
0U, // G_REV64
|
|
0U, // G_SADDLP
|
|
0U, // G_SADDLV
|
|
0U, // G_SDOT
|
|
0U, // G_SITOF
|
|
0U, // G_SMULL
|
|
0U, // G_TRN1
|
|
0U, // G_TRN2
|
|
0U, // G_UADDLP
|
|
0U, // G_UADDLV
|
|
0U, // G_UDOT
|
|
0U, // G_UITOF
|
|
0U, // G_UMULL
|
|
0U, // G_UZP1
|
|
0U, // G_UZP2
|
|
0U, // G_VASHR
|
|
0U, // G_VLSHR
|
|
0U, // G_ZIP1
|
|
0U, // G_ZIP2
|
|
0U, // HOM_Epilog
|
|
0U, // HOM_Prolog
|
|
0U, // HWASAN_CHECK_MEMACCESS
|
|
0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_B
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_D
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_H
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_Q
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_S
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_B
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_D
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_H
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_Q
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_S
|
|
0U, // IRGstack
|
|
0U, // JumpTableDest16
|
|
0U, // JumpTableDest32
|
|
0U, // JumpTableDest8
|
|
0U, // KCFI_CHECK
|
|
0U, // LD1B_2Z_IMM_PSEUDO
|
|
0U, // LD1B_2Z_PSEUDO
|
|
0U, // LD1B_4Z_IMM_PSEUDO
|
|
0U, // LD1B_4Z_PSEUDO
|
|
0U, // LD1D_2Z_IMM_PSEUDO
|
|
0U, // LD1D_2Z_PSEUDO
|
|
0U, // LD1D_4Z_IMM_PSEUDO
|
|
0U, // LD1D_4Z_PSEUDO
|
|
0U, // LD1H_2Z_IMM_PSEUDO
|
|
0U, // LD1H_2Z_PSEUDO
|
|
0U, // LD1H_4Z_IMM_PSEUDO
|
|
0U, // LD1H_4Z_PSEUDO
|
|
0U, // LD1W_2Z_IMM_PSEUDO
|
|
0U, // LD1W_2Z_PSEUDO
|
|
0U, // LD1W_4Z_IMM_PSEUDO
|
|
0U, // LD1W_4Z_PSEUDO
|
|
0U, // LD1_MXIPXX_H_PSEUDO_B
|
|
0U, // LD1_MXIPXX_H_PSEUDO_D
|
|
0U, // LD1_MXIPXX_H_PSEUDO_H
|
|
0U, // LD1_MXIPXX_H_PSEUDO_Q
|
|
0U, // LD1_MXIPXX_H_PSEUDO_S
|
|
0U, // LD1_MXIPXX_V_PSEUDO_B
|
|
0U, // LD1_MXIPXX_V_PSEUDO_D
|
|
0U, // LD1_MXIPXX_V_PSEUDO_H
|
|
0U, // LD1_MXIPXX_V_PSEUDO_Q
|
|
0U, // LD1_MXIPXX_V_PSEUDO_S
|
|
0U, // LDFF1B
|
|
0U, // LDFF1B_D
|
|
0U, // LDFF1B_H
|
|
0U, // LDFF1B_S
|
|
0U, // LDFF1D
|
|
0U, // LDFF1H
|
|
0U, // LDFF1H_D
|
|
0U, // LDFF1H_S
|
|
0U, // LDFF1SB_D
|
|
0U, // LDFF1SB_H
|
|
0U, // LDFF1SB_S
|
|
0U, // LDFF1SH_D
|
|
0U, // LDFF1SH_S
|
|
0U, // LDFF1SW_D
|
|
0U, // LDFF1W
|
|
0U, // LDFF1W_D
|
|
0U, // LDNF1B_D_IMM
|
|
0U, // LDNF1B_H_IMM
|
|
0U, // LDNF1B_IMM
|
|
0U, // LDNF1B_S_IMM
|
|
0U, // LDNF1D_IMM
|
|
0U, // LDNF1H_D_IMM
|
|
0U, // LDNF1H_IMM
|
|
0U, // LDNF1H_S_IMM
|
|
0U, // LDNF1SB_D_IMM
|
|
0U, // LDNF1SB_H_IMM
|
|
0U, // LDNF1SB_S_IMM
|
|
0U, // LDNF1SH_D_IMM
|
|
0U, // LDNF1SH_S_IMM
|
|
0U, // LDNF1SW_D_IMM
|
|
0U, // LDNF1W_D_IMM
|
|
0U, // LDNF1W_IMM
|
|
0U, // LDNT1B_2Z_IMM_PSEUDO
|
|
0U, // LDNT1B_2Z_PSEUDO
|
|
0U, // LDNT1B_4Z_IMM_PSEUDO
|
|
0U, // LDNT1B_4Z_PSEUDO
|
|
0U, // LDNT1D_2Z_IMM_PSEUDO
|
|
0U, // LDNT1D_2Z_PSEUDO
|
|
0U, // LDNT1D_4Z_IMM_PSEUDO
|
|
0U, // LDNT1D_4Z_PSEUDO
|
|
0U, // LDNT1H_2Z_IMM_PSEUDO
|
|
0U, // LDNT1H_2Z_PSEUDO
|
|
0U, // LDNT1H_4Z_IMM_PSEUDO
|
|
0U, // LDNT1H_4Z_PSEUDO
|
|
0U, // LDNT1W_2Z_IMM_PSEUDO
|
|
0U, // LDNT1W_2Z_PSEUDO
|
|
0U, // LDNT1W_4Z_IMM_PSEUDO
|
|
0U, // LDNT1W_4Z_PSEUDO
|
|
0U, // LDR_PPXI
|
|
0U, // LDR_TX_PSEUDO
|
|
0U, // LDR_ZA_PSEUDO
|
|
0U, // LDR_ZZXI
|
|
0U, // LDR_ZZZXI
|
|
0U, // LDR_ZZZZXI
|
|
0U, // LOADgot
|
|
0U, // LSL_ZPZI_B_UNDEF
|
|
0U, // LSL_ZPZI_B_ZERO
|
|
0U, // LSL_ZPZI_D_UNDEF
|
|
0U, // LSL_ZPZI_D_ZERO
|
|
0U, // LSL_ZPZI_H_UNDEF
|
|
0U, // LSL_ZPZI_H_ZERO
|
|
0U, // LSL_ZPZI_S_UNDEF
|
|
0U, // LSL_ZPZI_S_ZERO
|
|
0U, // LSL_ZPZZ_B_UNDEF
|
|
0U, // LSL_ZPZZ_B_ZERO
|
|
0U, // LSL_ZPZZ_D_UNDEF
|
|
0U, // LSL_ZPZZ_D_ZERO
|
|
0U, // LSL_ZPZZ_H_UNDEF
|
|
0U, // LSL_ZPZZ_H_ZERO
|
|
0U, // LSL_ZPZZ_S_UNDEF
|
|
0U, // LSL_ZPZZ_S_ZERO
|
|
0U, // LSR_ZPZI_B_UNDEF
|
|
0U, // LSR_ZPZI_B_ZERO
|
|
0U, // LSR_ZPZI_D_UNDEF
|
|
0U, // LSR_ZPZI_D_ZERO
|
|
0U, // LSR_ZPZI_H_UNDEF
|
|
0U, // LSR_ZPZI_H_ZERO
|
|
0U, // LSR_ZPZI_S_UNDEF
|
|
0U, // LSR_ZPZI_S_ZERO
|
|
0U, // LSR_ZPZZ_B_UNDEF
|
|
0U, // LSR_ZPZZ_B_ZERO
|
|
0U, // LSR_ZPZZ_D_UNDEF
|
|
0U, // LSR_ZPZZ_D_ZERO
|
|
0U, // LSR_ZPZZ_H_UNDEF
|
|
0U, // LSR_ZPZZ_H_ZERO
|
|
0U, // LSR_ZPZZ_S_UNDEF
|
|
0U, // LSR_ZPZZ_S_ZERO
|
|
0U, // MLA_ZPZZZ_B_UNDEF
|
|
0U, // MLA_ZPZZZ_D_UNDEF
|
|
0U, // MLA_ZPZZZ_H_UNDEF
|
|
0U, // MLA_ZPZZZ_S_UNDEF
|
|
0U, // MLS_ZPZZZ_B_UNDEF
|
|
0U, // MLS_ZPZZZ_D_UNDEF
|
|
0U, // MLS_ZPZZZ_H_UNDEF
|
|
0U, // MLS_ZPZZZ_S_UNDEF
|
|
0U, // MOPSMemoryCopyPseudo
|
|
0U, // MOPSMemoryMovePseudo
|
|
0U, // MOPSMemorySetPseudo
|
|
0U, // MOPSMemorySetTaggingPseudo
|
|
0U, // MOVA_MXI2Z_H_B_PSEUDO
|
|
0U, // MOVA_MXI2Z_H_D_PSEUDO
|
|
0U, // MOVA_MXI2Z_H_H_PSEUDO
|
|
0U, // MOVA_MXI2Z_H_S_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_B_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_D_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_H_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_S_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_B_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_D_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_H_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_S_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_B_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_D_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_H_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_S_PSEUDO
|
|
0U, // MOVA_VG2_MXI2Z_PSEUDO
|
|
0U, // MOVA_VG4_MXI4Z_PSEUDO
|
|
0U, // MOVMCSym
|
|
0U, // MOVaddr
|
|
0U, // MOVaddrBA
|
|
0U, // MOVaddrCP
|
|
0U, // MOVaddrEXT
|
|
0U, // MOVaddrJT
|
|
0U, // MOVaddrTLS
|
|
0U, // MOVbaseTLS
|
|
0U, // MOVi32imm
|
|
0U, // MOVi64imm
|
|
0U, // MRS_FPCR
|
|
0U, // MSR_FPCR
|
|
0U, // MSRpstatePseudo
|
|
0U, // MUL_ZPZZ_B_UNDEF
|
|
0U, // MUL_ZPZZ_D_UNDEF
|
|
0U, // MUL_ZPZZ_H_UNDEF
|
|
0U, // MUL_ZPZZ_S_UNDEF
|
|
0U, // NEG_ZPmZ_B_UNDEF
|
|
0U, // NEG_ZPmZ_D_UNDEF
|
|
0U, // NEG_ZPmZ_H_UNDEF
|
|
0U, // NEG_ZPmZ_S_UNDEF
|
|
0U, // NOT_ZPmZ_B_UNDEF
|
|
0U, // NOT_ZPmZ_D_UNDEF
|
|
0U, // NOT_ZPmZ_H_UNDEF
|
|
0U, // NOT_ZPmZ_S_UNDEF
|
|
0U, // ORNWrr
|
|
0U, // ORNXrr
|
|
0U, // ORRWrr
|
|
0U, // ORRXrr
|
|
0U, // ORR_ZPZZ_B_ZERO
|
|
0U, // ORR_ZPZZ_D_ZERO
|
|
0U, // ORR_ZPZZ_H_ZERO
|
|
0U, // ORR_ZPZZ_S_ZERO
|
|
0U, // PAUTH_EPILOGUE
|
|
0U, // PAUTH_PROLOGUE
|
|
0U, // PROBED_STACKALLOC
|
|
0U, // PROBED_STACKALLOC_DYN
|
|
0U, // PROBED_STACKALLOC_VAR
|
|
0U, // PTEST_PP_ANY
|
|
0U, // RDFFR_P
|
|
0U, // RDFFR_PPz
|
|
0U, // RET_ReallyLR
|
|
0U, // RestoreZAPseudo
|
|
0U, // SABD_ZPZZ_B_UNDEF
|
|
0U, // SABD_ZPZZ_D_UNDEF
|
|
0U, // SABD_ZPZZ_H_UNDEF
|
|
0U, // SABD_ZPZZ_S_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // SCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // SDIV_ZPZZ_D_UNDEF
|
|
0U, // SDIV_ZPZZ_S_UNDEF
|
|
0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // SEH_AddFP
|
|
0U, // SEH_EpilogEnd
|
|
0U, // SEH_EpilogStart
|
|
0U, // SEH_Nop
|
|
0U, // SEH_PACSignLR
|
|
0U, // SEH_PrologEnd
|
|
0U, // SEH_SaveAnyRegQP
|
|
0U, // SEH_SaveAnyRegQPX
|
|
0U, // SEH_SaveFPLR
|
|
0U, // SEH_SaveFPLR_X
|
|
0U, // SEH_SaveFReg
|
|
0U, // SEH_SaveFRegP
|
|
0U, // SEH_SaveFRegP_X
|
|
0U, // SEH_SaveFReg_X
|
|
0U, // SEH_SaveReg
|
|
0U, // SEH_SaveRegP
|
|
0U, // SEH_SaveRegP_X
|
|
0U, // SEH_SaveReg_X
|
|
0U, // SEH_SetFP
|
|
0U, // SEH_StackAlloc
|
|
0U, // SMAX_ZPZZ_B_UNDEF
|
|
0U, // SMAX_ZPZZ_D_UNDEF
|
|
0U, // SMAX_ZPZZ_H_UNDEF
|
|
0U, // SMAX_ZPZZ_S_UNDEF
|
|
0U, // SMIN_ZPZZ_B_UNDEF
|
|
0U, // SMIN_ZPZZ_D_UNDEF
|
|
0U, // SMIN_ZPZZ_H_UNDEF
|
|
0U, // SMIN_ZPZZ_S_UNDEF
|
|
0U, // SMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // SMLALL_MZZI_HtoD_PSEUDO
|
|
0U, // SMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // SMLALL_MZZ_HtoD_PSEUDO
|
|
0U, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // SMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // SMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // SMLAL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // SMLSLL_MZZI_BtoS_PSEUDO
|
|
0U, // SMLSLL_MZZI_HtoD_PSEUDO
|
|
0U, // SMLSLL_MZZ_BtoS_PSEUDO
|
|
0U, // SMLSLL_MZZ_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // SMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // SMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // SMLSL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // SMOPA_MPPZZ_D_PSEUDO
|
|
0U, // SMOPA_MPPZZ_HtoS_PSEUDO
|
|
0U, // SMOPA_MPPZZ_S_PSEUDO
|
|
0U, // SMOPS_MPPZZ_D_PSEUDO
|
|
0U, // SMOPS_MPPZZ_HtoS_PSEUDO
|
|
0U, // SMOPS_MPPZZ_S_PSEUDO
|
|
0U, // SMULH_ZPZZ_B_UNDEF
|
|
0U, // SMULH_ZPZZ_D_UNDEF
|
|
0U, // SMULH_ZPZZ_H_UNDEF
|
|
0U, // SMULH_ZPZZ_S_UNDEF
|
|
0U, // SPACE
|
|
0U, // SQABS_ZPmZ_B_UNDEF
|
|
0U, // SQABS_ZPmZ_D_UNDEF
|
|
0U, // SQABS_ZPmZ_H_UNDEF
|
|
0U, // SQABS_ZPmZ_S_UNDEF
|
|
0U, // SQNEG_ZPmZ_B_UNDEF
|
|
0U, // SQNEG_ZPmZ_D_UNDEF
|
|
0U, // SQNEG_ZPmZ_H_UNDEF
|
|
0U, // SQNEG_ZPmZ_S_UNDEF
|
|
0U, // SQRSHL_ZPZZ_B_UNDEF
|
|
0U, // SQRSHL_ZPZZ_D_UNDEF
|
|
0U, // SQRSHL_ZPZZ_H_UNDEF
|
|
0U, // SQRSHL_ZPZZ_S_UNDEF
|
|
0U, // SQSHLU_ZPZI_B_ZERO
|
|
0U, // SQSHLU_ZPZI_D_ZERO
|
|
0U, // SQSHLU_ZPZI_H_ZERO
|
|
0U, // SQSHLU_ZPZI_S_ZERO
|
|
0U, // SQSHL_ZPZI_B_ZERO
|
|
0U, // SQSHL_ZPZI_D_ZERO
|
|
0U, // SQSHL_ZPZI_H_ZERO
|
|
0U, // SQSHL_ZPZI_S_ZERO
|
|
0U, // SQSHL_ZPZZ_B_UNDEF
|
|
0U, // SQSHL_ZPZZ_D_UNDEF
|
|
0U, // SQSHL_ZPZZ_H_UNDEF
|
|
0U, // SQSHL_ZPZZ_S_UNDEF
|
|
0U, // SRSHL_ZPZZ_B_UNDEF
|
|
0U, // SRSHL_ZPZZ_D_UNDEF
|
|
0U, // SRSHL_ZPZZ_H_UNDEF
|
|
0U, // SRSHL_ZPZZ_S_UNDEF
|
|
0U, // SRSHR_ZPZI_B_ZERO
|
|
0U, // SRSHR_ZPZI_D_ZERO
|
|
0U, // SRSHR_ZPZI_H_ZERO
|
|
0U, // SRSHR_ZPZI_S_ZERO
|
|
0U, // STGloop
|
|
0U, // STGloop_wback
|
|
0U, // STR_PPXI
|
|
0U, // STR_TX_PSEUDO
|
|
0U, // STR_ZZXI
|
|
0U, // STR_ZZZXI
|
|
0U, // STR_ZZZZXI
|
|
0U, // STZGloop
|
|
0U, // STZGloop_wback
|
|
0U, // SUBR_ZPZZ_B_ZERO
|
|
0U, // SUBR_ZPZZ_D_ZERO
|
|
0U, // SUBR_ZPZZ_H_ZERO
|
|
0U, // SUBR_ZPZZ_S_ZERO
|
|
0U, // SUBSWrr
|
|
0U, // SUBSXrr
|
|
0U, // SUBWrr
|
|
0U, // SUBXrr
|
|
0U, // SUB_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // SUB_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // SUB_VG2_M2ZZ_D_PSEUDO
|
|
0U, // SUB_VG2_M2ZZ_S_PSEUDO
|
|
0U, // SUB_VG2_M2Z_D_PSEUDO
|
|
0U, // SUB_VG2_M2Z_S_PSEUDO
|
|
0U, // SUB_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // SUB_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // SUB_VG4_M4ZZ_D_PSEUDO
|
|
0U, // SUB_VG4_M4ZZ_S_PSEUDO
|
|
0U, // SUB_VG4_M4Z_D_PSEUDO
|
|
0U, // SUB_VG4_M4Z_S_PSEUDO
|
|
0U, // SUB_ZPZZ_B_ZERO
|
|
0U, // SUB_ZPZZ_D_ZERO
|
|
0U, // SUB_ZPZZ_H_ZERO
|
|
0U, // SUB_ZPZZ_S_ZERO
|
|
0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // SUDOT_VG2_M2ZZ_BToS_PSEUDO
|
|
0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // SUDOT_VG4_M4ZZ_BToS_PSEUDO
|
|
0U, // SUMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SUMOPA_MPPZZ_D_PSEUDO
|
|
0U, // SUMOPA_MPPZZ_S_PSEUDO
|
|
0U, // SUMOPS_MPPZZ_D_PSEUDO
|
|
0U, // SUMOPS_MPPZZ_S_PSEUDO
|
|
0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SXTB_ZPmZ_D_UNDEF
|
|
0U, // SXTB_ZPmZ_H_UNDEF
|
|
0U, // SXTB_ZPmZ_S_UNDEF
|
|
0U, // SXTH_ZPmZ_D_UNDEF
|
|
0U, // SXTH_ZPmZ_S_UNDEF
|
|
0U, // SXTW_ZPmZ_D_UNDEF
|
|
0U, // SpeculationBarrierISBDSBEndBB
|
|
0U, // SpeculationBarrierSBEndBB
|
|
0U, // SpeculationSafeValueW
|
|
0U, // SpeculationSafeValueX
|
|
0U, // StoreSwiftAsyncContext
|
|
0U, // TAGPstack
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNriALL
|
|
0U, // TCRETURNriBTI
|
|
25035U, // TLSDESCCALL
|
|
0U, // TLSDESC_CALLSEQ
|
|
0U, // UABD_ZPZZ_B_UNDEF
|
|
0U, // UABD_ZPZZ_D_UNDEF
|
|
0U, // UABD_ZPZZ_H_UNDEF
|
|
0U, // UABD_ZPZZ_S_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // UCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // UDIV_ZPZZ_D_UNDEF
|
|
0U, // UDIV_ZPZZ_S_UNDEF
|
|
0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // UMAX_ZPZZ_B_UNDEF
|
|
0U, // UMAX_ZPZZ_D_UNDEF
|
|
0U, // UMAX_ZPZZ_H_UNDEF
|
|
0U, // UMAX_ZPZZ_S_UNDEF
|
|
0U, // UMIN_ZPZZ_B_UNDEF
|
|
0U, // UMIN_ZPZZ_D_UNDEF
|
|
0U, // UMIN_ZPZZ_H_UNDEF
|
|
0U, // UMIN_ZPZZ_S_UNDEF
|
|
0U, // UMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // UMLALL_MZZI_HtoD_PSEUDO
|
|
0U, // UMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // UMLALL_MZZ_HtoD_PSEUDO
|
|
0U, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // UMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // UMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // UMLAL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // UMLSLL_MZZI_BtoS_PSEUDO
|
|
0U, // UMLSLL_MZZI_HtoD_PSEUDO
|
|
0U, // UMLSLL_MZZ_BtoS_PSEUDO
|
|
0U, // UMLSLL_MZZ_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // UMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // UMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // UMLSL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // UMOPA_MPPZZ_D_PSEUDO
|
|
0U, // UMOPA_MPPZZ_HtoS_PSEUDO
|
|
0U, // UMOPA_MPPZZ_S_PSEUDO
|
|
0U, // UMOPS_MPPZZ_D_PSEUDO
|
|
0U, // UMOPS_MPPZZ_HtoS_PSEUDO
|
|
0U, // UMOPS_MPPZZ_S_PSEUDO
|
|
0U, // UMULH_ZPZZ_B_UNDEF
|
|
0U, // UMULH_ZPZZ_D_UNDEF
|
|
0U, // UMULH_ZPZZ_H_UNDEF
|
|
0U, // UMULH_ZPZZ_S_UNDEF
|
|
0U, // UQRSHL_ZPZZ_B_UNDEF
|
|
0U, // UQRSHL_ZPZZ_D_UNDEF
|
|
0U, // UQRSHL_ZPZZ_H_UNDEF
|
|
0U, // UQRSHL_ZPZZ_S_UNDEF
|
|
0U, // UQSHL_ZPZI_B_ZERO
|
|
0U, // UQSHL_ZPZI_D_ZERO
|
|
0U, // UQSHL_ZPZI_H_ZERO
|
|
0U, // UQSHL_ZPZI_S_ZERO
|
|
0U, // UQSHL_ZPZZ_B_UNDEF
|
|
0U, // UQSHL_ZPZZ_D_UNDEF
|
|
0U, // UQSHL_ZPZZ_H_UNDEF
|
|
0U, // UQSHL_ZPZZ_S_UNDEF
|
|
0U, // URECPE_ZPmZ_S_UNDEF
|
|
0U, // URSHL_ZPZZ_B_UNDEF
|
|
0U, // URSHL_ZPZZ_D_UNDEF
|
|
0U, // URSHL_ZPZZ_H_UNDEF
|
|
0U, // URSHL_ZPZZ_S_UNDEF
|
|
0U, // URSHR_ZPZI_B_ZERO
|
|
0U, // URSHR_ZPZI_D_ZERO
|
|
0U, // URSHR_ZPZI_H_ZERO
|
|
0U, // URSHR_ZPZI_S_ZERO
|
|
0U, // URSQRTE_ZPmZ_S_UNDEF
|
|
0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO
|
|
0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // USDOT_VG2_M2ZZ_BToS_PSEUDO
|
|
0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO
|
|
0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // USDOT_VG4_M4ZZ_BToS_PSEUDO
|
|
0U, // USMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // USMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // USMOPA_MPPZZ_D_PSEUDO
|
|
0U, // USMOPA_MPPZZ_S_PSEUDO
|
|
0U, // USMOPS_MPPZZ_D_PSEUDO
|
|
0U, // USMOPS_MPPZZ_S_PSEUDO
|
|
0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UXTB_ZPmZ_D_UNDEF
|
|
0U, // UXTB_ZPmZ_H_UNDEF
|
|
0U, // UXTB_ZPmZ_S_UNDEF
|
|
0U, // UXTH_ZPmZ_D_UNDEF
|
|
0U, // UXTH_ZPmZ_S_UNDEF
|
|
0U, // UXTW_ZPmZ_D_UNDEF
|
|
0U, // ZERO_M_PSEUDO
|
|
0U, // ZERO_T_PSEUDO
|
|
2120165U, // ABSWr
|
|
2120165U, // ABSXr
|
|
270572005U, // ABS_ZPmZ_B
|
|
270588389U, // ABS_ZPmZ_D
|
|
541137381U, // ABS_ZPmZ_H
|
|
270621157U, // ABS_ZPmZ_S
|
|
811702757U, // ABSv16i8
|
|
2120165U, // ABSv1i64
|
|
813799909U, // ABSv2i32
|
|
815897061U, // ABSv2i64
|
|
817994213U, // ABSv4i16
|
|
820091365U, // ABSv4i32
|
|
822188517U, // ABSv8i16
|
|
824285669U, // ABSv8i8
|
|
1075889914U, // ADCLB_ZZZ_D
|
|
1344358138U, // ADCLB_ZZZ_S
|
|
1075895266U, // ADCLT_ZZZ_D
|
|
1344363490U, // ADCLT_ZZZ_S
|
|
2120204U, // ADCSWr
|
|
2120204U, // ADCSXr
|
|
2116174U, // ADCWr
|
|
2116174U, // ADCXr
|
|
2116821U, // ADDG
|
|
1631699779U, // ADDHA_MPPZ_D
|
|
1633796931U, // ADDHA_MPPZ_S
|
|
1881180127U, // ADDHNB_ZZZ_B
|
|
2172717023U, // ADDHNB_ZZZ_H
|
|
2418100191U, // ADDHNB_ZZZ_S
|
|
2686491817U, // ADDHNT_ZZZ_B
|
|
2174819497U, // ADDHNT_ZZZ_H
|
|
1075928233U, // ADDHNT_ZZZ_S
|
|
813798667U, // ADDHNv2i64_v2i32
|
|
2967601592U, // ADDHNv2i64_v4i32
|
|
817992971U, // ADDHNv4i32_v4i16
|
|
2969698744U, // ADDHNv4i32_v8i16
|
|
2959212984U, // ADDHNv8i16_v16i8
|
|
824284427U, // ADDHNv8i16_v8i8
|
|
2118438U, // ADDPL_XXI
|
|
2121085U, // ADDPT_shift
|
|
3223361070U, // ADDP_ZPmZ_B
|
|
3223377454U, // ADDP_ZPmZ_D
|
|
3519092270U, // ADDP_ZPmZ_H
|
|
3223410222U, // ADDP_ZPmZ_S
|
|
811701806U, // ADDPv16i8
|
|
813798958U, // ADDPv2i32
|
|
815896110U, // ADDPv2i64
|
|
807425582U, // ADDPv2i64p
|
|
817993262U, // ADDPv4i16
|
|
820090414U, // ADDPv4i32
|
|
822187566U, // ADDPv8i16
|
|
824284718U, // ADDPv8i8
|
|
3227623162U, // ADDQV_VPZ_B
|
|
3231817466U, // ADDQV_VPZ_D
|
|
3238108922U, // ADDQV_VPZ_H
|
|
3236011770U, // ADDQV_VPZ_S
|
|
2118517U, // ADDSPL_XXI
|
|
2118764U, // ADDSVL_XXI
|
|
2120216U, // ADDSWri
|
|
2120216U, // ADDSWrs
|
|
2120216U, // ADDSWrx
|
|
2120216U, // ADDSXri
|
|
2120216U, // ADDSXrs
|
|
2120216U, // ADDSXrx
|
|
2120216U, // ADDSXrx64
|
|
1631700157U, // ADDVA_MPPZ_D
|
|
1633797309U, // ADDVA_MPPZ_S
|
|
2118751U, // ADDVL_XXI
|
|
807427698U, // ADDVv16i8v
|
|
807427698U, // ADDVv4i16v
|
|
807427698U, // ADDVv4i32v
|
|
807427698U, // ADDVv8i16v
|
|
807427698U, // ADDVv8i8v
|
|
2116450U, // ADDWri
|
|
2116450U, // ADDWrs
|
|
2116450U, // ADDWrx
|
|
2116450U, // ADDXri
|
|
2116450U, // ADDXrs
|
|
2116450U, // ADDXrx
|
|
2116450U, // ADDXrx64
|
|
2179091298U, // ADD_VG2_2ZZ_B
|
|
2181204834U, // ADD_VG2_2ZZ_D
|
|
2183318370U, // ADD_VG2_2ZZ_H
|
|
2185431906U, // ADD_VG2_2ZZ_S
|
|
3798158178U, // ADD_VG2_M2Z2Z_D
|
|
3798174562U, // ADD_VG2_M2Z2Z_S
|
|
3798158178U, // ADD_VG2_M2ZZ_D
|
|
3798174562U, // ADD_VG2_M2ZZ_S
|
|
3798158178U, // ADD_VG2_M2Z_D
|
|
3798174562U, // ADD_VG2_M2Z_S
|
|
2179091298U, // ADD_VG4_4ZZ_B
|
|
2181204834U, // ADD_VG4_4ZZ_D
|
|
2183318370U, // ADD_VG4_4ZZ_H
|
|
2185431906U, // ADD_VG4_4ZZ_S
|
|
4066593634U, // ADD_VG4_M4Z4Z_D
|
|
4066610018U, // ADD_VG4_M4Z4Z_S
|
|
4066593634U, // ADD_VG4_M4ZZ_D
|
|
4066610018U, // ADD_VG4_M4ZZ_S
|
|
4066593634U, // ADD_VG4_M4Z_D
|
|
4066610018U, // ADD_VG4_M4Z_S
|
|
2132834U, // ADD_ZI_B
|
|
2418068322U, // ADD_ZI_D
|
|
2189495138U, // ADD_ZI_H
|
|
270617442U, // ADD_ZI_S
|
|
3223358306U, // ADD_ZPmZ_B
|
|
3223379325U, // ADD_ZPmZ_CPA
|
|
3223374690U, // ADD_ZPmZ_D
|
|
3519089506U, // ADD_ZPmZ_H
|
|
3223407458U, // ADD_ZPmZ_S
|
|
2132834U, // ADD_ZZZ_B
|
|
2418072957U, // ADD_ZZZ_CPA
|
|
2418068322U, // ADD_ZZZ_D
|
|
2189495138U, // ADD_ZZZ_H
|
|
270617442U, // ADD_ZZZ_S
|
|
811699042U, // ADDv16i8
|
|
2116450U, // ADDv1i64
|
|
813796194U, // ADDv2i32
|
|
815893346U, // ADDv2i64
|
|
817990498U, // ADDv4i16
|
|
820087650U, // ADDv4i32
|
|
822184802U, // ADDv8i16
|
|
824281954U, // ADDv8i8
|
|
538990684U, // ADR
|
|
538990323U, // ADRP
|
|
2460014684U, // ADR_LSL_ZZZ_D_0
|
|
2460014684U, // ADR_LSL_ZZZ_D_1
|
|
2460014684U, // ADR_LSL_ZZZ_D_2
|
|
2460014684U, // ADR_LSL_ZZZ_D_3
|
|
312563804U, // ADR_LSL_ZZZ_S_0
|
|
312563804U, // ADR_LSL_ZZZ_S_1
|
|
312563804U, // ADR_LSL_ZZZ_S_2
|
|
312563804U, // ADR_LSL_ZZZ_S_3
|
|
2460014684U, // ADR_SXTW_ZZZ_D_0
|
|
2460014684U, // ADR_SXTW_ZZZ_D_1
|
|
2460014684U, // ADR_SXTW_ZZZ_D_2
|
|
2460014684U, // ADR_SXTW_ZZZ_D_3
|
|
2460014684U, // ADR_UXTW_ZZZ_D_0
|
|
2460014684U, // ADR_UXTW_ZZZ_D_1
|
|
2460014684U, // ADR_UXTW_ZZZ_D_2
|
|
2460014684U, // ADR_UXTW_ZZZ_D_3
|
|
2132970U, // AESD_ZZZ_B
|
|
2959215594U, // AESDrr
|
|
2133117U, // AESE_ZZZ_B
|
|
2959215741U, // AESErr
|
|
2132575U, // AESIMC_ZZ_B
|
|
811698783U, // AESIMCrr
|
|
2132583U, // AESMC_ZZ_B
|
|
811698791U, // AESMCrr
|
|
3227623169U, // ANDQV_VPZ_B
|
|
3231817473U, // ANDQV_VPZ_D
|
|
3238108929U, // ANDQV_VPZ_H
|
|
3236011777U, // ANDQV_VPZ_S
|
|
2120223U, // ANDSWri
|
|
2120223U, // ANDSWrs
|
|
2120223U, // ANDSXri
|
|
2120223U, // ANDSXrs
|
|
3223362079U, // ANDS_PPzPP
|
|
253574U, // ANDV_VPZ_B
|
|
1657020038U, // ANDV_VPZ_D
|
|
1659133574U, // ANDV_VPZ_H
|
|
1638178438U, // ANDV_VPZ_S
|
|
2116552U, // ANDWri
|
|
2116552U, // ANDWrs
|
|
2116552U, // ANDXri
|
|
2116552U, // ANDXrs
|
|
3223358408U, // AND_PPzPP
|
|
2418068424U, // AND_ZI
|
|
3223358408U, // AND_ZPmZ_B
|
|
3223374792U, // AND_ZPmZ_D
|
|
3519089608U, // AND_ZPmZ_H
|
|
3223407560U, // AND_ZPmZ_S
|
|
2418068424U, // AND_ZZZ
|
|
811699144U, // ANDv16i8
|
|
824282056U, // ANDv8i8
|
|
3223358436U, // ASRD_ZPmI_B
|
|
3223374820U, // ASRD_ZPmI_D
|
|
3519089636U, // ASRD_ZPmI_H
|
|
3223407588U, // ASRD_ZPmI_S
|
|
3223361829U, // ASRR_ZPmZ_B
|
|
3223378213U, // ASRR_ZPmZ_D
|
|
3519093029U, // ASRR_ZPmZ_H
|
|
3223410981U, // ASRR_ZPmZ_S
|
|
2119991U, // ASRVWr
|
|
2119991U, // ASRVXr
|
|
3223361847U, // ASR_WIDE_ZPmZ_B
|
|
3519093047U, // ASR_WIDE_ZPmZ_H
|
|
3223410999U, // ASR_WIDE_ZPmZ_S
|
|
2136375U, // ASR_WIDE_ZZZ_B
|
|
2189498679U, // ASR_WIDE_ZZZ_H
|
|
270620983U, // ASR_WIDE_ZZZ_S
|
|
3223361847U, // ASR_ZPmI_B
|
|
3223378231U, // ASR_ZPmI_D
|
|
3519093047U, // ASR_ZPmI_H
|
|
3223410999U, // ASR_ZPmI_S
|
|
3223361847U, // ASR_ZPmZ_B
|
|
3223378231U, // ASR_ZPmZ_D
|
|
3519093047U, // ASR_ZPmZ_H
|
|
3223410999U, // ASR_ZPmZ_S
|
|
2136375U, // ASR_ZZI_B
|
|
2418071863U, // ASR_ZZI_D
|
|
2189498679U, // ASR_ZZI_H
|
|
270620983U, // ASR_ZZI_S
|
|
319749U, // AT_AS1ELX
|
|
807715637U, // AUTDA
|
|
807716388U, // AUTDB
|
|
312548U, // AUTDZA
|
|
313898U, // AUTDZB
|
|
807715665U, // AUTIA
|
|
8864U, // AUTIA1716
|
|
8903U, // AUTIA171615
|
|
8991U, // AUTIASP
|
|
330368U, // AUTIASPPCi
|
|
19072U, // AUTIASPPCr
|
|
8982U, // AUTIAZ
|
|
807716415U, // AUTIB
|
|
8873U, // AUTIB1716
|
|
8927U, // AUTIB171615
|
|
8855U, // AUTIBSP
|
|
330390U, // AUTIBSPPCi
|
|
19094U, // AUTIBSPPCr
|
|
8837U, // AUTIBZ
|
|
312564U, // AUTIZA
|
|
313914U, // AUTIZB
|
|
10346U, // AXFLAG
|
|
328959U, // B
|
|
811704503U, // BCAX
|
|
2418073783U, // BCAX_ZZZZ
|
|
352771U, // BCcc
|
|
2135609U, // BDEP_ZZZ_B
|
|
2418071097U, // BDEP_ZZZ_D
|
|
2189497913U, // BDEP_ZZZ_H
|
|
270620217U, // BDEP_ZZZ_S
|
|
2137621U, // BEXT_ZZZ_B
|
|
2418073109U, // BEXT_ZZZ_D
|
|
2189499925U, // BEXT_ZZZ_H
|
|
270622229U, // BEXT_ZZZ_S
|
|
2961317171U, // BF16DOTlanev4bf16
|
|
2967608627U, // BF16DOTlanev8bf16
|
|
822182290U, // BF1CVTL2v8f16
|
|
1661017210U, // BF1CVTLT_ZZ_BtoH
|
|
1661129770U, // BF1CVTL_2ZZ_BtoH_NAME
|
|
822187050U, // BF1CVTLv8f16
|
|
1661132234U, // BF1CVT_2ZZ_BtoH_NAME
|
|
1661017546U, // BF1CVT_ZZ_BtoH
|
|
822182300U, // BF2CVTL2v8f16
|
|
1661017220U, // BF2CVTLT_ZZ_BtoH
|
|
1661129779U, // BF2CVTL_2ZZ_BtoH_NAME
|
|
822187059U, // BF2CVTLv8f16
|
|
1661132242U, // BF2CVT_2ZZ_BtoH_NAME
|
|
1661017554U, // BF2CVT_ZZ_BtoH
|
|
3798305654U, // BFADD_VG2_M2Z_H
|
|
4066741110U, // BFADD_VG4_M4Z_H
|
|
3519089526U, // BFADD_ZPmZZ
|
|
2189495158U, // BFADD_ZZZ
|
|
2195904127U, // BFCLAMP_VG2_2ZZZ_H
|
|
2195904127U, // BFCLAMP_VG4_4ZZZ_H
|
|
2195789439U, // BFCLAMP_ZZZ
|
|
2121178U, // BFCVT
|
|
817993072U, // BFCVTN
|
|
2969698796U, // BFCVTN2
|
|
1078009069U, // BFCVTNT_ZPmZ
|
|
1344312688U, // BFCVTN_Z2Z_HtoB
|
|
1648432496U, // BFCVTN_Z2Z_StoH
|
|
1344314842U, // BFCVT_Z2Z_HtoB
|
|
1648434650U, // BFCVT_Z2Z_StoH
|
|
1078009306U, // BFCVT_ZPmZ
|
|
3798179123U, // BFDOT_VG2_M2Z2Z_HtoS
|
|
3798179123U, // BFDOT_VG2_M2ZZI_HtoS
|
|
3798179123U, // BFDOT_VG2_M2ZZ_HtoS
|
|
4066614579U, // BFDOT_VG4_M4Z4Z_HtoS
|
|
4066614579U, // BFDOT_VG4_M4ZZI_HtoS
|
|
4066614579U, // BFDOT_VG4_M4ZZ_HtoS
|
|
2686541107U, // BFDOT_ZZI
|
|
2686541107U, // BFDOT_ZZZ
|
|
2961317171U, // BFDOTv4bf16
|
|
2967608627U, // BFDOTv8bf16
|
|
2183320781U, // BFMAXNM_VG2_2Z2Z_H
|
|
2183320781U, // BFMAXNM_VG2_2ZZ_H
|
|
2183320781U, // BFMAXNM_VG4_4Z2Z_H
|
|
2183320781U, // BFMAXNM_VG4_4ZZ_H
|
|
3519091917U, // BFMAXNM_ZPmZZ
|
|
2183323844U, // BFMAX_VG2_2Z2Z_H
|
|
2183323844U, // BFMAX_VG2_2ZZ_H
|
|
2183323844U, // BFMAX_VG4_4Z2Z_H
|
|
2183323844U, // BFMAX_VG4_4ZZ_H
|
|
3519094980U, // BFMAX_ZPmZZ
|
|
2183320772U, // BFMINNM_VG2_2Z2Z_H
|
|
2183320772U, // BFMINNM_VG2_2ZZ_H
|
|
2183320772U, // BFMINNM_VG4_4Z2Z_H
|
|
2183320772U, // BFMINNM_VG4_4ZZ_H
|
|
3519091908U, // BFMINNM_ZPmZZ
|
|
2183320857U, // BFMIN_VG2_2Z2Z_H
|
|
2183320857U, // BFMIN_VG2_2ZZ_H
|
|
2183320857U, // BFMIN_VG4_4Z2Z_H
|
|
2183320857U, // BFMIN_VG4_4ZZ_H
|
|
3519091993U, // BFMIN_ZPmZZ
|
|
2967602800U, // BFMLALB
|
|
2967602800U, // BFMLALBIdx
|
|
2686535280U, // BFMLALB_ZZZ
|
|
2686535280U, // BFMLALB_ZZZI
|
|
2967608242U, // BFMLALT
|
|
2967608242U, // BFMLALTIdx
|
|
2686540722U, // BFMLALT_ZZZ
|
|
2686540722U, // BFMLALT_ZZZI
|
|
1663275252U, // BFMLAL_MZZI_HtoS
|
|
1663275252U, // BFMLAL_MZZ_HtoS
|
|
3810758900U, // BFMLAL_VG2_M2Z2Z_HtoS
|
|
3810758900U, // BFMLAL_VG2_M2ZZI_HtoS
|
|
3810758900U, // BFMLAL_VG2_M2ZZ_HtoS
|
|
4079194356U, // BFMLAL_VG4_M4Z4Z_HtoS
|
|
4079194356U, // BFMLAL_VG4_M4ZZI_HtoS
|
|
4079194356U, // BFMLAL_VG4_M4ZZ_HtoS
|
|
3798303589U, // BFMLA_VG2_M2Z2Z
|
|
3798303589U, // BFMLA_VG2_M2ZZ
|
|
3798303589U, // BFMLA_VG2_M2ZZI
|
|
4066739045U, // BFMLA_VG4_M4Z4Z
|
|
4066739045U, // BFMLA_VG4_M4ZZ
|
|
4066739045U, // BFMLA_VG4_M4ZZI
|
|
3519087461U, // BFMLA_ZPmZZ
|
|
2195784549U, // BFMLA_ZZZI
|
|
2686535578U, // BFMLSLB_ZZZI_S
|
|
2686535578U, // BFMLSLB_ZZZ_S
|
|
2686540897U, // BFMLSLT_ZZZI_S
|
|
2686540897U, // BFMLSLT_ZZZ_S
|
|
1663276019U, // BFMLSL_MZZI_HtoS
|
|
1663276019U, // BFMLSL_MZZ_HtoS
|
|
3810759667U, // BFMLSL_VG2_M2Z2Z_HtoS
|
|
3810759667U, // BFMLSL_VG2_M2ZZI_HtoS
|
|
3810759667U, // BFMLSL_VG2_M2ZZ_HtoS
|
|
4079195123U, // BFMLSL_VG4_M4Z4Z_HtoS
|
|
4079195123U, // BFMLSL_VG4_M4ZZI_HtoS
|
|
4079195123U, // BFMLSL_VG4_M4ZZ_HtoS
|
|
3798309457U, // BFMLS_VG2_M2Z2Z
|
|
3798309457U, // BFMLS_VG2_M2ZZ
|
|
3798309457U, // BFMLS_VG2_M2ZZI
|
|
4066744913U, // BFMLS_VG4_M4Z4Z
|
|
4066744913U, // BFMLS_VG4_M4ZZ
|
|
4066744913U, // BFMLS_VG4_M4ZZI
|
|
3519093329U, // BFMLS_ZPmZZ
|
|
2195790417U, // BFMLS_ZZZI
|
|
2967602028U, // BFMMLA
|
|
2686534508U, // BFMMLA_ZZZ
|
|
54641578U, // BFMOPA_MPPZZ
|
|
54641578U, // BFMOPA_MPPZZ_H
|
|
54647454U, // BFMOPS_MPPZZ
|
|
54647454U, // BFMOPS_MPPZZ_H
|
|
3519091779U, // BFMUL_ZPmZZ
|
|
2189497411U, // BFMUL_ZZZ
|
|
2189497411U, // BFMUL_ZZZI
|
|
807425173U, // BFMWri
|
|
807425173U, // BFMXri
|
|
3798305208U, // BFSUB_VG2_M2Z_H
|
|
4066740664U, // BFSUB_VG4_M4Z_H
|
|
3519089080U, // BFSUB_ZPmZZ
|
|
2189494712U, // BFSUB_ZZZ
|
|
3798179144U, // BFVDOT_VG2_M2ZZI_HtoS
|
|
2135801U, // BGRP_ZZZ_B
|
|
2418071289U, // BGRP_ZZZ_D
|
|
2189498105U, // BGRP_ZZZ_H
|
|
270620409U, // BGRP_ZZZ_S
|
|
2120210U, // BICSWrs
|
|
2120210U, // BICSXrs
|
|
3223362066U, // BICS_PPzPP
|
|
2116179U, // BICWrs
|
|
2116179U, // BICXrs
|
|
3223358035U, // BIC_PPzPP
|
|
3223358035U, // BIC_ZPmZ_B
|
|
3223374419U, // BIC_ZPmZ_D
|
|
3519089235U, // BIC_ZPmZ_H
|
|
3223407187U, // BIC_ZPmZ_S
|
|
2418068051U, // BIC_ZZZ
|
|
811698771U, // BICv16i8
|
|
1887570515U, // BICv2i32
|
|
1891764819U, // BICv4i16
|
|
1893861971U, // BICv4i32
|
|
1895959123U, // BICv8i16
|
|
824281683U, // BICv8i8
|
|
2959215785U, // BIFv16i8
|
|
2971798697U, // BIFv8i8
|
|
2959219590U, // BITv16i8
|
|
2971802502U, // BITv8i8
|
|
332306U, // BL
|
|
22694U, // BLR
|
|
2114316U, // BLRAA
|
|
24949U, // BLRAAZ
|
|
2114981U, // BLRAB
|
|
24971U, // BLRABZ
|
|
2170667939U, // BMOPA_MPPZZ_S
|
|
2170673815U, // BMOPS_MPPZZ_S
|
|
22584U, // BR
|
|
2114303U, // BRAA
|
|
24942U, // BRAAZ
|
|
2114968U, // BRAB
|
|
24964U, // BRABZ
|
|
10375U, // BRB_IALL
|
|
10353U, // BRB_INJ
|
|
381129U, // BRK
|
|
3223361997U, // BRKAS_PPzP
|
|
270566232U, // BRKA_PPmP
|
|
3223356248U, // BRKA_PPzP
|
|
3223362033U, // BRKBS_PPzP
|
|
270566982U, // BRKB_PPmP
|
|
3223356998U, // BRKB_PPzP
|
|
3223362163U, // BRKNS_PPzP
|
|
3223360816U, // BRKN_PPzP
|
|
3223362004U, // BRKPAS_PPzPP
|
|
3223356316U, // BRKPA_PPzPP
|
|
3223362040U, // BRKPBS_PPzPP
|
|
3223357533U, // BRKPB_PPzPP
|
|
2418070772U, // BSL1N_ZZZZ
|
|
2418070779U, // BSL2N_ZZZZ
|
|
2418070501U, // BSL_ZZZZ
|
|
2959217637U, // BSLv16i8
|
|
2971800549U, // BSLv8i8
|
|
352768U, // Bcc
|
|
2132833U, // CADD_ZZI_B
|
|
2418068321U, // CADD_ZZI_D
|
|
2189495137U, // CADD_ZZI_H
|
|
270617441U, // CADD_ZZI_S
|
|
807716286U, // CASAB
|
|
807718345U, // CASAH
|
|
807716539U, // CASALB
|
|
807718504U, // CASALH
|
|
807719374U, // CASALW
|
|
807719374U, // CASALX
|
|
807715971U, // CASAW
|
|
807715971U, // CASAX
|
|
807717160U, // CASB
|
|
807718889U, // CASH
|
|
807716745U, // CASLB
|
|
807718598U, // CASLH
|
|
807719893U, // CASLW
|
|
807719893U, // CASLX
|
|
397658U, // CASPALW
|
|
414042U, // CASPALX
|
|
394233U, // CASPAW
|
|
410617U, // CASPAX
|
|
398180U, // CASPLW
|
|
414564U, // CASPLX
|
|
399134U, // CASPW
|
|
415518U, // CASPX
|
|
807721408U, // CASW
|
|
807721408U, // CASX
|
|
2149605799U, // CBNZW
|
|
2149605799U, // CBNZX
|
|
2149605779U, // CBZW
|
|
2149605779U, // CBZX
|
|
2118966U, // CCMNWi
|
|
2118966U, // CCMNWr
|
|
2118966U, // CCMNXi
|
|
2118966U, // CCMNXr
|
|
2119321U, // CCMPWi
|
|
2119321U, // CCMPWr
|
|
2119321U, // CCMPXi
|
|
2119321U, // CCMPXr
|
|
2686508333U, // CDOT_ZZZI_D
|
|
2418105645U, // CDOT_ZZZI_S
|
|
2686508333U, // CDOT_ZZZ_D
|
|
2418105645U, // CDOT_ZZZ_S
|
|
10423U, // CFINV
|
|
8846U, // CHKFEAT
|
|
3223340213U, // CLASTA_RPZ_B
|
|
3223340213U, // CLASTA_RPZ_D
|
|
3223340213U, // CLASTA_RPZ_H
|
|
3223340213U, // CLASTA_RPZ_S
|
|
3223340213U, // CLASTA_VPZ_B
|
|
3223340213U, // CLASTA_VPZ_D
|
|
3223340213U, // CLASTA_VPZ_H
|
|
3223340213U, // CLASTA_VPZ_S
|
|
3223356597U, // CLASTA_ZPZ_B
|
|
3223372981U, // CLASTA_ZPZ_D
|
|
2176910517U, // CLASTA_ZPZ_H
|
|
3223405749U, // CLASTA_ZPZ_S
|
|
3223341476U, // CLASTB_RPZ_B
|
|
3223341476U, // CLASTB_RPZ_D
|
|
3223341476U, // CLASTB_RPZ_H
|
|
3223341476U, // CLASTB_RPZ_S
|
|
3223341476U, // CLASTB_VPZ_B
|
|
3223341476U, // CLASTB_VPZ_D
|
|
3223341476U, // CLASTB_VPZ_H
|
|
3223341476U, // CLASTB_VPZ_S
|
|
3223357860U, // CLASTB_ZPZ_B
|
|
3223374244U, // CLASTB_ZPZ_D
|
|
2176911780U, // CLASTB_ZPZ_H
|
|
3223407012U, // CLASTB_ZPZ_S
|
|
10391U, // CLR
|
|
24821U, // CLREX
|
|
2120259U, // CLSWr
|
|
2120259U, // CLSXr
|
|
270572099U, // CLS_ZPmZ_B
|
|
270588483U, // CLS_ZPmZ_D
|
|
541137475U, // CLS_ZPmZ_H
|
|
270621251U, // CLS_ZPmZ_S
|
|
811702851U, // CLSv16i8
|
|
813800003U, // CLSv2i32
|
|
817994307U, // CLSv4i16
|
|
820091459U, // CLSv4i32
|
|
822188611U, // CLSv8i16
|
|
824285763U, // CLSv8i8
|
|
2122146U, // CLZWr
|
|
2122146U, // CLZXr
|
|
270573986U, // CLZ_ZPmZ_B
|
|
270590370U, // CLZ_ZPmZ_D
|
|
541139362U, // CLZ_ZPmZ_H
|
|
270623138U, // CLZ_ZPmZ_S
|
|
811704738U, // CLZv16i8
|
|
813801890U, // CLZv2i32
|
|
817996194U, // CLZv4i16
|
|
820093346U, // CLZv4i32
|
|
822190498U, // CLZv8i16
|
|
824287650U, // CLZv8i8
|
|
811702237U, // CMEQv16i8
|
|
811702237U, // CMEQv16i8rz
|
|
2119645U, // CMEQv1i64
|
|
2119645U, // CMEQv1i64rz
|
|
813799389U, // CMEQv2i32
|
|
813799389U, // CMEQv2i32rz
|
|
815896541U, // CMEQv2i64
|
|
815896541U, // CMEQv2i64rz
|
|
817993693U, // CMEQv4i16
|
|
817993693U, // CMEQv4i16rz
|
|
820090845U, // CMEQv4i32
|
|
820090845U, // CMEQv4i32rz
|
|
822187997U, // CMEQv8i16
|
|
822187997U, // CMEQv8i16rz
|
|
824285149U, // CMEQv8i8
|
|
824285149U, // CMEQv8i8rz
|
|
811699227U, // CMGEv16i8
|
|
811699227U, // CMGEv16i8rz
|
|
2116635U, // CMGEv1i64
|
|
2116635U, // CMGEv1i64rz
|
|
813796379U, // CMGEv2i32
|
|
813796379U, // CMGEv2i32rz
|
|
815893531U, // CMGEv2i64
|
|
815893531U, // CMGEv2i64rz
|
|
817990683U, // CMGEv4i16
|
|
817990683U, // CMGEv4i16rz
|
|
820087835U, // CMGEv4i32
|
|
820087835U, // CMGEv4i32rz
|
|
822184987U, // CMGEv8i16
|
|
822184987U, // CMGEv8i16rz
|
|
824282139U, // CMGEv8i8
|
|
824282139U, // CMGEv8i8rz
|
|
811703160U, // CMGTv16i8
|
|
811703160U, // CMGTv16i8rz
|
|
2120568U, // CMGTv1i64
|
|
2120568U, // CMGTv1i64rz
|
|
813800312U, // CMGTv2i32
|
|
813800312U, // CMGTv2i32rz
|
|
815897464U, // CMGTv2i64
|
|
815897464U, // CMGTv2i64rz
|
|
817994616U, // CMGTv4i16
|
|
817994616U, // CMGTv4i16rz
|
|
820091768U, // CMGTv4i32
|
|
820091768U, // CMGTv4i32rz
|
|
822188920U, // CMGTv8i16
|
|
822188920U, // CMGTv8i16rz
|
|
824286072U, // CMGTv8i8
|
|
824286072U, // CMGTv8i8rz
|
|
811700351U, // CMHIv16i8
|
|
2117759U, // CMHIv1i64
|
|
813797503U, // CMHIv2i32
|
|
815894655U, // CMHIv2i64
|
|
817991807U, // CMHIv4i16
|
|
820088959U, // CMHIv4i32
|
|
822186111U, // CMHIv8i16
|
|
824283263U, // CMHIv8i8
|
|
811702838U, // CMHSv16i8
|
|
2120246U, // CMHSv1i64
|
|
813799990U, // CMHSv2i32
|
|
815897142U, // CMHSv2i64
|
|
817994294U, // CMHSv4i16
|
|
820091446U, // CMHSv4i32
|
|
822188598U, // CMHSv8i16
|
|
824285750U, // CMHSv8i8
|
|
2195784543U, // CMLA_ZZZI_H
|
|
1344357215U, // CMLA_ZZZI_S
|
|
2418049887U, // CMLA_ZZZ_B
|
|
1075888991U, // CMLA_ZZZ_D
|
|
2195784543U, // CMLA_ZZZ_H
|
|
1344357215U, // CMLA_ZZZ_S
|
|
811699258U, // CMLEv16i8rz
|
|
2116666U, // CMLEv1i64rz
|
|
813796410U, // CMLEv2i32rz
|
|
815893562U, // CMLEv2i64rz
|
|
817990714U, // CMLEv4i16rz
|
|
820087866U, // CMLEv4i32rz
|
|
822185018U, // CMLEv8i16rz
|
|
824282170U, // CMLEv8i8rz
|
|
811703370U, // CMLTv16i8rz
|
|
2120778U, // CMLTv1i64rz
|
|
813800522U, // CMLTv2i32rz
|
|
815897674U, // CMLTv2i64rz
|
|
817994826U, // CMLTv4i16rz
|
|
820091978U, // CMLTv4i32rz
|
|
822189130U, // CMLTv8i16rz
|
|
824286282U, // CMLTv8i8rz
|
|
3223361516U, // CMPEQ_PPzZI_B
|
|
3223377900U, // CMPEQ_PPzZI_D
|
|
2713786348U, // CMPEQ_PPzZI_H
|
|
3223410668U, // CMPEQ_PPzZI_S
|
|
3223361516U, // CMPEQ_PPzZZ_B
|
|
3223377900U, // CMPEQ_PPzZZ_D
|
|
2713786348U, // CMPEQ_PPzZZ_H
|
|
3223410668U, // CMPEQ_PPzZZ_S
|
|
3223361516U, // CMPEQ_WIDE_PPzZZ_B
|
|
2713786348U, // CMPEQ_WIDE_PPzZZ_H
|
|
3223410668U, // CMPEQ_WIDE_PPzZZ_S
|
|
3223358497U, // CMPGE_PPzZI_B
|
|
3223374881U, // CMPGE_PPzZI_D
|
|
2713783329U, // CMPGE_PPzZI_H
|
|
3223407649U, // CMPGE_PPzZI_S
|
|
3223358497U, // CMPGE_PPzZZ_B
|
|
3223374881U, // CMPGE_PPzZZ_D
|
|
2713783329U, // CMPGE_PPzZZ_H
|
|
3223407649U, // CMPGE_PPzZZ_S
|
|
3223358497U, // CMPGE_WIDE_PPzZZ_B
|
|
2713783329U, // CMPGE_WIDE_PPzZZ_H
|
|
3223407649U, // CMPGE_WIDE_PPzZZ_S
|
|
3223362430U, // CMPGT_PPzZI_B
|
|
3223378814U, // CMPGT_PPzZI_D
|
|
2713787262U, // CMPGT_PPzZI_H
|
|
3223411582U, // CMPGT_PPzZI_S
|
|
3223362430U, // CMPGT_PPzZZ_B
|
|
3223378814U, // CMPGT_PPzZZ_D
|
|
2713787262U, // CMPGT_PPzZZ_H
|
|
3223411582U, // CMPGT_PPzZZ_S
|
|
3223362430U, // CMPGT_WIDE_PPzZZ_B
|
|
2713787262U, // CMPGT_WIDE_PPzZZ_H
|
|
3223411582U, // CMPGT_WIDE_PPzZZ_S
|
|
3223359621U, // CMPHI_PPzZI_B
|
|
3223376005U, // CMPHI_PPzZI_D
|
|
2713784453U, // CMPHI_PPzZI_H
|
|
3223408773U, // CMPHI_PPzZI_S
|
|
3223359621U, // CMPHI_PPzZZ_B
|
|
3223376005U, // CMPHI_PPzZZ_D
|
|
2713784453U, // CMPHI_PPzZZ_H
|
|
3223408773U, // CMPHI_PPzZZ_S
|
|
3223359621U, // CMPHI_WIDE_PPzZZ_B
|
|
2713784453U, // CMPHI_WIDE_PPzZZ_H
|
|
3223408773U, // CMPHI_WIDE_PPzZZ_S
|
|
3223362108U, // CMPHS_PPzZI_B
|
|
3223378492U, // CMPHS_PPzZI_D
|
|
2713786940U, // CMPHS_PPzZI_H
|
|
3223411260U, // CMPHS_PPzZI_S
|
|
3223362108U, // CMPHS_PPzZZ_B
|
|
3223378492U, // CMPHS_PPzZZ_D
|
|
2713786940U, // CMPHS_PPzZZ_H
|
|
3223411260U, // CMPHS_PPzZZ_S
|
|
3223362108U, // CMPHS_WIDE_PPzZZ_B
|
|
2713786940U, // CMPHS_WIDE_PPzZZ_H
|
|
3223411260U, // CMPHS_WIDE_PPzZZ_S
|
|
3223358528U, // CMPLE_PPzZI_B
|
|
3223374912U, // CMPLE_PPzZI_D
|
|
2713783360U, // CMPLE_PPzZI_H
|
|
3223407680U, // CMPLE_PPzZI_S
|
|
3223358528U, // CMPLE_WIDE_PPzZZ_B
|
|
2713783360U, // CMPLE_WIDE_PPzZZ_H
|
|
3223407680U, // CMPLE_WIDE_PPzZZ_S
|
|
3223361004U, // CMPLO_PPzZI_B
|
|
3223377388U, // CMPLO_PPzZI_D
|
|
2713785836U, // CMPLO_PPzZI_H
|
|
3223410156U, // CMPLO_PPzZI_S
|
|
3223361004U, // CMPLO_WIDE_PPzZZ_B
|
|
2713785836U, // CMPLO_WIDE_PPzZZ_H
|
|
3223410156U, // CMPLO_WIDE_PPzZZ_S
|
|
3223362143U, // CMPLS_PPzZI_B
|
|
3223378527U, // CMPLS_PPzZI_D
|
|
2713786975U, // CMPLS_PPzZI_H
|
|
3223411295U, // CMPLS_PPzZI_S
|
|
3223362143U, // CMPLS_WIDE_PPzZZ_B
|
|
2713786975U, // CMPLS_WIDE_PPzZZ_H
|
|
3223411295U, // CMPLS_WIDE_PPzZZ_S
|
|
3223362640U, // CMPLT_PPzZI_B
|
|
3223379024U, // CMPLT_PPzZI_D
|
|
2713787472U, // CMPLT_PPzZI_H
|
|
3223411792U, // CMPLT_PPzZI_S
|
|
3223362640U, // CMPLT_WIDE_PPzZZ_B
|
|
2713787472U, // CMPLT_WIDE_PPzZZ_H
|
|
3223411792U, // CMPLT_WIDE_PPzZZ_S
|
|
3223358551U, // CMPNE_PPzZI_B
|
|
3223374935U, // CMPNE_PPzZI_D
|
|
2713783383U, // CMPNE_PPzZI_H
|
|
3223407703U, // CMPNE_PPzZI_S
|
|
3223358551U, // CMPNE_PPzZZ_B
|
|
3223374935U, // CMPNE_PPzZZ_D
|
|
2713783383U, // CMPNE_PPzZZ_H
|
|
3223407703U, // CMPNE_PPzZZ_S
|
|
3223358551U, // CMPNE_WIDE_PPzZZ_B
|
|
2713783383U, // CMPNE_WIDE_PPzZZ_H
|
|
3223407703U, // CMPNE_WIDE_PPzZZ_S
|
|
811703721U, // CMTSTv16i8
|
|
2121129U, // CMTSTv1i64
|
|
813800873U, // CMTSTv2i32
|
|
815898025U, // CMTSTv2i64
|
|
817995177U, // CMTSTv4i16
|
|
820092329U, // CMTSTv4i32
|
|
822189481U, // CMTSTv8i16
|
|
824286633U, // CMTSTv8i8
|
|
270572896U, // CNOT_ZPmZ_B
|
|
270589280U, // CNOT_ZPmZ_D
|
|
541138272U, // CNOT_ZPmZ_H
|
|
270622048U, // CNOT_ZPmZ_S
|
|
2954905999U, // CNTB_XPiI
|
|
2954906608U, // CNTD_XPiI
|
|
2954907690U, // CNTH_XPiI
|
|
3223344974U, // CNTP_XCI_B
|
|
3491780430U, // CNTP_XCI_D
|
|
3760215886U, // CNTP_XCI_H
|
|
4028651342U, // CNTP_XCI_S
|
|
3223344974U, // CNTP_XPP_B
|
|
3223344974U, // CNTP_XPP_D
|
|
3223344974U, // CNTP_XPP_H
|
|
3223344974U, // CNTP_XPP_S
|
|
2954911875U, // CNTW_XPiI
|
|
2120858U, // CNTWr
|
|
2120858U, // CNTXr
|
|
270572698U, // CNT_ZPmZ_B
|
|
270589082U, // CNT_ZPmZ_D
|
|
541138074U, // CNT_ZPmZ_H
|
|
270621850U, // CNT_ZPmZ_S
|
|
811703450U, // CNTv16i8
|
|
824286362U, // CNTv8i8
|
|
3223378747U, // COMPACT_ZPZ_D
|
|
3223411515U, // COMPACT_ZPZ_S
|
|
435121U, // CPYE
|
|
435184U, // CPYEN
|
|
435270U, // CPYERN
|
|
436158U, // CPYERT
|
|
435643U, // CPYERTN
|
|
435392U, // CPYERTRN
|
|
435890U, // CPYERTWN
|
|
436072U, // CPYET
|
|
435547U, // CPYETN
|
|
435328U, // CPYETRN
|
|
435826U, // CPYETWN
|
|
435768U, // CPYEWN
|
|
436215U, // CPYEWT
|
|
435706U, // CPYEWTN
|
|
435461U, // CPYEWTRN
|
|
435959U, // CPYEWTWN
|
|
435098U, // CPYFE
|
|
435158U, // CPYFEN
|
|
435260U, // CPYFERN
|
|
436148U, // CPYFERT
|
|
435632U, // CPYFERTN
|
|
435380U, // CPYFERTRN
|
|
435878U, // CPYFERTWN
|
|
436046U, // CPYFET
|
|
435518U, // CPYFETN
|
|
435317U, // CPYFETRN
|
|
435815U, // CPYFETWN
|
|
435758U, // CPYFEWN
|
|
436205U, // CPYFEWT
|
|
435695U, // CPYFEWTN
|
|
435449U, // CPYFEWTRN
|
|
435947U, // CPYFEWTWN
|
|
435128U, // CPYFM
|
|
435192U, // CPYFMN
|
|
435279U, // CPYFMRN
|
|
436167U, // CPYFMRT
|
|
435653U, // CPYFMRTN
|
|
435403U, // CPYFMRTRN
|
|
435901U, // CPYFMRTWN
|
|
436080U, // CPYFMT
|
|
435556U, // CPYFMTN
|
|
435338U, // CPYFMTRN
|
|
435836U, // CPYFMTWN
|
|
435777U, // CPYFMWN
|
|
436224U, // CPYFMWT
|
|
435716U, // CPYFMWTN
|
|
435472U, // CPYFMWTRN
|
|
435970U, // CPYFMWTWN
|
|
436016U, // CPYFP
|
|
435226U, // CPYFPN
|
|
435298U, // CPYFPRN
|
|
436186U, // CPYFPRT
|
|
435674U, // CPYFPRTN
|
|
435426U, // CPYFPRTRN
|
|
435924U, // CPYFPRTWN
|
|
436114U, // CPYFPT
|
|
435594U, // CPYFPTN
|
|
435359U, // CPYFPTRN
|
|
435857U, // CPYFPTWN
|
|
435796U, // CPYFPWN
|
|
436243U, // CPYFPWT
|
|
435737U, // CPYFPWTN
|
|
435495U, // CPYFPWTRN
|
|
435993U, // CPYFPWTWN
|
|
435151U, // CPYM
|
|
435218U, // CPYMN
|
|
435289U, // CPYMRN
|
|
436177U, // CPYMRT
|
|
435664U, // CPYMRTN
|
|
435415U, // CPYMRTRN
|
|
435913U, // CPYMRTWN
|
|
436106U, // CPYMT
|
|
435585U, // CPYMTN
|
|
435349U, // CPYMTRN
|
|
435847U, // CPYMTWN
|
|
435787U, // CPYMWN
|
|
436234U, // CPYMWT
|
|
435727U, // CPYMWTN
|
|
435484U, // CPYMWTRN
|
|
435982U, // CPYMWTWN
|
|
436039U, // CPYP
|
|
435252U, // CPYPN
|
|
435308U, // CPYPRN
|
|
436196U, // CPYPRT
|
|
435685U, // CPYPRTN
|
|
435438U, // CPYPRTRN
|
|
435936U, // CPYPRTWN
|
|
436140U, // CPYPT
|
|
435623U, // CPYPTN
|
|
435370U, // CPYPTRN
|
|
435868U, // CPYPTWN
|
|
435806U, // CPYPWN
|
|
436253U, // CPYPWT
|
|
435748U, // CPYPWTN
|
|
435507U, // CPYPWTRN
|
|
436005U, // CPYPWTWN
|
|
270573897U, // CPY_ZPmI_B
|
|
270590281U, // CPY_ZPmI_D
|
|
4268361U, // CPY_ZPmI_H
|
|
270623049U, // CPY_ZPmI_S
|
|
270573897U, // CPY_ZPmR_B
|
|
270590281U, // CPY_ZPmR_D
|
|
272703817U, // CPY_ZPmR_H
|
|
270623049U, // CPY_ZPmR_S
|
|
270573897U, // CPY_ZPmV_B
|
|
270590281U, // CPY_ZPmV_D
|
|
272703817U, // CPY_ZPmV_H
|
|
270623049U, // CPY_ZPmV_S
|
|
3223363913U, // CPY_ZPzI_B
|
|
3223380297U, // CPY_ZPzI_D
|
|
2713788745U, // CPY_ZPzI_H
|
|
3223413065U, // CPY_ZPzI_S
|
|
2114865U, // CRC32Brr
|
|
2115052U, // CRC32CBrr
|
|
2117101U, // CRC32CHrr
|
|
2121684U, // CRC32CWrr
|
|
2121952U, // CRC32CXrr
|
|
2116937U, // CRC32Hrr
|
|
2121626U, // CRC32Wrr
|
|
2121883U, // CRC32Xrr
|
|
2118258U, // CSELWr
|
|
2118258U, // CSELXr
|
|
2116206U, // CSINCWr
|
|
2116206U, // CSINCXr
|
|
2121434U, // CSINVWr
|
|
2121434U, // CSINVXr
|
|
2116845U, // CSNEGWr
|
|
2116845U, // CSNEGXr
|
|
2119651U, // CTERMEQ_WW
|
|
2119651U, // CTERMEQ_XX
|
|
2116686U, // CTERMNE_WW
|
|
2116686U, // CTERMNE_XX
|
|
2122163U, // CTZWr
|
|
2122163U, // CTZXr
|
|
376923U, // DCPS1
|
|
377414U, // DCPS2
|
|
377488U, // DCPS3
|
|
538985975U, // DECB_XPiI
|
|
538987330U, // DECD_XPiI
|
|
539020098U, // DECD_ZPiI
|
|
538988024U, // DECH_XPiI
|
|
56692216U, // DECH_ZPiI
|
|
2119183U, // DECP_XP_B
|
|
2418038287U, // DECP_XP_D
|
|
1881167375U, // DECP_XP_H
|
|
270554639U, // DECP_XP_S
|
|
1075893775U, // DECP_ZP_D
|
|
1658918415U, // DECP_ZP_H
|
|
1344361999U, // DECP_ZP_S
|
|
538992607U, // DECW_XPiI
|
|
539058143U, // DECW_ZPiI
|
|
444368U, // DMB
|
|
10395U, // DRPS
|
|
444719U, // DSB
|
|
461103U, // DSBnXS
|
|
807458015U, // DUPM_ZI
|
|
2136057U, // DUPQ_ZZI_B
|
|
2418071545U, // DUPQ_ZZI_D
|
|
1115756537U, // DUPQ_ZZI_H
|
|
270620665U, // DUPQ_ZZI_S
|
|
1344313186U, // DUP_ZI_B
|
|
1612765026U, // DUP_ZI_D
|
|
58791778U, // DUP_ZI_H
|
|
1881233250U, // DUP_ZI_S
|
|
2135906U, // DUP_ZR_B
|
|
2152290U, // DUP_ZR_D
|
|
1671501666U, // DUP_ZR_H
|
|
2185058U, // DUP_ZR_S
|
|
2135906U, // DUP_ZZI_B
|
|
2418071394U, // DUP_ZZI_D
|
|
1115756386U, // DUP_ZZI_H
|
|
1137137506U, // DUP_ZZI_Q
|
|
270620514U, // DUP_ZZI_S
|
|
807427810U, // DUPi16
|
|
807427810U, // DUPi32
|
|
807427810U, // DUPi64
|
|
807427810U, // DUPi8
|
|
6395746U, // DUPv16i8gpr
|
|
811702114U, // DUPv16i8lane
|
|
8492898U, // DUPv2i32gpr
|
|
813799266U, // DUPv2i32lane
|
|
10590050U, // DUPv2i64gpr
|
|
815896418U, // DUPv2i64lane
|
|
12687202U, // DUPv4i16gpr
|
|
817993570U, // DUPv4i16lane
|
|
14784354U, // DUPv4i32gpr
|
|
820090722U, // DUPv4i32lane
|
|
16881506U, // DUPv8i16gpr
|
|
822187874U, // DUPv8i16lane
|
|
18978658U, // DUPv8i8gpr
|
|
824285026U, // DUPv8i8lane
|
|
2118972U, // EONWrs
|
|
2118972U, // EONXrs
|
|
811696778U, // EOR3
|
|
2418066058U, // EOR3_ZZZZ
|
|
2418055988U, // EORBT_ZZZ_B
|
|
1075895092U, // EORBT_ZZZ_D
|
|
2195790644U, // EORBT_ZZZ_H
|
|
1344363316U, // EORBT_ZZZ_S
|
|
3227623220U, // EORQV_VPZ_B
|
|
3231817524U, // EORQV_VPZ_D
|
|
3238108980U, // EORQV_VPZ_H
|
|
3236011828U, // EORQV_VPZ_S
|
|
3223362251U, // EORS_PPzPP
|
|
2418051485U, // EORTB_ZZZ_B
|
|
1075890589U, // EORTB_ZZZ_D
|
|
2195786141U, // EORTB_ZZZ_H
|
|
1344358813U, // EORTB_ZZZ_S
|
|
253779U, // EORV_VPZ_B
|
|
1657020243U, // EORV_VPZ_D
|
|
1659133779U, // EORV_VPZ_H
|
|
1638178643U, // EORV_VPZ_S
|
|
2119946U, // EORWri
|
|
2119946U, // EORWrs
|
|
2119946U, // EORXri
|
|
2119946U, // EORXrs
|
|
3223361802U, // EOR_PPzPP
|
|
2418071818U, // EOR_ZI
|
|
3223361802U, // EOR_ZPmZ_B
|
|
3223378186U, // EOR_ZPmZ_D
|
|
3519093002U, // EOR_ZPmZ_H
|
|
3223410954U, // EOR_ZPmZ_S
|
|
2418071818U, // EOR_ZZZ
|
|
811702538U, // EORv16i8
|
|
824285450U, // EORv8i8
|
|
10400U, // ERET
|
|
10278U, // ERETAA
|
|
10285U, // ERETAB
|
|
2136063U, // EXTQ_ZZI
|
|
270566596U, // EXTRACT_ZPMXI_H_B
|
|
270582980U, // EXTRACT_ZPMXI_H_D
|
|
2151744708U, // EXTRACT_ZPMXI_H_H
|
|
2152154308U, // EXTRACT_ZPMXI_H_Q
|
|
270615748U, // EXTRACT_ZPMXI_H_S
|
|
270566596U, // EXTRACT_ZPMXI_V_B
|
|
270582980U, // EXTRACT_ZPMXI_V_D
|
|
2420180164U, // EXTRACT_ZPMXI_V_H
|
|
2420589764U, // EXTRACT_ZPMXI_V_Q
|
|
270615748U, // EXTRACT_ZPMXI_V_S
|
|
2120035U, // EXTRWrri
|
|
24863U, // EXTRX
|
|
2120035U, // EXTRXrri
|
|
24910U, // EXTRY
|
|
2137622U, // EXT_ZZI
|
|
2686492182U, // EXT_ZZI_B
|
|
811703830U, // EXTv16i8
|
|
824286742U, // EXTv8i8
|
|
822182291U, // F1CVTL2v8f16
|
|
1661017211U, // F1CVTLT_ZZ_BtoH
|
|
1661129771U, // F1CVTL_2ZZ_BtoH_NAME
|
|
822187051U, // F1CVTLv8f16
|
|
1661132235U, // F1CVT_2ZZ_BtoH_NAME
|
|
1661017547U, // F1CVT_ZZ_BtoH
|
|
822182301U, // F2CVTL2v8f16
|
|
1661017221U, // F2CVTLT_ZZ_BtoH
|
|
1661129780U, // F2CVTL_2ZZ_BtoH_NAME
|
|
822187060U, // F2CVTLv8f16
|
|
1661132243U, // F2CVT_2ZZ_BtoH_NAME
|
|
1661017555U, // F2CVT_ZZ_BtoH
|
|
2116391U, // FABD16
|
|
2116391U, // FABD32
|
|
2116391U, // FABD64
|
|
3223374631U, // FABD_ZPmZ_D
|
|
3519089447U, // FABD_ZPmZ_H
|
|
3223407399U, // FABD_ZPmZ_S
|
|
813796135U, // FABDv2f32
|
|
815893287U, // FABDv2f64
|
|
817990439U, // FABDv4f16
|
|
820087591U, // FABDv4f32
|
|
822184743U, // FABDv8f16
|
|
2120164U, // FABSDr
|
|
2120164U, // FABSHr
|
|
2120164U, // FABSSr
|
|
270588388U, // FABS_ZPmZ_D
|
|
541137380U, // FABS_ZPmZ_H
|
|
270621156U, // FABS_ZPmZ_S
|
|
813799908U, // FABSv2f32
|
|
815897060U, // FABSv2f64
|
|
817994212U, // FABSv4f16
|
|
820091364U, // FABSv4f32
|
|
822188516U, // FABSv8f16
|
|
2116618U, // FACGE16
|
|
2116618U, // FACGE32
|
|
2116618U, // FACGE64
|
|
3223374858U, // FACGE_PPzZZ_D
|
|
2713783306U, // FACGE_PPzZZ_H
|
|
3223407626U, // FACGE_PPzZZ_S
|
|
813796362U, // FACGEv2f32
|
|
815893514U, // FACGEv2f64
|
|
817990666U, // FACGEv4f16
|
|
820087818U, // FACGEv4f32
|
|
822184970U, // FACGEv8f16
|
|
2120551U, // FACGT16
|
|
2120551U, // FACGT32
|
|
2120551U, // FACGT64
|
|
3223378791U, // FACGT_PPzZZ_D
|
|
2713787239U, // FACGT_PPzZZ_H
|
|
3223411559U, // FACGT_PPzZZ_S
|
|
813800295U, // FACGTv2f32
|
|
815897447U, // FACGTv2f64
|
|
817994599U, // FACGTv4f16
|
|
820091751U, // FACGTv4f32
|
|
822188903U, // FACGTv8f16
|
|
65274670U, // FADDA_VPZ_D
|
|
2214871854U, // FADDA_VPZ_H
|
|
69501742U, // FADDA_VPZ_S
|
|
2116471U, // FADDDrr
|
|
2116471U, // FADDHrr
|
|
3223377453U, // FADDP_ZPmZZ_D
|
|
3519092269U, // FADDP_ZPmZZ_H
|
|
3223410221U, // FADDP_ZPmZZ_S
|
|
813798957U, // FADDPv2f32
|
|
815896109U, // FADDPv2f64
|
|
807425581U, // FADDPv2i16p
|
|
807425581U, // FADDPv2i32p
|
|
807425581U, // FADDPv2i64p
|
|
817993261U, // FADDPv4f16
|
|
820090413U, // FADDPv4f32
|
|
822187565U, // FADDPv8f16
|
|
3231817465U, // FADDQV_D
|
|
3238108921U, // FADDQV_H
|
|
3236011769U, // FADDQV_S
|
|
2116471U, // FADDSrr
|
|
1657020017U, // FADDV_VPZ_D
|
|
1659133553U, // FADDV_VPZ_H
|
|
1638178417U, // FADDV_VPZ_S
|
|
3798158199U, // FADD_VG2_M2Z_D
|
|
3798305655U, // FADD_VG2_M2Z_H
|
|
3798174583U, // FADD_VG2_M2Z_S
|
|
4066593655U, // FADD_VG4_M4Z_D
|
|
4066741111U, // FADD_VG4_M4Z_H
|
|
4066610039U, // FADD_VG4_M4Z_S
|
|
3223374711U, // FADD_ZPmI_D
|
|
3519089527U, // FADD_ZPmI_H
|
|
3223407479U, // FADD_ZPmI_S
|
|
3223374711U, // FADD_ZPmZ_D
|
|
3519089527U, // FADD_ZPmZ_H
|
|
3223407479U, // FADD_ZPmZ_S
|
|
2418068343U, // FADD_ZZZ_D
|
|
2189495159U, // FADD_ZZZ_H
|
|
270617463U, // FADD_ZZZ_S
|
|
813796215U, // FADDv2f32
|
|
815893367U, // FADDv2f64
|
|
817990519U, // FADDv4f16
|
|
820087671U, // FADDv4f32
|
|
822184823U, // FADDv8f16
|
|
2181210301U, // FAMAX_2Z2Z_D
|
|
2183323837U, // FAMAX_2Z2Z_H
|
|
2185437373U, // FAMAX_2Z2Z_S
|
|
2181210301U, // FAMAX_4Z4Z_D
|
|
2183323837U, // FAMAX_4Z4Z_H
|
|
2185437373U, // FAMAX_4Z4Z_S
|
|
3223380157U, // FAMAX_ZPmZ_D
|
|
3519094973U, // FAMAX_ZPmZ_H
|
|
3223412925U, // FAMAX_ZPmZ_S
|
|
813801661U, // FAMAXv2f32
|
|
815898813U, // FAMAXv2f64
|
|
817995965U, // FAMAXv4f16
|
|
820093117U, // FAMAXv4f32
|
|
822190269U, // FAMAXv8f16
|
|
2181207314U, // FAMIN_2Z2Z_D
|
|
2183320850U, // FAMIN_2Z2Z_H
|
|
2185434386U, // FAMIN_2Z2Z_S
|
|
2181207314U, // FAMIN_4Z4Z_D
|
|
2183320850U, // FAMIN_4Z4Z_H
|
|
2185434386U, // FAMIN_4Z4Z_S
|
|
3223377170U, // FAMIN_ZPmZ_D
|
|
3519091986U, // FAMIN_ZPmZ_H
|
|
3223409938U, // FAMIN_ZPmZ_S
|
|
813798674U, // FAMINv2f32
|
|
815895826U, // FAMINv2f64
|
|
817992978U, // FAMINv4f16
|
|
820090130U, // FAMINv4f32
|
|
822187282U, // FAMINv8f16
|
|
3223374688U, // FCADD_ZPmZ_D
|
|
3519089504U, // FCADD_ZPmZ_H
|
|
3223407456U, // FCADD_ZPmZ_S
|
|
813796192U, // FCADDv2f32
|
|
815893344U, // FCADDv2f64
|
|
817990496U, // FCADDv4f16
|
|
820087648U, // FCADDv4f32
|
|
822184800U, // FCADDv8f16
|
|
2119320U, // FCCMPDrr
|
|
2116718U, // FCCMPEDrr
|
|
2116718U, // FCCMPEHrr
|
|
2116718U, // FCCMPESrr
|
|
2119320U, // FCCMPHrr
|
|
2119320U, // FCCMPSrr
|
|
2193790592U, // FCLAMP_VG2_2Z2Z_D
|
|
2195904128U, // FCLAMP_VG2_2Z2Z_H
|
|
2174948992U, // FCLAMP_VG2_2Z2Z_S
|
|
2193790592U, // FCLAMP_VG4_4Z4Z_D
|
|
2195904128U, // FCLAMP_VG4_4Z4Z_H
|
|
2174948992U, // FCLAMP_VG4_4Z4Z_S
|
|
1075893888U, // FCLAMP_ZZZ_D
|
|
2195789440U, // FCLAMP_ZZZ_H
|
|
1344362112U, // FCLAMP_ZZZ_S
|
|
2119644U, // FCMEQ16
|
|
2119644U, // FCMEQ32
|
|
2119644U, // FCMEQ64
|
|
3223377884U, // FCMEQ_PPzZ0_D
|
|
2713786332U, // FCMEQ_PPzZ0_H
|
|
3223410652U, // FCMEQ_PPzZ0_S
|
|
3223377884U, // FCMEQ_PPzZZ_D
|
|
2713786332U, // FCMEQ_PPzZZ_H
|
|
3223410652U, // FCMEQ_PPzZZ_S
|
|
2119644U, // FCMEQv1i16rz
|
|
2119644U, // FCMEQv1i32rz
|
|
2119644U, // FCMEQv1i64rz
|
|
813799388U, // FCMEQv2f32
|
|
815896540U, // FCMEQv2f64
|
|
813799388U, // FCMEQv2i32rz
|
|
815896540U, // FCMEQv2i64rz
|
|
817993692U, // FCMEQv4f16
|
|
820090844U, // FCMEQv4f32
|
|
817993692U, // FCMEQv4i16rz
|
|
820090844U, // FCMEQv4i32rz
|
|
822187996U, // FCMEQv8f16
|
|
822187996U, // FCMEQv8i16rz
|
|
2116634U, // FCMGE16
|
|
2116634U, // FCMGE32
|
|
2116634U, // FCMGE64
|
|
3223374874U, // FCMGE_PPzZ0_D
|
|
2713783322U, // FCMGE_PPzZ0_H
|
|
3223407642U, // FCMGE_PPzZ0_S
|
|
3223374874U, // FCMGE_PPzZZ_D
|
|
2713783322U, // FCMGE_PPzZZ_H
|
|
3223407642U, // FCMGE_PPzZZ_S
|
|
2116634U, // FCMGEv1i16rz
|
|
2116634U, // FCMGEv1i32rz
|
|
2116634U, // FCMGEv1i64rz
|
|
813796378U, // FCMGEv2f32
|
|
815893530U, // FCMGEv2f64
|
|
813796378U, // FCMGEv2i32rz
|
|
815893530U, // FCMGEv2i64rz
|
|
817990682U, // FCMGEv4f16
|
|
820087834U, // FCMGEv4f32
|
|
817990682U, // FCMGEv4i16rz
|
|
820087834U, // FCMGEv4i32rz
|
|
822184986U, // FCMGEv8f16
|
|
822184986U, // FCMGEv8i16rz
|
|
2120567U, // FCMGT16
|
|
2120567U, // FCMGT32
|
|
2120567U, // FCMGT64
|
|
3223378807U, // FCMGT_PPzZ0_D
|
|
2713787255U, // FCMGT_PPzZ0_H
|
|
3223411575U, // FCMGT_PPzZ0_S
|
|
3223378807U, // FCMGT_PPzZZ_D
|
|
2713787255U, // FCMGT_PPzZZ_H
|
|
3223411575U, // FCMGT_PPzZZ_S
|
|
2120567U, // FCMGTv1i16rz
|
|
2120567U, // FCMGTv1i32rz
|
|
2120567U, // FCMGTv1i64rz
|
|
813800311U, // FCMGTv2f32
|
|
815897463U, // FCMGTv2f64
|
|
813800311U, // FCMGTv2i32rz
|
|
815897463U, // FCMGTv2i64rz
|
|
817994615U, // FCMGTv4f16
|
|
820091767U, // FCMGTv4f32
|
|
817994615U, // FCMGTv4i16rz
|
|
820091767U, // FCMGTv4i32rz
|
|
822188919U, // FCMGTv8f16
|
|
822188919U, // FCMGTv8i16rz
|
|
3223372638U, // FCMLA_ZPmZZ_D
|
|
3519087454U, // FCMLA_ZPmZZ_H
|
|
3223405406U, // FCMLA_ZPmZZ_S
|
|
2195784542U, // FCMLA_ZZZI_H
|
|
1344357214U, // FCMLA_ZZZI_S
|
|
2961310558U, // FCMLAv2f32
|
|
2963407710U, // FCMLAv2f64
|
|
2965504862U, // FCMLAv4f16
|
|
2965504862U, // FCMLAv4f16_indexed
|
|
2967602014U, // FCMLAv4f32
|
|
2967602014U, // FCMLAv4f32_indexed
|
|
2969699166U, // FCMLAv8f16
|
|
2969699166U, // FCMLAv8f16_indexed
|
|
3223374905U, // FCMLE_PPzZ0_D
|
|
2713783353U, // FCMLE_PPzZ0_H
|
|
3223407673U, // FCMLE_PPzZ0_S
|
|
2116665U, // FCMLEv1i16rz
|
|
2116665U, // FCMLEv1i32rz
|
|
2116665U, // FCMLEv1i64rz
|
|
813796409U, // FCMLEv2i32rz
|
|
815893561U, // FCMLEv2i64rz
|
|
817990713U, // FCMLEv4i16rz
|
|
820087865U, // FCMLEv4i32rz
|
|
822185017U, // FCMLEv8i16rz
|
|
3223379017U, // FCMLT_PPzZ0_D
|
|
2713787465U, // FCMLT_PPzZ0_H
|
|
3223411785U, // FCMLT_PPzZ0_S
|
|
2120777U, // FCMLTv1i16rz
|
|
2120777U, // FCMLTv1i32rz
|
|
2120777U, // FCMLTv1i64rz
|
|
813800521U, // FCMLTv2i32rz
|
|
815897673U, // FCMLTv2i64rz
|
|
817994825U, // FCMLTv4i16rz
|
|
820091977U, // FCMLTv4i32rz
|
|
822189129U, // FCMLTv8i16rz
|
|
3223374919U, // FCMNE_PPzZ0_D
|
|
2713783367U, // FCMNE_PPzZ0_H
|
|
3223407687U, // FCMNE_PPzZ0_S
|
|
3223374919U, // FCMNE_PPzZZ_D
|
|
2713783367U, // FCMNE_PPzZZ_H
|
|
3223407687U, // FCMNE_PPzZZ_S
|
|
71325343U, // FCMPDri
|
|
2119327U, // FCMPDrr
|
|
71322742U, // FCMPEDri
|
|
2116726U, // FCMPEDrr
|
|
71322742U, // FCMPEHri
|
|
2116726U, // FCMPEHrr
|
|
71322742U, // FCMPESri
|
|
2116726U, // FCMPESrr
|
|
71325343U, // FCMPHri
|
|
2119327U, // FCMPHrr
|
|
71325343U, // FCMPSri
|
|
2119327U, // FCMPSrr
|
|
3223377401U, // FCMUO_PPzZZ_D
|
|
2713785849U, // FCMUO_PPzZZ_H
|
|
3223410169U, // FCMUO_PPzZZ_S
|
|
270590280U, // FCPY_ZPmI_D
|
|
2957058376U, // FCPY_ZPmI_H
|
|
270623048U, // FCPY_ZPmI_S
|
|
2118257U, // FCSELDrrr
|
|
2118257U, // FCSELHrrr
|
|
2118257U, // FCSELSrrr
|
|
2120156U, // FCVTASUWDr
|
|
2120156U, // FCVTASUWHr
|
|
2120156U, // FCVTASUWSr
|
|
2120156U, // FCVTASUXDr
|
|
2120156U, // FCVTASUXHr
|
|
2120156U, // FCVTASUXSr
|
|
2120156U, // FCVTASv1f16
|
|
2120156U, // FCVTASv1i32
|
|
2120156U, // FCVTASv1i64
|
|
813799900U, // FCVTASv2f32
|
|
815897052U, // FCVTASv2f64
|
|
817994204U, // FCVTASv4f16
|
|
820091356U, // FCVTASv4f32
|
|
822188508U, // FCVTASv8f16
|
|
2121256U, // FCVTAUUWDr
|
|
2121256U, // FCVTAUUWHr
|
|
2121256U, // FCVTAUUWSr
|
|
2121256U, // FCVTAUUXDr
|
|
2121256U, // FCVTAUUXHr
|
|
2121256U, // FCVTAUUXSr
|
|
2121256U, // FCVTAUv1f16
|
|
2121256U, // FCVTAUv1i32
|
|
2121256U, // FCVTAUv1i64
|
|
813801000U, // FCVTAUv2f32
|
|
815898152U, // FCVTAUv2f64
|
|
817995304U, // FCVTAUv4f16
|
|
820092456U, // FCVTAUv4f32
|
|
822189608U, // FCVTAUv8f16
|
|
2121179U, // FCVTDHr
|
|
2121179U, // FCVTDSr
|
|
2121179U, // FCVTHDr
|
|
2121179U, // FCVTHSr
|
|
270621838U, // FCVTLT_ZPmZ_HtoS
|
|
270589070U, // FCVTLT_ZPmZ_StoD
|
|
1652757564U, // FCVTL_2ZZ_H_S
|
|
815895612U, // FCVTLv2i32
|
|
820089916U, // FCVTLv4i16
|
|
815890854U, // FCVTLv4i32
|
|
820085158U, // FCVTLv8i16
|
|
2120294U, // FCVTMSUWDr
|
|
2120294U, // FCVTMSUWHr
|
|
2120294U, // FCVTMSUWSr
|
|
2120294U, // FCVTMSUXDr
|
|
2120294U, // FCVTMSUXHr
|
|
2120294U, // FCVTMSUXSr
|
|
2120294U, // FCVTMSv1f16
|
|
2120294U, // FCVTMSv1i32
|
|
2120294U, // FCVTMSv1i64
|
|
813800038U, // FCVTMSv2f32
|
|
815897190U, // FCVTMSv2f64
|
|
817994342U, // FCVTMSv4f16
|
|
820091494U, // FCVTMSv4f32
|
|
822188646U, // FCVTMSv8f16
|
|
2121272U, // FCVTMUUWDr
|
|
2121272U, // FCVTMUUWHr
|
|
2121272U, // FCVTMUUWSr
|
|
2121272U, // FCVTMUUXDr
|
|
2121272U, // FCVTMUUXHr
|
|
2121272U, // FCVTMUUXSr
|
|
2121272U, // FCVTMUv1f16
|
|
2121272U, // FCVTMUv1i32
|
|
2121272U, // FCVTMUv1i64
|
|
813801016U, // FCVTMUv2f32
|
|
815898168U, // FCVTMUv2f64
|
|
817995320U, // FCVTMUv4f16
|
|
820092472U, // FCVTMUv4f32
|
|
822189624U, // FCVTMUv8f16
|
|
3223357471U, // FCVTNB_Z2Z_StoB
|
|
2120320U, // FCVTNSUWDr
|
|
2120320U, // FCVTNSUWHr
|
|
2120320U, // FCVTNSUWSr
|
|
2120320U, // FCVTNSUXDr
|
|
2120320U, // FCVTNSUXHr
|
|
2120320U, // FCVTNSUXSr
|
|
2120320U, // FCVTNSv1f16
|
|
2120320U, // FCVTNSv1i32
|
|
2120320U, // FCVTNSv1i64
|
|
813800064U, // FCVTNSv2f32
|
|
815897216U, // FCVTNSv2f64
|
|
817994368U, // FCVTNSv4f16
|
|
820091520U, // FCVTNSv4f32
|
|
822188672U, // FCVTNSv8f16
|
|
3223362798U, // FCVTNT_Z2Z_StoB
|
|
270621934U, // FCVTNT_ZPmZ_DtoS
|
|
1078009070U, // FCVTNT_ZPmZ_StoH
|
|
2121280U, // FCVTNUUWDr
|
|
2121280U, // FCVTNUUWHr
|
|
2121280U, // FCVTNUUWSr
|
|
2121280U, // FCVTNUUXDr
|
|
2121280U, // FCVTNUUXHr
|
|
2121280U, // FCVTNUUXSr
|
|
2121280U, // FCVTNUv1f16
|
|
2121280U, // FCVTNUv1i32
|
|
2121280U, // FCVTNUv1i64
|
|
813801024U, // FCVTNUv2f32
|
|
815898176U, // FCVTNUv2f64
|
|
817995328U, // FCVTNUv4f16
|
|
820092480U, // FCVTNUv4f32
|
|
822189632U, // FCVTNUv8f16
|
|
811701617U, // FCVTN_F16_F8v16f8
|
|
824284529U, // FCVTN_F16_F8v8f8
|
|
2959213037U, // FCVTN_F32_F82v16f8
|
|
824284529U, // FCVTN_F32_F8v8f8
|
|
1344312689U, // FCVTN_Z2Z_HtoB
|
|
1648432497U, // FCVTN_Z2Z_StoH
|
|
3223360881U, // FCVTN_Z4Z_StoB_NAME
|
|
813798769U, // FCVTNv2i32
|
|
817993073U, // FCVTNv4i16
|
|
2967601645U, // FCVTNv4i32
|
|
2969698797U, // FCVTNv8i16
|
|
2120374U, // FCVTPSUWDr
|
|
2120374U, // FCVTPSUWHr
|
|
2120374U, // FCVTPSUWSr
|
|
2120374U, // FCVTPSUXDr
|
|
2120374U, // FCVTPSUXHr
|
|
2120374U, // FCVTPSUXSr
|
|
2120374U, // FCVTPSv1f16
|
|
2120374U, // FCVTPSv1i32
|
|
2120374U, // FCVTPSv1i64
|
|
813800118U, // FCVTPSv2f32
|
|
815897270U, // FCVTPSv2f64
|
|
817994422U, // FCVTPSv4f16
|
|
820091574U, // FCVTPSv4f32
|
|
822188726U, // FCVTPSv8f16
|
|
2121288U, // FCVTPUUWDr
|
|
2121288U, // FCVTPUUWHr
|
|
2121288U, // FCVTPUUWSr
|
|
2121288U, // FCVTPUUXDr
|
|
2121288U, // FCVTPUUXHr
|
|
2121288U, // FCVTPUUXSr
|
|
2121288U, // FCVTPUv1f16
|
|
2121288U, // FCVTPUv1i32
|
|
2121288U, // FCVTPUv1i64
|
|
813801032U, // FCVTPUv2f32
|
|
815898184U, // FCVTPUv2f64
|
|
817995336U, // FCVTPUv4f16
|
|
820092488U, // FCVTPUv4f32
|
|
822189640U, // FCVTPUv8f16
|
|
2121179U, // FCVTSDr
|
|
2121179U, // FCVTSHr
|
|
270621988U, // FCVTXNT_ZPmZ_DtoS
|
|
2119104U, // FCVTXNv1i64
|
|
813798848U, // FCVTXNv2f32
|
|
2967601699U, // FCVTXNv4f32
|
|
270623027U, // FCVTX_ZPmZ_DtoS
|
|
2120433U, // FCVTZSSWDri
|
|
2120433U, // FCVTZSSWHri
|
|
2120433U, // FCVTZSSWSri
|
|
2120433U, // FCVTZSSXDri
|
|
2120433U, // FCVTZSSXHri
|
|
2120433U, // FCVTZSSXSri
|
|
2120433U, // FCVTZSUWDr
|
|
2120433U, // FCVTZSUWHr
|
|
2120433U, // FCVTZSUWSr
|
|
2120433U, // FCVTZSUXDr
|
|
2120433U, // FCVTZSUXHr
|
|
2120433U, // FCVTZSUXSr
|
|
1648564977U, // FCVTZS_2Z2Z_StoS
|
|
1648564977U, // FCVTZS_4Z4Z_StoS
|
|
270588657U, // FCVTZS_ZPmZ_DtoD
|
|
270621425U, // FCVTZS_ZPmZ_DtoS
|
|
270588657U, // FCVTZS_ZPmZ_HtoD
|
|
541137649U, // FCVTZS_ZPmZ_HtoH
|
|
270621425U, // FCVTZS_ZPmZ_HtoS
|
|
270588657U, // FCVTZS_ZPmZ_StoD
|
|
270621425U, // FCVTZS_ZPmZ_StoS
|
|
2120433U, // FCVTZSd
|
|
2120433U, // FCVTZSh
|
|
2120433U, // FCVTZSs
|
|
2120433U, // FCVTZSv1f16
|
|
2120433U, // FCVTZSv1i32
|
|
2120433U, // FCVTZSv1i64
|
|
813800177U, // FCVTZSv2f32
|
|
815897329U, // FCVTZSv2f64
|
|
813800177U, // FCVTZSv2i32_shift
|
|
815897329U, // FCVTZSv2i64_shift
|
|
817994481U, // FCVTZSv4f16
|
|
820091633U, // FCVTZSv4f32
|
|
817994481U, // FCVTZSv4i16_shift
|
|
820091633U, // FCVTZSv4i32_shift
|
|
822188785U, // FCVTZSv8f16
|
|
822188785U, // FCVTZSv8i16_shift
|
|
2121313U, // FCVTZUSWDri
|
|
2121313U, // FCVTZUSWHri
|
|
2121313U, // FCVTZUSWSri
|
|
2121313U, // FCVTZUSXDri
|
|
2121313U, // FCVTZUSXHri
|
|
2121313U, // FCVTZUSXSri
|
|
2121313U, // FCVTZUUWDr
|
|
2121313U, // FCVTZUUWHr
|
|
2121313U, // FCVTZUUWSr
|
|
2121313U, // FCVTZUUXDr
|
|
2121313U, // FCVTZUUXHr
|
|
2121313U, // FCVTZUUXSr
|
|
1648565857U, // FCVTZU_2Z2Z_StoS
|
|
1648565857U, // FCVTZU_4Z4Z_StoS
|
|
270589537U, // FCVTZU_ZPmZ_DtoD
|
|
270622305U, // FCVTZU_ZPmZ_DtoS
|
|
270589537U, // FCVTZU_ZPmZ_HtoD
|
|
541138529U, // FCVTZU_ZPmZ_HtoH
|
|
270622305U, // FCVTZU_ZPmZ_HtoS
|
|
270589537U, // FCVTZU_ZPmZ_StoD
|
|
270622305U, // FCVTZU_ZPmZ_StoS
|
|
2121313U, // FCVTZUd
|
|
2121313U, // FCVTZUh
|
|
2121313U, // FCVTZUs
|
|
2121313U, // FCVTZUv1f16
|
|
2121313U, // FCVTZUv1i32
|
|
2121313U, // FCVTZUv1i64
|
|
813801057U, // FCVTZUv2f32
|
|
815898209U, // FCVTZUv2f64
|
|
813801057U, // FCVTZUv2i32_shift
|
|
815898209U, // FCVTZUv2i64_shift
|
|
817995361U, // FCVTZUv4f16
|
|
820092513U, // FCVTZUv4f32
|
|
817995361U, // FCVTZUv4i16_shift
|
|
820092513U, // FCVTZUv4i32_shift
|
|
822189665U, // FCVTZUv8f16
|
|
822189665U, // FCVTZUv8i16_shift
|
|
1652760027U, // FCVT_2ZZ_H_S
|
|
1344314843U, // FCVT_Z2Z_HtoB
|
|
1648434651U, // FCVT_Z2Z_StoH
|
|
3223363035U, // FCVT_Z4Z_StoB_NAME
|
|
3493928411U, // FCVT_ZPmZ_DtoH
|
|
270622171U, // FCVT_ZPmZ_DtoS
|
|
270589403U, // FCVT_ZPmZ_HtoD
|
|
270622171U, // FCVT_ZPmZ_HtoS
|
|
270589403U, // FCVT_ZPmZ_StoD
|
|
1078009307U, // FCVT_ZPmZ_StoH
|
|
2121361U, // FDIVDrr
|
|
2121361U, // FDIVHrr
|
|
3223378308U, // FDIVR_ZPmZ_D
|
|
3519093124U, // FDIVR_ZPmZ_H
|
|
3223411076U, // FDIVR_ZPmZ_S
|
|
2121361U, // FDIVSrr
|
|
3223379601U, // FDIV_ZPmZ_D
|
|
3519094417U, // FDIV_ZPmZ_H
|
|
3223412369U, // FDIV_ZPmZ_S
|
|
813801105U, // FDIVv2f32
|
|
815898257U, // FDIVv2f64
|
|
817995409U, // FDIVv4f16
|
|
820092561U, // FDIVv4f32
|
|
822189713U, // FDIVv8f16
|
|
3798310196U, // FDOT_VG2_M2Z2Z_BtoH
|
|
3798179124U, // FDOT_VG2_M2Z2Z_BtoS
|
|
3798179124U, // FDOT_VG2_M2Z2Z_HtoS
|
|
3798310196U, // FDOT_VG2_M2ZZI_BtoH
|
|
3798179124U, // FDOT_VG2_M2ZZI_BtoS
|
|
3798179124U, // FDOT_VG2_M2ZZI_HtoS
|
|
3798310196U, // FDOT_VG2_M2ZZ_BtoH
|
|
3798179124U, // FDOT_VG2_M2ZZ_BtoS
|
|
3798179124U, // FDOT_VG2_M2ZZ_HtoS
|
|
4066745652U, // FDOT_VG4_M4Z4Z_BtoH
|
|
4066614580U, // FDOT_VG4_M4Z4Z_BtoS
|
|
4066614580U, // FDOT_VG4_M4Z4Z_HtoS
|
|
4066745652U, // FDOT_VG4_M4ZZI_BtoH
|
|
4066614580U, // FDOT_VG4_M4ZZI_BtoS
|
|
4066614580U, // FDOT_VG4_M4ZZI_HtoS
|
|
4066745652U, // FDOT_VG4_M4ZZ_BtoH
|
|
4066614580U, // FDOT_VG4_M4ZZ_BtoS
|
|
4066614580U, // FDOT_VG4_M4ZZ_HtoS
|
|
2220956980U, // FDOT_ZZZI_BtoH
|
|
2418105652U, // FDOT_ZZZI_BtoS
|
|
2686541108U, // FDOT_ZZZI_S
|
|
2220956980U, // FDOT_ZZZ_BtoH
|
|
2418105652U, // FDOT_ZZZ_BtoS
|
|
2686541108U, // FDOT_ZZZ_S
|
|
2967608628U, // FDOTlanev16f8
|
|
2965511476U, // FDOTlanev4f16
|
|
2969705780U, // FDOTlanev8f16
|
|
2961317172U, // FDOTlanev8f8
|
|
2961317172U, // FDOTv2f32
|
|
2965511476U, // FDOTv4f16
|
|
2967608628U, // FDOTv4f32
|
|
2969705780U, // FDOTv8f16
|
|
3760248673U, // FDUP_ZI_D
|
|
75568993U, // FDUP_ZI_H
|
|
3760281441U, // FDUP_ZI_S
|
|
2418066491U, // FEXPA_ZZ_D
|
|
1652622395U, // FEXPA_ZZ_H
|
|
270615611U, // FEXPA_ZZ_S
|
|
2120441U, // FJCVTZS
|
|
270583345U, // FLOGB_ZPmZ_D
|
|
541132337U, // FLOGB_ZPmZ_H
|
|
270616113U, // FLOGB_ZPmZ_S
|
|
17090U, // FMA16
|
|
16551U, // FMA32
|
|
17052U, // FMA64
|
|
2116507U, // FMADDDrrr
|
|
2116507U, // FMADDHrrr
|
|
2116507U, // FMADDSrrr
|
|
3223374611U, // FMAD_ZPmZZ_D
|
|
3519089427U, // FMAD_ZPmZZ_H
|
|
3223407379U, // FMAD_ZPmZZ_S
|
|
2121925U, // FMAXDrr
|
|
2121925U, // FMAXHrr
|
|
2118862U, // FMAXNMDrr
|
|
2118862U, // FMAXNMHrr
|
|
3223377582U, // FMAXNMP_ZPmZZ_D
|
|
3519092398U, // FMAXNMP_ZPmZZ_H
|
|
3223410350U, // FMAXNMP_ZPmZZ_S
|
|
813799086U, // FMAXNMPv2f32
|
|
815896238U, // FMAXNMPv2f64
|
|
807425710U, // FMAXNMPv2i16p
|
|
807425710U, // FMAXNMPv2i32p
|
|
807425710U, // FMAXNMPv2i64p
|
|
817993390U, // FMAXNMPv4f16
|
|
820090542U, // FMAXNMPv4f32
|
|
822187694U, // FMAXNMPv8f16
|
|
3231817490U, // FMAXNMQV_D
|
|
3238108946U, // FMAXNMQV_H
|
|
3236011794U, // FMAXNMQV_S
|
|
2118862U, // FMAXNMSrr
|
|
1657020092U, // FMAXNMV_VPZ_D
|
|
1659133628U, // FMAXNMV_VPZ_H
|
|
1638178492U, // FMAXNMV_VPZ_S
|
|
807427772U, // FMAXNMVv4i16v
|
|
807427772U, // FMAXNMVv4i32v
|
|
807427772U, // FMAXNMVv8i16v
|
|
2181207246U, // FMAXNM_VG2_2Z2Z_D
|
|
2183320782U, // FMAXNM_VG2_2Z2Z_H
|
|
2185434318U, // FMAXNM_VG2_2Z2Z_S
|
|
2181207246U, // FMAXNM_VG2_2ZZ_D
|
|
2183320782U, // FMAXNM_VG2_2ZZ_H
|
|
2185434318U, // FMAXNM_VG2_2ZZ_S
|
|
2181207246U, // FMAXNM_VG4_4Z4Z_D
|
|
2183320782U, // FMAXNM_VG4_4Z4Z_H
|
|
2185434318U, // FMAXNM_VG4_4Z4Z_S
|
|
2181207246U, // FMAXNM_VG4_4ZZ_D
|
|
2183320782U, // FMAXNM_VG4_4ZZ_H
|
|
2185434318U, // FMAXNM_VG4_4ZZ_S
|
|
3223377102U, // FMAXNM_ZPmI_D
|
|
3519091918U, // FMAXNM_ZPmI_H
|
|
3223409870U, // FMAXNM_ZPmI_S
|
|
3223377102U, // FMAXNM_ZPmZ_D
|
|
3519091918U, // FMAXNM_ZPmZ_H
|
|
3223409870U, // FMAXNM_ZPmZ_S
|
|
813798606U, // FMAXNMv2f32
|
|
815895758U, // FMAXNMv2f64
|
|
817992910U, // FMAXNMv4f16
|
|
820090062U, // FMAXNMv4f32
|
|
822187214U, // FMAXNMv8f16
|
|
3223377791U, // FMAXP_ZPmZZ_D
|
|
3519092607U, // FMAXP_ZPmZZ_H
|
|
3223410559U, // FMAXP_ZPmZZ_S
|
|
813799295U, // FMAXPv2f32
|
|
815896447U, // FMAXPv2f64
|
|
807425919U, // FMAXPv2i16p
|
|
807425919U, // FMAXPv2i32p
|
|
807425919U, // FMAXPv2i64p
|
|
817993599U, // FMAXPv4f16
|
|
820090751U, // FMAXPv4f32
|
|
822187903U, // FMAXPv8f16
|
|
3231817531U, // FMAXQV_D
|
|
3238108987U, // FMAXQV_H
|
|
3236011835U, // FMAXQV_S
|
|
2121925U, // FMAXSrr
|
|
1657020249U, // FMAXV_VPZ_D
|
|
1659133785U, // FMAXV_VPZ_H
|
|
1638178649U, // FMAXV_VPZ_S
|
|
807427929U, // FMAXVv4i16v
|
|
807427929U, // FMAXVv4i32v
|
|
807427929U, // FMAXVv8i16v
|
|
2181210309U, // FMAX_VG2_2Z2Z_D
|
|
2183323845U, // FMAX_VG2_2Z2Z_H
|
|
2185437381U, // FMAX_VG2_2Z2Z_S
|
|
2181210309U, // FMAX_VG2_2ZZ_D
|
|
2183323845U, // FMAX_VG2_2ZZ_H
|
|
2185437381U, // FMAX_VG2_2ZZ_S
|
|
2181210309U, // FMAX_VG4_4Z4Z_D
|
|
2183323845U, // FMAX_VG4_4Z4Z_H
|
|
2185437381U, // FMAX_VG4_4Z4Z_S
|
|
2181210309U, // FMAX_VG4_4ZZ_D
|
|
2183323845U, // FMAX_VG4_4ZZ_H
|
|
2185437381U, // FMAX_VG4_4ZZ_S
|
|
3223380165U, // FMAX_ZPmI_D
|
|
3519094981U, // FMAX_ZPmI_H
|
|
3223412933U, // FMAX_ZPmI_S
|
|
3223380165U, // FMAX_ZPmZ_D
|
|
3519094981U, // FMAX_ZPmZ_H
|
|
3223412933U, // FMAX_ZPmZ_S
|
|
813801669U, // FMAXv2f32
|
|
815898821U, // FMAXv2f64
|
|
817995973U, // FMAXv4f16
|
|
820093125U, // FMAXv4f32
|
|
822190277U, // FMAXv8f16
|
|
2118938U, // FMINDrr
|
|
2118938U, // FMINHrr
|
|
2118853U, // FMINNMDrr
|
|
2118853U, // FMINNMHrr
|
|
3223377573U, // FMINNMP_ZPmZZ_D
|
|
3519092389U, // FMINNMP_ZPmZZ_H
|
|
3223410341U, // FMINNMP_ZPmZZ_S
|
|
813799077U, // FMINNMPv2f32
|
|
815896229U, // FMINNMPv2f64
|
|
807425701U, // FMINNMPv2i16p
|
|
807425701U, // FMINNMPv2i32p
|
|
807425701U, // FMINNMPv2i64p
|
|
817993381U, // FMINNMPv4f16
|
|
820090533U, // FMINNMPv4f32
|
|
822187685U, // FMINNMPv8f16
|
|
3231817480U, // FMINNMQV_D
|
|
3238108936U, // FMINNMQV_H
|
|
3236011784U, // FMINNMQV_S
|
|
2118853U, // FMINNMSrr
|
|
1657020083U, // FMINNMV_VPZ_D
|
|
1659133619U, // FMINNMV_VPZ_H
|
|
1638178483U, // FMINNMV_VPZ_S
|
|
807427763U, // FMINNMVv4i16v
|
|
807427763U, // FMINNMVv4i32v
|
|
807427763U, // FMINNMVv8i16v
|
|
2181207237U, // FMINNM_VG2_2Z2Z_D
|
|
2183320773U, // FMINNM_VG2_2Z2Z_H
|
|
2185434309U, // FMINNM_VG2_2Z2Z_S
|
|
2181207237U, // FMINNM_VG2_2ZZ_D
|
|
2183320773U, // FMINNM_VG2_2ZZ_H
|
|
2185434309U, // FMINNM_VG2_2ZZ_S
|
|
2181207237U, // FMINNM_VG4_4Z4Z_D
|
|
2183320773U, // FMINNM_VG4_4Z4Z_H
|
|
2185434309U, // FMINNM_VG4_4Z4Z_S
|
|
2181207237U, // FMINNM_VG4_4ZZ_D
|
|
2183320773U, // FMINNM_VG4_4ZZ_H
|
|
2185434309U, // FMINNM_VG4_4ZZ_S
|
|
3223377093U, // FMINNM_ZPmI_D
|
|
3519091909U, // FMINNM_ZPmI_H
|
|
3223409861U, // FMINNM_ZPmI_S
|
|
3223377093U, // FMINNM_ZPmZ_D
|
|
3519091909U, // FMINNM_ZPmZ_H
|
|
3223409861U, // FMINNM_ZPmZ_S
|
|
813798597U, // FMINNMv2f32
|
|
815895749U, // FMINNMv2f64
|
|
817992901U, // FMINNMv4f16
|
|
820090053U, // FMINNMv4f32
|
|
822187205U, // FMINNMv8f16
|
|
3223377597U, // FMINP_ZPmZZ_D
|
|
3519092413U, // FMINP_ZPmZZ_H
|
|
3223410365U, // FMINP_ZPmZZ_S
|
|
813799101U, // FMINPv2f32
|
|
815896253U, // FMINPv2f64
|
|
807425725U, // FMINPv2i16p
|
|
807425725U, // FMINPv2i32p
|
|
807425725U, // FMINPv2i64p
|
|
817993405U, // FMINPv4f16
|
|
820090557U, // FMINPv4f32
|
|
822187709U, // FMINPv8f16
|
|
3231817500U, // FMINQV_D
|
|
3238108956U, // FMINQV_H
|
|
3236011804U, // FMINQV_S
|
|
2118938U, // FMINSrr
|
|
1657020101U, // FMINV_VPZ_D
|
|
1659133637U, // FMINV_VPZ_H
|
|
1638178501U, // FMINV_VPZ_S
|
|
807427781U, // FMINVv4i16v
|
|
807427781U, // FMINVv4i32v
|
|
807427781U, // FMINVv8i16v
|
|
2181207322U, // FMIN_VG2_2Z2Z_D
|
|
2183320858U, // FMIN_VG2_2Z2Z_H
|
|
2185434394U, // FMIN_VG2_2Z2Z_S
|
|
2181207322U, // FMIN_VG2_2ZZ_D
|
|
2183320858U, // FMIN_VG2_2ZZ_H
|
|
2185434394U, // FMIN_VG2_2ZZ_S
|
|
2181207322U, // FMIN_VG4_4Z4Z_D
|
|
2183320858U, // FMIN_VG4_4Z4Z_H
|
|
2185434394U, // FMIN_VG4_4Z4Z_S
|
|
2181207322U, // FMIN_VG4_4ZZ_D
|
|
2183320858U, // FMIN_VG4_4ZZ_H
|
|
2185434394U, // FMIN_VG4_4ZZ_S
|
|
3223377178U, // FMIN_ZPmI_D
|
|
3519091994U, // FMIN_ZPmI_H
|
|
3223409946U, // FMIN_ZPmI_S
|
|
3223377178U, // FMIN_ZPmZ_D
|
|
3519091994U, // FMIN_ZPmZ_H
|
|
3223409946U, // FMIN_ZPmZ_S
|
|
813798682U, // FMINv2f32
|
|
815895834U, // FMINv2f64
|
|
817992986U, // FMINv4f16
|
|
820090138U, // FMINv4f32
|
|
822187290U, // FMINv8f16
|
|
2961309942U, // FMLAL2lanev4f16
|
|
2967601398U, // FMLAL2lanev8f16
|
|
2961309942U, // FMLAL2v4f16
|
|
2967601398U, // FMLAL2v8f16
|
|
2220951153U, // FMLALB_ZZZ
|
|
2220951153U, // FMLALB_ZZZI
|
|
2686535281U, // FMLALB_ZZZI_SHH
|
|
2686535281U, // FMLALB_ZZZ_SHH
|
|
2969699953U, // FMLALBlanev8f16
|
|
2969699953U, // FMLALBv8f16
|
|
2418099682U, // FMLALLBB_ZZZ
|
|
2418099682U, // FMLALLBB_ZZZI
|
|
2967602658U, // FMLALLBBlanev4f32
|
|
2967602658U, // FMLALLBBv4f32
|
|
2418105119U, // FMLALLBT_ZZZ
|
|
2418105119U, // FMLALLBT_ZZZI
|
|
2967608095U, // FMLALLBTlanev4f32
|
|
2967608095U, // FMLALLBTv4f32
|
|
2418100613U, // FMLALLTB_ZZZ
|
|
2418100613U, // FMLALLTB_ZZZI
|
|
2967603589U, // FMLALLTBlanev4f32
|
|
2967603589U, // FMLALLTBv4f32
|
|
2418105776U, // FMLALLTT_ZZZ
|
|
2418105776U, // FMLALLTT_ZZZI
|
|
2967608752U, // FMLALLTTlanev4f32
|
|
2967608752U, // FMLALLTTv4f32
|
|
1688441534U, // FMLALL_MZZI_BtoS
|
|
1688441534U, // FMLALL_MZZ_BtoS
|
|
3835925182U, // FMLALL_VG2_M2Z2Z_BtoS
|
|
3835925182U, // FMLALL_VG2_M2ZZI_BtoS
|
|
4104360638U, // FMLALL_VG2_M2ZZ_BtoS
|
|
4104360638U, // FMLALL_VG4_M4Z4Z_BtoS
|
|
4104360638U, // FMLALL_VG4_M4ZZI_BtoS
|
|
77828798U, // FMLALL_VG4_M4ZZ_BtoS
|
|
2220956595U, // FMLALT_ZZZ
|
|
2220956595U, // FMLALT_ZZZI
|
|
2686540723U, // FMLALT_ZZZI_SHH
|
|
2686540723U, // FMLALT_ZZZ_SHH
|
|
2969705395U, // FMLALTlanev8f16
|
|
2969705395U, // FMLALTv8f16
|
|
1663406325U, // FMLAL_MZZI_BtoH
|
|
1663275253U, // FMLAL_MZZI_HtoS
|
|
1663275253U, // FMLAL_MZZ_HtoS
|
|
3810889973U, // FMLAL_VG2_M2Z2Z_BtoH
|
|
3810758901U, // FMLAL_VG2_M2Z2Z_HtoS
|
|
3810889973U, // FMLAL_VG2_M2ZZI_BtoH
|
|
3810758901U, // FMLAL_VG2_M2ZZI_HtoS
|
|
3810889973U, // FMLAL_VG2_M2ZZ_BtoH
|
|
3810758901U, // FMLAL_VG2_M2ZZ_HtoS
|
|
1663406325U, // FMLAL_VG2_MZZ_BtoH
|
|
4079325429U, // FMLAL_VG4_M4Z4Z_BtoH
|
|
4079194357U, // FMLAL_VG4_M4Z4Z_HtoS
|
|
4079325429U, // FMLAL_VG4_M4ZZI_BtoH
|
|
4079194357U, // FMLAL_VG4_M4ZZI_HtoS
|
|
4079325429U, // FMLAL_VG4_M4ZZ_BtoH
|
|
4079194357U, // FMLAL_VG4_M4ZZ_HtoS
|
|
2961314037U, // FMLALlanev4f16
|
|
2967605493U, // FMLALlanev8f16
|
|
2961314037U, // FMLALv4f16
|
|
2967605493U, // FMLALv8f16
|
|
3798156134U, // FMLA_VG2_M2Z2Z_D
|
|
3798172518U, // FMLA_VG2_M2Z2Z_S
|
|
3798303590U, // FMLA_VG2_M2Z4Z_H
|
|
3798156134U, // FMLA_VG2_M2ZZI_D
|
|
3798303590U, // FMLA_VG2_M2ZZI_H
|
|
3798172518U, // FMLA_VG2_M2ZZI_S
|
|
3798156134U, // FMLA_VG2_M2ZZ_D
|
|
3798303590U, // FMLA_VG2_M2ZZ_H
|
|
3798172518U, // FMLA_VG2_M2ZZ_S
|
|
4066591590U, // FMLA_VG4_M4Z4Z_D
|
|
4066739046U, // FMLA_VG4_M4Z4Z_H
|
|
4066607974U, // FMLA_VG4_M4Z4Z_S
|
|
4066591590U, // FMLA_VG4_M4ZZI_D
|
|
4066739046U, // FMLA_VG4_M4ZZI_H
|
|
4066607974U, // FMLA_VG4_M4ZZI_S
|
|
4066591590U, // FMLA_VG4_M4ZZ_D
|
|
4066739046U, // FMLA_VG4_M4ZZ_H
|
|
4066607974U, // FMLA_VG4_M4ZZ_S
|
|
3223372646U, // FMLA_ZPmZZ_D
|
|
3519087462U, // FMLA_ZPmZZ_H
|
|
3223405414U, // FMLA_ZPmZZ_S
|
|
1075888998U, // FMLA_ZZZI_D
|
|
2195784550U, // FMLA_ZZZI_H
|
|
1344357222U, // FMLA_ZZZI_S
|
|
807715686U, // FMLAv1i16_indexed
|
|
807715686U, // FMLAv1i32_indexed
|
|
807715686U, // FMLAv1i64_indexed
|
|
2961310566U, // FMLAv2f32
|
|
2963407718U, // FMLAv2f64
|
|
2961310566U, // FMLAv2i32_indexed
|
|
2963407718U, // FMLAv2i64_indexed
|
|
2965504870U, // FMLAv4f16
|
|
2967602022U, // FMLAv4f32
|
|
2965504870U, // FMLAv4i16_indexed
|
|
2967602022U, // FMLAv4i32_indexed
|
|
2969699174U, // FMLAv8f16
|
|
2969699174U, // FMLAv8i16_indexed
|
|
2961310074U, // FMLSL2lanev4f16
|
|
2967601530U, // FMLSL2lanev8f16
|
|
2961310074U, // FMLSL2v4f16
|
|
2967601530U, // FMLSL2v8f16
|
|
2686535579U, // FMLSLB_ZZZI_SHH
|
|
2686535579U, // FMLSLB_ZZZ_SHH
|
|
2686540898U, // FMLSLT_ZZZI_SHH
|
|
2686540898U, // FMLSLT_ZZZ_SHH
|
|
1663276020U, // FMLSL_MZZI_HtoS
|
|
1663276020U, // FMLSL_MZZ_HtoS
|
|
3810759668U, // FMLSL_VG2_M2Z2Z_HtoS
|
|
3810759668U, // FMLSL_VG2_M2ZZI_HtoS
|
|
3810759668U, // FMLSL_VG2_M2ZZ_HtoS
|
|
4079195124U, // FMLSL_VG4_M4Z4Z_HtoS
|
|
4079195124U, // FMLSL_VG4_M4ZZI_HtoS
|
|
4079195124U, // FMLSL_VG4_M4ZZ_HtoS
|
|
2961314804U, // FMLSLlanev4f16
|
|
2967606260U, // FMLSLlanev8f16
|
|
2961314804U, // FMLSLv4f16
|
|
2967606260U, // FMLSLv8f16
|
|
3798162002U, // FMLS_VG2_M2Z2Z_D
|
|
3798309458U, // FMLS_VG2_M2Z2Z_H
|
|
3798178386U, // FMLS_VG2_M2Z2Z_S
|
|
3798162002U, // FMLS_VG2_M2ZZI_D
|
|
3798309458U, // FMLS_VG2_M2ZZI_H
|
|
3798178386U, // FMLS_VG2_M2ZZI_S
|
|
3798162002U, // FMLS_VG2_M2ZZ_D
|
|
3798309458U, // FMLS_VG2_M2ZZ_H
|
|
3798178386U, // FMLS_VG2_M2ZZ_S
|
|
4066744914U, // FMLS_VG4_M4Z2Z_H
|
|
4066597458U, // FMLS_VG4_M4Z4Z_D
|
|
4066613842U, // FMLS_VG4_M4Z4Z_S
|
|
4066597458U, // FMLS_VG4_M4ZZI_D
|
|
4066744914U, // FMLS_VG4_M4ZZI_H
|
|
4066613842U, // FMLS_VG4_M4ZZI_S
|
|
4066597458U, // FMLS_VG4_M4ZZ_D
|
|
4066744914U, // FMLS_VG4_M4ZZ_H
|
|
4066613842U, // FMLS_VG4_M4ZZ_S
|
|
3223378514U, // FMLS_ZPmZZ_D
|
|
3519093330U, // FMLS_ZPmZZ_H
|
|
3223411282U, // FMLS_ZPmZZ_S
|
|
1075894866U, // FMLS_ZZZI_D
|
|
2195790418U, // FMLS_ZZZI_H
|
|
1344363090U, // FMLS_ZZZI_S
|
|
807721554U, // FMLSv1i16_indexed
|
|
807721554U, // FMLSv1i32_indexed
|
|
807721554U, // FMLSv1i64_indexed
|
|
2961316434U, // FMLSv2f32
|
|
2963413586U, // FMLSv2f64
|
|
2961316434U, // FMLSv2i32_indexed
|
|
2963413586U, // FMLSv2i64_indexed
|
|
2965510738U, // FMLSv4f16
|
|
2967607890U, // FMLSv4f32
|
|
2965510738U, // FMLSv4i16_indexed
|
|
2967607890U, // FMLSv4i32_indexed
|
|
2969705042U, // FMLSv8f16
|
|
2969705042U, // FMLSv8i16_indexed
|
|
1075889005U, // FMMLA_ZZZ_D
|
|
1344357229U, // FMMLA_ZZZ_S
|
|
54641579U, // FMOPAL_MPPZZ
|
|
79807403U, // FMOPA_MPPZZ_BtoH
|
|
79807403U, // FMOPA_MPPZZ_BtoS
|
|
2168570795U, // FMOPA_MPPZZ_D
|
|
54641579U, // FMOPA_MPPZZ_H
|
|
2170667947U, // FMOPA_MPPZZ_S
|
|
54647455U, // FMOPSL_MPPZZ
|
|
2168576671U, // FMOPS_MPPZZ_D
|
|
54647455U, // FMOPS_MPPZZ_H
|
|
2170673823U, // FMOPS_MPPZZ_S
|
|
807427809U, // FMOVDXHighr
|
|
2121441U, // FMOVDXr
|
|
3760217825U, // FMOVDi
|
|
2121441U, // FMOVDr
|
|
2121441U, // FMOVHWr
|
|
2121441U, // FMOVHXr
|
|
3760217825U, // FMOVHi
|
|
2121441U, // FMOVHr
|
|
2121441U, // FMOVSWr
|
|
3760217825U, // FMOVSi
|
|
2121441U, // FMOVSr
|
|
2121441U, // FMOVWHr
|
|
2121441U, // FMOVWSr
|
|
81895137U, // FMOVXDHighr
|
|
2121441U, // FMOVXDr
|
|
2121441U, // FMOVXHr
|
|
3766591201U, // FMOVv2f32_ns
|
|
3768688353U, // FMOVv2f64_ns
|
|
3770785505U, // FMOVv4f16_ns
|
|
3772882657U, // FMOVv4f32_ns
|
|
3774979809U, // FMOVv8f16_ns
|
|
17112U, // FMS16
|
|
16558U, // FMS32
|
|
17059U, // FMS64
|
|
3223374137U, // FMSB_ZPmZZ_D
|
|
3519088953U, // FMSB_ZPmZZ_H
|
|
3223406905U, // FMSB_ZPmZZ_S
|
|
2116045U, // FMSUBDrrr
|
|
2116045U, // FMSUBHrrr
|
|
2116045U, // FMSUBSrrr
|
|
2118724U, // FMULDrr
|
|
2118724U, // FMULHrr
|
|
2118724U, // FMULSrr
|
|
2122000U, // FMULX16
|
|
2122000U, // FMULX32
|
|
2122000U, // FMULX64
|
|
3223380240U, // FMULX_ZPmZ_D
|
|
3519095056U, // FMULX_ZPmZ_H
|
|
3223413008U, // FMULX_ZPmZ_S
|
|
2122000U, // FMULXv1i16_indexed
|
|
2122000U, // FMULXv1i32_indexed
|
|
2122000U, // FMULXv1i64_indexed
|
|
813801744U, // FMULXv2f32
|
|
815898896U, // FMULXv2f64
|
|
813801744U, // FMULXv2i32_indexed
|
|
815898896U, // FMULXv2i64_indexed
|
|
817996048U, // FMULXv4f16
|
|
820093200U, // FMULXv4f32
|
|
817996048U, // FMULXv4i16_indexed
|
|
820093200U, // FMULXv4i32_indexed
|
|
822190352U, // FMULXv8f16
|
|
822190352U, // FMULXv8i16_indexed
|
|
3223376964U, // FMUL_ZPmI_D
|
|
3519091780U, // FMUL_ZPmI_H
|
|
3223409732U, // FMUL_ZPmI_S
|
|
3223376964U, // FMUL_ZPmZ_D
|
|
3519091780U, // FMUL_ZPmZ_H
|
|
3223409732U, // FMUL_ZPmZ_S
|
|
2418070596U, // FMUL_ZZZI_D
|
|
2189497412U, // FMUL_ZZZI_H
|
|
270619716U, // FMUL_ZZZI_S
|
|
2418070596U, // FMUL_ZZZ_D
|
|
2189497412U, // FMUL_ZZZ_H
|
|
270619716U, // FMUL_ZZZ_S
|
|
2118724U, // FMULv1i16_indexed
|
|
2118724U, // FMULv1i32_indexed
|
|
2118724U, // FMULv1i64_indexed
|
|
813798468U, // FMULv2f32
|
|
815895620U, // FMULv2f64
|
|
813798468U, // FMULv2i32_indexed
|
|
815895620U, // FMULv2i64_indexed
|
|
817992772U, // FMULv4f16
|
|
820089924U, // FMULv4f32
|
|
817992772U, // FMULv4i16_indexed
|
|
820089924U, // FMULv4i32_indexed
|
|
822187076U, // FMULv8f16
|
|
822187076U, // FMULv8i16_indexed
|
|
2116832U, // FNEGDr
|
|
2116832U, // FNEGHr
|
|
2116832U, // FNEGSr
|
|
270585056U, // FNEG_ZPmZ_D
|
|
541134048U, // FNEG_ZPmZ_H
|
|
270617824U, // FNEG_ZPmZ_S
|
|
813796576U, // FNEGv2f32
|
|
815893728U, // FNEGv2f64
|
|
817990880U, // FNEGv4f16
|
|
820088032U, // FNEGv4f32
|
|
822185184U, // FNEGv8f16
|
|
2116514U, // FNMADDDrrr
|
|
2116514U, // FNMADDHrrr
|
|
2116514U, // FNMADDSrrr
|
|
3223374617U, // FNMAD_ZPmZZ_D
|
|
3519089433U, // FNMAD_ZPmZZ_H
|
|
3223407385U, // FNMAD_ZPmZZ_S
|
|
3223372675U, // FNMLA_ZPmZZ_D
|
|
3519087491U, // FNMLA_ZPmZZ_H
|
|
3223405443U, // FNMLA_ZPmZZ_S
|
|
3223378520U, // FNMLS_ZPmZZ_D
|
|
3519093336U, // FNMLS_ZPmZZ_H
|
|
3223411288U, // FNMLS_ZPmZZ_S
|
|
3223374143U, // FNMSB_ZPmZZ_D
|
|
3519088959U, // FNMSB_ZPmZZ_H
|
|
3223406911U, // FNMSB_ZPmZZ_S
|
|
2116052U, // FNMSUBDrrr
|
|
2116052U, // FNMSUBHrrr
|
|
2116052U, // FNMSUBSrrr
|
|
2118730U, // FNMULDrr
|
|
2118730U, // FNMULHrr
|
|
2118730U, // FNMULSrr
|
|
2418068574U, // FRECPE_ZZ_D
|
|
1652624478U, // FRECPE_ZZ_H
|
|
270617694U, // FRECPE_ZZ_S
|
|
2116702U, // FRECPEv1f16
|
|
2116702U, // FRECPEv1i32
|
|
2116702U, // FRECPEv1i64
|
|
813796446U, // FRECPEv2f32
|
|
815893598U, // FRECPEv2f64
|
|
817990750U, // FRECPEv4f16
|
|
820087902U, // FRECPEv4f32
|
|
822185054U, // FRECPEv8f16
|
|
2120335U, // FRECPS16
|
|
2120335U, // FRECPS32
|
|
2120335U, // FRECPS64
|
|
2418072207U, // FRECPS_ZZZ_D
|
|
2189499023U, // FRECPS_ZZZ_H
|
|
270621327U, // FRECPS_ZZZ_S
|
|
813800079U, // FRECPSv2f32
|
|
815897231U, // FRECPSv2f64
|
|
817994383U, // FRECPSv4f16
|
|
820091535U, // FRECPSv4f32
|
|
822188687U, // FRECPSv8f16
|
|
270590231U, // FRECPX_ZPmZ_D
|
|
541139223U, // FRECPX_ZPmZ_H
|
|
270622999U, // FRECPX_ZPmZ_S
|
|
2122007U, // FRECPXv1f16
|
|
2122007U, // FRECPXv1i32
|
|
2122007U, // FRECPXv1i64
|
|
2121891U, // FRINT32XDr
|
|
2121891U, // FRINT32XSr
|
|
813801635U, // FRINT32Xv2f32
|
|
815898787U, // FRINT32Xv2f64
|
|
820093091U, // FRINT32Xv4f32
|
|
2122074U, // FRINT32ZDr
|
|
2122074U, // FRINT32ZSr
|
|
813801818U, // FRINT32Zv2f32
|
|
815898970U, // FRINT32Zv2f64
|
|
820093274U, // FRINT32Zv4f32
|
|
2121901U, // FRINT64XDr
|
|
2121901U, // FRINT64XSr
|
|
813801645U, // FRINT64Xv2f32
|
|
815898797U, // FRINT64Xv2f64
|
|
820093101U, // FRINT64Xv4f32
|
|
2122084U, // FRINT64ZDr
|
|
2122084U, // FRINT64ZSr
|
|
813801828U, // FRINT64Zv2f32
|
|
815898980U, // FRINT64Zv2f64
|
|
820093284U, // FRINT64Zv4f32
|
|
2114733U, // FRINTADr
|
|
2114733U, // FRINTAHr
|
|
2114733U, // FRINTASr
|
|
1648559277U, // FRINTA_2Z2Z_S
|
|
1648559277U, // FRINTA_4Z4Z_S
|
|
270582957U, // FRINTA_ZPmZ_D
|
|
541131949U, // FRINTA_ZPmZ_H
|
|
270615725U, // FRINTA_ZPmZ_S
|
|
813794477U, // FRINTAv2f32
|
|
815891629U, // FRINTAv2f64
|
|
817988781U, // FRINTAv4f16
|
|
820085933U, // FRINTAv4f32
|
|
822183085U, // FRINTAv8f16
|
|
2117793U, // FRINTIDr
|
|
2117793U, // FRINTIHr
|
|
2117793U, // FRINTISr
|
|
270586017U, // FRINTI_ZPmZ_D
|
|
541135009U, // FRINTI_ZPmZ_H
|
|
270618785U, // FRINTI_ZPmZ_S
|
|
813797537U, // FRINTIv2f32
|
|
815894689U, // FRINTIv2f64
|
|
817991841U, // FRINTIv4f16
|
|
820088993U, // FRINTIv4f32
|
|
822186145U, // FRINTIv8f16
|
|
2118885U, // FRINTMDr
|
|
2118885U, // FRINTMHr
|
|
2118885U, // FRINTMSr
|
|
1648563429U, // FRINTM_2Z2Z_S
|
|
1648563429U, // FRINTM_4Z4Z_S
|
|
270587109U, // FRINTM_ZPmZ_D
|
|
541136101U, // FRINTM_ZPmZ_H
|
|
270619877U, // FRINTM_ZPmZ_S
|
|
813798629U, // FRINTMv2f32
|
|
815895781U, // FRINTMv2f64
|
|
817992933U, // FRINTMv4f16
|
|
820090085U, // FRINTMv4f32
|
|
822187237U, // FRINTMv8f16
|
|
2119016U, // FRINTNDr
|
|
2119016U, // FRINTNHr
|
|
2119016U, // FRINTNSr
|
|
1648563560U, // FRINTN_2Z2Z_S
|
|
1648563560U, // FRINTN_4Z4Z_S
|
|
270587240U, // FRINTN_ZPmZ_D
|
|
541136232U, // FRINTN_ZPmZ_H
|
|
270620008U, // FRINTN_ZPmZ_S
|
|
813798760U, // FRINTNv2f32
|
|
815895912U, // FRINTNv2f64
|
|
817993064U, // FRINTNv4f16
|
|
820090216U, // FRINTNv4f32
|
|
822187368U, // FRINTNv8f16
|
|
2119508U, // FRINTPDr
|
|
2119508U, // FRINTPHr
|
|
2119508U, // FRINTPSr
|
|
1648564052U, // FRINTP_2Z2Z_S
|
|
1648564052U, // FRINTP_4Z4Z_S
|
|
270587732U, // FRINTP_ZPmZ_D
|
|
541136724U, // FRINTP_ZPmZ_H
|
|
270620500U, // FRINTP_ZPmZ_S
|
|
813799252U, // FRINTPv2f32
|
|
815896404U, // FRINTPv2f64
|
|
817993556U, // FRINTPv4f16
|
|
820090708U, // FRINTPv4f32
|
|
822187860U, // FRINTPv8f16
|
|
2122022U, // FRINTXDr
|
|
2122022U, // FRINTXHr
|
|
2122022U, // FRINTXSr
|
|
270590246U, // FRINTX_ZPmZ_D
|
|
541139238U, // FRINTX_ZPmZ_H
|
|
270623014U, // FRINTX_ZPmZ_S
|
|
813801766U, // FRINTXv2f32
|
|
815898918U, // FRINTXv2f64
|
|
817996070U, // FRINTXv4f16
|
|
820093222U, // FRINTXv4f32
|
|
822190374U, // FRINTXv8f16
|
|
2122168U, // FRINTZDr
|
|
2122168U, // FRINTZHr
|
|
2122168U, // FRINTZSr
|
|
270590392U, // FRINTZ_ZPmZ_D
|
|
541139384U, // FRINTZ_ZPmZ_H
|
|
270623160U, // FRINTZ_ZPmZ_S
|
|
813801912U, // FRINTZv2f32
|
|
815899064U, // FRINTZv2f64
|
|
817996216U, // FRINTZv4f16
|
|
820093368U, // FRINTZv4f32
|
|
822190520U, // FRINTZv8f16
|
|
2418068619U, // FRSQRTE_ZZ_D
|
|
1652624523U, // FRSQRTE_ZZ_H
|
|
270617739U, // FRSQRTE_ZZ_S
|
|
2116747U, // FRSQRTEv1f16
|
|
2116747U, // FRSQRTEv1i32
|
|
2116747U, // FRSQRTEv1i64
|
|
813796491U, // FRSQRTEv2f32
|
|
815893643U, // FRSQRTEv2f64
|
|
817990795U, // FRSQRTEv4f16
|
|
820087947U, // FRSQRTEv4f32
|
|
822185099U, // FRSQRTEv8f16
|
|
2120419U, // FRSQRTS16
|
|
2120419U, // FRSQRTS32
|
|
2120419U, // FRSQRTS64
|
|
2418072291U, // FRSQRTS_ZZZ_D
|
|
2189499107U, // FRSQRTS_ZZZ_H
|
|
270621411U, // FRSQRTS_ZZZ_S
|
|
813800163U, // FRSQRTSv2f32
|
|
815897315U, // FRSQRTSv2f64
|
|
817994467U, // FRSQRTSv4f16
|
|
820091619U, // FRSQRTSv4f32
|
|
822188771U, // FRSQRTSv8f16
|
|
2181205032U, // FSCALE_2Z2Z_D
|
|
2183318568U, // FSCALE_2Z2Z_H
|
|
2185432104U, // FSCALE_2Z2Z_S
|
|
2181205032U, // FSCALE_2ZZ_D
|
|
2183318568U, // FSCALE_2ZZ_H
|
|
2185432104U, // FSCALE_2ZZ_S
|
|
2181205032U, // FSCALE_4Z4Z_D
|
|
2183318568U, // FSCALE_4Z4Z_H
|
|
2185432104U, // FSCALE_4Z4Z_S
|
|
2181205032U, // FSCALE_4ZZ_D
|
|
2183318568U, // FSCALE_4ZZ_H
|
|
2185432104U, // FSCALE_4ZZ_S
|
|
3223374888U, // FSCALE_ZPmZ_D
|
|
3519089704U, // FSCALE_ZPmZ_H
|
|
3223407656U, // FSCALE_ZPmZ_S
|
|
813796392U, // FSCALEv2f32
|
|
815893544U, // FSCALEv2f64
|
|
817990696U, // FSCALEv4f16
|
|
820087848U, // FSCALEv4f32
|
|
822185000U, // FSCALEv8f16
|
|
2121100U, // FSQRTDr
|
|
2121100U, // FSQRTHr
|
|
2121100U, // FSQRTSr
|
|
270589324U, // FSQRT_ZPmZ_D
|
|
541138316U, // FSQRT_ZPmZ_H
|
|
270622092U, // FSQRT_ZPmZ_S
|
|
813800844U, // FSQRTv2f32
|
|
815897996U, // FSQRTv2f64
|
|
817995148U, // FSQRTv4f16
|
|
820092300U, // FSQRTv4f32
|
|
822189452U, // FSQRTv8f16
|
|
2116025U, // FSUBDrr
|
|
2116025U, // FSUBHrr
|
|
3223377973U, // FSUBR_ZPmI_D
|
|
3519092789U, // FSUBR_ZPmI_H
|
|
3223410741U, // FSUBR_ZPmI_S
|
|
3223377973U, // FSUBR_ZPmZ_D
|
|
3519092789U, // FSUBR_ZPmZ_H
|
|
3223410741U, // FSUBR_ZPmZ_S
|
|
2116025U, // FSUBSrr
|
|
3798157753U, // FSUB_VG2_M2Z_D
|
|
3798305209U, // FSUB_VG2_M2Z_H
|
|
3798174137U, // FSUB_VG2_M2Z_S
|
|
4066593209U, // FSUB_VG4_M4Z_D
|
|
4066740665U, // FSUB_VG4_M4Z_H
|
|
4066609593U, // FSUB_VG4_M4Z_S
|
|
3223374265U, // FSUB_ZPmI_D
|
|
3519089081U, // FSUB_ZPmI_H
|
|
3223407033U, // FSUB_ZPmI_S
|
|
3223374265U, // FSUB_ZPmZ_D
|
|
3519089081U, // FSUB_ZPmZ_H
|
|
3223407033U, // FSUB_ZPmZ_S
|
|
2418067897U, // FSUB_ZZZ_D
|
|
2189494713U, // FSUB_ZZZ_H
|
|
270617017U, // FSUB_ZZZ_S
|
|
813795769U, // FSUBv2f32
|
|
815892921U, // FSUBv2f64
|
|
817990073U, // FSUBv4f16
|
|
820087225U, // FSUBv4f32
|
|
822184377U, // FSUBv8f16
|
|
2418068256U, // FTMAD_ZZI_D
|
|
2189495072U, // FTMAD_ZZI_H
|
|
270617376U, // FTMAD_ZZI_S
|
|
2418070615U, // FTSMUL_ZZZ_D
|
|
2189497431U, // FTSMUL_ZZZ_H
|
|
270619735U, // FTSMUL_ZZZ_S
|
|
2418070142U, // FTSSEL_ZZZ_D
|
|
2189496958U, // FTSSEL_ZZZ_H
|
|
270619262U, // FTSSEL_ZZZ_S
|
|
4066609557U, // FVDOTB_VG4_M2ZZI_BtoS
|
|
4066614714U, // FVDOTT_VG4_M2ZZI_BtoS
|
|
3798310217U, // FVDOT_VG2_M2ZZI_BtoH
|
|
3798179145U, // FVDOT_VG2_M2ZZI_HtoS
|
|
10429U, // GCSPOPCX
|
|
21718U, // GCSPOPM
|
|
10447U, // GCSPOPX
|
|
21690U, // GCSPUSHM
|
|
10438U, // GCSPUSHX
|
|
16490U, // GCSSS1
|
|
16973U, // GCSSS2
|
|
2120018U, // GCSSTR
|
|
2120026U, // GCSSTTR
|
|
24002U, // GENLUT
|
|
22630U, // GENTER
|
|
10417U, // GEXIT
|
|
297960700U, // GLD1B_D_IMM_REAL
|
|
297960700U, // GLD1B_D_REAL
|
|
297960700U, // GLD1B_D_SXTW_REAL
|
|
297960700U, // GLD1B_D_UXTW_REAL
|
|
297993468U, // GLD1B_S_IMM_REAL
|
|
297993468U, // GLD1B_S_SXTW_REAL
|
|
297993468U, // GLD1B_S_UXTW_REAL
|
|
297962155U, // GLD1D_IMM_REAL
|
|
297962155U, // GLD1D_REAL
|
|
297962155U, // GLD1D_SCALED_REAL
|
|
297962155U, // GLD1D_SXTW_REAL
|
|
297962155U, // GLD1D_SXTW_SCALED_REAL
|
|
297962155U, // GLD1D_UXTW_REAL
|
|
297962155U, // GLD1D_UXTW_SCALED_REAL
|
|
297962772U, // GLD1H_D_IMM_REAL
|
|
297962772U, // GLD1H_D_REAL
|
|
297962772U, // GLD1H_D_SCALED_REAL
|
|
297962772U, // GLD1H_D_SXTW_REAL
|
|
297962772U, // GLD1H_D_SXTW_SCALED_REAL
|
|
297962772U, // GLD1H_D_UXTW_REAL
|
|
297962772U, // GLD1H_D_UXTW_SCALED_REAL
|
|
297995540U, // GLD1H_S_IMM_REAL
|
|
297995540U, // GLD1H_S_SXTW_REAL
|
|
297995540U, // GLD1H_S_SXTW_SCALED_REAL
|
|
297995540U, // GLD1H_S_UXTW_REAL
|
|
297995540U, // GLD1H_S_UXTW_SCALED_REAL
|
|
298293164U, // GLD1Q
|
|
297961734U, // GLD1SB_D_IMM_REAL
|
|
297961734U, // GLD1SB_D_REAL
|
|
297961734U, // GLD1SB_D_SXTW_REAL
|
|
297961734U, // GLD1SB_D_UXTW_REAL
|
|
297994502U, // GLD1SB_S_IMM_REAL
|
|
297994502U, // GLD1SB_S_SXTW_REAL
|
|
297994502U, // GLD1SB_S_UXTW_REAL
|
|
297963463U, // GLD1SH_D_IMM_REAL
|
|
297963463U, // GLD1SH_D_REAL
|
|
297963463U, // GLD1SH_D_SCALED_REAL
|
|
297963463U, // GLD1SH_D_SXTW_REAL
|
|
297963463U, // GLD1SH_D_SXTW_SCALED_REAL
|
|
297963463U, // GLD1SH_D_UXTW_REAL
|
|
297963463U, // GLD1SH_D_UXTW_SCALED_REAL
|
|
297996231U, // GLD1SH_S_IMM_REAL
|
|
297996231U, // GLD1SH_S_SXTW_REAL
|
|
297996231U, // GLD1SH_S_SXTW_SCALED_REAL
|
|
297996231U, // GLD1SH_S_UXTW_REAL
|
|
297996231U, // GLD1SH_S_UXTW_SCALED_REAL
|
|
297967665U, // GLD1SW_D_IMM_REAL
|
|
297967665U, // GLD1SW_D_REAL
|
|
297967665U, // GLD1SW_D_SCALED_REAL
|
|
297967665U, // GLD1SW_D_SXTW_REAL
|
|
297967665U, // GLD1SW_D_SXTW_SCALED_REAL
|
|
297967665U, // GLD1SW_D_UXTW_REAL
|
|
297967665U, // GLD1SW_D_UXTW_SCALED_REAL
|
|
297967470U, // GLD1W_D_IMM_REAL
|
|
297967470U, // GLD1W_D_REAL
|
|
297967470U, // GLD1W_D_SCALED_REAL
|
|
297967470U, // GLD1W_D_SXTW_REAL
|
|
297967470U, // GLD1W_D_SXTW_SCALED_REAL
|
|
297967470U, // GLD1W_D_UXTW_REAL
|
|
297967470U, // GLD1W_D_UXTW_SCALED_REAL
|
|
298000238U, // GLD1W_IMM_REAL
|
|
298000238U, // GLD1W_SXTW_REAL
|
|
298000238U, // GLD1W_SXTW_SCALED_REAL
|
|
298000238U, // GLD1W_UXTW_REAL
|
|
298000238U, // GLD1W_UXTW_SCALED_REAL
|
|
297960706U, // GLDFF1B_D_IMM_REAL
|
|
297960706U, // GLDFF1B_D_REAL
|
|
297960706U, // GLDFF1B_D_SXTW_REAL
|
|
297960706U, // GLDFF1B_D_UXTW_REAL
|
|
297993474U, // GLDFF1B_S_IMM_REAL
|
|
297993474U, // GLDFF1B_S_SXTW_REAL
|
|
297993474U, // GLDFF1B_S_UXTW_REAL
|
|
297962161U, // GLDFF1D_IMM_REAL
|
|
297962161U, // GLDFF1D_REAL
|
|
297962161U, // GLDFF1D_SCALED_REAL
|
|
297962161U, // GLDFF1D_SXTW_REAL
|
|
297962161U, // GLDFF1D_SXTW_SCALED_REAL
|
|
297962161U, // GLDFF1D_UXTW_REAL
|
|
297962161U, // GLDFF1D_UXTW_SCALED_REAL
|
|
297962778U, // GLDFF1H_D_IMM_REAL
|
|
297962778U, // GLDFF1H_D_REAL
|
|
297962778U, // GLDFF1H_D_SCALED_REAL
|
|
297962778U, // GLDFF1H_D_SXTW_REAL
|
|
297962778U, // GLDFF1H_D_SXTW_SCALED_REAL
|
|
297962778U, // GLDFF1H_D_UXTW_REAL
|
|
297962778U, // GLDFF1H_D_UXTW_SCALED_REAL
|
|
297995546U, // GLDFF1H_S_IMM_REAL
|
|
297995546U, // GLDFF1H_S_SXTW_REAL
|
|
297995546U, // GLDFF1H_S_SXTW_SCALED_REAL
|
|
297995546U, // GLDFF1H_S_UXTW_REAL
|
|
297995546U, // GLDFF1H_S_UXTW_SCALED_REAL
|
|
297961741U, // GLDFF1SB_D_IMM_REAL
|
|
297961741U, // GLDFF1SB_D_REAL
|
|
297961741U, // GLDFF1SB_D_SXTW_REAL
|
|
297961741U, // GLDFF1SB_D_UXTW_REAL
|
|
297994509U, // GLDFF1SB_S_IMM_REAL
|
|
297994509U, // GLDFF1SB_S_SXTW_REAL
|
|
297994509U, // GLDFF1SB_S_UXTW_REAL
|
|
297963470U, // GLDFF1SH_D_IMM_REAL
|
|
297963470U, // GLDFF1SH_D_REAL
|
|
297963470U, // GLDFF1SH_D_SCALED_REAL
|
|
297963470U, // GLDFF1SH_D_SXTW_REAL
|
|
297963470U, // GLDFF1SH_D_SXTW_SCALED_REAL
|
|
297963470U, // GLDFF1SH_D_UXTW_REAL
|
|
297963470U, // GLDFF1SH_D_UXTW_SCALED_REAL
|
|
297996238U, // GLDFF1SH_S_IMM_REAL
|
|
297996238U, // GLDFF1SH_S_SXTW_REAL
|
|
297996238U, // GLDFF1SH_S_SXTW_SCALED_REAL
|
|
297996238U, // GLDFF1SH_S_UXTW_REAL
|
|
297996238U, // GLDFF1SH_S_UXTW_SCALED_REAL
|
|
297967672U, // GLDFF1SW_D_IMM_REAL
|
|
297967672U, // GLDFF1SW_D_REAL
|
|
297967672U, // GLDFF1SW_D_SCALED_REAL
|
|
297967672U, // GLDFF1SW_D_SXTW_REAL
|
|
297967672U, // GLDFF1SW_D_SXTW_SCALED_REAL
|
|
297967672U, // GLDFF1SW_D_UXTW_REAL
|
|
297967672U, // GLDFF1SW_D_UXTW_SCALED_REAL
|
|
297967476U, // GLDFF1W_D_IMM_REAL
|
|
297967476U, // GLDFF1W_D_REAL
|
|
297967476U, // GLDFF1W_D_SCALED_REAL
|
|
297967476U, // GLDFF1W_D_SXTW_REAL
|
|
297967476U, // GLDFF1W_D_SXTW_SCALED_REAL
|
|
297967476U, // GLDFF1W_D_UXTW_REAL
|
|
297967476U, // GLDFF1W_D_UXTW_SCALED_REAL
|
|
298000244U, // GLDFF1W_IMM_REAL
|
|
298000244U, // GLDFF1W_SXTW_REAL
|
|
298000244U, // GLDFF1W_SXTW_SCALED_REAL
|
|
298000244U, // GLDFF1W_UXTW_REAL
|
|
298000244U, // GLDFF1W_UXTW_SCALED_REAL
|
|
2117777U, // GMI
|
|
515257U, // HINT
|
|
3223379094U, // HISTCNT_ZPzZZ_D
|
|
3223411862U, // HISTCNT_ZPzZZ_S
|
|
2133236U, // HISTSEG_ZZZ
|
|
384018U, // HLT
|
|
379553U, // HVC
|
|
538985991U, // INCB_XPiI
|
|
538987346U, // INCD_XPiI
|
|
539020114U, // INCD_ZPiI
|
|
538988040U, // INCH_XPiI
|
|
56692232U, // INCH_ZPiI
|
|
2119199U, // INCP_XP_B
|
|
2418038303U, // INCP_XP_D
|
|
1881167391U, // INCP_XP_H
|
|
270554655U, // INCP_XP_S
|
|
1075893791U, // INCP_ZP_D
|
|
1658918431U, // INCP_ZP_H
|
|
1344362015U, // INCP_ZP_S
|
|
538992623U, // INCW_XPiI
|
|
539058159U, // INCW_ZPiI
|
|
539009262U, // INDEX_II_B
|
|
2154734U, // INDEX_II_D
|
|
889266414U, // INDEX_II_H
|
|
2187502U, // INDEX_II_S
|
|
539009262U, // INDEX_IR_B
|
|
2154734U, // INDEX_IR_D
|
|
889266414U, // INDEX_IR_H
|
|
2187502U, // INDEX_IR_S
|
|
2138350U, // INDEX_RI_B
|
|
2154734U, // INDEX_RI_D
|
|
2208375022U, // INDEX_RI_H
|
|
2187502U, // INDEX_RI_S
|
|
2138350U, // INDEX_RR_B
|
|
2154734U, // INDEX_RR_D
|
|
2208375022U, // INDEX_RR_H
|
|
2187502U, // INDEX_RR_S
|
|
2233992388U, // INSERT_MXIPZ_H_B
|
|
2233992388U, // INSERT_MXIPZ_H_D
|
|
2233992388U, // INSERT_MXIPZ_H_H
|
|
2233992388U, // INSERT_MXIPZ_H_Q
|
|
2233992388U, // INSERT_MXIPZ_H_S
|
|
2234008772U, // INSERT_MXIPZ_V_B
|
|
2234008772U, // INSERT_MXIPZ_V_D
|
|
2234008772U, // INSERT_MXIPZ_V_H
|
|
2234008772U, // INSERT_MXIPZ_V_Q
|
|
2234008772U, // INSERT_MXIPZ_V_S
|
|
807442758U, // INSR_ZR_B
|
|
807459142U, // INSR_ZR_D
|
|
1696667974U, // INSR_ZR_H
|
|
807491910U, // INSR_ZR_S
|
|
1075878214U, // INSR_ZV_B
|
|
1344330054U, // INSR_ZV_D
|
|
1677793606U, // INSR_ZV_H
|
|
1612798278U, // INSR_ZV_S
|
|
356653678U, // INSvi16gpr
|
|
1967266414U, // INSvi16lane
|
|
358750830U, // INSvi32gpr
|
|
1969363566U, // INSvi32lane
|
|
350362222U, // INSvi64gpr
|
|
1960974958U, // INSvi64lane
|
|
360847982U, // INSvi8gpr
|
|
1971460718U, // INSvi8lane
|
|
2116861U, // IRG
|
|
444724U, // ISB
|
|
3223340214U, // LASTA_RPZ_B
|
|
3223340214U, // LASTA_RPZ_D
|
|
3223340214U, // LASTA_RPZ_H
|
|
3223340214U, // LASTA_RPZ_S
|
|
3223340214U, // LASTA_VPZ_B
|
|
3223340214U, // LASTA_VPZ_D
|
|
3223340214U, // LASTA_VPZ_H
|
|
3223340214U, // LASTA_VPZ_S
|
|
3223341477U, // LASTB_RPZ_B
|
|
3223341477U, // LASTB_RPZ_D
|
|
3223341477U, // LASTB_RPZ_H
|
|
3223341477U, // LASTB_RPZ_S
|
|
3223341477U, // LASTB_VPZ_B
|
|
3223341477U, // LASTB_VPZ_D
|
|
3223341477U, // LASTB_VPZ_H
|
|
3223341477U, // LASTB_VPZ_S
|
|
297944316U, // LD1B
|
|
362956028U, // LD1B_2Z
|
|
362956028U, // LD1B_2Z_IMM
|
|
2150139132U, // LD1B_2Z_STRIDED
|
|
2150139132U, // LD1B_2Z_STRIDED_IMM
|
|
362956028U, // LD1B_4Z
|
|
362956028U, // LD1B_4Z_IMM
|
|
362956028U, // LD1B_4Z_STRIDED
|
|
362956028U, // LD1B_4Z_STRIDED_IMM
|
|
297960700U, // LD1B_D
|
|
297960700U, // LD1B_D_IMM
|
|
297977084U, // LD1B_H
|
|
297977084U, // LD1B_H_IMM
|
|
297944316U, // LD1B_IMM
|
|
297993468U, // LD1B_S
|
|
297993468U, // LD1B_S_IMM
|
|
297962155U, // LD1D
|
|
362973867U, // LD1D_2Z
|
|
362973867U, // LD1D_2Z_IMM
|
|
362973867U, // LD1D_2Z_STRIDED
|
|
362973867U, // LD1D_2Z_STRIDED_IMM
|
|
362973867U, // LD1D_4Z
|
|
362973867U, // LD1D_4Z_IMM
|
|
362973867U, // LD1D_4Z_STRIDED
|
|
362973867U, // LD1D_4Z_STRIDED_IMM
|
|
297962155U, // LD1D_IMM
|
|
298289835U, // LD1D_Q
|
|
298289835U, // LD1D_Q_IMM
|
|
573481U, // LD1Fourv16b
|
|
97058857U, // LD1Fourv16b_POST
|
|
606249U, // LD1Fourv1d
|
|
99188777U, // LD1Fourv1d_POST
|
|
639017U, // LD1Fourv2d
|
|
97124393U, // LD1Fourv2d_POST
|
|
671785U, // LD1Fourv2s
|
|
99254313U, // LD1Fourv2s_POST
|
|
704553U, // LD1Fourv4h
|
|
99287081U, // LD1Fourv4h_POST
|
|
737321U, // LD1Fourv4s
|
|
97222697U, // LD1Fourv4s_POST
|
|
770089U, // LD1Fourv8b
|
|
99352617U, // LD1Fourv8b_POST
|
|
802857U, // LD1Fourv8h
|
|
97288233U, // LD1Fourv8h_POST
|
|
297979156U, // LD1H
|
|
362990868U, // LD1H_2Z
|
|
362990868U, // LD1H_2Z_IMM
|
|
2150419732U, // LD1H_2Z_STRIDED
|
|
2150419732U, // LD1H_2Z_STRIDED_IMM
|
|
362990868U, // LD1H_4Z
|
|
362990868U, // LD1H_4Z_IMM
|
|
362990868U, // LD1H_4Z_STRIDED
|
|
362990868U, // LD1H_4Z_STRIDED_IMM
|
|
297962772U, // LD1H_D
|
|
297962772U, // LD1H_D_IMM
|
|
297979156U, // LD1H_IMM
|
|
297995540U, // LD1H_S
|
|
297995540U, // LD1H_S_IMM
|
|
573481U, // LD1Onev16b
|
|
101253161U, // LD1Onev16b_POST
|
|
606249U, // LD1Onev1d
|
|
103383081U, // LD1Onev1d_POST
|
|
639017U, // LD1Onev2d
|
|
101318697U, // LD1Onev2d_POST
|
|
671785U, // LD1Onev2s
|
|
103448617U, // LD1Onev2s_POST
|
|
704553U, // LD1Onev4h
|
|
103481385U, // LD1Onev4h_POST
|
|
737321U, // LD1Onev4s
|
|
101417001U, // LD1Onev4s_POST
|
|
770089U, // LD1Onev8b
|
|
103546921U, // LD1Onev8b_POST
|
|
802857U, // LD1Onev8h
|
|
101482537U, // LD1Onev8h_POST
|
|
297961586U, // LD1RB_D_IMM
|
|
297977970U, // LD1RB_H_IMM
|
|
297945202U, // LD1RB_IMM
|
|
297994354U, // LD1RB_S_IMM
|
|
297962461U, // LD1RD_IMM
|
|
297963315U, // LD1RH_D_IMM
|
|
297979699U, // LD1RH_IMM
|
|
297996083U, // LD1RH_S_IMM
|
|
297945173U, // LD1RO_B
|
|
297945173U, // LD1RO_B_IMM
|
|
297962445U, // LD1RO_D
|
|
297962445U, // LD1RO_D_IMM
|
|
297979677U, // LD1RO_H
|
|
297979677U, // LD1RO_H_IMM
|
|
298000401U, // LD1RO_W
|
|
298000401U, // LD1RO_W_IMM
|
|
297945194U, // LD1RQ_B
|
|
297945194U, // LD1RQ_B_IMM
|
|
297962453U, // LD1RQ_D
|
|
297962453U, // LD1RQ_D_IMM
|
|
297979691U, // LD1RQ_H
|
|
297979691U, // LD1RQ_H_IMM
|
|
298000409U, // LD1RQ_W
|
|
298000409U, // LD1RQ_W_IMM
|
|
297961798U, // LD1RSB_D_IMM
|
|
297978182U, // LD1RSB_H_IMM
|
|
297994566U, // LD1RSB_S_IMM
|
|
297963513U, // LD1RSH_D_IMM
|
|
297996281U, // LD1RSH_S_IMM
|
|
297967706U, // LD1RSW_IMM
|
|
297967649U, // LD1RW_D_IMM
|
|
298000417U, // LD1RW_IMM
|
|
579595U, // LD1Rv16b
|
|
105453579U, // LD1Rv16b_POST
|
|
612363U, // LD1Rv1d
|
|
103389195U, // LD1Rv1d_POST
|
|
645131U, // LD1Rv2d
|
|
103421963U, // LD1Rv2d_POST
|
|
677899U, // LD1Rv2s
|
|
107649035U, // LD1Rv2s_POST
|
|
710667U, // LD1Rv4h
|
|
109778955U, // LD1Rv4h_POST
|
|
743435U, // LD1Rv4s
|
|
107714571U, // LD1Rv4s_POST
|
|
776203U, // LD1Rv8b
|
|
105650187U, // LD1Rv8b_POST
|
|
808971U, // LD1Rv8h
|
|
109877259U, // LD1Rv8h_POST
|
|
297961734U, // LD1SB_D
|
|
297961734U, // LD1SB_D_IMM
|
|
297978118U, // LD1SB_H
|
|
297978118U, // LD1SB_H_IMM
|
|
297994502U, // LD1SB_S
|
|
297994502U, // LD1SB_S_IMM
|
|
297963463U, // LD1SH_D
|
|
297963463U, // LD1SH_D_IMM
|
|
297996231U, // LD1SH_S
|
|
297996231U, // LD1SH_S_IMM
|
|
297967665U, // LD1SW_D
|
|
297967665U, // LD1SW_D_IMM
|
|
573481U, // LD1Threev16b
|
|
111738921U, // LD1Threev16b_POST
|
|
606249U, // LD1Threev1d
|
|
113868841U, // LD1Threev1d_POST
|
|
639017U, // LD1Threev2d
|
|
111804457U, // LD1Threev2d_POST
|
|
671785U, // LD1Threev2s
|
|
113934377U, // LD1Threev2s_POST
|
|
704553U, // LD1Threev4h
|
|
113967145U, // LD1Threev4h_POST
|
|
737321U, // LD1Threev4s
|
|
111902761U, // LD1Threev4s_POST
|
|
770089U, // LD1Threev8b
|
|
114032681U, // LD1Threev8b_POST
|
|
802857U, // LD1Threev8h
|
|
111968297U, // LD1Threev8h_POST
|
|
573481U, // LD1Twov16b
|
|
99156009U, // LD1Twov16b_POST
|
|
606249U, // LD1Twov1d
|
|
101285929U, // LD1Twov1d_POST
|
|
639017U, // LD1Twov2d
|
|
99221545U, // LD1Twov2d_POST
|
|
671785U, // LD1Twov2s
|
|
101351465U, // LD1Twov2s_POST
|
|
704553U, // LD1Twov4h
|
|
101384233U, // LD1Twov4h_POST
|
|
737321U, // LD1Twov4s
|
|
99319849U, // LD1Twov4s_POST
|
|
770089U, // LD1Twov8b
|
|
101449769U, // LD1Twov8b_POST
|
|
802857U, // LD1Twov8h
|
|
99385385U, // LD1Twov8h_POST
|
|
298000238U, // LD1W
|
|
363011950U, // LD1W_2Z
|
|
363011950U, // LD1W_2Z_IMM
|
|
363011950U, // LD1W_2Z_STRIDED
|
|
363011950U, // LD1W_2Z_STRIDED_IMM
|
|
363011950U, // LD1W_4Z
|
|
363011950U, // LD1W_4Z_IMM
|
|
363011950U, // LD1W_4Z_STRIDED
|
|
363011950U, // LD1W_4Z_STRIDED_IMM
|
|
297967470U, // LD1W_D
|
|
297967470U, // LD1W_D_IMM
|
|
298000238U, // LD1W_IMM
|
|
298295150U, // LD1W_Q
|
|
298295150U, // LD1W_Q_IMM
|
|
2208835799U, // LD1_MXIPXX_H_B
|
|
2208835813U, // LD1_MXIPXX_H_D
|
|
2208835827U, // LD1_MXIPXX_H_H
|
|
2208835841U, // LD1_MXIPXX_H_Q
|
|
2208835855U, // LD1_MXIPXX_H_S
|
|
2208852183U, // LD1_MXIPXX_V_B
|
|
2208852197U, // LD1_MXIPXX_V_D
|
|
2208852211U, // LD1_MXIPXX_V_H
|
|
2208852225U, // LD1_MXIPXX_V_Q
|
|
2208852239U, // LD1_MXIPXX_V_S
|
|
116195369U, // LD1i16
|
|
118308905U, // LD1i16_POST
|
|
116228137U, // LD1i32
|
|
120438825U, // LD1i32_POST
|
|
116260905U, // LD1i64
|
|
122568745U, // LD1i64_POST
|
|
116293673U, // LD1i8
|
|
124698665U, // LD1i8_POST
|
|
297944377U, // LD2B
|
|
297944377U, // LD2B_IMM
|
|
297962223U, // LD2D
|
|
297962223U, // LD2D_IMM
|
|
297979217U, // LD2H
|
|
297979217U, // LD2H_IMM
|
|
298293176U, // LD2Q
|
|
298293176U, // LD2Q_IMM
|
|
579601U, // LD2Rv16b
|
|
109647889U, // LD2Rv16b_POST
|
|
612369U, // LD2Rv1d
|
|
101292049U, // LD2Rv1d_POST
|
|
645137U, // LD2Rv2d
|
|
101324817U, // LD2Rv2d_POST
|
|
677905U, // LD2Rv2s
|
|
103454737U, // LD2Rv2s_POST
|
|
710673U, // LD2Rv4h
|
|
107681809U, // LD2Rv4h_POST
|
|
743441U, // LD2Rv4s
|
|
103520273U, // LD2Rv4s_POST
|
|
776209U, // LD2Rv8b
|
|
109844497U, // LD2Rv8b_POST
|
|
808977U, // LD2Rv8h
|
|
107780113U, // LD2Rv8h_POST
|
|
573628U, // LD2Twov16b
|
|
99156156U, // LD2Twov16b_POST
|
|
639164U, // LD2Twov2d
|
|
99221692U, // LD2Twov2d_POST
|
|
671932U, // LD2Twov2s
|
|
101351612U, // LD2Twov2s_POST
|
|
704700U, // LD2Twov4h
|
|
101384380U, // LD2Twov4h_POST
|
|
737468U, // LD2Twov4s
|
|
99319996U, // LD2Twov4s_POST
|
|
770236U, // LD2Twov8b
|
|
101449916U, // LD2Twov8b_POST
|
|
803004U, // LD2Twov8h
|
|
99385532U, // LD2Twov8h_POST
|
|
298000290U, // LD2W
|
|
298000290U, // LD2W_IMM
|
|
116195516U, // LD2i16
|
|
120406204U, // LD2i16_POST
|
|
116228284U, // LD2i32
|
|
122536124U, // LD2i32_POST
|
|
116261052U, // LD2i64
|
|
126763196U, // LD2i64_POST
|
|
116293820U, // LD2i8
|
|
118407356U, // LD2i8_POST
|
|
297944398U, // LD3B
|
|
297944398U, // LD3B_IMM
|
|
297962235U, // LD3D
|
|
297962235U, // LD3D_IMM
|
|
297979229U, // LD3H
|
|
297979229U, // LD3H_IMM
|
|
298293188U, // LD3Q
|
|
298293188U, // LD3Q_IMM
|
|
579607U, // LD3Rv16b
|
|
128522263U, // LD3Rv16b_POST
|
|
612375U, // LD3Rv1d
|
|
113874967U, // LD3Rv1d_POST
|
|
645143U, // LD3Rv2d
|
|
113907735U, // LD3Rv2d_POST
|
|
677911U, // LD3Rv2s
|
|
130717719U, // LD3Rv2s_POST
|
|
710679U, // LD3Rv4h
|
|
132847639U, // LD3Rv4h_POST
|
|
743447U, // LD3Rv4s
|
|
130783255U, // LD3Rv4s_POST
|
|
776215U, // LD3Rv8b
|
|
128718871U, // LD3Rv8b_POST
|
|
808983U, // LD3Rv8h
|
|
132945943U, // LD3Rv8h_POST
|
|
574085U, // LD3Threev16b
|
|
111739525U, // LD3Threev16b_POST
|
|
639621U, // LD3Threev2d
|
|
111805061U, // LD3Threev2d_POST
|
|
672389U, // LD3Threev2s
|
|
113934981U, // LD3Threev2s_POST
|
|
705157U, // LD3Threev4h
|
|
113967749U, // LD3Threev4h_POST
|
|
737925U, // LD3Threev4s
|
|
111903365U, // LD3Threev4s_POST
|
|
770693U, // LD3Threev8b
|
|
114033285U, // LD3Threev8b_POST
|
|
803461U, // LD3Threev8h
|
|
111968901U, // LD3Threev8h_POST
|
|
298000302U, // LD3W
|
|
298000302U, // LD3W_IMM
|
|
116195973U, // LD3i16
|
|
135086725U, // LD3i16_POST
|
|
116228741U, // LD3i32
|
|
137216645U, // LD3i32_POST
|
|
116261509U, // LD3i64
|
|
139346565U, // LD3i64_POST
|
|
116294277U, // LD3i8
|
|
141476485U, // LD3i8_POST
|
|
297944424U, // LD4B
|
|
297944424U, // LD4B_IMM
|
|
297962247U, // LD4D
|
|
297962247U, // LD4D_IMM
|
|
574129U, // LD4Fourv16b
|
|
97059505U, // LD4Fourv16b_POST
|
|
639665U, // LD4Fourv2d
|
|
97125041U, // LD4Fourv2d_POST
|
|
672433U, // LD4Fourv2s
|
|
99254961U, // LD4Fourv2s_POST
|
|
705201U, // LD4Fourv4h
|
|
99287729U, // LD4Fourv4h_POST
|
|
737969U, // LD4Fourv4s
|
|
97223345U, // LD4Fourv4s_POST
|
|
770737U, // LD4Fourv8b
|
|
99353265U, // LD4Fourv8b_POST
|
|
803505U, // LD4Fourv8h
|
|
97288881U, // LD4Fourv8h_POST
|
|
297979241U, // LD4H
|
|
297979241U, // LD4H_IMM
|
|
298293200U, // LD4Q
|
|
298293200U, // LD4Q_IMM
|
|
579613U, // LD4Rv16b
|
|
107550749U, // LD4Rv16b_POST
|
|
612381U, // LD4Rv1d
|
|
99194909U, // LD4Rv1d_POST
|
|
645149U, // LD4Rv2d
|
|
99227677U, // LD4Rv2d_POST
|
|
677917U, // LD4Rv2s
|
|
101357597U, // LD4Rv2s_POST
|
|
710685U, // LD4Rv4h
|
|
103487517U, // LD4Rv4h_POST
|
|
743453U, // LD4Rv4s
|
|
101423133U, // LD4Rv4s_POST
|
|
776221U, // LD4Rv8b
|
|
107747357U, // LD4Rv8b_POST
|
|
808989U, // LD4Rv8h
|
|
103585821U, // LD4Rv8h_POST
|
|
298000314U, // LD4W
|
|
298000314U, // LD4W_IMM
|
|
116196017U, // LD4i16
|
|
122503857U, // LD4i16_POST
|
|
116228785U, // LD4i32
|
|
126730929U, // LD4i32_POST
|
|
116261553U, // LD4i64
|
|
143540913U, // LD4i64_POST
|
|
116294321U, // LD4i8
|
|
120505009U, // LD4i8_POST
|
|
984410U, // LD64B
|
|
2418328948U, // LDADDAB
|
|
2418331006U, // LDADDAH
|
|
2418329180U, // LDADDALB
|
|
2418331180U, // LDADDALH
|
|
2418331874U, // LDADDALW
|
|
2418331874U, // LDADDALX
|
|
2418328358U, // LDADDAW
|
|
2418328358U, // LDADDAX
|
|
2418329116U, // LDADDB
|
|
2418331166U, // LDADDH
|
|
2418329361U, // LDADDLB
|
|
2418331280U, // LDADDLH
|
|
2418332226U, // LDADDLW
|
|
2418332226U, // LDADDLX
|
|
2418330479U, // LDADDW
|
|
2418330479U, // LDADDX
|
|
116260922U, // LDAP1
|
|
44058797U, // LDAPRB
|
|
44060526U, // LDAPRH
|
|
44063001U, // LDAPRW
|
|
849664281U, // LDAPRWpost
|
|
44063001U, // LDAPRX
|
|
849664281U, // LDAPRXpost
|
|
44058840U, // LDAPURBi
|
|
44060569U, // LDAPURHi
|
|
44058981U, // LDAPURSBWi
|
|
44058981U, // LDAPURSBXi
|
|
44060696U, // LDAPURSHWi
|
|
44060696U, // LDAPURSHXi
|
|
44064889U, // LDAPURSWi
|
|
44063094U, // LDAPURXi
|
|
44063094U, // LDAPURbi
|
|
44063094U, // LDAPURdi
|
|
44063094U, // LDAPURhi
|
|
44063094U, // LDAPURi
|
|
44063094U, // LDAPURqi
|
|
44063094U, // LDAPURsi
|
|
44058745U, // LDARB
|
|
44060474U, // LDARH
|
|
44062755U, // LDARW
|
|
44062755U, // LDARX
|
|
2119544U, // LDAXPW
|
|
2119544U, // LDAXPX
|
|
44058856U, // LDAXRB
|
|
44060585U, // LDAXRH
|
|
44063138U, // LDAXRW
|
|
44063138U, // LDAXRX
|
|
2418329004U, // LDCLRAB
|
|
2418331063U, // LDCLRAH
|
|
2418329255U, // LDCLRALB
|
|
2418331220U, // LDCLRALH
|
|
2418332067U, // LDCLRALW
|
|
2418332067U, // LDCLRALX
|
|
2418328642U, // LDCLRAW
|
|
2418328642U, // LDCLRAX
|
|
2418329742U, // LDCLRB
|
|
2418331471U, // LDCLRH
|
|
2418329463U, // LDCLRLB
|
|
2418331316U, // LDCLRLH
|
|
2418332590U, // LDCLRLW
|
|
2418332590U, // LDCLRLX
|
|
271537919U, // LDCLRP
|
|
271533015U, // LDCLRPA
|
|
271536437U, // LDCLRPAL
|
|
271536962U, // LDCLRPL
|
|
2418333867U, // LDCLRW
|
|
2418333867U, // LDCLRX
|
|
2418329013U, // LDEORAB
|
|
2418331072U, // LDEORAH
|
|
2418329265U, // LDEORALB
|
|
2418331230U, // LDEORALH
|
|
2418332097U, // LDEORALW
|
|
2418332097U, // LDEORALX
|
|
2418328669U, // LDEORAW
|
|
2418328669U, // LDEORAX
|
|
2418329765U, // LDEORB
|
|
2418331494U, // LDEORH
|
|
2418329472U, // LDEORLB
|
|
2418331325U, // LDEORLH
|
|
2418332617U, // LDEORLW
|
|
2418332617U, // LDEORLX
|
|
2418333960U, // LDEORW
|
|
2418333960U, // LDEORX
|
|
297960706U, // LDFF1B_D_REAL
|
|
297977090U, // LDFF1B_H_REAL
|
|
297944322U, // LDFF1B_REAL
|
|
297993474U, // LDFF1B_S_REAL
|
|
297962161U, // LDFF1D_REAL
|
|
297962778U, // LDFF1H_D_REAL
|
|
297979162U, // LDFF1H_REAL
|
|
297995546U, // LDFF1H_S_REAL
|
|
297961741U, // LDFF1SB_D_REAL
|
|
297978125U, // LDFF1SB_H_REAL
|
|
297994509U, // LDFF1SB_S_REAL
|
|
297963470U, // LDFF1SH_D_REAL
|
|
297996238U, // LDFF1SH_S_REAL
|
|
297967672U, // LDFF1SW_D_REAL
|
|
297967476U, // LDFF1W_D_REAL
|
|
298000244U, // LDFF1W_REAL
|
|
849661147U, // LDG
|
|
44061863U, // LDGM
|
|
2119384U, // LDIAPPW
|
|
807720664U, // LDIAPPWpost
|
|
2119384U, // LDIAPPX
|
|
807720664U, // LDIAPPXpost
|
|
44058752U, // LDLARB
|
|
44060481U, // LDLARH
|
|
44062761U, // LDLARW
|
|
44062761U, // LDLARX
|
|
297960714U, // LDNF1B_D_IMM_REAL
|
|
297977098U, // LDNF1B_H_IMM_REAL
|
|
297944330U, // LDNF1B_IMM_REAL
|
|
297993482U, // LDNF1B_S_IMM_REAL
|
|
297962169U, // LDNF1D_IMM_REAL
|
|
297962786U, // LDNF1H_D_IMM_REAL
|
|
297979170U, // LDNF1H_IMM_REAL
|
|
297995554U, // LDNF1H_S_IMM_REAL
|
|
297961750U, // LDNF1SB_D_IMM_REAL
|
|
297978134U, // LDNF1SB_H_IMM_REAL
|
|
297994518U, // LDNF1SB_S_IMM_REAL
|
|
297963479U, // LDNF1SH_D_IMM_REAL
|
|
297996247U, // LDNF1SH_S_IMM_REAL
|
|
297967681U, // LDNF1SW_D_IMM_REAL
|
|
297967484U, // LDNF1W_D_IMM_REAL
|
|
298000252U, // LDNF1W_IMM_REAL
|
|
2119351U, // LDNPDi
|
|
2119351U, // LDNPQi
|
|
2119351U, // LDNPSi
|
|
2119351U, // LDNPWi
|
|
2119351U, // LDNPXi
|
|
362956050U, // LDNT1B_2Z
|
|
362956050U, // LDNT1B_2Z_IMM
|
|
2150139154U, // LDNT1B_2Z_STRIDED
|
|
2150139154U, // LDNT1B_2Z_STRIDED_IMM
|
|
362956050U, // LDNT1B_4Z
|
|
362956050U, // LDNT1B_4Z_IMM
|
|
362956050U, // LDNT1B_4Z_STRIDED
|
|
362956050U, // LDNT1B_4Z_STRIDED_IMM
|
|
297944338U, // LDNT1B_ZRI
|
|
297944338U, // LDNT1B_ZRR
|
|
297960722U, // LDNT1B_ZZR_D_REAL
|
|
297993490U, // LDNT1B_ZZR_S_REAL
|
|
362973889U, // LDNT1D_2Z
|
|
362973889U, // LDNT1D_2Z_IMM
|
|
362973889U, // LDNT1D_2Z_STRIDED
|
|
362973889U, // LDNT1D_2Z_STRIDED_IMM
|
|
362973889U, // LDNT1D_4Z
|
|
362973889U, // LDNT1D_4Z_IMM
|
|
362973889U, // LDNT1D_4Z_STRIDED
|
|
362973889U, // LDNT1D_4Z_STRIDED_IMM
|
|
297962177U, // LDNT1D_ZRI
|
|
297962177U, // LDNT1D_ZRR
|
|
297962177U, // LDNT1D_ZZR_D_REAL
|
|
362990890U, // LDNT1H_2Z
|
|
362990890U, // LDNT1H_2Z_IMM
|
|
2150419754U, // LDNT1H_2Z_STRIDED
|
|
2150419754U, // LDNT1H_2Z_STRIDED_IMM
|
|
362990890U, // LDNT1H_4Z
|
|
362990890U, // LDNT1H_4Z_IMM
|
|
362990890U, // LDNT1H_4Z_STRIDED
|
|
362990890U, // LDNT1H_4Z_STRIDED_IMM
|
|
297979178U, // LDNT1H_ZRI
|
|
297979178U, // LDNT1H_ZRR
|
|
297962794U, // LDNT1H_ZZR_D_REAL
|
|
297995562U, // LDNT1H_ZZR_S_REAL
|
|
297961759U, // LDNT1SB_ZZR_D_REAL
|
|
297994527U, // LDNT1SB_ZZR_S_REAL
|
|
297963488U, // LDNT1SH_ZZR_D_REAL
|
|
297996256U, // LDNT1SH_ZZR_S_REAL
|
|
297967690U, // LDNT1SW_ZZR_D_REAL
|
|
363011972U, // LDNT1W_2Z
|
|
363011972U, // LDNT1W_2Z_IMM
|
|
363011972U, // LDNT1W_2Z_STRIDED
|
|
363011972U, // LDNT1W_2Z_STRIDED_IMM
|
|
363011972U, // LDNT1W_4Z
|
|
363011972U, // LDNT1W_4Z_IMM
|
|
363011972U, // LDNT1W_4Z_STRIDED
|
|
363011972U, // LDNT1W_4Z_STRIDED_IMM
|
|
298000260U, // LDNT1W_ZRI
|
|
298000260U, // LDNT1W_ZRR
|
|
297967492U, // LDNT1W_ZZR_D_REAL
|
|
298000260U, // LDNT1W_ZZR_S_REAL
|
|
2119220U, // LDPDi
|
|
807720500U, // LDPDpost
|
|
807720500U, // LDPDpre
|
|
2119220U, // LDPQi
|
|
807720500U, // LDPQpost
|
|
807720500U, // LDPQpre
|
|
2121811U, // LDPSWi
|
|
807723091U, // LDPSWpost
|
|
807723091U, // LDPSWpre
|
|
2119220U, // LDPSi
|
|
807720500U, // LDPSpost
|
|
807720500U, // LDPSpre
|
|
2119220U, // LDPWi
|
|
807720500U, // LDPWpost
|
|
807720500U, // LDPWpre
|
|
2119220U, // LDPXi
|
|
807720500U, // LDPXpost
|
|
807720500U, // LDPXpre
|
|
44057349U, // LDRAAindexed
|
|
849658629U, // LDRAAwriteback
|
|
44058014U, // LDRABindexed
|
|
849659294U, // LDRABwriteback
|
|
849660040U, // LDRBBpost
|
|
849660040U, // LDRBBpre
|
|
44058760U, // LDRBBroW
|
|
44058760U, // LDRBBroX
|
|
44058760U, // LDRBBui
|
|
849664097U, // LDRBpost
|
|
849664097U, // LDRBpre
|
|
44062817U, // LDRBroW
|
|
44062817U, // LDRBroX
|
|
44062817U, // LDRBui
|
|
2149603425U, // LDRDl
|
|
849664097U, // LDRDpost
|
|
849664097U, // LDRDpre
|
|
44062817U, // LDRDroW
|
|
44062817U, // LDRDroX
|
|
44062817U, // LDRDui
|
|
849661769U, // LDRHHpost
|
|
849661769U, // LDRHHpre
|
|
44060489U, // LDRHHroW
|
|
44060489U, // LDRHHroX
|
|
44060489U, // LDRHHui
|
|
849664097U, // LDRHpost
|
|
849664097U, // LDRHpre
|
|
44062817U, // LDRHroW
|
|
44062817U, // LDRHroX
|
|
44062817U, // LDRHui
|
|
2149603425U, // LDRQl
|
|
849664097U, // LDRQpost
|
|
849664097U, // LDRQpre
|
|
44062817U, // LDRQroW
|
|
44062817U, // LDRQroX
|
|
44062817U, // LDRQui
|
|
849660238U, // LDRSBWpost
|
|
849660238U, // LDRSBWpre
|
|
44058958U, // LDRSBWroW
|
|
44058958U, // LDRSBWroX
|
|
44058958U, // LDRSBWui
|
|
849660238U, // LDRSBXpost
|
|
849660238U, // LDRSBXpre
|
|
44058958U, // LDRSBXroW
|
|
44058958U, // LDRSBXroX
|
|
44058958U, // LDRSBXui
|
|
849661953U, // LDRSHWpost
|
|
849661953U, // LDRSHWpre
|
|
44060673U, // LDRSHWroW
|
|
44060673U, // LDRSHWroX
|
|
44060673U, // LDRSHWui
|
|
849661953U, // LDRSHXpost
|
|
849661953U, // LDRSHXpre
|
|
44060673U, // LDRSHXroW
|
|
44060673U, // LDRSHXroX
|
|
44060673U, // LDRSHXui
|
|
2149605474U, // LDRSWl
|
|
849666146U, // LDRSWpost
|
|
849666146U, // LDRSWpre
|
|
44064866U, // LDRSWroW
|
|
44064866U, // LDRSWroX
|
|
44064866U, // LDRSWui
|
|
2149603425U, // LDRSl
|
|
849664097U, // LDRSpost
|
|
849664097U, // LDRSpre
|
|
44062817U, // LDRSroW
|
|
44062817U, // LDRSroX
|
|
44062817U, // LDRSui
|
|
2149603425U, // LDRWl
|
|
849664097U, // LDRWpost
|
|
849664097U, // LDRWpre
|
|
44062817U, // LDRWroW
|
|
44062817U, // LDRWroX
|
|
44062817U, // LDRWui
|
|
2149603425U, // LDRXl
|
|
849664097U, // LDRXpost
|
|
849664097U, // LDRXpre
|
|
44062817U, // LDRXroW
|
|
44062817U, // LDRXroX
|
|
44062817U, // LDRXui
|
|
45062241U, // LDR_PXI
|
|
44062817U, // LDR_TX
|
|
1038433U, // LDR_ZA
|
|
45062241U, // LDR_ZXI
|
|
2418329029U, // LDSETAB
|
|
2418331088U, // LDSETAH
|
|
2418329283U, // LDSETALB
|
|
2418331248U, // LDSETALH
|
|
2418332127U, // LDSETALW
|
|
2418332127U, // LDSETALX
|
|
2418328722U, // LDSETAW
|
|
2418328722U, // LDSETAX
|
|
2418329972U, // LDSETB
|
|
2418331682U, // LDSETH
|
|
2418329523U, // LDSETLB
|
|
2418331341U, // LDSETLH
|
|
2418332687U, // LDSETLW
|
|
2418332687U, // LDSETLX
|
|
271537971U, // LDSETP
|
|
271533066U, // LDSETPA
|
|
271536493U, // LDSETPAL
|
|
271537021U, // LDSETPL
|
|
2418334543U, // LDSETW
|
|
2418334543U, // LDSETX
|
|
2418329038U, // LDSMAXAB
|
|
2418331097U, // LDSMAXAH
|
|
2418329293U, // LDSMAXALB
|
|
2418331258U, // LDSMAXALH
|
|
2418332157U, // LDSMAXALW
|
|
2418332157U, // LDSMAXALX
|
|
2418328778U, // LDSMAXAW
|
|
2418328778U, // LDSMAXAX
|
|
2418330128U, // LDSMAXB
|
|
2418331714U, // LDSMAXH
|
|
2418329532U, // LDSMAXLB
|
|
2418331383U, // LDSMAXLH
|
|
2418332795U, // LDSMAXLW
|
|
2418332795U, // LDSMAXLX
|
|
2418335947U, // LDSMAXW
|
|
2418335947U, // LDSMAXX
|
|
2418328957U, // LDSMINAB
|
|
2418331036U, // LDSMINAH
|
|
2418329225U, // LDSMINALB
|
|
2418331190U, // LDSMINALH
|
|
2418331914U, // LDSMINALW
|
|
2418331914U, // LDSMINALX
|
|
2418328458U, // LDSMINAW
|
|
2418328458U, // LDSMINAX
|
|
2418329575U, // LDSMINB
|
|
2418331403U, // LDSMINH
|
|
2418329436U, // LDSMINLB
|
|
2418331289U, // LDSMINLH
|
|
2418332436U, // LDSMINLW
|
|
2418332436U, // LDSMINLX
|
|
2418332960U, // LDSMINW
|
|
2418332960U, // LDSMINX
|
|
44058805U, // LDTRBi
|
|
44060534U, // LDTRHi
|
|
44058965U, // LDTRSBWi
|
|
44058965U, // LDTRSBXi
|
|
44060680U, // LDTRSHWi
|
|
44060680U, // LDTRSHXi
|
|
44064873U, // LDTRSWi
|
|
44063052U, // LDTRWi
|
|
44063052U, // LDTRXi
|
|
2418329048U, // LDUMAXAB
|
|
2418331107U, // LDUMAXAH
|
|
2418329304U, // LDUMAXALB
|
|
2418331269U, // LDUMAXALH
|
|
2418332167U, // LDUMAXALW
|
|
2418332167U, // LDUMAXALX
|
|
2418328787U, // LDUMAXAW
|
|
2418328787U, // LDUMAXAX
|
|
2418330137U, // LDUMAXB
|
|
2418331723U, // LDUMAXH
|
|
2418329542U, // LDUMAXLB
|
|
2418331393U, // LDUMAXLH
|
|
2418332804U, // LDUMAXLW
|
|
2418332804U, // LDUMAXLX
|
|
2418335955U, // LDUMAXW
|
|
2418335955U, // LDUMAXX
|
|
2418328967U, // LDUMINAB
|
|
2418331046U, // LDUMINAH
|
|
2418329236U, // LDUMINALB
|
|
2418331201U, // LDUMINALH
|
|
2418331924U, // LDUMINALW
|
|
2418331924U, // LDUMINALX
|
|
2418328467U, // LDUMINAW
|
|
2418328467U, // LDUMINAX
|
|
2418329584U, // LDUMINB
|
|
2418331412U, // LDUMINH
|
|
2418329446U, // LDUMINLB
|
|
2418331299U, // LDUMINLH
|
|
2418332445U, // LDUMINLW
|
|
2418332445U, // LDUMINLX
|
|
2418332968U, // LDUMINW
|
|
2418332968U, // LDUMINX
|
|
44058825U, // LDURBBi
|
|
44063081U, // LDURBi
|
|
44063081U, // LDURDi
|
|
44060554U, // LDURHHi
|
|
44063081U, // LDURHi
|
|
44063081U, // LDURQi
|
|
44058973U, // LDURSBWi
|
|
44058973U, // LDURSBXi
|
|
44060688U, // LDURSHWi
|
|
44060688U, // LDURSHXi
|
|
44064881U, // LDURSWi
|
|
44063081U, // LDURSi
|
|
44063081U, // LDURWi
|
|
44063081U, // LDURXi
|
|
24809U, // LDX
|
|
2119572U, // LDXPW
|
|
2119572U, // LDXPX
|
|
44058864U, // LDXRB
|
|
44060593U, // LDXRH
|
|
44063145U, // LDXRW
|
|
44063145U, // LDXRX
|
|
24890U, // LDY
|
|
24989U, // LDZ
|
|
20655U, // LDZI
|
|
3223361788U, // LSLR_ZPmZ_B
|
|
3223378172U, // LSLR_ZPmZ_D
|
|
3519092988U, // LSLR_ZPmZ_H
|
|
3223410940U, // LSLR_ZPmZ_S
|
|
2118638U, // LSLVWr
|
|
2118638U, // LSLVXr
|
|
3223360494U, // LSL_WIDE_ZPmZ_B
|
|
3519091694U, // LSL_WIDE_ZPmZ_H
|
|
3223409646U, // LSL_WIDE_ZPmZ_S
|
|
2135022U, // LSL_WIDE_ZZZ_B
|
|
2189497326U, // LSL_WIDE_ZZZ_H
|
|
270619630U, // LSL_WIDE_ZZZ_S
|
|
3223360494U, // LSL_ZPmI_B
|
|
3223376878U, // LSL_ZPmI_D
|
|
3519091694U, // LSL_ZPmI_H
|
|
3223409646U, // LSL_ZPmI_S
|
|
3223360494U, // LSL_ZPmZ_B
|
|
3223376878U, // LSL_ZPmZ_D
|
|
3519091694U, // LSL_ZPmZ_H
|
|
3223409646U, // LSL_ZPmZ_S
|
|
2135022U, // LSL_ZZI_B
|
|
2418070510U, // LSL_ZZI_D
|
|
2189497326U, // LSL_ZZI_H
|
|
270619630U, // LSL_ZZI_S
|
|
3223361835U, // LSRR_ZPmZ_B
|
|
3223378219U, // LSRR_ZPmZ_D
|
|
3519093035U, // LSRR_ZPmZ_H
|
|
3223410987U, // LSRR_ZPmZ_S
|
|
2119996U, // LSRVWr
|
|
2119996U, // LSRVXr
|
|
3223361852U, // LSR_WIDE_ZPmZ_B
|
|
3519093052U, // LSR_WIDE_ZPmZ_H
|
|
3223411004U, // LSR_WIDE_ZPmZ_S
|
|
2136380U, // LSR_WIDE_ZZZ_B
|
|
2189498684U, // LSR_WIDE_ZZZ_H
|
|
270620988U, // LSR_WIDE_ZZZ_S
|
|
3223361852U, // LSR_ZPmI_B
|
|
3223378236U, // LSR_ZPmI_D
|
|
3519093052U, // LSR_ZPmI_H
|
|
3223411004U, // LSR_ZPmI_S
|
|
3223361852U, // LSR_ZPmZ_B
|
|
3223378236U, // LSR_ZPmZ_D
|
|
3519093052U, // LSR_ZPmZ_H
|
|
3223411004U, // LSR_ZPmZ_S
|
|
2136380U, // LSR_ZZI_B
|
|
2418071868U, // LSR_ZZI_D
|
|
2189498684U, // LSR_ZZI_H
|
|
270620988U, // LSR_ZZI_S
|
|
2690744533U, // LUT2v16f8
|
|
2969665749U, // LUT2v8f16
|
|
2690745014U, // LUT4v16f8
|
|
2969666230U, // LUT4v8f16
|
|
2208448725U, // LUTI2_2ZTZI_B
|
|
2208481493U, // LUTI2_2ZTZI_H
|
|
2208497877U, // LUTI2_2ZTZI_S
|
|
2208448725U, // LUTI2_4ZTZI_B
|
|
2208481493U, // LUTI2_4ZTZI_H
|
|
2208497877U, // LUTI2_4ZTZI_S
|
|
2654421U, // LUTI2_S_2ZTZI_B
|
|
2932949U, // LUTI2_S_2ZTZI_H
|
|
2208448725U, // LUTI2_S_4ZTZI_B
|
|
2208481493U, // LUTI2_S_4ZTZI_H
|
|
2130133U, // LUTI2_ZTZI_B
|
|
2208366805U, // LUTI2_ZTZI_H
|
|
2179285U, // LUTI2_ZTZI_S
|
|
2686484693U, // LUTI2_ZZZI_B
|
|
2183200981U, // LUTI2_ZZZI_H
|
|
2208449206U, // LUTI4_2ZTZI_B
|
|
2208481974U, // LUTI4_2ZTZI_H
|
|
2208498358U, // LUTI4_2ZTZI_S
|
|
2208481974U, // LUTI4_4ZTZI_H
|
|
2208498358U, // LUTI4_4ZTZI_S
|
|
2208449206U, // LUTI4_4ZZT2Z
|
|
2654902U, // LUTI4_S_2ZTZI_B
|
|
2933430U, // LUTI4_S_2ZTZI_H
|
|
2208481974U, // LUTI4_S_4ZTZI_H
|
|
2208449206U, // LUTI4_S_4ZZT2Z
|
|
2183201462U, // LUTI4_Z2ZZI_H
|
|
2130614U, // LUTI4_ZTZI_B
|
|
2208367286U, // LUTI4_ZTZI_H
|
|
2179766U, // LUTI4_ZTZI_S
|
|
2686485174U, // LUTI4_ZZZI_B
|
|
2183201462U, // LUTI4_ZZZI_H
|
|
17097U, // MAC16
|
|
2121084U, // MADDPT
|
|
2116508U, // MADDWrrr
|
|
2116508U, // MADDXrrr
|
|
1075895669U, // MAD_CPA
|
|
3223358228U, // MAD_ZPmZZ_B
|
|
3223374612U, // MAD_ZPmZZ_D
|
|
3519089428U, // MAD_ZPmZZ_H
|
|
3223407380U, // MAD_ZPmZZ_S
|
|
3223358999U, // MATCH_PPzZZ_B
|
|
2713783831U, // MATCH_PPzZZ_H
|
|
22086U, // MATFP
|
|
23743U, // MATINT
|
|
1075895654U, // MLA_CPA
|
|
3223356256U, // MLA_ZPmZZ_B
|
|
3223372640U, // MLA_ZPmZZ_D
|
|
3519087456U, // MLA_ZPmZZ_H
|
|
3223405408U, // MLA_ZPmZZ_S
|
|
1075888992U, // MLA_ZZZI_D
|
|
2195784544U, // MLA_ZZZI_H
|
|
1344357216U, // MLA_ZZZI_S
|
|
2959213408U, // MLAv16i8
|
|
2961310560U, // MLAv2i32
|
|
2961310560U, // MLAv2i32_indexed
|
|
2965504864U, // MLAv4i16
|
|
2965504864U, // MLAv4i16_indexed
|
|
2967602016U, // MLAv4i32
|
|
2967602016U, // MLAv4i32_indexed
|
|
2969699168U, // MLAv8i16
|
|
2969699168U, // MLAv8i16_indexed
|
|
2971796320U, // MLAv8i8
|
|
3223362131U, // MLS_ZPmZZ_B
|
|
3223378515U, // MLS_ZPmZZ_D
|
|
3519093331U, // MLS_ZPmZZ_H
|
|
3223411283U, // MLS_ZPmZZ_S
|
|
1075894867U, // MLS_ZZZI_D
|
|
2195790419U, // MLS_ZZZI_H
|
|
1344363091U, // MLS_ZZZI_S
|
|
2959219283U, // MLSv16i8
|
|
2961316435U, // MLSv2i32
|
|
2961316435U, // MLSv2i32_indexed
|
|
2965510739U, // MLSv4i16
|
|
2965510739U, // MLSv4i16_indexed
|
|
2967607891U, // MLSv4i32
|
|
2967607891U, // MLSv4i32_indexed
|
|
2969705043U, // MLSv8i16
|
|
2969705043U, // MLSv8i16_indexed
|
|
2971802195U, // MLSv8i8
|
|
145712034U, // MOPSSETGE
|
|
145712095U, // MOPSSETGEN
|
|
145712983U, // MOPSSETGET
|
|
145712456U, // MOPSSETGETN
|
|
3368182141U, // MOVAZ_2ZMI_H_B
|
|
3368198525U, // MOVAZ_2ZMI_H_D
|
|
3368214909U, // MOVAZ_2ZMI_H_H
|
|
3368231293U, // MOVAZ_2ZMI_H_S
|
|
3370279293U, // MOVAZ_2ZMI_V_B
|
|
3370295677U, // MOVAZ_2ZMI_V_D
|
|
3370312061U, // MOVAZ_2ZMI_V_H
|
|
3370328445U, // MOVAZ_2ZMI_V_S
|
|
3636617597U, // MOVAZ_4ZMI_H_B
|
|
3636633981U, // MOVAZ_4ZMI_H_D
|
|
3636650365U, // MOVAZ_4ZMI_H_H
|
|
3636666749U, // MOVAZ_4ZMI_H_S
|
|
3638714749U, // MOVAZ_4ZMI_V_B
|
|
3638731133U, // MOVAZ_4ZMI_V_D
|
|
3638747517U, // MOVAZ_4ZMI_V_H
|
|
3638763901U, // MOVAZ_4ZMI_V_S
|
|
3909263741U, // MOVAZ_VG2_2ZM
|
|
4177699197U, // MOVAZ_VG4_4ZM
|
|
2138493U, // MOVAZ_ZMI_H_B
|
|
2154877U, // MOVAZ_ZMI_H_D
|
|
421601661U, // MOVAZ_ZMI_H_H
|
|
422011261U, // MOVAZ_ZMI_H_Q
|
|
2187645U, // MOVAZ_ZMI_H_S
|
|
270573949U, // MOVAZ_ZMI_V_B
|
|
270590333U, // MOVAZ_ZMI_V_D
|
|
423698813U, // MOVAZ_ZMI_V_H
|
|
424108413U, // MOVAZ_ZMI_V_Q
|
|
270623101U, // MOVAZ_ZMI_V_S
|
|
958547140U, // MOVA_2ZMXI_H_B
|
|
958563524U, // MOVA_2ZMXI_H_D
|
|
958579908U, // MOVA_2ZMXI_H_H
|
|
958596292U, // MOVA_2ZMXI_H_S
|
|
960644292U, // MOVA_2ZMXI_V_B
|
|
960660676U, // MOVA_2ZMXI_V_D
|
|
960677060U, // MOVA_2ZMXI_V_H
|
|
960693444U, // MOVA_2ZMXI_V_S
|
|
958547140U, // MOVA_4ZMXI_H_B
|
|
958563524U, // MOVA_4ZMXI_H_D
|
|
958579908U, // MOVA_4ZMXI_H_H
|
|
958596292U, // MOVA_4ZMXI_H_S
|
|
960644292U, // MOVA_4ZMXI_V_B
|
|
960660676U, // MOVA_4ZMXI_V_D
|
|
960677060U, // MOVA_4ZMXI_V_H
|
|
960693444U, // MOVA_4ZMXI_V_S
|
|
2233992388U, // MOVA_MXI2Z_H_B
|
|
2233992388U, // MOVA_MXI2Z_H_D
|
|
2233992388U, // MOVA_MXI2Z_H_H
|
|
2233992388U, // MOVA_MXI2Z_H_S
|
|
2234008772U, // MOVA_MXI2Z_V_B
|
|
2234008772U, // MOVA_MXI2Z_V_D
|
|
2234008772U, // MOVA_MXI2Z_V_H
|
|
2234008772U, // MOVA_MXI2Z_V_S
|
|
2233992388U, // MOVA_MXI4Z_H_B
|
|
2233992388U, // MOVA_MXI4Z_H_D
|
|
2233992388U, // MOVA_MXI4Z_H_H
|
|
2233992388U, // MOVA_MXI4Z_H_S
|
|
2234008772U, // MOVA_MXI4Z_V_B
|
|
2234008772U, // MOVA_MXI4Z_V_D
|
|
2234008772U, // MOVA_MXI4Z_V_H
|
|
2234008772U, // MOVA_MXI4Z_V_S
|
|
3915547844U, // MOVA_VG2_2ZMXI
|
|
3798156484U, // MOVA_VG2_MXI2Z
|
|
4183983300U, // MOVA_VG4_4ZMXI
|
|
4066591940U, // MOVA_VG4_MXI4Z
|
|
538988713U, // MOVID
|
|
811700393U, // MOVIv16b_ns
|
|
547459241U, // MOVIv2d_ns
|
|
813797545U, // MOVIv2i32
|
|
813797545U, // MOVIv2s_msl
|
|
817991849U, // MOVIv4i16
|
|
820089001U, // MOVIv4i32
|
|
820089001U, // MOVIv4s_msl
|
|
824283305U, // MOVIv8b_ns
|
|
822186153U, // MOVIv8i16
|
|
1881166030U, // MOVKWi
|
|
1881166030U, // MOVKXi
|
|
807425466U, // MOVNWi
|
|
807425466U, // MOVNXi
|
|
270573820U, // MOVPRFX_ZPmZ_B
|
|
270590204U, // MOVPRFX_ZPmZ_D
|
|
541139196U, // MOVPRFX_ZPmZ_H
|
|
270622972U, // MOVPRFX_ZPmZ_S
|
|
3223363836U, // MOVPRFX_ZPzZ_B
|
|
3223380220U, // MOVPRFX_ZPzZ_D
|
|
2713788668U, // MOVPRFX_ZPzZ_H
|
|
3223412988U, // MOVPRFX_ZPzZ_S
|
|
3224346876U, // MOVPRFX_ZZ
|
|
1233149423U, // MOVT
|
|
1501584879U, // MOVT_TIX
|
|
2121199U, // MOVT_XTI
|
|
807428549U, // MOVZWi
|
|
807428549U, // MOVZXi
|
|
1055447U, // MRRS
|
|
1612733126U, // MRS
|
|
3223357754U, // MSB_ZPmZZ_B
|
|
3223374138U, // MSB_ZPmZZ_D
|
|
3519088954U, // MSB_ZPmZZ_H
|
|
3223406906U, // MSB_ZPmZZ_S
|
|
1672501569U, // MSR
|
|
162552113U, // MSRR
|
|
1087809U, // MSRpstateImm1
|
|
1087809U, // MSRpstateImm4
|
|
1104193U, // MSRpstatesvcrImm1
|
|
2121069U, // MSUBPT
|
|
2116046U, // MSUBWrrr
|
|
2116046U, // MSUBXrrr
|
|
2955021015U, // MUL53HI
|
|
2955021027U, // MUL53LO
|
|
2135109U, // MUL_ZI_B
|
|
2418070597U, // MUL_ZI_D
|
|
2189497413U, // MUL_ZI_H
|
|
270619717U, // MUL_ZI_S
|
|
3223360581U, // MUL_ZPmZ_B
|
|
3223376965U, // MUL_ZPmZ_D
|
|
3519091781U, // MUL_ZPmZ_H
|
|
3223409733U, // MUL_ZPmZ_S
|
|
2418070597U, // MUL_ZZZI_D
|
|
2189497413U, // MUL_ZZZI_H
|
|
270619717U, // MUL_ZZZI_S
|
|
2135109U, // MUL_ZZZ_B
|
|
2418070597U, // MUL_ZZZ_D
|
|
2189497413U, // MUL_ZZZ_H
|
|
270619717U, // MUL_ZZZ_S
|
|
811701317U, // MULv16i8
|
|
813798469U, // MULv2i32
|
|
813798469U, // MULv2i32_indexed
|
|
817992773U, // MULv4i16
|
|
817992773U, // MULv4i16_indexed
|
|
820089925U, // MULv4i32
|
|
820089925U, // MULv4i32_indexed
|
|
822187077U, // MULv8i16
|
|
822187077U, // MULv8i16_indexed
|
|
824284229U, // MULv8i8
|
|
813797526U, // MVNIv2i32
|
|
813797526U, // MVNIv2s_msl
|
|
817991830U, // MVNIv4i16
|
|
820088982U, // MVNIv4i32
|
|
820088982U, // MVNIv4s_msl
|
|
822186134U, // MVNIv8i16
|
|
3223362078U, // NANDS_PPzPP
|
|
3223358407U, // NAND_PPzPP
|
|
2418070500U, // NBSL_ZZZZ
|
|
270568673U, // NEG_ZPmZ_B
|
|
270585057U, // NEG_ZPmZ_D
|
|
541134049U, // NEG_ZPmZ_H
|
|
270617825U, // NEG_ZPmZ_S
|
|
811699425U, // NEGv16i8
|
|
2116833U, // NEGv1i64
|
|
813796577U, // NEGv2i32
|
|
815893729U, // NEGv2i64
|
|
817990881U, // NEGv4i16
|
|
820088033U, // NEGv4i32
|
|
822185185U, // NEGv8i16
|
|
824282337U, // NEGv8i8
|
|
3223358998U, // NMATCH_PPzZZ_B
|
|
2713783830U, // NMATCH_PPzZZ_H
|
|
3223362257U, // NORS_PPzPP
|
|
3223361807U, // NOR_PPzPP
|
|
270572897U, // NOT_ZPmZ_B
|
|
270589281U, // NOT_ZPmZ_D
|
|
541138273U, // NOT_ZPmZ_H
|
|
270622049U, // NOT_ZPmZ_S
|
|
811703649U, // NOTv16i8
|
|
824286561U, // NOTv8i8
|
|
3223362170U, // ORNS_PPzPP
|
|
2119011U, // ORNWrs
|
|
2119011U, // ORNXrs
|
|
3223360867U, // ORN_PPzPP
|
|
811701603U, // ORNv16i8
|
|
824284515U, // ORNv8i8
|
|
3227623221U, // ORQV_VPZ_B
|
|
3231817525U, // ORQV_VPZ_D
|
|
3238108981U, // ORQV_VPZ_H
|
|
3236011829U, // ORQV_VPZ_S
|
|
3223362269U, // ORRS_PPzPP
|
|
2119968U, // ORRWri
|
|
2119968U, // ORRWrs
|
|
2119968U, // ORRXri
|
|
2119968U, // ORRXrs
|
|
3223361824U, // ORR_PPzPP
|
|
2418071840U, // ORR_ZI
|
|
3223361824U, // ORR_ZPmZ_B
|
|
3223378208U, // ORR_ZPmZ_D
|
|
3519093024U, // ORR_ZPmZ_H
|
|
3223410976U, // ORR_ZPmZ_S
|
|
2418071840U, // ORR_ZZZ
|
|
811702560U, // ORRv16i8
|
|
1887574304U, // ORRv2i32
|
|
1891768608U, // ORRv4i16
|
|
1893865760U, // ORRv4i32
|
|
1895962912U, // ORRv8i16
|
|
824285472U, // ORRv8i8
|
|
253780U, // ORV_VPZ_B
|
|
1657020244U, // ORV_VPZ_D
|
|
1659133780U, // ORV_VPZ_H
|
|
1638178644U, // ORV_VPZ_S
|
|
807715615U, // PACDA
|
|
807716373U, // PACDB
|
|
312540U, // PACDZA
|
|
313890U, // PACDZB
|
|
2114364U, // PACGA
|
|
807715658U, // PACIA
|
|
8974U, // PACIA1716
|
|
8891U, // PACIA171615
|
|
8939U, // PACIASP
|
|
10307U, // PACIASPPC
|
|
8882U, // PACIAZ
|
|
807716408U, // PACIB
|
|
8828U, // PACIB1716
|
|
8915U, // PACIB171615
|
|
8965U, // PACIBSP
|
|
10329U, // PACIBSPPC
|
|
8948U, // PACIBZ
|
|
312556U, // PACIZA
|
|
313906U, // PACIZB
|
|
9000U, // PACM
|
|
10295U, // PACNBIASPPC
|
|
10317U, // PACNBIBSPPC
|
|
1168268834U, // PEXT_2PCI_B
|
|
1168285218U, // PEXT_2PCI_D
|
|
1168301602U, // PEXT_2PCI_H
|
|
1168317986U, // PEXT_2PCI_S
|
|
2149621282U, // PEXT_PCI_B
|
|
2149637666U, // PEXT_PCI_D
|
|
1168186914U, // PEXT_PCI_H
|
|
2149670434U, // PEXT_PCI_S
|
|
35971U, // PFALSE
|
|
3223362977U, // PFIRST_B
|
|
3223363303U, // PMOV_PZI_B
|
|
3223379687U, // PMOV_PZI_D
|
|
1103175399U, // PMOV_PZI_H
|
|
3223412455U, // PMOV_PZI_S
|
|
2043649767U, // PMOV_ZIP_B
|
|
3654262503U, // PMOV_ZIP_D
|
|
701472487U, // PMOV_ZIP_H
|
|
1238343399U, // PMOV_ZIP_S
|
|
270583620U, // PMULLB_ZZZ_D
|
|
2197882692U, // PMULLB_ZZZ_H
|
|
166152004U, // PMULLB_ZZZ_Q
|
|
270588977U, // PMULLT_ZZZ_D
|
|
2197888049U, // PMULLT_ZZZ_H
|
|
166157361U, // PMULLT_ZZZ_Q
|
|
822182232U, // PMULLv16i8
|
|
2315358975U, // PMULLv1i64
|
|
2583789912U, // PMULLv2i64
|
|
822186751U, // PMULLv8i8
|
|
2135121U, // PMUL_ZZZ_B
|
|
811701329U, // PMULv16i8
|
|
824284241U, // PMULv8i8
|
|
3223363099U, // PNEXT_B
|
|
3223379483U, // PNEXT_D
|
|
2176917019U, // PNEXT_H
|
|
3223412251U, // PNEXT_S
|
|
2194736683U, // PRFB_D_PZI
|
|
2234582571U, // PRFB_D_SCALED
|
|
2234582571U, // PRFB_D_SXTW_SCALED
|
|
2234582571U, // PRFB_D_UXTW_SCALED
|
|
2234582571U, // PRFB_PRI
|
|
2234582571U, // PRFB_PRR
|
|
2175862315U, // PRFB_S_PZI
|
|
2234582571U, // PRFB_S_SXTW_SCALED
|
|
2234582571U, // PRFB_S_UXTW_SCALED
|
|
2194738106U, // PRFD_D_PZI
|
|
2234583994U, // PRFD_D_SCALED
|
|
2234583994U, // PRFD_D_SXTW_SCALED
|
|
2234583994U, // PRFD_D_UXTW_SCALED
|
|
2234583994U, // PRFD_PRI
|
|
2234583994U, // PRFD_PRR
|
|
2175863738U, // PRFD_S_PZI
|
|
2234583994U, // PRFD_S_SXTW_SCALED
|
|
2234583994U, // PRFD_S_UXTW_SCALED
|
|
2194738726U, // PRFH_D_PZI
|
|
2234584614U, // PRFH_D_SCALED
|
|
2234584614U, // PRFH_D_SXTW_SCALED
|
|
2234584614U, // PRFH_D_UXTW_SCALED
|
|
2234584614U, // PRFH_PRI
|
|
2234584614U, // PRFH_PRR
|
|
2175864358U, // PRFH_S_PZI
|
|
2234584614U, // PRFH_S_SXTW_SCALED
|
|
2234584614U, // PRFH_S_UXTW_SCALED
|
|
2150716577U, // PRFMl
|
|
45175969U, // PRFMroW
|
|
45175969U, // PRFMroX
|
|
45175969U, // PRFMui
|
|
45176045U, // PRFUMi
|
|
2194743307U, // PRFW_D_PZI
|
|
2234589195U, // PRFW_D_SCALED
|
|
2234589195U, // PRFW_D_SXTW_SCALED
|
|
2234589195U, // PRFW_D_UXTW_SCALED
|
|
2234589195U, // PRFW_PRI
|
|
2234589195U, // PRFW_PRR
|
|
2175868939U, // PRFW_S_PZI
|
|
2234589195U, // PRFW_S_SXTW_SCALED
|
|
2234589195U, // PRFW_S_UXTW_SCALED
|
|
3224343160U, // PSEL_PPPRI_B
|
|
3224343160U, // PSEL_PPPRI_D
|
|
3224343160U, // PSEL_PPPRI_H
|
|
3224343160U, // PSEL_PPPRI_S
|
|
3120531U, // PTEST_PP
|
|
2954926629U, // PTRUES_B
|
|
2954943013U, // PTRUES_D
|
|
169941541U, // PTRUES_H
|
|
2954975781U, // PTRUES_S
|
|
2954923165U, // PTRUE_B
|
|
1150109U, // PTRUE_C_B
|
|
1166493U, // PTRUE_C_D
|
|
1182877U, // PTRUE_C_H
|
|
1199261U, // PTRUE_C_S
|
|
2954939549U, // PTRUE_D
|
|
169938077U, // PTRUE_H
|
|
2954972317U, // PTRUE_S
|
|
1661014116U, // PUNPKHI_PP
|
|
1661015505U, // PUNPKLO_PP
|
|
1881180126U, // RADDHNB_ZZZ_B
|
|
2172717022U, // RADDHNB_ZZZ_H
|
|
2418100190U, // RADDHNB_ZZZ_S
|
|
2686491816U, // RADDHNT_ZZZ_B
|
|
2174819496U, // RADDHNT_ZZZ_H
|
|
1075928232U, // RADDHNT_ZZZ_S
|
|
813798666U, // RADDHNv2i64_v2i32
|
|
2967601591U, // RADDHNv2i64_v4i32
|
|
817992970U, // RADDHNv4i32_v4i16
|
|
2969698743U, // RADDHNv4i32_v8i16
|
|
2959212983U, // RADDHNv8i16_v16i8
|
|
824284426U, // RADDHNv8i16_v8i8
|
|
815890593U, // RAX1
|
|
2418065569U, // RAX1_ZZZ_D
|
|
2120581U, // RBITWr
|
|
2120581U, // RBITXr
|
|
270572421U, // RBIT_ZPmZ_B
|
|
270588805U, // RBIT_ZPmZ_D
|
|
541137797U, // RBIT_ZPmZ_H
|
|
270621573U, // RBIT_ZPmZ_S
|
|
811703173U, // RBITv16i8
|
|
824286085U, // RBITv8i8
|
|
807721413U, // RCWCAS
|
|
807715977U, // RCWCASA
|
|
807719381U, // RCWCASAL
|
|
807719899U, // RCWCASL
|
|
415524U, // RCWCASP
|
|
410624U, // RCWCASPA
|
|
414050U, // RCWCASPAL
|
|
414571U, // RCWCASPL
|
|
2418333883U, // RCWCLR
|
|
2418328660U, // RCWCLRA
|
|
2418332087U, // RCWCLRAL
|
|
2418332608U, // RCWCLRL
|
|
271537937U, // RCWCLRP
|
|
271533035U, // RCWCLRPA
|
|
271536459U, // RCWCLRPAL
|
|
271536982U, // RCWCLRPL
|
|
2418333874U, // RCWCLRS
|
|
2418328650U, // RCWCLRSA
|
|
2418332076U, // RCWCLRSAL
|
|
2418332598U, // RCWCLRSL
|
|
271537927U, // RCWCLRSP
|
|
271533024U, // RCWCLRSPA
|
|
271536447U, // RCWCLRSPAL
|
|
271536971U, // RCWCLRSPL
|
|
807721404U, // RCWSCAS
|
|
807715967U, // RCWSCASA
|
|
807719370U, // RCWSCASAL
|
|
807719889U, // RCWSCASL
|
|
415514U, // RCWSCASP
|
|
410613U, // RCWSCASPA
|
|
414038U, // RCWSCASPAL
|
|
414560U, // RCWSCASPL
|
|
2418334559U, // RCWSET
|
|
2418328740U, // RCWSETA
|
|
2418332147U, // RCWSETAL
|
|
2418332705U, // RCWSETL
|
|
271537989U, // RCWSETP
|
|
271533086U, // RCWSETPA
|
|
271536515U, // RCWSETPAL
|
|
271537041U, // RCWSETPL
|
|
2418334550U, // RCWSETS
|
|
2418328730U, // RCWSETSA
|
|
2418332136U, // RCWSETSAL
|
|
2418332695U, // RCWSETSL
|
|
271537979U, // RCWSETSP
|
|
271533075U, // RCWSETSPA
|
|
271536503U, // RCWSETSPAL
|
|
271537030U, // RCWSETSPL
|
|
2418333552U, // RCWSWP
|
|
2418328626U, // RCWSWPA
|
|
2418332057U, // RCWSWPAL
|
|
2418332581U, // RCWSWPL
|
|
271537898U, // RCWSWPP
|
|
271533005U, // RCWSWPPA
|
|
271536426U, // RCWSWPPAL
|
|
271536952U, // RCWSWPPL
|
|
2418333543U, // RCWSWPS
|
|
2418328616U, // RCWSWPSA
|
|
2418332046U, // RCWSWPSAL
|
|
2418332571U, // RCWSWPSL
|
|
271537888U, // RCWSWPSP
|
|
271532994U, // RCWSWPSPA
|
|
271536414U, // RCWSWPSPAL
|
|
271536941U, // RCWSWPSPL
|
|
3223362238U, // RDFFRS_PPz
|
|
3223361646U, // RDFFR_PPz_REAL
|
|
39022U, // RDFFR_P_REAL
|
|
2118772U, // RDSVLI_XI
|
|
2118758U, // RDVLI_XI
|
|
23370U, // RET
|
|
10279U, // RETAA
|
|
330357U, // RETAASPPCi
|
|
19061U, // RETAASPPCr
|
|
10286U, // RETAB
|
|
330379U, // RETABSPPCi
|
|
19083U, // RETABSPPCr
|
|
2114271U, // REV16Wr
|
|
2114271U, // REV16Xr
|
|
811696863U, // REV16v16i8
|
|
824279775U, // REV16v8i8
|
|
2113717U, // REV32Xr
|
|
811696309U, // REV32v16i8
|
|
817987765U, // REV32v4i16
|
|
822182069U, // REV32v8i16
|
|
824279221U, // REV32v8i8
|
|
811696810U, // REV64v16i8
|
|
813793962U, // REV64v2i32
|
|
817988266U, // REV64v4i16
|
|
820085418U, // REV64v4i32
|
|
822182570U, // REV64v8i16
|
|
824279722U, // REV64v8i8
|
|
270584298U, // REVB_ZPmZ_D
|
|
541133290U, // REVB_ZPmZ_H
|
|
270617066U, // REVB_ZPmZ_S
|
|
2689027062U, // REVD_ZPmZ
|
|
270585916U, // REVH_ZPmZ_D
|
|
270618684U, // REVH_ZPmZ_S
|
|
270590101U, // REVW_ZPmZ_D
|
|
2121356U, // REVWr
|
|
2121356U, // REVXr
|
|
2137740U, // REV_PP_B
|
|
2418073228U, // REV_PP_D
|
|
1652629132U, // REV_PP_H
|
|
270622348U, // REV_PP_S
|
|
2137740U, // REV_ZZ_B
|
|
2418073228U, // REV_ZZ_D
|
|
1652629132U, // REV_ZZ_H
|
|
270622348U, // REV_ZZ_S
|
|
2116782U, // RMIF
|
|
2119956U, // RORVWr
|
|
2119956U, // RORVXr
|
|
1217696U, // RPRFM
|
|
1881180173U, // RSHRNB_ZZI_B
|
|
2172717069U, // RSHRNB_ZZI_H
|
|
2418100237U, // RSHRNB_ZZI_S
|
|
2686491867U, // RSHRNT_ZZI_B
|
|
2174819547U, // RSHRNT_ZZI_H
|
|
1075928283U, // RSHRNT_ZZI_S
|
|
2959213012U, // RSHRNv16i8_shift
|
|
813798739U, // RSHRNv2i32_shift
|
|
817993043U, // RSHRNv4i16_shift
|
|
2967601620U, // RSHRNv4i32_shift
|
|
2969698772U, // RSHRNv8i16_shift
|
|
824284499U, // RSHRNv8i8_shift
|
|
1881180117U, // RSUBHNB_ZZZ_B
|
|
2172717013U, // RSUBHNB_ZZZ_H
|
|
2418100181U, // RSUBHNB_ZZZ_S
|
|
2686491807U, // RSUBHNT_ZZZ_B
|
|
2174819487U, // RSUBHNT_ZZZ_H
|
|
1075928223U, // RSUBHNT_ZZZ_S
|
|
813798658U, // RSUBHNv2i64_v2i32
|
|
2967601582U, // RSUBHNv2i64_v4i32
|
|
817992962U, // RSUBHNv4i32_v4i16
|
|
2969698734U, // RSUBHNv4i32_v8i16
|
|
2959212974U, // RSUBHNv8i16_v16i8
|
|
824284418U, // RSUBHNv8i16_v8i8
|
|
1344325196U, // SABALB_ZZZ_D
|
|
2220951116U, // SABALB_ZZZ_H
|
|
2686535244U, // SABALB_ZZZ_S
|
|
1344330648U, // SABALT_ZZZ_D
|
|
2220956568U, // SABALT_ZZZ_H
|
|
2686540696U, // SABALT_ZZZ_S
|
|
2969698524U, // SABALv16i8_v8i16
|
|
2963411156U, // SABALv2i32_v2i64
|
|
2967605460U, // SABALv4i16_v4i32
|
|
2963407068U, // SABALv4i32_v2i64
|
|
2967601372U, // SABALv8i16_v4i32
|
|
2969702612U, // SABALv8i8_v8i16
|
|
2418049811U, // SABA_ZZZ_B
|
|
1075888915U, // SABA_ZZZ_D
|
|
2195784467U, // SABA_ZZZ_H
|
|
1344357139U, // SABA_ZZZ_S
|
|
2959213331U, // SABAv16i8
|
|
2961310483U, // SABAv2i32
|
|
2965504787U, // SABAv4i16
|
|
2967601939U, // SABAv4i32
|
|
2969699091U, // SABAv8i16
|
|
2971796243U, // SABAv8i8
|
|
270583553U, // SABDLB_ZZZ_D
|
|
2197882625U, // SABDLB_ZZZ_H
|
|
1881229057U, // SABDLB_ZZZ_S
|
|
270588905U, // SABDLT_ZZZ_D
|
|
2197887977U, // SABDLT_ZZZ_H
|
|
1881234409U, // SABDLT_ZZZ_S
|
|
822182174U, // SABDLv16i8_v8i16
|
|
815895092U, // SABDLv2i32_v2i64
|
|
820089396U, // SABDLv4i16_v4i32
|
|
815890718U, // SABDLv4i32_v2i64
|
|
820085022U, // SABDLv8i16_v4i32
|
|
822186548U, // SABDLv8i8_v8i16
|
|
3223358253U, // SABD_ZPmZ_B
|
|
3223374637U, // SABD_ZPmZ_D
|
|
3519089453U, // SABD_ZPmZ_H
|
|
3223407405U, // SABD_ZPmZ_S
|
|
811698989U, // SABDv16i8
|
|
813796141U, // SABDv2i32
|
|
817990445U, // SABDv4i16
|
|
820087597U, // SABDv4i32
|
|
822184749U, // SABDv8i16
|
|
824281901U, // SABDv8i8
|
|
3223377496U, // SADALP_ZPmZ_D
|
|
3519092312U, // SADALP_ZPmZ_H
|
|
3223410264U, // SADALP_ZPmZ_S
|
|
2969704024U, // SADALPv16i8_v8i16
|
|
3124893272U, // SADALPv2i32_v1i64
|
|
2961315416U, // SADALPv4i16_v2i32
|
|
2963412568U, // SADALPv4i32_v2i64
|
|
2967606872U, // SADALPv8i16_v4i32
|
|
2965509720U, // SADALPv8i8_v4i16
|
|
270588694U, // SADDLBT_ZZZ_D
|
|
2197887766U, // SADDLBT_ZZZ_H
|
|
1881234198U, // SADDLBT_ZZZ_S
|
|
270583578U, // SADDLB_ZZZ_D
|
|
2197882650U, // SADDLB_ZZZ_H
|
|
1881229082U, // SADDLB_ZZZ_S
|
|
822187624U, // SADDLPv16i8_v8i16
|
|
977376872U, // SADDLPv2i32_v1i64
|
|
813799016U, // SADDLPv4i16_v2i32
|
|
815896168U, // SADDLPv4i32_v2i64
|
|
820090472U, // SADDLPv8i16_v4i32
|
|
817993320U, // SADDLPv8i8_v4i16
|
|
270588921U, // SADDLT_ZZZ_D
|
|
2197887993U, // SADDLT_ZZZ_H
|
|
1881234425U, // SADDLT_ZZZ_S
|
|
807427747U, // SADDLVv16i8v
|
|
807427747U, // SADDLVv4i16v
|
|
807427747U, // SADDLVv4i32v
|
|
807427747U, // SADDLVv8i16v
|
|
807427747U, // SADDLVv8i8v
|
|
822182190U, // SADDLv16i8_v8i16
|
|
815895130U, // SADDLv2i32_v2i64
|
|
820089434U, // SADDLv4i16_v4i32
|
|
815890734U, // SADDLv4i32_v2i64
|
|
820085038U, // SADDLv8i16_v4i32
|
|
822186586U, // SADDLv8i8_v8i16
|
|
1684283000U, // SADDV_VPZ_B
|
|
1659117176U, // SADDV_VPZ_H
|
|
1638145656U, // SADDV_VPZ_S
|
|
2418067968U, // SADDWB_ZZZ_D
|
|
2189494784U, // SADDWB_ZZZ_H
|
|
270617088U, // SADDWB_ZZZ_S
|
|
2418073093U, // SADDWT_ZZZ_D
|
|
2189499909U, // SADDWT_ZZZ_H
|
|
270622213U, // SADDWT_ZZZ_S
|
|
822182506U, // SADDWv16i8_v8i16
|
|
815898621U, // SADDWv2i32_v2i64
|
|
820092925U, // SADDWv4i16_v4i32
|
|
815891050U, // SADDWv4i32_v2i64
|
|
820085354U, // SADDWv8i16_v4i32
|
|
822190077U, // SADDWv8i8_v8i16
|
|
10292U, // SB
|
|
1075889907U, // SBCLB_ZZZ_D
|
|
1344358131U, // SBCLB_ZZZ_S
|
|
1075895259U, // SBCLT_ZZZ_D
|
|
1344363483U, // SBCLT_ZZZ_S
|
|
2120198U, // SBCSWr
|
|
2120198U, // SBCSXr
|
|
2116169U, // SBCWr
|
|
2116169U, // SBCXr
|
|
2118804U, // SBFMWri
|
|
2118804U, // SBFMXri
|
|
2221037192U, // SCLAMP_VG2_2Z2Z_B
|
|
2193790600U, // SCLAMP_VG2_2Z2Z_D
|
|
2195904136U, // SCLAMP_VG2_2Z2Z_H
|
|
2174949000U, // SCLAMP_VG2_2Z2Z_S
|
|
2221037192U, // SCLAMP_VG4_4Z4Z_B
|
|
2193790600U, // SCLAMP_VG4_4Z4Z_D
|
|
2195904136U, // SCLAMP_VG4_4Z4Z_H
|
|
2174949000U, // SCLAMP_VG4_4Z4Z_S
|
|
2418054792U, // SCLAMP_ZZZ_B
|
|
1075893896U, // SCLAMP_ZZZ_D
|
|
2195789448U, // SCLAMP_ZZZ_H
|
|
1344362120U, // SCLAMP_ZZZ_S
|
|
2116788U, // SCVTFSWDri
|
|
2116788U, // SCVTFSWHri
|
|
2116788U, // SCVTFSWSri
|
|
2116788U, // SCVTFSXDri
|
|
2116788U, // SCVTFSXHri
|
|
2116788U, // SCVTFSXSri
|
|
2116788U, // SCVTFUWDri
|
|
2116788U, // SCVTFUWHri
|
|
2116788U, // SCVTFUWSri
|
|
2116788U, // SCVTFUXDri
|
|
2116788U, // SCVTFUXHri
|
|
2116788U, // SCVTFUXSri
|
|
1648561332U, // SCVTF_2Z2Z_StoS
|
|
1648561332U, // SCVTF_4Z4Z_StoS
|
|
270585012U, // SCVTF_ZPmZ_DtoD
|
|
3493924020U, // SCVTF_ZPmZ_DtoH
|
|
270617780U, // SCVTF_ZPmZ_DtoS
|
|
541134004U, // SCVTF_ZPmZ_HtoH
|
|
270585012U, // SCVTF_ZPmZ_StoD
|
|
1078004916U, // SCVTF_ZPmZ_StoH
|
|
270617780U, // SCVTF_ZPmZ_StoS
|
|
2116788U, // SCVTFd
|
|
2116788U, // SCVTFh
|
|
2116788U, // SCVTFs
|
|
2116788U, // SCVTFv1i16
|
|
2116788U, // SCVTFv1i32
|
|
2116788U, // SCVTFv1i64
|
|
813796532U, // SCVTFv2f32
|
|
815893684U, // SCVTFv2f64
|
|
813796532U, // SCVTFv2i32_shift
|
|
815893684U, // SCVTFv2i64_shift
|
|
817990836U, // SCVTFv4f16
|
|
820087988U, // SCVTFv4f32
|
|
817990836U, // SCVTFv4i16_shift
|
|
820087988U, // SCVTFv4i32_shift
|
|
822185140U, // SCVTFv8f16
|
|
822185140U, // SCVTFv8i16_shift
|
|
3223378315U, // SDIVR_ZPmZ_D
|
|
3223411083U, // SDIVR_ZPmZ_S
|
|
2121367U, // SDIVWr
|
|
2121367U, // SDIVXr
|
|
3223379607U, // SDIV_ZPmZ_D
|
|
3223412375U, // SDIV_ZPmZ_S
|
|
3798179131U, // SDOT_VG2_M2Z2Z_BtoS
|
|
3798162747U, // SDOT_VG2_M2Z2Z_HtoD
|
|
3798179131U, // SDOT_VG2_M2Z2Z_HtoS
|
|
3798179131U, // SDOT_VG2_M2ZZI_BToS
|
|
3798179131U, // SDOT_VG2_M2ZZI_HToS
|
|
3798162747U, // SDOT_VG2_M2ZZI_HtoD
|
|
3798179131U, // SDOT_VG2_M2ZZ_BtoS
|
|
3798162747U, // SDOT_VG2_M2ZZ_HtoD
|
|
3798179131U, // SDOT_VG2_M2ZZ_HtoS
|
|
4066614587U, // SDOT_VG4_M4Z4Z_BtoS
|
|
4066598203U, // SDOT_VG4_M4Z4Z_HtoD
|
|
4066614587U, // SDOT_VG4_M4Z4Z_HtoS
|
|
4066614587U, // SDOT_VG4_M4ZZI_BToS
|
|
4066614587U, // SDOT_VG4_M4ZZI_HToS
|
|
4066598203U, // SDOT_VG4_M4ZZI_HtoD
|
|
4066614587U, // SDOT_VG4_M4ZZ_BtoS
|
|
4066598203U, // SDOT_VG4_M4ZZ_HtoD
|
|
4066614587U, // SDOT_VG4_M4ZZ_HtoS
|
|
2686508347U, // SDOT_ZZZI_D
|
|
2686541115U, // SDOT_ZZZI_HtoS
|
|
2418105659U, // SDOT_ZZZI_S
|
|
2686508347U, // SDOT_ZZZ_D
|
|
2686541115U, // SDOT_ZZZ_HtoS
|
|
2418105659U, // SDOT_ZZZ_S
|
|
2967608635U, // SDOTlanev16i8
|
|
2961317179U, // SDOTlanev8i8
|
|
2967608635U, // SDOTv16i8
|
|
2961317179U, // SDOTv8i8
|
|
1231150U, // SDSB
|
|
3223360115U, // SEL_PPPP
|
|
2242007667U, // SEL_VG2_2ZC2Z2Z_B
|
|
2242024051U, // SEL_VG2_2ZC2Z2Z_D
|
|
2242040435U, // SEL_VG2_2ZC2Z2Z_H
|
|
2242056819U, // SEL_VG2_2ZC2Z2Z_S
|
|
2242007667U, // SEL_VG4_4ZC4Z4Z_B
|
|
2242024051U, // SEL_VG4_4ZC4Z4Z_D
|
|
2242040435U, // SEL_VG4_4ZC4Z4Z_H
|
|
2242056819U, // SEL_VG4_4ZC4Z4Z_S
|
|
3223360115U, // SEL_ZPZZ_B
|
|
3223376499U, // SEL_ZPZZ_D
|
|
2176914035U, // SEL_ZPZZ_H
|
|
3223409267U, // SEL_ZPZZ_S
|
|
10405U, // SET
|
|
145712042U, // SETE
|
|
145712104U, // SETEN
|
|
145712992U, // SETET
|
|
145712466U, // SETETN
|
|
17104U, // SETF16
|
|
17126U, // SETF8
|
|
10384U, // SETFFR
|
|
145712064U, // SETGM
|
|
145712129U, // SETGMN
|
|
145713017U, // SETGMT
|
|
145712494U, // SETGMTN
|
|
145712952U, // SETGP
|
|
145712163U, // SETGPN
|
|
145713051U, // SETGPT
|
|
145712532U, // SETGPTN
|
|
145712072U, // SETM
|
|
145712138U, // SETMN
|
|
145713026U, // SETMT
|
|
145712504U, // SETMTN
|
|
145712960U, // SETP
|
|
145712172U, // SETPN
|
|
145713060U, // SETPT
|
|
145712542U, // SETPTN
|
|
807717442U, // SHA1Crrr
|
|
2116877U, // SHA1Hrr
|
|
807720077U, // SHA1Mrrr
|
|
807720448U, // SHA1Prrr
|
|
2967601153U, // SHA1SU0rrr
|
|
2967601271U, // SHA1SU1rr
|
|
807715019U, // SHA256H2rrr
|
|
807718261U, // SHA256Hrrr
|
|
2967601173U, // SHA256SU0rr
|
|
2967601291U, // SHA256SU1rrr
|
|
807718208U, // SHA512H
|
|
807715009U, // SHA512H2
|
|
2963406858U, // SHA512SU0
|
|
2963406976U, // SHA512SU1
|
|
3223358349U, // SHADD_ZPmZ_B
|
|
3223374733U, // SHADD_ZPmZ_D
|
|
3519089549U, // SHADD_ZPmZ_H
|
|
3223407501U, // SHADD_ZPmZ_S
|
|
811699085U, // SHADDv16i8
|
|
813796237U, // SHADDv2i32
|
|
817990541U, // SHADDv4i16
|
|
820087693U, // SHADDv4i32
|
|
822184845U, // SHADDv8i16
|
|
824281997U, // SHADDv8i8
|
|
822182207U, // SHLLv16i8
|
|
815895257U, // SHLLv2i32
|
|
820089561U, // SHLLv4i16
|
|
815890751U, // SHLLv4i32
|
|
820085055U, // SHLLv8i16
|
|
822186713U, // SHLLv8i8
|
|
2118280U, // SHLd
|
|
811700872U, // SHLv16i8_shift
|
|
813798024U, // SHLv2i32_shift
|
|
815895176U, // SHLv2i64_shift
|
|
817992328U, // SHLv4i16_shift
|
|
820089480U, // SHLv4i32_shift
|
|
822186632U, // SHLv8i16_shift
|
|
824283784U, // SHLv8i8_shift
|
|
1881180155U, // SHRNB_ZZI_B
|
|
2172717051U, // SHRNB_ZZI_H
|
|
2418100219U, // SHRNB_ZZI_S
|
|
2686491849U, // SHRNT_ZZI_B
|
|
2174819529U, // SHRNT_ZZI_H
|
|
1075928265U, // SHRNT_ZZI_S
|
|
2959212994U, // SHRNv16i8_shift
|
|
813798723U, // SHRNv2i32_shift
|
|
817993027U, // SHRNv4i16_shift
|
|
2967601602U, // SHRNv4i32_shift
|
|
2969698754U, // SHRNv8i16_shift
|
|
824284483U, // SHRNv8i8_shift
|
|
3223361596U, // SHSUBR_ZPmZ_B
|
|
3223377980U, // SHSUBR_ZPmZ_D
|
|
3519092796U, // SHSUBR_ZPmZ_H
|
|
3223410748U, // SHSUBR_ZPmZ_S
|
|
3223357887U, // SHSUB_ZPmZ_B
|
|
3223374271U, // SHSUB_ZPmZ_D
|
|
3519089087U, // SHSUB_ZPmZ_H
|
|
3223407039U, // SHSUB_ZPmZ_S
|
|
811698623U, // SHSUBv16i8
|
|
813795775U, // SHSUBv2i32
|
|
817990079U, // SHSUBv4i16
|
|
820087231U, // SHSUBv4i32
|
|
822184383U, // SHSUBv8i16
|
|
824281535U, // SHSUBv8i8
|
|
2418053260U, // SLI_ZZI_B
|
|
1075892364U, // SLI_ZZI_D
|
|
2195787916U, // SLI_ZZI_H
|
|
1344360588U, // SLI_ZZI_S
|
|
807719052U, // SLId
|
|
2959216780U, // SLIv16i8_shift
|
|
2961313932U, // SLIv2i32_shift
|
|
2963411084U, // SLIv2i64_shift
|
|
2965508236U, // SLIv4i16_shift
|
|
2967605388U, // SLIv4i32_shift
|
|
2969702540U, // SLIv8i16_shift
|
|
2971799692U, // SLIv8i8_shift
|
|
2967601302U, // SM3PARTW1
|
|
2967601786U, // SM3PARTW2
|
|
820084834U, // SM3SS1
|
|
2967601901U, // SM3TT1A
|
|
2967602472U, // SM3TT1B
|
|
2967601910U, // SM3TT2A
|
|
2967602501U, // SM3TT2B
|
|
2967604220U, // SM4E
|
|
270623039U, // SM4EKEY_ZZZ_S
|
|
820093247U, // SM4ENCKEY
|
|
270617596U, // SM4E_ZZZ_S
|
|
2118218U, // SMADDLrrr
|
|
3223361414U, // SMAXP_ZPmZ_B
|
|
3223377798U, // SMAXP_ZPmZ_D
|
|
3519092614U, // SMAXP_ZPmZ_H
|
|
3223410566U, // SMAXP_ZPmZ_S
|
|
811702150U, // SMAXPv16i8
|
|
813799302U, // SMAXPv2i32
|
|
817993606U, // SMAXPv4i16
|
|
820090758U, // SMAXPv4i32
|
|
822187910U, // SMAXPv8i16
|
|
824285062U, // SMAXPv8i8
|
|
3227623235U, // SMAXQV_VPZ_B
|
|
3231817539U, // SMAXQV_VPZ_D
|
|
3238108995U, // SMAXQV_VPZ_H
|
|
3236011843U, // SMAXQV_VPZ_S
|
|
253792U, // SMAXV_VPZ_B
|
|
1657020256U, // SMAXV_VPZ_D
|
|
1659133792U, // SMAXV_VPZ_H
|
|
1638178656U, // SMAXV_VPZ_S
|
|
807427936U, // SMAXVv16i8v
|
|
807427936U, // SMAXVv4i16v
|
|
807427936U, // SMAXVv4i32v
|
|
807427936U, // SMAXVv8i16v
|
|
807427936U, // SMAXVv8i8v
|
|
2121933U, // SMAXWri
|
|
2121933U, // SMAXWrr
|
|
2121933U, // SMAXXri
|
|
2121933U, // SMAXXrr
|
|
2179096781U, // SMAX_VG2_2Z2Z_B
|
|
2181210317U, // SMAX_VG2_2Z2Z_D
|
|
2183323853U, // SMAX_VG2_2Z2Z_H
|
|
2185437389U, // SMAX_VG2_2Z2Z_S
|
|
2179096781U, // SMAX_VG2_2ZZ_B
|
|
2181210317U, // SMAX_VG2_2ZZ_D
|
|
2183323853U, // SMAX_VG2_2ZZ_H
|
|
2185437389U, // SMAX_VG2_2ZZ_S
|
|
2179096781U, // SMAX_VG4_4Z4Z_B
|
|
2181210317U, // SMAX_VG4_4Z4Z_D
|
|
2183323853U, // SMAX_VG4_4Z4Z_H
|
|
2185437389U, // SMAX_VG4_4Z4Z_S
|
|
2179096781U, // SMAX_VG4_4ZZ_B
|
|
2181210317U, // SMAX_VG4_4ZZ_D
|
|
2183323853U, // SMAX_VG4_4ZZ_H
|
|
2185437389U, // SMAX_VG4_4ZZ_S
|
|
2138317U, // SMAX_ZI_B
|
|
2418073805U, // SMAX_ZI_D
|
|
2189500621U, // SMAX_ZI_H
|
|
270622925U, // SMAX_ZI_S
|
|
3223363789U, // SMAX_ZPmZ_B
|
|
3223380173U, // SMAX_ZPmZ_D
|
|
3519094989U, // SMAX_ZPmZ_H
|
|
3223412941U, // SMAX_ZPmZ_S
|
|
811704525U, // SMAXv16i8
|
|
813801677U, // SMAXv2i32
|
|
817995981U, // SMAXv4i16
|
|
820093133U, // SMAXv4i32
|
|
822190285U, // SMAXv8i16
|
|
824287437U, // SMAXv8i8
|
|
379497U, // SMC
|
|
3223361220U, // SMINP_ZPmZ_B
|
|
3223377604U, // SMINP_ZPmZ_D
|
|
3519092420U, // SMINP_ZPmZ_H
|
|
3223410372U, // SMINP_ZPmZ_S
|
|
811701956U, // SMINPv16i8
|
|
813799108U, // SMINPv2i32
|
|
817993412U, // SMINPv4i16
|
|
820090564U, // SMINPv4i32
|
|
822187716U, // SMINPv8i16
|
|
824284868U, // SMINPv8i8
|
|
3227623204U, // SMINQV_VPZ_B
|
|
3231817508U, // SMINQV_VPZ_D
|
|
3238108964U, // SMINQV_VPZ_H
|
|
3236011812U, // SMINQV_VPZ_S
|
|
253644U, // SMINV_VPZ_B
|
|
1657020108U, // SMINV_VPZ_D
|
|
1659133644U, // SMINV_VPZ_H
|
|
1638178508U, // SMINV_VPZ_S
|
|
807427788U, // SMINVv16i8v
|
|
807427788U, // SMINVv4i16v
|
|
807427788U, // SMINVv4i32v
|
|
807427788U, // SMINVv8i16v
|
|
807427788U, // SMINVv8i8v
|
|
2118946U, // SMINWri
|
|
2118946U, // SMINWrr
|
|
2118946U, // SMINXri
|
|
2118946U, // SMINXrr
|
|
2179093794U, // SMIN_VG2_2Z2Z_B
|
|
2181207330U, // SMIN_VG2_2Z2Z_D
|
|
2183320866U, // SMIN_VG2_2Z2Z_H
|
|
2185434402U, // SMIN_VG2_2Z2Z_S
|
|
2179093794U, // SMIN_VG2_2ZZ_B
|
|
2181207330U, // SMIN_VG2_2ZZ_D
|
|
2183320866U, // SMIN_VG2_2ZZ_H
|
|
2185434402U, // SMIN_VG2_2ZZ_S
|
|
2179093794U, // SMIN_VG4_4Z4Z_B
|
|
2181207330U, // SMIN_VG4_4Z4Z_D
|
|
2183320866U, // SMIN_VG4_4Z4Z_H
|
|
2185434402U, // SMIN_VG4_4Z4Z_S
|
|
2179093794U, // SMIN_VG4_4ZZ_B
|
|
2181207330U, // SMIN_VG4_4ZZ_D
|
|
2183320866U, // SMIN_VG4_4ZZ_H
|
|
2185434402U, // SMIN_VG4_4ZZ_S
|
|
2135330U, // SMIN_ZI_B
|
|
2418070818U, // SMIN_ZI_D
|
|
2189497634U, // SMIN_ZI_H
|
|
270619938U, // SMIN_ZI_S
|
|
3223360802U, // SMIN_ZPmZ_B
|
|
3223377186U, // SMIN_ZPmZ_D
|
|
3519092002U, // SMIN_ZPmZ_H
|
|
3223409954U, // SMIN_ZPmZ_S
|
|
811701538U, // SMINv16i8
|
|
813798690U, // SMINv2i32
|
|
817992994U, // SMINv4i16
|
|
820090146U, // SMINv4i32
|
|
822187298U, // SMINv8i16
|
|
824284450U, // SMINv8i8
|
|
1344325241U, // SMLALB_ZZZI_D
|
|
2686535289U, // SMLALB_ZZZI_S
|
|
1344325241U, // SMLALB_ZZZ_D
|
|
2220951161U, // SMLALB_ZZZ_H
|
|
2686535289U, // SMLALB_ZZZ_S
|
|
1688441543U, // SMLALL_MZZI_BtoS
|
|
1688425159U, // SMLALL_MZZI_HtoD
|
|
1688441543U, // SMLALL_MZZ_BtoS
|
|
1688425159U, // SMLALL_MZZ_HtoD
|
|
3835925191U, // SMLALL_VG2_M2Z2Z_BtoS
|
|
3835908807U, // SMLALL_VG2_M2Z2Z_HtoD
|
|
3835925191U, // SMLALL_VG2_M2ZZI_BtoS
|
|
3835908807U, // SMLALL_VG2_M2ZZI_HtoD
|
|
4104360647U, // SMLALL_VG2_M2ZZ_BtoS
|
|
4104344263U, // SMLALL_VG2_M2ZZ_HtoD
|
|
4104360647U, // SMLALL_VG4_M4Z4Z_BtoS
|
|
4104344263U, // SMLALL_VG4_M4Z4Z_HtoD
|
|
4104360647U, // SMLALL_VG4_M4ZZI_BtoS
|
|
4104344263U, // SMLALL_VG4_M4ZZI_HtoD
|
|
77828807U, // SMLALL_VG4_M4ZZ_BtoS
|
|
77812423U, // SMLALL_VG4_M4ZZ_HtoD
|
|
1344330683U, // SMLALT_ZZZI_D
|
|
2686540731U, // SMLALT_ZZZI_S
|
|
1344330683U, // SMLALT_ZZZ_D
|
|
2220956603U, // SMLALT_ZZZ_H
|
|
2686540731U, // SMLALT_ZZZ_S
|
|
1663275260U, // SMLAL_MZZI_HtoS
|
|
1663275260U, // SMLAL_MZZ_HtoS
|
|
3810758908U, // SMLAL_VG2_M2Z2Z_HtoS
|
|
3810758908U, // SMLAL_VG2_M2ZZI_S
|
|
3810758908U, // SMLAL_VG2_M2ZZ_HtoS
|
|
4079194364U, // SMLAL_VG4_M4Z4Z_HtoS
|
|
4079194364U, // SMLAL_VG4_M4ZZI_HtoS
|
|
4079194364U, // SMLAL_VG4_M4ZZ_HtoS
|
|
2969698558U, // SMLALv16i8_v8i16
|
|
2963411196U, // SMLALv2i32_indexed
|
|
2963411196U, // SMLALv2i32_v2i64
|
|
2967605500U, // SMLALv4i16_indexed
|
|
2967605500U, // SMLALv4i16_v4i32
|
|
2963407102U, // SMLALv4i32_indexed
|
|
2963407102U, // SMLALv4i32_v2i64
|
|
2967601406U, // SMLALv8i16_indexed
|
|
2967601406U, // SMLALv8i16_v4i32
|
|
2969702652U, // SMLALv8i8_v8i16
|
|
1344325539U, // SMLSLB_ZZZI_D
|
|
2686535587U, // SMLSLB_ZZZI_S
|
|
1344325539U, // SMLSLB_ZZZ_D
|
|
2220951459U, // SMLSLB_ZZZ_H
|
|
2686535587U, // SMLSLB_ZZZ_S
|
|
1688441574U, // SMLSLL_MZZI_BtoS
|
|
1688425190U, // SMLSLL_MZZI_HtoD
|
|
1688441574U, // SMLSLL_MZZ_BtoS
|
|
1688425190U, // SMLSLL_MZZ_HtoD
|
|
3835925222U, // SMLSLL_VG2_M2Z2Z_BtoS
|
|
3835908838U, // SMLSLL_VG2_M2Z2Z_HtoD
|
|
3835925222U, // SMLSLL_VG2_M2ZZI_BtoS
|
|
3835908838U, // SMLSLL_VG2_M2ZZI_HtoD
|
|
4104360678U, // SMLSLL_VG2_M2ZZ_BtoS
|
|
4104344294U, // SMLSLL_VG2_M2ZZ_HtoD
|
|
4104360678U, // SMLSLL_VG4_M4Z4Z_BtoS
|
|
4104344294U, // SMLSLL_VG4_M4Z4Z_HtoD
|
|
4104360678U, // SMLSLL_VG4_M4ZZI_BtoS
|
|
4104344294U, // SMLSLL_VG4_M4ZZI_HtoD
|
|
77828838U, // SMLSLL_VG4_M4ZZ_BtoS
|
|
77812454U, // SMLSLL_VG4_M4ZZ_HtoD
|
|
1344330858U, // SMLSLT_ZZZI_D
|
|
2686540906U, // SMLSLT_ZZZI_S
|
|
1344330858U, // SMLSLT_ZZZ_D
|
|
2220956778U, // SMLSLT_ZZZ_H
|
|
2686540906U, // SMLSLT_ZZZ_S
|
|
1663276027U, // SMLSL_MZZI_HtoS
|
|
1663276027U, // SMLSL_MZZ_HtoS
|
|
3810759675U, // SMLSL_VG2_M2Z2Z_HtoS
|
|
3810759675U, // SMLSL_VG2_M2ZZI_S
|
|
3810759675U, // SMLSL_VG2_M2ZZ_HtoS
|
|
4079195131U, // SMLSL_VG4_M4Z4Z_HtoS
|
|
4079195131U, // SMLSL_VG4_M4ZZI_HtoS
|
|
4079195131U, // SMLSL_VG4_M4ZZ_HtoS
|
|
2969698690U, // SMLSLv16i8_v8i16
|
|
2963411963U, // SMLSLv2i32_indexed
|
|
2963411963U, // SMLSLv2i32_v2i64
|
|
2967606267U, // SMLSLv4i16_indexed
|
|
2967606267U, // SMLSLv4i16_v4i32
|
|
2963407234U, // SMLSLv4i32_indexed
|
|
2963407234U, // SMLSLv4i32_v2i64
|
|
2967601538U, // SMLSLv8i16_indexed
|
|
2967601538U, // SMLSLv8i16_v4i32
|
|
2969703419U, // SMLSLv8i8_v8i16
|
|
2967602037U, // SMMLA
|
|
2418099061U, // SMMLA_ZZZ
|
|
54641587U, // SMOPA_MPPZZ_D
|
|
54641587U, // SMOPA_MPPZZ_HtoS
|
|
79807411U, // SMOPA_MPPZZ_S
|
|
54647463U, // SMOPS_MPPZZ_D
|
|
54647463U, // SMOPS_MPPZZ_HtoS
|
|
79813287U, // SMOPS_MPPZZ_S
|
|
807427821U, // SMOVvi16to32
|
|
807427821U, // SMOVvi16to32_idx0
|
|
807427821U, // SMOVvi16to64
|
|
807427821U, // SMOVvi16to64_idx0
|
|
807427821U, // SMOVvi32to64
|
|
807427821U, // SMOVvi32to64_idx0
|
|
807427821U, // SMOVvi8to32
|
|
807427821U, // SMOVvi8to32_idx0
|
|
807427821U, // SMOVvi8to64
|
|
807427821U, // SMOVvi8to64_idx0
|
|
2118166U, // SMSUBLrrr
|
|
3223359209U, // SMULH_ZPmZ_B
|
|
3223375593U, // SMULH_ZPmZ_D
|
|
3519090409U, // SMULH_ZPmZ_H
|
|
3223408361U, // SMULH_ZPmZ_S
|
|
2133737U, // SMULH_ZZZ_B
|
|
2418069225U, // SMULH_ZZZ_D
|
|
2189496041U, // SMULH_ZZZ_H
|
|
270618345U, // SMULH_ZZZ_S
|
|
2117353U, // SMULHrr
|
|
270583628U, // SMULLB_ZZZI_D
|
|
1881229132U, // SMULLB_ZZZI_S
|
|
270583628U, // SMULLB_ZZZ_D
|
|
2197882700U, // SMULLB_ZZZ_H
|
|
1881229132U, // SMULLB_ZZZ_S
|
|
270588985U, // SMULLT_ZZZI_D
|
|
1881234489U, // SMULLT_ZZZI_S
|
|
270588985U, // SMULLT_ZZZ_D
|
|
2197888057U, // SMULLT_ZZZ_H
|
|
1881234489U, // SMULLT_ZZZ_S
|
|
822182240U, // SMULLv16i8_v8i16
|
|
815895302U, // SMULLv2i32_indexed
|
|
815895302U, // SMULLv2i32_v2i64
|
|
820089606U, // SMULLv4i16_indexed
|
|
820089606U, // SMULLv4i16_v4i32
|
|
815890784U, // SMULLv4i32_indexed
|
|
815890784U, // SMULLv4i32_v2i64
|
|
820085088U, // SMULLv8i16_indexed
|
|
820085088U, // SMULLv8i16_v4i32
|
|
822186758U, // SMULLv8i8_v8i16
|
|
3223358466U, // SPLICE_ZPZZ_B
|
|
3223374850U, // SPLICE_ZPZZ_D
|
|
2176912386U, // SPLICE_ZPZZ_H
|
|
3223407618U, // SPLICE_ZPZZ_S
|
|
3223358466U, // SPLICE_ZPZ_B
|
|
3223374850U, // SPLICE_ZPZ_D
|
|
2176912386U, // SPLICE_ZPZ_H
|
|
3223407618U, // SPLICE_ZPZ_S
|
|
270572010U, // SQABS_ZPmZ_B
|
|
270588394U, // SQABS_ZPmZ_D
|
|
541137386U, // SQABS_ZPmZ_H
|
|
270621162U, // SQABS_ZPmZ_S
|
|
811702762U, // SQABSv16i8
|
|
2120170U, // SQABSv1i16
|
|
2120170U, // SQABSv1i32
|
|
2120170U, // SQABSv1i64
|
|
2120170U, // SQABSv1i8
|
|
813799914U, // SQABSv2i32
|
|
815897066U, // SQABSv2i64
|
|
817994218U, // SQABSv4i16
|
|
820091370U, // SQABSv4i32
|
|
822188522U, // SQABSv8i16
|
|
824285674U, // SQABSv8i8
|
|
2132907U, // SQADD_ZI_B
|
|
2418068395U, // SQADD_ZI_D
|
|
2189495211U, // SQADD_ZI_H
|
|
270617515U, // SQADD_ZI_S
|
|
3223358379U, // SQADD_ZPmZ_B
|
|
3223374763U, // SQADD_ZPmZ_D
|
|
3519089579U, // SQADD_ZPmZ_H
|
|
3223407531U, // SQADD_ZPmZ_S
|
|
2132907U, // SQADD_ZZZ_B
|
|
2418068395U, // SQADD_ZZZ_D
|
|
2189495211U, // SQADD_ZZZ_H
|
|
270617515U, // SQADD_ZZZ_S
|
|
811699115U, // SQADDv16i8
|
|
2116523U, // SQADDv1i16
|
|
2116523U, // SQADDv1i32
|
|
2116523U, // SQADDv1i64
|
|
2116523U, // SQADDv1i8
|
|
813796267U, // SQADDv2i32
|
|
815893419U, // SQADDv2i64
|
|
817990571U, // SQADDv4i16
|
|
820087723U, // SQADDv4i32
|
|
822184875U, // SQADDv8i16
|
|
824282027U, // SQADDv8i8
|
|
2132839U, // SQCADD_ZZI_B
|
|
2418068327U, // SQCADD_ZZI_D
|
|
2189495143U, // SQCADD_ZZI_H
|
|
270617447U, // SQCADD_ZZI_S
|
|
1648432504U, // SQCVTN_Z2Z_StoH
|
|
1644238200U, // SQCVTN_Z4Z_DtoH
|
|
3223360888U, // SQCVTN_Z4Z_StoB
|
|
1648432553U, // SQCVTUN_Z2Z_StoH
|
|
1644238249U, // SQCVTUN_Z4Z_DtoH
|
|
3223360937U, // SQCVTUN_Z4Z_StoB
|
|
1648434777U, // SQCVTU_Z2Z_StoH
|
|
1644240473U, // SQCVTU_Z4Z_DtoH
|
|
3223363161U, // SQCVTU_Z4Z_StoB
|
|
1648434657U, // SQCVT_Z2Z_StoH
|
|
1644240353U, // SQCVT_Z4Z_DtoH
|
|
3223363041U, // SQCVT_Z4Z_StoB
|
|
538985973U, // SQDECB_XPiI
|
|
2954905077U, // SQDECB_XPiWdI
|
|
538987328U, // SQDECD_XPiI
|
|
2954906432U, // SQDECD_XPiWdI
|
|
539020096U, // SQDECD_ZPiI
|
|
538988022U, // SQDECH_XPiI
|
|
2954907126U, // SQDECH_XPiWdI
|
|
56692214U, // SQDECH_ZPiI
|
|
2119181U, // SQDECP_XPWd_B
|
|
2418038285U, // SQDECP_XPWd_D
|
|
1881167373U, // SQDECP_XPWd_H
|
|
270554637U, // SQDECP_XPWd_S
|
|
2119181U, // SQDECP_XP_B
|
|
2418038285U, // SQDECP_XP_D
|
|
1881167373U, // SQDECP_XP_H
|
|
270554637U, // SQDECP_XP_S
|
|
1075893773U, // SQDECP_ZP_D
|
|
1658918413U, // SQDECP_ZP_H
|
|
1344361997U, // SQDECP_ZP_S
|
|
538992605U, // SQDECW_XPiI
|
|
2954911709U, // SQDECW_XPiWdI
|
|
539058141U, // SQDECW_ZPiI
|
|
1344330498U, // SQDMLALBT_ZZZ_D
|
|
2220956418U, // SQDMLALBT_ZZZ_H
|
|
2686540546U, // SQDMLALBT_ZZZ_S
|
|
1344325222U, // SQDMLALB_ZZZI_D
|
|
2686535270U, // SQDMLALB_ZZZI_S
|
|
1344325222U, // SQDMLALB_ZZZ_D
|
|
2220951142U, // SQDMLALB_ZZZ_H
|
|
2686535270U, // SQDMLALB_ZZZ_S
|
|
1344330664U, // SQDMLALT_ZZZI_D
|
|
2686540712U, // SQDMLALT_ZZZI_S
|
|
1344330664U, // SQDMLALT_ZZZ_D
|
|
2220956584U, // SQDMLALT_ZZZ_H
|
|
2686540712U, // SQDMLALT_ZZZ_S
|
|
807719147U, // SQDMLALi16
|
|
807719147U, // SQDMLALi32
|
|
807719147U, // SQDMLALv1i32_indexed
|
|
807719147U, // SQDMLALv1i64_indexed
|
|
2963411179U, // SQDMLALv2i32_indexed
|
|
2963411179U, // SQDMLALv2i32_v2i64
|
|
2967605483U, // SQDMLALv4i16_indexed
|
|
2967605483U, // SQDMLALv4i16_v4i32
|
|
2963407084U, // SQDMLALv4i32_indexed
|
|
2963407084U, // SQDMLALv4i32_v2i64
|
|
2967601388U, // SQDMLALv8i16_indexed
|
|
2967601388U, // SQDMLALv8i16_v4i32
|
|
1344330537U, // SQDMLSLBT_ZZZ_D
|
|
2220956457U, // SQDMLSLBT_ZZZ_H
|
|
2686540585U, // SQDMLSLBT_ZZZ_S
|
|
1344325520U, // SQDMLSLB_ZZZI_D
|
|
2686535568U, // SQDMLSLB_ZZZI_S
|
|
1344325520U, // SQDMLSLB_ZZZ_D
|
|
2220951440U, // SQDMLSLB_ZZZ_H
|
|
2686535568U, // SQDMLSLB_ZZZ_S
|
|
1344330839U, // SQDMLSLT_ZZZI_D
|
|
2686540887U, // SQDMLSLT_ZZZI_S
|
|
1344330839U, // SQDMLSLT_ZZZ_D
|
|
2220956759U, // SQDMLSLT_ZZZ_H
|
|
2686540887U, // SQDMLSLT_ZZZ_S
|
|
807719914U, // SQDMLSLi16
|
|
807719914U, // SQDMLSLi32
|
|
807719914U, // SQDMLSLv1i32_indexed
|
|
807719914U, // SQDMLSLv1i64_indexed
|
|
2963411946U, // SQDMLSLv2i32_indexed
|
|
2963411946U, // SQDMLSLv2i32_v2i64
|
|
2967606250U, // SQDMLSLv4i16_indexed
|
|
2967606250U, // SQDMLSLv4i16_v4i32
|
|
2963407216U, // SQDMLSLv4i32_indexed
|
|
2963407216U, // SQDMLSLv4i32_v2i64
|
|
2967601520U, // SQDMLSLv8i16_indexed
|
|
2967601520U, // SQDMLSLv8i16_v4i32
|
|
2179092182U, // SQDMULH_VG2_2Z2Z_B
|
|
2181205718U, // SQDMULH_VG2_2Z2Z_D
|
|
2183319254U, // SQDMULH_VG2_2Z2Z_H
|
|
2185432790U, // SQDMULH_VG2_2Z2Z_S
|
|
2179092182U, // SQDMULH_VG2_2ZZ_B
|
|
2181205718U, // SQDMULH_VG2_2ZZ_D
|
|
2183319254U, // SQDMULH_VG2_2ZZ_H
|
|
2185432790U, // SQDMULH_VG2_2ZZ_S
|
|
2179092182U, // SQDMULH_VG4_4Z4Z_B
|
|
2181205718U, // SQDMULH_VG4_4Z4Z_D
|
|
2183319254U, // SQDMULH_VG4_4Z4Z_H
|
|
2185432790U, // SQDMULH_VG4_4Z4Z_S
|
|
2179092182U, // SQDMULH_VG4_4ZZ_B
|
|
2181205718U, // SQDMULH_VG4_4ZZ_D
|
|
2183319254U, // SQDMULH_VG4_4ZZ_H
|
|
2185432790U, // SQDMULH_VG4_4ZZ_S
|
|
2418069206U, // SQDMULH_ZZZI_D
|
|
2189496022U, // SQDMULH_ZZZI_H
|
|
270618326U, // SQDMULH_ZZZI_S
|
|
2133718U, // SQDMULH_ZZZ_B
|
|
2418069206U, // SQDMULH_ZZZ_D
|
|
2189496022U, // SQDMULH_ZZZ_H
|
|
270618326U, // SQDMULH_ZZZ_S
|
|
2117334U, // SQDMULHv1i16
|
|
2117334U, // SQDMULHv1i16_indexed
|
|
2117334U, // SQDMULHv1i32
|
|
2117334U, // SQDMULHv1i32_indexed
|
|
813797078U, // SQDMULHv2i32
|
|
813797078U, // SQDMULHv2i32_indexed
|
|
817991382U, // SQDMULHv4i16
|
|
817991382U, // SQDMULHv4i16_indexed
|
|
820088534U, // SQDMULHv4i32
|
|
820088534U, // SQDMULHv4i32_indexed
|
|
822185686U, // SQDMULHv8i16
|
|
822185686U, // SQDMULHv8i16_indexed
|
|
270583610U, // SQDMULLB_ZZZI_D
|
|
1881229114U, // SQDMULLB_ZZZI_S
|
|
270583610U, // SQDMULLB_ZZZ_D
|
|
2197882682U, // SQDMULLB_ZZZ_H
|
|
1881229114U, // SQDMULLB_ZZZ_S
|
|
270588967U, // SQDMULLT_ZZZI_D
|
|
1881234471U, // SQDMULLT_ZZZI_S
|
|
270588967U, // SQDMULLT_ZZZ_D
|
|
2197888039U, // SQDMULLT_ZZZ_H
|
|
1881234471U, // SQDMULLT_ZZZ_S
|
|
2118390U, // SQDMULLi16
|
|
2118390U, // SQDMULLi32
|
|
2118390U, // SQDMULLv1i32_indexed
|
|
2118390U, // SQDMULLv1i64_indexed
|
|
815895286U, // SQDMULLv2i32_indexed
|
|
815895286U, // SQDMULLv2i32_v2i64
|
|
820089590U, // SQDMULLv4i16_indexed
|
|
820089590U, // SQDMULLv4i16_v4i32
|
|
815890766U, // SQDMULLv4i32_indexed
|
|
815890766U, // SQDMULLv4i32_v2i64
|
|
820085070U, // SQDMULLv8i16_indexed
|
|
820085070U, // SQDMULLv8i16_v4i32
|
|
538985989U, // SQINCB_XPiI
|
|
2954905093U, // SQINCB_XPiWdI
|
|
538987344U, // SQINCD_XPiI
|
|
2954906448U, // SQINCD_XPiWdI
|
|
539020112U, // SQINCD_ZPiI
|
|
538988038U, // SQINCH_XPiI
|
|
2954907142U, // SQINCH_XPiWdI
|
|
56692230U, // SQINCH_ZPiI
|
|
2119197U, // SQINCP_XPWd_B
|
|
2418038301U, // SQINCP_XPWd_D
|
|
1881167389U, // SQINCP_XPWd_H
|
|
270554653U, // SQINCP_XPWd_S
|
|
2119197U, // SQINCP_XP_B
|
|
2418038301U, // SQINCP_XP_D
|
|
1881167389U, // SQINCP_XP_H
|
|
270554653U, // SQINCP_XP_S
|
|
1075893789U, // SQINCP_ZP_D
|
|
1658918429U, // SQINCP_ZP_H
|
|
1344362013U, // SQINCP_ZP_S
|
|
538992621U, // SQINCW_XPiI
|
|
2954911725U, // SQINCW_XPiWdI
|
|
539058157U, // SQINCW_ZPiI
|
|
270568678U, // SQNEG_ZPmZ_B
|
|
270585062U, // SQNEG_ZPmZ_D
|
|
541134054U, // SQNEG_ZPmZ_H
|
|
270617830U, // SQNEG_ZPmZ_S
|
|
811699430U, // SQNEGv16i8
|
|
2116838U, // SQNEGv1i16
|
|
2116838U, // SQNEGv1i32
|
|
2116838U, // SQNEGv1i64
|
|
2116838U, // SQNEGv1i8
|
|
813796582U, // SQNEGv2i32
|
|
815893734U, // SQNEGv2i64
|
|
817990886U, // SQNEGv4i16
|
|
820088038U, // SQNEGv4i32
|
|
822185190U, // SQNEGv8i16
|
|
824282342U, // SQNEGv8i8
|
|
2195787143U, // SQRDCMLAH_ZZZI_H
|
|
1344359815U, // SQRDCMLAH_ZZZI_S
|
|
2418052487U, // SQRDCMLAH_ZZZ_B
|
|
1075891591U, // SQRDCMLAH_ZZZ_D
|
|
2195787143U, // SQRDCMLAH_ZZZ_H
|
|
1344359815U, // SQRDCMLAH_ZZZ_S
|
|
1075891602U, // SQRDMLAH_ZZZI_D
|
|
2195787154U, // SQRDMLAH_ZZZI_H
|
|
1344359826U, // SQRDMLAH_ZZZI_S
|
|
2418052498U, // SQRDMLAH_ZZZ_B
|
|
1075891602U, // SQRDMLAH_ZZZ_D
|
|
2195787154U, // SQRDMLAH_ZZZ_H
|
|
1344359826U, // SQRDMLAH_ZZZ_S
|
|
807718290U, // SQRDMLAHv1i16
|
|
807718290U, // SQRDMLAHv1i16_indexed
|
|
807718290U, // SQRDMLAHv1i32
|
|
807718290U, // SQRDMLAHv1i32_indexed
|
|
2961313170U, // SQRDMLAHv2i32
|
|
2961313170U, // SQRDMLAHv2i32_indexed
|
|
2965507474U, // SQRDMLAHv4i16
|
|
2965507474U, // SQRDMLAHv4i16_indexed
|
|
2967604626U, // SQRDMLAHv4i32
|
|
2967604626U, // SQRDMLAHv4i32_indexed
|
|
2969701778U, // SQRDMLAHv8i16
|
|
2969701778U, // SQRDMLAHv8i16_indexed
|
|
1075892207U, // SQRDMLSH_ZZZI_D
|
|
2195787759U, // SQRDMLSH_ZZZI_H
|
|
1344360431U, // SQRDMLSH_ZZZI_S
|
|
2418053103U, // SQRDMLSH_ZZZ_B
|
|
1075892207U, // SQRDMLSH_ZZZ_D
|
|
2195787759U, // SQRDMLSH_ZZZ_H
|
|
1344360431U, // SQRDMLSH_ZZZ_S
|
|
807718895U, // SQRDMLSHv1i16
|
|
807718895U, // SQRDMLSHv1i16_indexed
|
|
807718895U, // SQRDMLSHv1i32
|
|
807718895U, // SQRDMLSHv1i32_indexed
|
|
2961313775U, // SQRDMLSHv2i32
|
|
2961313775U, // SQRDMLSHv2i32_indexed
|
|
2965508079U, // SQRDMLSHv4i16
|
|
2965508079U, // SQRDMLSHv4i16_indexed
|
|
2967605231U, // SQRDMLSHv4i32
|
|
2967605231U, // SQRDMLSHv4i32_indexed
|
|
2969702383U, // SQRDMLSHv8i16
|
|
2969702383U, // SQRDMLSHv8i16_indexed
|
|
2418069215U, // SQRDMULH_ZZZI_D
|
|
2189496031U, // SQRDMULH_ZZZI_H
|
|
270618335U, // SQRDMULH_ZZZI_S
|
|
2133727U, // SQRDMULH_ZZZ_B
|
|
2418069215U, // SQRDMULH_ZZZ_D
|
|
2189496031U, // SQRDMULH_ZZZ_H
|
|
270618335U, // SQRDMULH_ZZZ_S
|
|
2117343U, // SQRDMULHv1i16
|
|
2117343U, // SQRDMULHv1i16_indexed
|
|
2117343U, // SQRDMULHv1i32
|
|
2117343U, // SQRDMULHv1i32_indexed
|
|
813797087U, // SQRDMULHv2i32
|
|
813797087U, // SQRDMULHv2i32_indexed
|
|
817991391U, // SQRDMULHv4i16
|
|
817991391U, // SQRDMULHv4i16_indexed
|
|
820088543U, // SQRDMULHv4i32
|
|
820088543U, // SQRDMULHv4i32_indexed
|
|
822185695U, // SQRDMULHv8i16
|
|
822185695U, // SQRDMULHv8i16_indexed
|
|
3223361747U, // SQRSHLR_ZPmZ_B
|
|
3223378131U, // SQRSHLR_ZPmZ_D
|
|
3519092947U, // SQRSHLR_ZPmZ_H
|
|
3223410899U, // SQRSHLR_ZPmZ_S
|
|
3223360148U, // SQRSHL_ZPmZ_B
|
|
3223376532U, // SQRSHL_ZPmZ_D
|
|
3519091348U, // SQRSHL_ZPmZ_H
|
|
3223409300U, // SQRSHL_ZPmZ_S
|
|
811700884U, // SQRSHLv16i8
|
|
2118292U, // SQRSHLv1i16
|
|
2118292U, // SQRSHLv1i32
|
|
2118292U, // SQRSHLv1i64
|
|
2118292U, // SQRSHLv1i8
|
|
813798036U, // SQRSHLv2i32
|
|
815895188U, // SQRSHLv2i64
|
|
817992340U, // SQRSHLv4i16
|
|
820089492U, // SQRSHLv4i32
|
|
822186644U, // SQRSHLv8i16
|
|
824283796U, // SQRSHLv8i8
|
|
1881180171U, // SQRSHRNB_ZZI_B
|
|
2172717067U, // SQRSHRNB_ZZI_H
|
|
2418100235U, // SQRSHRNB_ZZI_S
|
|
2686491865U, // SQRSHRNT_ZZI_B
|
|
2174819545U, // SQRSHRNT_ZZI_H
|
|
1075928281U, // SQRSHRNT_ZZI_S
|
|
3223360849U, // SQRSHRN_VG4_Z4ZI_B
|
|
2181109073U, // SQRSHRN_VG4_Z4ZI_H
|
|
2185303377U, // SQRSHRN_Z2ZI_StoH
|
|
2118993U, // SQRSHRNb
|
|
2118993U, // SQRSHRNh
|
|
2118993U, // SQRSHRNs
|
|
2959213010U, // SQRSHRNv16i8_shift
|
|
813798737U, // SQRSHRNv2i32_shift
|
|
817993041U, // SQRSHRNv4i16_shift
|
|
2967601618U, // SQRSHRNv4i32_shift
|
|
2969698770U, // SQRSHRNv8i16_shift
|
|
824284497U, // SQRSHRNv8i8_shift
|
|
1881180225U, // SQRSHRUNB_ZZI_B
|
|
2172717121U, // SQRSHRUNB_ZZI_H
|
|
2418100289U, // SQRSHRUNB_ZZI_S
|
|
2686491920U, // SQRSHRUNT_ZZI_B
|
|
2174819600U, // SQRSHRUNT_ZZI_H
|
|
1075928336U, // SQRSHRUNT_ZZI_S
|
|
3223360927U, // SQRSHRUN_VG4_Z4ZI_B
|
|
2181109151U, // SQRSHRUN_VG4_Z4ZI_H
|
|
2185303455U, // SQRSHRUN_Z2ZI_StoH
|
|
2119071U, // SQRSHRUNb
|
|
2119071U, // SQRSHRUNh
|
|
2119071U, // SQRSHRUNs
|
|
2959213071U, // SQRSHRUNv16i8_shift
|
|
813798815U, // SQRSHRUNv2i32_shift
|
|
817993119U, // SQRSHRUNv4i16_shift
|
|
2967601679U, // SQRSHRUNv4i32_shift
|
|
2969698831U, // SQRSHRUNv8i16_shift
|
|
824284575U, // SQRSHRUNv8i8_shift
|
|
2185305680U, // SQRSHRU_VG2_Z2ZI_H
|
|
3223363152U, // SQRSHRU_VG4_Z4ZI_B
|
|
2181111376U, // SQRSHRU_VG4_Z4ZI_H
|
|
2185304188U, // SQRSHR_VG2_Z2ZI_H
|
|
3223361660U, // SQRSHR_VG4_Z4ZI_B
|
|
2181109884U, // SQRSHR_VG4_Z4ZI_H
|
|
3223361731U, // SQSHLR_ZPmZ_B
|
|
3223378115U, // SQSHLR_ZPmZ_D
|
|
3519092931U, // SQSHLR_ZPmZ_H
|
|
3223410883U, // SQSHLR_ZPmZ_S
|
|
3223363120U, // SQSHLU_ZPmI_B
|
|
3223379504U, // SQSHLU_ZPmI_D
|
|
3519094320U, // SQSHLU_ZPmI_H
|
|
3223412272U, // SQSHLU_ZPmI_S
|
|
2121264U, // SQSHLUb
|
|
2121264U, // SQSHLUd
|
|
2121264U, // SQSHLUh
|
|
2121264U, // SQSHLUs
|
|
811703856U, // SQSHLUv16i8_shift
|
|
813801008U, // SQSHLUv2i32_shift
|
|
815898160U, // SQSHLUv2i64_shift
|
|
817995312U, // SQSHLUv4i16_shift
|
|
820092464U, // SQSHLUv4i32_shift
|
|
822189616U, // SQSHLUv8i16_shift
|
|
824286768U, // SQSHLUv8i8_shift
|
|
3223360134U, // SQSHL_ZPmI_B
|
|
3223376518U, // SQSHL_ZPmI_D
|
|
3519091334U, // SQSHL_ZPmI_H
|
|
3223409286U, // SQSHL_ZPmI_S
|
|
3223360134U, // SQSHL_ZPmZ_B
|
|
3223376518U, // SQSHL_ZPmZ_D
|
|
3519091334U, // SQSHL_ZPmZ_H
|
|
3223409286U, // SQSHL_ZPmZ_S
|
|
2118278U, // SQSHLb
|
|
2118278U, // SQSHLd
|
|
2118278U, // SQSHLh
|
|
2118278U, // SQSHLs
|
|
811700870U, // SQSHLv16i8
|
|
811700870U, // SQSHLv16i8_shift
|
|
2118278U, // SQSHLv1i16
|
|
2118278U, // SQSHLv1i32
|
|
2118278U, // SQSHLv1i64
|
|
2118278U, // SQSHLv1i8
|
|
813798022U, // SQSHLv2i32
|
|
813798022U, // SQSHLv2i32_shift
|
|
815895174U, // SQSHLv2i64
|
|
815895174U, // SQSHLv2i64_shift
|
|
817992326U, // SQSHLv4i16
|
|
817992326U, // SQSHLv4i16_shift
|
|
820089478U, // SQSHLv4i32
|
|
820089478U, // SQSHLv4i32_shift
|
|
822186630U, // SQSHLv8i16
|
|
822186630U, // SQSHLv8i16_shift
|
|
824283782U, // SQSHLv8i8
|
|
824283782U, // SQSHLv8i8_shift
|
|
1881180153U, // SQSHRNB_ZZI_B
|
|
2172717049U, // SQSHRNB_ZZI_H
|
|
2418100217U, // SQSHRNB_ZZI_S
|
|
2686491847U, // SQSHRNT_ZZI_B
|
|
2174819527U, // SQSHRNT_ZZI_H
|
|
1075928263U, // SQSHRNT_ZZI_S
|
|
2118977U, // SQSHRNb
|
|
2118977U, // SQSHRNh
|
|
2118977U, // SQSHRNs
|
|
2959212992U, // SQSHRNv16i8_shift
|
|
813798721U, // SQSHRNv2i32_shift
|
|
817993025U, // SQSHRNv4i16_shift
|
|
2967601600U, // SQSHRNv4i32_shift
|
|
2969698752U, // SQSHRNv8i16_shift
|
|
824284481U, // SQSHRNv8i8_shift
|
|
1881180215U, // SQSHRUNB_ZZI_B
|
|
2172717111U, // SQSHRUNB_ZZI_H
|
|
2418100279U, // SQSHRUNB_ZZI_S
|
|
2686491910U, // SQSHRUNT_ZZI_B
|
|
2174819590U, // SQSHRUNT_ZZI_H
|
|
1075928326U, // SQSHRUNT_ZZI_S
|
|
2119062U, // SQSHRUNb
|
|
2119062U, // SQSHRUNh
|
|
2119062U, // SQSHRUNs
|
|
2959213061U, // SQSHRUNv16i8_shift
|
|
813798806U, // SQSHRUNv2i32_shift
|
|
817993110U, // SQSHRUNv4i16_shift
|
|
2967601669U, // SQSHRUNv4i32_shift
|
|
2969698821U, // SQSHRUNv8i16_shift
|
|
824284566U, // SQSHRUNv8i8_shift
|
|
3223361612U, // SQSUBR_ZPmZ_B
|
|
3223377996U, // SQSUBR_ZPmZ_D
|
|
3519092812U, // SQSUBR_ZPmZ_H
|
|
3223410764U, // SQSUBR_ZPmZ_S
|
|
2132444U, // SQSUB_ZI_B
|
|
2418067932U, // SQSUB_ZI_D
|
|
2189494748U, // SQSUB_ZI_H
|
|
270617052U, // SQSUB_ZI_S
|
|
3223357916U, // SQSUB_ZPmZ_B
|
|
3223374300U, // SQSUB_ZPmZ_D
|
|
3519089116U, // SQSUB_ZPmZ_H
|
|
3223407068U, // SQSUB_ZPmZ_S
|
|
2132444U, // SQSUB_ZZZ_B
|
|
2418067932U, // SQSUB_ZZZ_D
|
|
2189494748U, // SQSUB_ZZZ_H
|
|
270617052U, // SQSUB_ZZZ_S
|
|
811698652U, // SQSUBv16i8
|
|
2116060U, // SQSUBv1i16
|
|
2116060U, // SQSUBv1i32
|
|
2116060U, // SQSUBv1i64
|
|
2116060U, // SQSUBv1i8
|
|
813795804U, // SQSUBv2i32
|
|
815892956U, // SQSUBv2i64
|
|
817990108U, // SQSUBv4i16
|
|
820087260U, // SQSUBv4i32
|
|
822184412U, // SQSUBv8i16
|
|
824281564U, // SQSUBv8i8
|
|
1881180199U, // SQXTNB_ZZ_B
|
|
1635846183U, // SQXTNB_ZZ_H
|
|
2418100263U, // SQXTNB_ZZ_S
|
|
2686491894U, // SQXTNT_ZZ_B
|
|
1637948662U, // SQXTNT_ZZ_H
|
|
1075928310U, // SQXTNT_ZZ_S
|
|
2959213045U, // SQXTNv16i8
|
|
2119048U, // SQXTNv1i16
|
|
2119048U, // SQXTNv1i32
|
|
2119048U, // SQXTNv1i8
|
|
813798792U, // SQXTNv2i32
|
|
817993096U, // SQXTNv4i16
|
|
2967601653U, // SQXTNv4i32
|
|
2969698805U, // SQXTNv8i16
|
|
824284552U, // SQXTNv8i8
|
|
1881180236U, // SQXTUNB_ZZ_B
|
|
1635846220U, // SQXTUNB_ZZ_H
|
|
2418100300U, // SQXTUNB_ZZ_S
|
|
2686491931U, // SQXTUNT_ZZ_B
|
|
1637948699U, // SQXTUNT_ZZ_H
|
|
1075928347U, // SQXTUNT_ZZ_S
|
|
2959213082U, // SQXTUNv16i8
|
|
2119090U, // SQXTUNv1i16
|
|
2119090U, // SQXTUNv1i32
|
|
2119090U, // SQXTUNv1i8
|
|
813798834U, // SQXTUNv2i32
|
|
817993138U, // SQXTUNv4i16
|
|
2967601690U, // SQXTUNv4i32
|
|
2969698842U, // SQXTUNv8i16
|
|
824284594U, // SQXTUNv8i8
|
|
3223358333U, // SRHADD_ZPmZ_B
|
|
3223374717U, // SRHADD_ZPmZ_D
|
|
3519089533U, // SRHADD_ZPmZ_H
|
|
3223407485U, // SRHADD_ZPmZ_S
|
|
811699069U, // SRHADDv16i8
|
|
813796221U, // SRHADDv2i32
|
|
817990525U, // SRHADDv4i16
|
|
820087677U, // SRHADDv4i32
|
|
822184829U, // SRHADDv8i16
|
|
824281981U, // SRHADDv8i8
|
|
2418053276U, // SRI_ZZI_B
|
|
1075892380U, // SRI_ZZI_D
|
|
2195787932U, // SRI_ZZI_H
|
|
1344360604U, // SRI_ZZI_S
|
|
807719068U, // SRId
|
|
2959216796U, // SRIv16i8_shift
|
|
2961313948U, // SRIv2i32_shift
|
|
2963411100U, // SRIv2i64_shift
|
|
2965508252U, // SRIv4i16_shift
|
|
2967605404U, // SRIv4i32_shift
|
|
2969702556U, // SRIv8i16_shift
|
|
2971799708U, // SRIv8i8_shift
|
|
3223361765U, // SRSHLR_ZPmZ_B
|
|
3223378149U, // SRSHLR_ZPmZ_D
|
|
3519092965U, // SRSHLR_ZPmZ_H
|
|
3223410917U, // SRSHLR_ZPmZ_S
|
|
2179093156U, // SRSHL_VG2_2Z2Z_B
|
|
2181206692U, // SRSHL_VG2_2Z2Z_D
|
|
2183320228U, // SRSHL_VG2_2Z2Z_H
|
|
2185433764U, // SRSHL_VG2_2Z2Z_S
|
|
2179093156U, // SRSHL_VG2_2ZZ_B
|
|
2181206692U, // SRSHL_VG2_2ZZ_D
|
|
2183320228U, // SRSHL_VG2_2ZZ_H
|
|
2185433764U, // SRSHL_VG2_2ZZ_S
|
|
2179093156U, // SRSHL_VG4_4Z4Z_B
|
|
2181206692U, // SRSHL_VG4_4Z4Z_D
|
|
2183320228U, // SRSHL_VG4_4Z4Z_H
|
|
2185433764U, // SRSHL_VG4_4Z4Z_S
|
|
2179093156U, // SRSHL_VG4_4ZZ_B
|
|
2181206692U, // SRSHL_VG4_4ZZ_D
|
|
2183320228U, // SRSHL_VG4_4ZZ_H
|
|
2185433764U, // SRSHL_VG4_4ZZ_S
|
|
3223360164U, // SRSHL_ZPmZ_B
|
|
3223376548U, // SRSHL_ZPmZ_D
|
|
3519091364U, // SRSHL_ZPmZ_H
|
|
3223409316U, // SRSHL_ZPmZ_S
|
|
811700900U, // SRSHLv16i8
|
|
2118308U, // SRSHLv1i64
|
|
813798052U, // SRSHLv2i32
|
|
815895204U, // SRSHLv2i64
|
|
817992356U, // SRSHLv4i16
|
|
820089508U, // SRSHLv4i32
|
|
822186660U, // SRSHLv8i16
|
|
824283812U, // SRSHLv8i8
|
|
3223361676U, // SRSHR_ZPmI_B
|
|
3223378060U, // SRSHR_ZPmI_D
|
|
3519092876U, // SRSHR_ZPmI_H
|
|
3223410828U, // SRSHR_ZPmI_S
|
|
2119820U, // SRSHRd
|
|
811702412U, // SRSHRv16i8_shift
|
|
813799564U, // SRSHRv2i32_shift
|
|
815896716U, // SRSHRv2i64_shift
|
|
817993868U, // SRSHRv4i16_shift
|
|
820091020U, // SRSHRv4i32_shift
|
|
822188172U, // SRSHRv8i16_shift
|
|
824285324U, // SRSHRv8i8_shift
|
|
2418050149U, // SRSRA_ZZI_B
|
|
1075889253U, // SRSRA_ZZI_D
|
|
2195784805U, // SRSRA_ZZI_H
|
|
1344357477U, // SRSRA_ZZI_S
|
|
807715941U, // SRSRAd
|
|
2959213669U, // SRSRAv16i8_shift
|
|
2961310821U, // SRSRAv2i32_shift
|
|
2963407973U, // SRSRAv2i64_shift
|
|
2965505125U, // SRSRAv4i16_shift
|
|
2967602277U, // SRSRAv4i32_shift
|
|
2969699429U, // SRSRAv8i16_shift
|
|
2971796581U, // SRSRAv8i8_shift
|
|
270583594U, // SSHLLB_ZZI_D
|
|
2197882666U, // SSHLLB_ZZI_H
|
|
1881229098U, // SSHLLB_ZZI_S
|
|
270588951U, // SSHLLT_ZZI_D
|
|
2197888023U, // SSHLLT_ZZI_H
|
|
1881234455U, // SSHLLT_ZZI_S
|
|
822182206U, // SSHLLv16i8_shift
|
|
815895256U, // SSHLLv2i32_shift
|
|
820089560U, // SSHLLv4i16_shift
|
|
815890750U, // SSHLLv4i32_shift
|
|
820085054U, // SSHLLv8i16_shift
|
|
822186712U, // SSHLLv8i8_shift
|
|
811700914U, // SSHLv16i8
|
|
2118322U, // SSHLv1i64
|
|
813798066U, // SSHLv2i32
|
|
815895218U, // SSHLv2i64
|
|
817992370U, // SSHLv4i16
|
|
820089522U, // SSHLv4i32
|
|
822186674U, // SSHLv8i16
|
|
824283826U, // SSHLv8i8
|
|
2119834U, // SSHRd
|
|
811702426U, // SSHRv16i8_shift
|
|
813799578U, // SSHRv2i32_shift
|
|
815896730U, // SSHRv2i64_shift
|
|
817993882U, // SSHRv4i16_shift
|
|
820091034U, // SSHRv4i32_shift
|
|
822188186U, // SSHRv8i16_shift
|
|
824285338U, // SSHRv8i8_shift
|
|
2418050163U, // SSRA_ZZI_B
|
|
1075889267U, // SSRA_ZZI_D
|
|
2195784819U, // SSRA_ZZI_H
|
|
1344357491U, // SSRA_ZZI_S
|
|
807715955U, // SSRAd
|
|
2959213683U, // SSRAv16i8_shift
|
|
2961310835U, // SSRAv2i32_shift
|
|
2963407987U, // SSRAv2i64_shift
|
|
2965505139U, // SSRAv4i16_shift
|
|
2967602291U, // SSRAv4i32_shift
|
|
2969699443U, // SSRAv8i16_shift
|
|
2971796595U, // SSRAv8i8_shift
|
|
3250750754U, // SST1B_D
|
|
3250750754U, // SST1B_D_IMM
|
|
3250750754U, // SST1B_D_SXTW
|
|
3250750754U, // SST1B_D_UXTW
|
|
3250783522U, // SST1B_S_IMM
|
|
3250783522U, // SST1B_S_SXTW
|
|
3250783522U, // SST1B_S_UXTW
|
|
3250752209U, // SST1D
|
|
3250752209U, // SST1D_IMM
|
|
3250752209U, // SST1D_SCALED
|
|
3250752209U, // SST1D_SXTW
|
|
3250752209U, // SST1D_SXTW_SCALED
|
|
3250752209U, // SST1D_UXTW
|
|
3250752209U, // SST1D_UXTW_SCALED
|
|
3250752826U, // SST1H_D
|
|
3250752826U, // SST1H_D_IMM
|
|
3250752826U, // SST1H_D_SCALED
|
|
3250752826U, // SST1H_D_SXTW
|
|
3250752826U, // SST1H_D_SXTW_SCALED
|
|
3250752826U, // SST1H_D_UXTW
|
|
3250752826U, // SST1H_D_UXTW_SCALED
|
|
3250785594U, // SST1H_S_IMM
|
|
3250785594U, // SST1H_S_SXTW
|
|
3250785594U, // SST1H_S_SXTW_SCALED
|
|
3250785594U, // SST1H_S_UXTW
|
|
3250785594U, // SST1H_S_UXTW_SCALED
|
|
3251083186U, // SST1Q
|
|
3250757524U, // SST1W_D
|
|
3250757524U, // SST1W_D_IMM
|
|
3250757524U, // SST1W_D_SCALED
|
|
3250757524U, // SST1W_D_SXTW
|
|
3250757524U, // SST1W_D_SXTW_SCALED
|
|
3250757524U, // SST1W_D_UXTW
|
|
3250757524U, // SST1W_D_UXTW_SCALED
|
|
3250790292U, // SST1W_IMM
|
|
3250790292U, // SST1W_SXTW
|
|
3250790292U, // SST1W_SXTW_SCALED
|
|
3250790292U, // SST1W_UXTW
|
|
3250790292U, // SST1W_UXTW_SCALED
|
|
270588685U, // SSUBLBT_ZZZ_D
|
|
2197887757U, // SSUBLBT_ZZZ_H
|
|
1881234189U, // SSUBLBT_ZZZ_S
|
|
270583523U, // SSUBLB_ZZZ_D
|
|
2197882595U, // SSUBLB_ZZZ_H
|
|
1881229027U, // SSUBLB_ZZZ_S
|
|
270584188U, // SSUBLTB_ZZZ_D
|
|
2197883260U, // SSUBLTB_ZZZ_H
|
|
1881229692U, // SSUBLTB_ZZZ_S
|
|
270588875U, // SSUBLT_ZZZ_D
|
|
2197887947U, // SSUBLT_ZZZ_H
|
|
1881234379U, // SSUBLT_ZZZ_S
|
|
822182158U, // SSUBLv16i8_v8i16
|
|
815895078U, // SSUBLv2i32_v2i64
|
|
820089382U, // SSUBLv4i16_v4i32
|
|
815890702U, // SSUBLv4i32_v2i64
|
|
820085006U, // SSUBLv8i16_v4i32
|
|
822186534U, // SSUBLv8i8_v8i16
|
|
2418067952U, // SSUBWB_ZZZ_D
|
|
2189494768U, // SSUBWB_ZZZ_H
|
|
270617072U, // SSUBWB_ZZZ_S
|
|
2418073077U, // SSUBWT_ZZZ_D
|
|
2189499893U, // SSUBWT_ZZZ_H
|
|
270622197U, // SSUBWT_ZZZ_S
|
|
822182490U, // SSUBWv16i8_v8i16
|
|
815898566U, // SSUBWv2i32_v2i64
|
|
820092870U, // SSUBWv4i16_v4i32
|
|
815891034U, // SSUBWv4i32_v2i64
|
|
820085338U, // SSUBWv8i16_v4i32
|
|
822190022U, // SSUBWv8i8_v8i16
|
|
3250734370U, // ST1B
|
|
3315746082U, // ST1B_2Z
|
|
3315746082U, // ST1B_2Z_IMM
|
|
2150139170U, // ST1B_2Z_STRIDED
|
|
2150139170U, // ST1B_2Z_STRIDED_IMM
|
|
3315746082U, // ST1B_4Z
|
|
3315746082U, // ST1B_4Z_IMM
|
|
3315746082U, // ST1B_4Z_STRIDED
|
|
3315746082U, // ST1B_4Z_STRIDED_IMM
|
|
3250750754U, // ST1B_D
|
|
3250750754U, // ST1B_D_IMM
|
|
3250767138U, // ST1B_H
|
|
3250767138U, // ST1B_H_IMM
|
|
3250734370U, // ST1B_IMM
|
|
3250783522U, // ST1B_S
|
|
3250783522U, // ST1B_S_IMM
|
|
3250752209U, // ST1D
|
|
3315763921U, // ST1D_2Z
|
|
3315763921U, // ST1D_2Z_IMM
|
|
3315763921U, // ST1D_2Z_STRIDED
|
|
3315763921U, // ST1D_2Z_STRIDED_IMM
|
|
3315763921U, // ST1D_4Z
|
|
3315763921U, // ST1D_4Z_IMM
|
|
3315763921U, // ST1D_4Z_STRIDED
|
|
3315763921U, // ST1D_4Z_STRIDED_IMM
|
|
3250752209U, // ST1D_IMM
|
|
3251079889U, // ST1D_Q
|
|
3251079889U, // ST1D_Q_IMM
|
|
573554U, // ST1Fourv16b
|
|
97058930U, // ST1Fourv16b_POST
|
|
606322U, // ST1Fourv1d
|
|
99188850U, // ST1Fourv1d_POST
|
|
639090U, // ST1Fourv2d
|
|
97124466U, // ST1Fourv2d_POST
|
|
671858U, // ST1Fourv2s
|
|
99254386U, // ST1Fourv2s_POST
|
|
704626U, // ST1Fourv4h
|
|
99287154U, // ST1Fourv4h_POST
|
|
737394U, // ST1Fourv4s
|
|
97222770U, // ST1Fourv4s_POST
|
|
770162U, // ST1Fourv8b
|
|
99352690U, // ST1Fourv8b_POST
|
|
802930U, // ST1Fourv8h
|
|
97288306U, // ST1Fourv8h_POST
|
|
3250769210U, // ST1H
|
|
3315780922U, // ST1H_2Z
|
|
3315780922U, // ST1H_2Z_IMM
|
|
2150419770U, // ST1H_2Z_STRIDED
|
|
2150419770U, // ST1H_2Z_STRIDED_IMM
|
|
3315780922U, // ST1H_4Z
|
|
3315780922U, // ST1H_4Z_IMM
|
|
3315780922U, // ST1H_4Z_STRIDED
|
|
3315780922U, // ST1H_4Z_STRIDED_IMM
|
|
3250752826U, // ST1H_D
|
|
3250752826U, // ST1H_D_IMM
|
|
3250769210U, // ST1H_IMM
|
|
3250785594U, // ST1H_S
|
|
3250785594U, // ST1H_S_IMM
|
|
573554U, // ST1Onev16b
|
|
101253234U, // ST1Onev16b_POST
|
|
606322U, // ST1Onev1d
|
|
103383154U, // ST1Onev1d_POST
|
|
639090U, // ST1Onev2d
|
|
101318770U, // ST1Onev2d_POST
|
|
671858U, // ST1Onev2s
|
|
103448690U, // ST1Onev2s_POST
|
|
704626U, // ST1Onev4h
|
|
103481458U, // ST1Onev4h_POST
|
|
737394U, // ST1Onev4s
|
|
101417074U, // ST1Onev4s_POST
|
|
770162U, // ST1Onev8b
|
|
103546994U, // ST1Onev8b_POST
|
|
802930U, // ST1Onev8h
|
|
101482610U, // ST1Onev8h_POST
|
|
573554U, // ST1Threev16b
|
|
111738994U, // ST1Threev16b_POST
|
|
606322U, // ST1Threev1d
|
|
113868914U, // ST1Threev1d_POST
|
|
639090U, // ST1Threev2d
|
|
111804530U, // ST1Threev2d_POST
|
|
671858U, // ST1Threev2s
|
|
113934450U, // ST1Threev2s_POST
|
|
704626U, // ST1Threev4h
|
|
113967218U, // ST1Threev4h_POST
|
|
737394U, // ST1Threev4s
|
|
111902834U, // ST1Threev4s_POST
|
|
770162U, // ST1Threev8b
|
|
114032754U, // ST1Threev8b_POST
|
|
802930U, // ST1Threev8h
|
|
111968370U, // ST1Threev8h_POST
|
|
573554U, // ST1Twov16b
|
|
99156082U, // ST1Twov16b_POST
|
|
606322U, // ST1Twov1d
|
|
101286002U, // ST1Twov1d_POST
|
|
639090U, // ST1Twov2d
|
|
99221618U, // ST1Twov2d_POST
|
|
671858U, // ST1Twov2s
|
|
101351538U, // ST1Twov2s_POST
|
|
704626U, // ST1Twov4h
|
|
101384306U, // ST1Twov4h_POST
|
|
737394U, // ST1Twov4s
|
|
99319922U, // ST1Twov4s_POST
|
|
770162U, // ST1Twov8b
|
|
101449842U, // ST1Twov8b_POST
|
|
802930U, // ST1Twov8h
|
|
99385458U, // ST1Twov8h_POST
|
|
3250790292U, // ST1W
|
|
3315802004U, // ST1W_2Z
|
|
3315802004U, // ST1W_2Z_IMM
|
|
3315802004U, // ST1W_2Z_STRIDED
|
|
3315802004U, // ST1W_2Z_STRIDED_IMM
|
|
3315802004U, // ST1W_4Z
|
|
3315802004U, // ST1W_4Z_IMM
|
|
3315802004U, // ST1W_4Z_STRIDED
|
|
3315802004U, // ST1W_4Z_STRIDED_IMM
|
|
3250757524U, // ST1W_D
|
|
3250757524U, // ST1W_D_IMM
|
|
3250790292U, // ST1W_IMM
|
|
3251085204U, // ST1W_Q
|
|
3251085204U, // ST1W_Q_IMM
|
|
2208835806U, // ST1_MXIPXX_H_B
|
|
2208835820U, // ST1_MXIPXX_H_D
|
|
2208835834U, // ST1_MXIPXX_H_H
|
|
2208835848U, // ST1_MXIPXX_H_Q
|
|
2208835862U, // ST1_MXIPXX_H_S
|
|
2208852190U, // ST1_MXIPXX_V_B
|
|
2208852204U, // ST1_MXIPXX_V_D
|
|
2208852218U, // ST1_MXIPXX_V_H
|
|
2208852232U, // ST1_MXIPXX_V_Q
|
|
2208852246U, // ST1_MXIPXX_V_S
|
|
174899314U, // ST1i16
|
|
3666673778U, // ST1i16_POST
|
|
1245298U, // ST1i32
|
|
3935142002U, // ST1i32_POST
|
|
1261682U, // ST1i64
|
|
4203610226U, // ST1i64_POST
|
|
174620786U, // ST1i8
|
|
177111154U, // ST1i8_POST
|
|
3250734399U, // ST2B
|
|
3250734399U, // ST2B_IMM
|
|
3250752245U, // ST2D
|
|
3250752245U, // ST2D_IMM
|
|
849661122U, // ST2GPostIndex
|
|
849661122U, // ST2GPreIndex
|
|
44059842U, // ST2Gi
|
|
3250769239U, // ST2H
|
|
3250769239U, // ST2H_IMM
|
|
3251083198U, // ST2Q
|
|
3251083198U, // ST2Q_IMM
|
|
574037U, // ST2Twov16b
|
|
99156565U, // ST2Twov16b_POST
|
|
639573U, // ST2Twov2d
|
|
99222101U, // ST2Twov2d_POST
|
|
672341U, // ST2Twov2s
|
|
101352021U, // ST2Twov2s_POST
|
|
705109U, // ST2Twov4h
|
|
101384789U, // ST2Twov4h_POST
|
|
737877U, // ST2Twov4s
|
|
99320405U, // ST2Twov4s_POST
|
|
770645U, // ST2Twov8b
|
|
101450325U, // ST2Twov8b_POST
|
|
803413U, // ST2Twov8h
|
|
99385941U, // ST2Twov8h_POST
|
|
3250790312U, // ST2W
|
|
3250790312U, // ST2W_IMM
|
|
174899797U, // ST2i16
|
|
3935109717U, // ST2i16_POST
|
|
1245781U, // ST2i32
|
|
4203577941U, // ST2i32_POST
|
|
1262165U, // ST2i64
|
|
445514325U, // ST2i64_POST
|
|
174621269U, // ST2i8
|
|
3666772565U, // ST2i8_POST
|
|
3250734420U, // ST3B
|
|
3250734420U, // ST3B_IMM
|
|
3250752257U, // ST3D
|
|
3250752257U, // ST3D_IMM
|
|
3250769251U, // ST3H
|
|
3250769251U, // ST3H_IMM
|
|
3251083210U, // ST3Q
|
|
3251083210U, // ST3Q_IMM
|
|
574103U, // ST3Threev16b
|
|
111739543U, // ST3Threev16b_POST
|
|
639639U, // ST3Threev2d
|
|
111805079U, // ST3Threev2d_POST
|
|
672407U, // ST3Threev2s
|
|
113934999U, // ST3Threev2s_POST
|
|
705175U, // ST3Threev4h
|
|
113967767U, // ST3Threev4h_POST
|
|
737943U, // ST3Threev4s
|
|
111903383U, // ST3Threev4s_POST
|
|
770711U, // ST3Threev8b
|
|
114033303U, // ST3Threev8b_POST
|
|
803479U, // ST3Threev8h
|
|
111968919U, // ST3Threev8h_POST
|
|
3250790324U, // ST3W
|
|
3250790324U, // ST3W_IMM
|
|
174899863U, // ST3i16
|
|
713884311U, // ST3i16_POST
|
|
1245847U, // ST3i32
|
|
982352535U, // ST3i32_POST
|
|
1262231U, // ST3i64
|
|
1250820759U, // ST3i64_POST
|
|
174621335U, // ST3i8
|
|
1519288983U, // ST3i8_POST
|
|
3250734446U, // ST4B
|
|
3250734446U, // ST4B_IMM
|
|
3250752269U, // ST4D
|
|
3250752269U, // ST4D_IMM
|
|
574141U, // ST4Fourv16b
|
|
97059517U, // ST4Fourv16b_POST
|
|
639677U, // ST4Fourv2d
|
|
97125053U, // ST4Fourv2d_POST
|
|
672445U, // ST4Fourv2s
|
|
99254973U, // ST4Fourv2s_POST
|
|
705213U, // ST4Fourv4h
|
|
99287741U, // ST4Fourv4h_POST
|
|
737981U, // ST4Fourv4s
|
|
97223357U, // ST4Fourv4s_POST
|
|
770749U, // ST4Fourv8b
|
|
99353277U, // ST4Fourv8b_POST
|
|
803517U, // ST4Fourv8h
|
|
97288893U, // ST4Fourv8h_POST
|
|
3250769263U, // ST4H
|
|
3250769263U, // ST4H_IMM
|
|
3251083222U, // ST4Q
|
|
3251083222U, // ST4Q_IMM
|
|
3250790336U, // ST4W
|
|
3250790336U, // ST4W_IMM
|
|
174899901U, // ST4i16
|
|
4203545277U, // ST4i16_POST
|
|
1245885U, // ST4i32
|
|
445481661U, // ST4i32_POST
|
|
1262269U, // ST4i64
|
|
1787691709U, // ST4i64_POST
|
|
174621373U, // ST4i8
|
|
3935208125U, // ST4i8_POST
|
|
984417U, // ST64B
|
|
1881169513U, // ST64BV
|
|
1881161760U, // ST64BV0
|
|
44061869U, // STGM
|
|
2119245U, // STGPi
|
|
849661186U, // STGPostIndex
|
|
807720525U, // STGPpost
|
|
807720525U, // STGPpre
|
|
849661186U, // STGPreIndex
|
|
44059906U, // STGi
|
|
2119288U, // STILPW
|
|
807720568U, // STILPWpre
|
|
2119288U, // STILPX
|
|
807720568U, // STILPXpre
|
|
1261614U, // STL1
|
|
44058774U, // STLLRB
|
|
44060503U, // STLLRH
|
|
44062965U, // STLLRW
|
|
44062965U, // STLLRX
|
|
44058782U, // STLRB
|
|
44060511U, // STLRH
|
|
44062978U, // STLRW
|
|
849664258U, // STLRWpre
|
|
44062978U, // STLRX
|
|
849664258U, // STLRXpre
|
|
44058832U, // STLURBi
|
|
44060561U, // STLURHi
|
|
44063087U, // STLURWi
|
|
44063087U, // STLURXi
|
|
44063087U, // STLURbi
|
|
44063087U, // STLURdi
|
|
44063087U, // STLURhi
|
|
44063087U, // STLURqi
|
|
44063087U, // STLURsi
|
|
2119578U, // STLXPW
|
|
2119578U, // STLXPX
|
|
2115831U, // STLXRB
|
|
2117560U, // STLXRH
|
|
2120111U, // STLXRW
|
|
2120111U, // STLXRX
|
|
2119378U, // STNPDi
|
|
2119378U, // STNPQi
|
|
2119378U, // STNPSi
|
|
2119378U, // STNPWi
|
|
2119378U, // STNPXi
|
|
3315746074U, // STNT1B_2Z
|
|
3315746074U, // STNT1B_2Z_IMM
|
|
2150139162U, // STNT1B_2Z_STRIDED
|
|
2150139162U, // STNT1B_2Z_STRIDED_IMM
|
|
3315746074U, // STNT1B_4Z
|
|
3315746074U, // STNT1B_4Z_IMM
|
|
3315746074U, // STNT1B_4Z_STRIDED
|
|
3315746074U, // STNT1B_4Z_STRIDED_IMM
|
|
3250734362U, // STNT1B_ZRI
|
|
3250734362U, // STNT1B_ZRR
|
|
3250750746U, // STNT1B_ZZR_D_REAL
|
|
3250783514U, // STNT1B_ZZR_S_REAL
|
|
3315763913U, // STNT1D_2Z
|
|
3315763913U, // STNT1D_2Z_IMM
|
|
3315763913U, // STNT1D_2Z_STRIDED
|
|
3315763913U, // STNT1D_2Z_STRIDED_IMM
|
|
3315763913U, // STNT1D_4Z
|
|
3315763913U, // STNT1D_4Z_IMM
|
|
3315763913U, // STNT1D_4Z_STRIDED
|
|
3315763913U, // STNT1D_4Z_STRIDED_IMM
|
|
3250752201U, // STNT1D_ZRI
|
|
3250752201U, // STNT1D_ZRR
|
|
3250752201U, // STNT1D_ZZR_D_REAL
|
|
3315780914U, // STNT1H_2Z
|
|
3315780914U, // STNT1H_2Z_IMM
|
|
2150419762U, // STNT1H_2Z_STRIDED
|
|
2150419762U, // STNT1H_2Z_STRIDED_IMM
|
|
3315780914U, // STNT1H_4Z
|
|
3315780914U, // STNT1H_4Z_IMM
|
|
3315780914U, // STNT1H_4Z_STRIDED
|
|
3315780914U, // STNT1H_4Z_STRIDED_IMM
|
|
3250769202U, // STNT1H_ZRI
|
|
3250769202U, // STNT1H_ZRR
|
|
3250752818U, // STNT1H_ZZR_D_REAL
|
|
3250785586U, // STNT1H_ZZR_S_REAL
|
|
3315801996U, // STNT1W_2Z
|
|
3315801996U, // STNT1W_2Z_IMM
|
|
3315801996U, // STNT1W_2Z_STRIDED
|
|
3315801996U, // STNT1W_2Z_STRIDED_IMM
|
|
3315801996U, // STNT1W_4Z
|
|
3315801996U, // STNT1W_4Z_IMM
|
|
3315801996U, // STNT1W_4Z_STRIDED
|
|
3315801996U, // STNT1W_4Z_STRIDED_IMM
|
|
3250790284U, // STNT1W_ZRI
|
|
3250790284U, // STNT1W_ZRR
|
|
3250757516U, // STNT1W_ZZR_D_REAL
|
|
3250790284U, // STNT1W_ZZR_S_REAL
|
|
2119516U, // STPDi
|
|
807720796U, // STPDpost
|
|
807720796U, // STPDpre
|
|
2119516U, // STPQi
|
|
807720796U, // STPQpost
|
|
807720796U, // STPQpre
|
|
2119516U, // STPSi
|
|
807720796U, // STPSpost
|
|
807720796U, // STPSpre
|
|
2119516U, // STPWi
|
|
807720796U, // STPWpost
|
|
807720796U, // STPWpre
|
|
2119516U, // STPXi
|
|
807720796U, // STPXpost
|
|
807720796U, // STPXpre
|
|
849660092U, // STRBBpost
|
|
849660092U, // STRBBpre
|
|
44058812U, // STRBBroW
|
|
44058812U, // STRBBroX
|
|
44058812U, // STRBBui
|
|
849664341U, // STRBpost
|
|
849664341U, // STRBpre
|
|
44063061U, // STRBroW
|
|
44063061U, // STRBroX
|
|
44063061U, // STRBui
|
|
849664341U, // STRDpost
|
|
849664341U, // STRDpre
|
|
44063061U, // STRDroW
|
|
44063061U, // STRDroX
|
|
44063061U, // STRDui
|
|
849661821U, // STRHHpost
|
|
849661821U, // STRHHpre
|
|
44060541U, // STRHHroW
|
|
44060541U, // STRHHroX
|
|
44060541U, // STRHHui
|
|
849664341U, // STRHpost
|
|
849664341U, // STRHpre
|
|
44063061U, // STRHroW
|
|
44063061U, // STRHroX
|
|
44063061U, // STRHui
|
|
849664341U, // STRQpost
|
|
849664341U, // STRQpre
|
|
44063061U, // STRQroW
|
|
44063061U, // STRQroX
|
|
44063061U, // STRQui
|
|
849664341U, // STRSpost
|
|
849664341U, // STRSpre
|
|
44063061U, // STRSroW
|
|
44063061U, // STRSroX
|
|
44063061U, // STRSui
|
|
849664341U, // STRWpost
|
|
849664341U, // STRWpre
|
|
44063061U, // STRWroW
|
|
44063061U, // STRWroX
|
|
44063061U, // STRWui
|
|
849664341U, // STRXpost
|
|
849664341U, // STRXpre
|
|
44063061U, // STRXroW
|
|
44063061U, // STRXroX
|
|
44063061U, // STRXui
|
|
45062485U, // STR_PXI
|
|
44063061U, // STR_TX
|
|
1038677U, // STR_ZA
|
|
45062485U, // STR_ZXI
|
|
44058818U, // STTRBi
|
|
44060547U, // STTRHi
|
|
44063069U, // STTRWi
|
|
44063069U, // STTRXi
|
|
44058849U, // STURBBi
|
|
44063102U, // STURBi
|
|
44063102U, // STURDi
|
|
44060578U, // STURHHi
|
|
44063102U, // STURHi
|
|
44063102U, // STURQi
|
|
44063102U, // STURSi
|
|
44063102U, // STURWi
|
|
44063102U, // STURXi
|
|
24878U, // STX
|
|
2119585U, // STXPW
|
|
2119585U, // STXPX
|
|
2115839U, // STXRB
|
|
2117568U, // STXRH
|
|
2120118U, // STXRW
|
|
2120118U, // STXRX
|
|
24917U, // STY
|
|
25024U, // STZ
|
|
849661128U, // STZ2GPostIndex
|
|
849661128U, // STZ2GPreIndex
|
|
44059848U, // STZ2Gi
|
|
44061875U, // STZGM
|
|
849661191U, // STZGPostIndex
|
|
849661191U, // STZGPreIndex
|
|
44059911U, // STZGi
|
|
20661U, // STZI
|
|
2116815U, // SUBG
|
|
1881180118U, // SUBHNB_ZZZ_B
|
|
2172717014U, // SUBHNB_ZZZ_H
|
|
2418100182U, // SUBHNB_ZZZ_S
|
|
2686491808U, // SUBHNT_ZZZ_B
|
|
2174819488U, // SUBHNT_ZZZ_H
|
|
1075928224U, // SUBHNT_ZZZ_S
|
|
813798659U, // SUBHNv2i64_v2i32
|
|
2967601583U, // SUBHNv2i64_v4i32
|
|
817992963U, // SUBHNv4i32_v4i16
|
|
2969698735U, // SUBHNv4i32_v8i16
|
|
2959212975U, // SUBHNv8i16_v16i8
|
|
824284419U, // SUBHNv8i16_v8i8
|
|
2119175U, // SUBP
|
|
2120328U, // SUBPS
|
|
2121070U, // SUBPT_shift
|
|
2136118U, // SUBR_ZI_B
|
|
2418071606U, // SUBR_ZI_D
|
|
2189498422U, // SUBR_ZI_H
|
|
270620726U, // SUBR_ZI_S
|
|
3223361590U, // SUBR_ZPmZ_B
|
|
3223377974U, // SUBR_ZPmZ_D
|
|
3519092790U, // SUBR_ZPmZ_H
|
|
3223410742U, // SUBR_ZPmZ_S
|
|
2120192U, // SUBSWri
|
|
2120192U, // SUBSWrs
|
|
2120192U, // SUBSWrx
|
|
2120192U, // SUBSXri
|
|
2120192U, // SUBSXrs
|
|
2120192U, // SUBSXrx
|
|
2120192U, // SUBSXrx64
|
|
2116026U, // SUBWri
|
|
2116026U, // SUBWrs
|
|
2116026U, // SUBWrx
|
|
2116026U, // SUBXri
|
|
2116026U, // SUBXrs
|
|
2116026U, // SUBXrx
|
|
2116026U, // SUBXrx64
|
|
3798157754U, // SUB_VG2_M2Z2Z_D
|
|
3798174138U, // SUB_VG2_M2Z2Z_S
|
|
3798157754U, // SUB_VG2_M2ZZ_D
|
|
3798174138U, // SUB_VG2_M2ZZ_S
|
|
3798157754U, // SUB_VG2_M2Z_D
|
|
3798174138U, // SUB_VG2_M2Z_S
|
|
4066593210U, // SUB_VG4_M4Z4Z_D
|
|
4066609594U, // SUB_VG4_M4Z4Z_S
|
|
4066593210U, // SUB_VG4_M4ZZ_D
|
|
4066609594U, // SUB_VG4_M4ZZ_S
|
|
4066593210U, // SUB_VG4_M4Z_D
|
|
4066609594U, // SUB_VG4_M4Z_S
|
|
2132410U, // SUB_ZI_B
|
|
2418067898U, // SUB_ZI_D
|
|
2189494714U, // SUB_ZI_H
|
|
270617018U, // SUB_ZI_S
|
|
3223357882U, // SUB_ZPmZ_B
|
|
3223379310U, // SUB_ZPmZ_CPA
|
|
3223374266U, // SUB_ZPmZ_D
|
|
3519089082U, // SUB_ZPmZ_H
|
|
3223407034U, // SUB_ZPmZ_S
|
|
2132410U, // SUB_ZZZ_B
|
|
2418072942U, // SUB_ZZZ_CPA
|
|
2418067898U, // SUB_ZZZ_D
|
|
2189494714U, // SUB_ZZZ_H
|
|
270617018U, // SUB_ZZZ_S
|
|
811698618U, // SUBv16i8
|
|
2116026U, // SUBv1i64
|
|
813795770U, // SUBv2i32
|
|
815892922U, // SUBv2i64
|
|
817990074U, // SUBv4i16
|
|
820087226U, // SUBv4i32
|
|
822184378U, // SUBv8i16
|
|
824281530U, // SUBv8i8
|
|
3798179137U, // SUDOT_VG2_M2ZZI_BToS
|
|
3798179137U, // SUDOT_VG2_M2ZZ_BToS
|
|
4066614593U, // SUDOT_VG4_M4ZZI_BToS
|
|
4066614593U, // SUDOT_VG4_M4ZZ_BToS
|
|
2418105665U, // SUDOT_ZZZI
|
|
2967608641U, // SUDOTlanev16i8
|
|
2961317185U, // SUDOTlanev8i8
|
|
1688441551U, // SUMLALL_MZZI_BtoS
|
|
3835925199U, // SUMLALL_VG2_M2ZZI_BtoS
|
|
4104360655U, // SUMLALL_VG2_M2ZZ_BtoS
|
|
4104360655U, // SUMLALL_VG4_M4ZZI_BtoS
|
|
77828815U, // SUMLALL_VG4_M4ZZ_BtoS
|
|
54641594U, // SUMOPA_MPPZZ_D
|
|
79807418U, // SUMOPA_MPPZZ_S
|
|
54647470U, // SUMOPS_MPPZZ_D
|
|
79813294U, // SUMOPS_MPPZZ_S
|
|
270585965U, // SUNPKHI_ZZ_D
|
|
1661014125U, // SUNPKHI_ZZ_H
|
|
1881231469U, // SUNPKHI_ZZ_S
|
|
270587354U, // SUNPKLO_ZZ_D
|
|
1661015514U, // SUNPKLO_ZZ_H
|
|
1881232858U, // SUNPKLO_ZZ_S
|
|
1635946683U, // SUNPK_VG2_2ZZ_D
|
|
1661128891U, // SUNPK_VG2_2ZZ_H
|
|
1652756667U, // SUNPK_VG2_2ZZ_S
|
|
1648529595U, // SUNPK_VG4_4Z2Z_D
|
|
1642254523U, // SUNPK_VG4_4Z2Z_H
|
|
1646465211U, // SUNPK_VG4_4Z2Z_S
|
|
3223358386U, // SUQADD_ZPmZ_B
|
|
3223374770U, // SUQADD_ZPmZ_D
|
|
3519089586U, // SUQADD_ZPmZ_H
|
|
3223407538U, // SUQADD_ZPmZ_S
|
|
2959215538U, // SUQADDv16i8
|
|
807717810U, // SUQADDv1i16
|
|
807717810U, // SUQADDv1i32
|
|
807717810U, // SUQADDv1i64
|
|
807717810U, // SUQADDv1i8
|
|
2961312690U, // SUQADDv2i32
|
|
2963409842U, // SUQADDv2i64
|
|
2965506994U, // SUQADDv4i16
|
|
2967604146U, // SUQADDv4i32
|
|
2969701298U, // SUQADDv8i16
|
|
2971798450U, // SUQADDv8i8
|
|
4066614616U, // SUVDOT_VG4_M4ZZI_BToS
|
|
379558U, // SVC
|
|
3798179153U, // SVDOT_VG2_M2ZZI_HtoS
|
|
4066614609U, // SVDOT_VG4_M4ZZI_BtoS
|
|
4066598225U, // SVDOT_VG4_M4ZZI_HtoD
|
|
2418328977U, // SWPAB
|
|
2418331056U, // SWPAH
|
|
2418329247U, // SWPALB
|
|
2418331212U, // SWPALH
|
|
2418332050U, // SWPALW
|
|
2418332050U, // SWPALX
|
|
2418328620U, // SWPAW
|
|
2418328620U, // SWPAX
|
|
2418329700U, // SWPB
|
|
2418331429U, // SWPH
|
|
2418329456U, // SWPLB
|
|
2418331309U, // SWPLH
|
|
2418332575U, // SWPLW
|
|
2418332575U, // SWPLX
|
|
271537892U, // SWPP
|
|
271532998U, // SWPPA
|
|
271536418U, // SWPPAL
|
|
271536945U, // SWPPL
|
|
2418333547U, // SWPW
|
|
2418333547U, // SWPX
|
|
270584236U, // SXTB_ZPmZ_D
|
|
541133228U, // SXTB_ZPmZ_H
|
|
270617004U, // SXTB_ZPmZ_S
|
|
270585904U, // SXTH_ZPmZ_D
|
|
270618672U, // SXTH_ZPmZ_S
|
|
270590089U, // SXTW_ZPmZ_D
|
|
2118665U, // SYSLxt
|
|
2149603117U, // SYSPxt
|
|
2149603117U, // SYSPxt_XZR
|
|
2149604076U, // SYSxt
|
|
2686490611U, // TBLQ_ZZZ_B
|
|
2418071539U, // TBLQ_ZZZ_D
|
|
2183206899U, // TBLQ_ZZZ_H
|
|
3223410675U, // TBLQ_ZZZ_S
|
|
2686489105U, // TBL_ZZZZ_B
|
|
2418070033U, // TBL_ZZZZ_D
|
|
2183205393U, // TBL_ZZZZ_H
|
|
3223409169U, // TBL_ZZZZ_S
|
|
2686489105U, // TBL_ZZZ_B
|
|
2418070033U, // TBL_ZZZ_D
|
|
2183205393U, // TBL_ZZZ_H
|
|
3223409169U, // TBL_ZZZ_S
|
|
2690748945U, // TBLv16i8Four
|
|
2690748945U, // TBLv16i8One
|
|
2690748945U, // TBLv16i8Three
|
|
2690748945U, // TBLv16i8Two
|
|
2703331857U, // TBLv8i8Four
|
|
2703331857U, // TBLv8i8One
|
|
2703331857U, // TBLv8i8Three
|
|
2703331857U, // TBLv8i8Two
|
|
2122157U, // TBNZW
|
|
2122157U, // TBNZX
|
|
2418055173U, // TBXQ_ZZZ_B
|
|
1075894277U, // TBXQ_ZZZ_D
|
|
2195789829U, // TBXQ_ZZZ_H
|
|
1344362501U, // TBXQ_ZZZ_S
|
|
2418057435U, // TBX_ZZZ_B
|
|
1075896539U, // TBX_ZZZ_D
|
|
2195792091U, // TBX_ZZZ_H
|
|
1344364763U, // TBX_ZZZ_S
|
|
2690785499U, // TBXv16i8Four
|
|
2690785499U, // TBXv16i8One
|
|
2690785499U, // TBXv16i8Three
|
|
2690785499U, // TBXv16i8Two
|
|
2703368411U, // TBXv8i8Four
|
|
2703368411U, // TBXv8i8One
|
|
2703368411U, // TBXv8i8Three
|
|
2703368411U, // TBXv8i8Two
|
|
2122136U, // TBZW
|
|
2122136U, // TBZX
|
|
381544U, // TCANCEL
|
|
10409U, // TCOMMIT
|
|
23435U, // TRCIT
|
|
2129972U, // TRN1_PPP_B
|
|
2418065460U, // TRN1_PPP_D
|
|
2189492276U, // TRN1_PPP_H
|
|
270614580U, // TRN1_PPP_S
|
|
2129972U, // TRN1_ZZZ_B
|
|
2418065460U, // TRN1_ZZZ_D
|
|
2189492276U, // TRN1_ZZZ_H
|
|
2210873396U, // TRN1_ZZZ_Q
|
|
270614580U, // TRN1_ZZZ_S
|
|
811696180U, // TRN1v16i8
|
|
813793332U, // TRN1v2i32
|
|
815890484U, // TRN1v2i64
|
|
817987636U, // TRN1v4i16
|
|
820084788U, // TRN1v4i32
|
|
822181940U, // TRN1v8i16
|
|
824279092U, // TRN1v8i8
|
|
2130406U, // TRN2_PPP_B
|
|
2418065894U, // TRN2_PPP_D
|
|
2189492710U, // TRN2_PPP_H
|
|
270615014U, // TRN2_PPP_S
|
|
2130406U, // TRN2_ZZZ_B
|
|
2418065894U, // TRN2_ZZZ_D
|
|
2189492710U, // TRN2_ZZZ_H
|
|
2210873830U, // TRN2_ZZZ_Q
|
|
270615014U, // TRN2_ZZZ_S
|
|
811696614U, // TRN2v16i8
|
|
813793766U, // TRN2v2i32
|
|
815890918U, // TRN2v2i64
|
|
817988070U, // TRN2v4i16
|
|
820085222U, // TRN2v4i32
|
|
822182374U, // TRN2v8i16
|
|
824279526U, // TRN2v8i8
|
|
444783U, // TSB
|
|
23940U, // TSTART
|
|
23962U, // TTEST
|
|
1344325204U, // UABALB_ZZZ_D
|
|
2220951124U, // UABALB_ZZZ_H
|
|
2686535252U, // UABALB_ZZZ_S
|
|
1344330656U, // UABALT_ZZZ_D
|
|
2220956576U, // UABALT_ZZZ_H
|
|
2686540704U, // UABALT_ZZZ_S
|
|
2969698532U, // UABALv16i8_v8i16
|
|
2963411163U, // UABALv2i32_v2i64
|
|
2967605467U, // UABALv4i16_v4i32
|
|
2963407076U, // UABALv4i32_v2i64
|
|
2967601380U, // UABALv8i16_v4i32
|
|
2969702619U, // UABALv8i8_v8i16
|
|
2418049817U, // UABA_ZZZ_B
|
|
1075888921U, // UABA_ZZZ_D
|
|
2195784473U, // UABA_ZZZ_H
|
|
1344357145U, // UABA_ZZZ_S
|
|
2959213337U, // UABAv16i8
|
|
2961310489U, // UABAv2i32
|
|
2965504793U, // UABAv4i16
|
|
2967601945U, // UABAv4i32
|
|
2969699097U, // UABAv8i16
|
|
2971796249U, // UABAv8i8
|
|
270583561U, // UABDLB_ZZZ_D
|
|
2197882633U, // UABDLB_ZZZ_H
|
|
1881229065U, // UABDLB_ZZZ_S
|
|
270588913U, // UABDLT_ZZZ_D
|
|
2197887985U, // UABDLT_ZZZ_H
|
|
1881234417U, // UABDLT_ZZZ_S
|
|
822182182U, // UABDLv16i8_v8i16
|
|
815895099U, // UABDLv2i32_v2i64
|
|
820089403U, // UABDLv4i16_v4i32
|
|
815890726U, // UABDLv4i32_v2i64
|
|
820085030U, // UABDLv8i16_v4i32
|
|
822186555U, // UABDLv8i8_v8i16
|
|
3223358259U, // UABD_ZPmZ_B
|
|
3223374643U, // UABD_ZPmZ_D
|
|
3519089459U, // UABD_ZPmZ_H
|
|
3223407411U, // UABD_ZPmZ_S
|
|
811698995U, // UABDv16i8
|
|
813796147U, // UABDv2i32
|
|
817990451U, // UABDv4i16
|
|
820087603U, // UABDv4i32
|
|
822184755U, // UABDv8i16
|
|
824281907U, // UABDv8i8
|
|
3223377504U, // UADALP_ZPmZ_D
|
|
3519092320U, // UADALP_ZPmZ_H
|
|
3223410272U, // UADALP_ZPmZ_S
|
|
2969704032U, // UADALPv16i8_v8i16
|
|
3124893280U, // UADALPv2i32_v1i64
|
|
2961315424U, // UADALPv4i16_v2i32
|
|
2963412576U, // UADALPv4i32_v2i64
|
|
2967606880U, // UADALPv8i16_v4i32
|
|
2965509728U, // UADALPv8i8_v4i16
|
|
270583586U, // UADDLB_ZZZ_D
|
|
2197882658U, // UADDLB_ZZZ_H
|
|
1881229090U, // UADDLB_ZZZ_S
|
|
822187632U, // UADDLPv16i8_v8i16
|
|
977376880U, // UADDLPv2i32_v1i64
|
|
813799024U, // UADDLPv4i16_v2i32
|
|
815896176U, // UADDLPv4i32_v2i64
|
|
820090480U, // UADDLPv8i16_v4i32
|
|
817993328U, // UADDLPv8i8_v4i16
|
|
270588929U, // UADDLT_ZZZ_D
|
|
2197888001U, // UADDLT_ZZZ_H
|
|
1881234433U, // UADDLT_ZZZ_S
|
|
807427755U, // UADDLVv16i8v
|
|
807427755U, // UADDLVv4i16v
|
|
807427755U, // UADDLVv4i32v
|
|
807427755U, // UADDLVv8i16v
|
|
807427755U, // UADDLVv8i8v
|
|
822182198U, // UADDLv16i8_v8i16
|
|
815895137U, // UADDLv2i32_v2i64
|
|
820089441U, // UADDLv4i16_v4i32
|
|
815890742U, // UADDLv4i32_v2i64
|
|
820085046U, // UADDLv8i16_v4i32
|
|
822186593U, // UADDLv8i8_v8i16
|
|
1684283007U, // UADDV_VPZ_B
|
|
1657020031U, // UADDV_VPZ_D
|
|
1659117183U, // UADDV_VPZ_H
|
|
1638145663U, // UADDV_VPZ_S
|
|
2418067976U, // UADDWB_ZZZ_D
|
|
2189494792U, // UADDWB_ZZZ_H
|
|
270617096U, // UADDWB_ZZZ_S
|
|
2418073101U, // UADDWT_ZZZ_D
|
|
2189499917U, // UADDWT_ZZZ_H
|
|
270622221U, // UADDWT_ZZZ_S
|
|
822182514U, // UADDWv16i8_v8i16
|
|
815898628U, // UADDWv2i32_v2i64
|
|
820092932U, // UADDWv4i16_v4i32
|
|
815891058U, // UADDWv4i32_v2i64
|
|
820085362U, // UADDWv8i16_v4i32
|
|
822190084U, // UADDWv8i8_v8i16
|
|
2118810U, // UBFMWri
|
|
2118810U, // UBFMXri
|
|
2221037200U, // UCLAMP_VG2_2Z2Z_B
|
|
2193790608U, // UCLAMP_VG2_2Z2Z_D
|
|
2195904144U, // UCLAMP_VG2_2Z2Z_H
|
|
2174949008U, // UCLAMP_VG2_2Z2Z_S
|
|
2221037200U, // UCLAMP_VG4_4Z4Z_B
|
|
2193790608U, // UCLAMP_VG4_4Z4Z_D
|
|
2195904144U, // UCLAMP_VG4_4Z4Z_H
|
|
2174949008U, // UCLAMP_VG4_4Z4Z_S
|
|
2418054800U, // UCLAMP_ZZZ_B
|
|
1075893904U, // UCLAMP_ZZZ_D
|
|
2195789456U, // UCLAMP_ZZZ_H
|
|
1344362128U, // UCLAMP_ZZZ_S
|
|
2116795U, // UCVTFSWDri
|
|
2116795U, // UCVTFSWHri
|
|
2116795U, // UCVTFSWSri
|
|
2116795U, // UCVTFSXDri
|
|
2116795U, // UCVTFSXHri
|
|
2116795U, // UCVTFSXSri
|
|
2116795U, // UCVTFUWDri
|
|
2116795U, // UCVTFUWHri
|
|
2116795U, // UCVTFUWSri
|
|
2116795U, // UCVTFUXDri
|
|
2116795U, // UCVTFUXHri
|
|
2116795U, // UCVTFUXSri
|
|
1648561339U, // UCVTF_2Z2Z_StoS
|
|
1648561339U, // UCVTF_4Z4Z_StoS
|
|
270585019U, // UCVTF_ZPmZ_DtoD
|
|
3493924027U, // UCVTF_ZPmZ_DtoH
|
|
270617787U, // UCVTF_ZPmZ_DtoS
|
|
541134011U, // UCVTF_ZPmZ_HtoH
|
|
270585019U, // UCVTF_ZPmZ_StoD
|
|
1078004923U, // UCVTF_ZPmZ_StoH
|
|
270617787U, // UCVTF_ZPmZ_StoS
|
|
2116795U, // UCVTFd
|
|
2116795U, // UCVTFh
|
|
2116795U, // UCVTFs
|
|
2116795U, // UCVTFv1i16
|
|
2116795U, // UCVTFv1i32
|
|
2116795U, // UCVTFv1i64
|
|
813796539U, // UCVTFv2f32
|
|
815893691U, // UCVTFv2f64
|
|
813796539U, // UCVTFv2i32_shift
|
|
815893691U, // UCVTFv2i64_shift
|
|
817990843U, // UCVTFv4f16
|
|
820087995U, // UCVTFv4f32
|
|
817990843U, // UCVTFv4i16_shift
|
|
820087995U, // UCVTFv4i32_shift
|
|
822185147U, // UCVTFv8f16
|
|
822185147U, // UCVTFv8i16_shift
|
|
19620U, // UDF
|
|
3223378322U, // UDIVR_ZPmZ_D
|
|
3223411090U, // UDIVR_ZPmZ_S
|
|
2121373U, // UDIVWr
|
|
2121373U, // UDIVXr
|
|
3223379613U, // UDIV_ZPmZ_D
|
|
3223412381U, // UDIV_ZPmZ_S
|
|
3798179138U, // UDOT_VG2_M2Z2Z_BtoS
|
|
3798162754U, // UDOT_VG2_M2Z2Z_HtoD
|
|
3798179138U, // UDOT_VG2_M2Z2Z_HtoS
|
|
3798179138U, // UDOT_VG2_M2ZZI_BToS
|
|
3798179138U, // UDOT_VG2_M2ZZI_HToS
|
|
3798162754U, // UDOT_VG2_M2ZZI_HtoD
|
|
3798179138U, // UDOT_VG2_M2ZZ_BtoS
|
|
3798162754U, // UDOT_VG2_M2ZZ_HtoD
|
|
3798179138U, // UDOT_VG2_M2ZZ_HtoS
|
|
4066614594U, // UDOT_VG4_M4Z4Z_BtoS
|
|
4066598210U, // UDOT_VG4_M4Z4Z_HtoD
|
|
4066614594U, // UDOT_VG4_M4Z4Z_HtoS
|
|
4066614594U, // UDOT_VG4_M4ZZI_BtoS
|
|
4066614594U, // UDOT_VG4_M4ZZI_HToS
|
|
4066598210U, // UDOT_VG4_M4ZZI_HtoD
|
|
4066614594U, // UDOT_VG4_M4ZZ_BtoS
|
|
4066598210U, // UDOT_VG4_M4ZZ_HtoD
|
|
4066614594U, // UDOT_VG4_M4ZZ_HtoS
|
|
2686508354U, // UDOT_ZZZI_D
|
|
2686541122U, // UDOT_ZZZI_HtoS
|
|
2418105666U, // UDOT_ZZZI_S
|
|
2686508354U, // UDOT_ZZZ_D
|
|
2686541122U, // UDOT_ZZZ_HtoS
|
|
2418105666U, // UDOT_ZZZ_S
|
|
2967608642U, // UDOTlanev16i8
|
|
2961317186U, // UDOTlanev8i8
|
|
2967608642U, // UDOTv16i8
|
|
2961317186U, // UDOTv8i8
|
|
3223358356U, // UHADD_ZPmZ_B
|
|
3223374740U, // UHADD_ZPmZ_D
|
|
3519089556U, // UHADD_ZPmZ_H
|
|
3223407508U, // UHADD_ZPmZ_S
|
|
811699092U, // UHADDv16i8
|
|
813796244U, // UHADDv2i32
|
|
817990548U, // UHADDv4i16
|
|
820087700U, // UHADDv4i32
|
|
822184852U, // UHADDv8i16
|
|
824282004U, // UHADDv8i8
|
|
3223361604U, // UHSUBR_ZPmZ_B
|
|
3223377988U, // UHSUBR_ZPmZ_D
|
|
3519092804U, // UHSUBR_ZPmZ_H
|
|
3223410756U, // UHSUBR_ZPmZ_S
|
|
3223357894U, // UHSUB_ZPmZ_B
|
|
3223374278U, // UHSUB_ZPmZ_D
|
|
3519089094U, // UHSUB_ZPmZ_H
|
|
3223407046U, // UHSUB_ZPmZ_S
|
|
811698630U, // UHSUBv16i8
|
|
813795782U, // UHSUBv2i32
|
|
817990086U, // UHSUBv4i16
|
|
820087238U, // UHSUBv4i32
|
|
822184390U, // UHSUBv8i16
|
|
824281542U, // UHSUBv8i8
|
|
2118226U, // UMADDLrrr
|
|
3223361421U, // UMAXP_ZPmZ_B
|
|
3223377805U, // UMAXP_ZPmZ_D
|
|
3519092621U, // UMAXP_ZPmZ_H
|
|
3223410573U, // UMAXP_ZPmZ_S
|
|
811702157U, // UMAXPv16i8
|
|
813799309U, // UMAXPv2i32
|
|
817993613U, // UMAXPv4i16
|
|
820090765U, // UMAXPv4i32
|
|
822187917U, // UMAXPv8i16
|
|
824285069U, // UMAXPv8i8
|
|
3227623243U, // UMAXQV_VPZ_B
|
|
3231817547U, // UMAXQV_VPZ_D
|
|
3238109003U, // UMAXQV_VPZ_H
|
|
3236011851U, // UMAXQV_VPZ_S
|
|
253799U, // UMAXV_VPZ_B
|
|
1657020263U, // UMAXV_VPZ_D
|
|
1659133799U, // UMAXV_VPZ_H
|
|
1638178663U, // UMAXV_VPZ_S
|
|
807427943U, // UMAXVv16i8v
|
|
807427943U, // UMAXVv4i16v
|
|
807427943U, // UMAXVv4i32v
|
|
807427943U, // UMAXVv8i16v
|
|
807427943U, // UMAXVv8i8v
|
|
2121941U, // UMAXWri
|
|
2121941U, // UMAXWrr
|
|
2121941U, // UMAXXri
|
|
2121941U, // UMAXXrr
|
|
2179096789U, // UMAX_VG2_2Z2Z_B
|
|
2181210325U, // UMAX_VG2_2Z2Z_D
|
|
2183323861U, // UMAX_VG2_2Z2Z_H
|
|
2185437397U, // UMAX_VG2_2Z2Z_S
|
|
2179096789U, // UMAX_VG2_2ZZ_B
|
|
2181210325U, // UMAX_VG2_2ZZ_D
|
|
2183323861U, // UMAX_VG2_2ZZ_H
|
|
2185437397U, // UMAX_VG2_2ZZ_S
|
|
2179096789U, // UMAX_VG4_4Z4Z_B
|
|
2181210325U, // UMAX_VG4_4Z4Z_D
|
|
2183323861U, // UMAX_VG4_4Z4Z_H
|
|
2185437397U, // UMAX_VG4_4Z4Z_S
|
|
2179096789U, // UMAX_VG4_4ZZ_B
|
|
2181210325U, // UMAX_VG4_4ZZ_D
|
|
2183323861U, // UMAX_VG4_4ZZ_H
|
|
2185437397U, // UMAX_VG4_4ZZ_S
|
|
2138325U, // UMAX_ZI_B
|
|
2418073813U, // UMAX_ZI_D
|
|
2189500629U, // UMAX_ZI_H
|
|
270622933U, // UMAX_ZI_S
|
|
3223363797U, // UMAX_ZPmZ_B
|
|
3223380181U, // UMAX_ZPmZ_D
|
|
3519094997U, // UMAX_ZPmZ_H
|
|
3223412949U, // UMAX_ZPmZ_S
|
|
811704533U, // UMAXv16i8
|
|
813801685U, // UMAXv2i32
|
|
817995989U, // UMAXv4i16
|
|
820093141U, // UMAXv4i32
|
|
822190293U, // UMAXv8i16
|
|
824287445U, // UMAXv8i8
|
|
3223361227U, // UMINP_ZPmZ_B
|
|
3223377611U, // UMINP_ZPmZ_D
|
|
3519092427U, // UMINP_ZPmZ_H
|
|
3223410379U, // UMINP_ZPmZ_S
|
|
811701963U, // UMINPv16i8
|
|
813799115U, // UMINPv2i32
|
|
817993419U, // UMINPv4i16
|
|
820090571U, // UMINPv4i32
|
|
822187723U, // UMINPv8i16
|
|
824284875U, // UMINPv8i8
|
|
3227623212U, // UMINQV_VPZ_B
|
|
3231817516U, // UMINQV_VPZ_D
|
|
3238108972U, // UMINQV_VPZ_H
|
|
3236011820U, // UMINQV_VPZ_S
|
|
253651U, // UMINV_VPZ_B
|
|
1657020115U, // UMINV_VPZ_D
|
|
1659133651U, // UMINV_VPZ_H
|
|
1638178515U, // UMINV_VPZ_S
|
|
807427795U, // UMINVv16i8v
|
|
807427795U, // UMINVv4i16v
|
|
807427795U, // UMINVv4i32v
|
|
807427795U, // UMINVv8i16v
|
|
807427795U, // UMINVv8i8v
|
|
2118954U, // UMINWri
|
|
2118954U, // UMINWrr
|
|
2118954U, // UMINXri
|
|
2118954U, // UMINXrr
|
|
2179093802U, // UMIN_VG2_2Z2Z_B
|
|
2181207338U, // UMIN_VG2_2Z2Z_D
|
|
2183320874U, // UMIN_VG2_2Z2Z_H
|
|
2185434410U, // UMIN_VG2_2Z2Z_S
|
|
2179093802U, // UMIN_VG2_2ZZ_B
|
|
2181207338U, // UMIN_VG2_2ZZ_D
|
|
2183320874U, // UMIN_VG2_2ZZ_H
|
|
2185434410U, // UMIN_VG2_2ZZ_S
|
|
2179093802U, // UMIN_VG4_4Z4Z_B
|
|
2181207338U, // UMIN_VG4_4Z4Z_D
|
|
2183320874U, // UMIN_VG4_4Z4Z_H
|
|
2185434410U, // UMIN_VG4_4Z4Z_S
|
|
2179093802U, // UMIN_VG4_4ZZ_B
|
|
2181207338U, // UMIN_VG4_4ZZ_D
|
|
2183320874U, // UMIN_VG4_4ZZ_H
|
|
2185434410U, // UMIN_VG4_4ZZ_S
|
|
2135338U, // UMIN_ZI_B
|
|
2418070826U, // UMIN_ZI_D
|
|
2189497642U, // UMIN_ZI_H
|
|
270619946U, // UMIN_ZI_S
|
|
3223360810U, // UMIN_ZPmZ_B
|
|
3223377194U, // UMIN_ZPmZ_D
|
|
3519092010U, // UMIN_ZPmZ_H
|
|
3223409962U, // UMIN_ZPmZ_S
|
|
811701546U, // UMINv16i8
|
|
813798698U, // UMINv2i32
|
|
817993002U, // UMINv4i16
|
|
820090154U, // UMINv4i32
|
|
822187306U, // UMINv8i16
|
|
824284458U, // UMINv8i8
|
|
1344325249U, // UMLALB_ZZZI_D
|
|
2686535297U, // UMLALB_ZZZI_S
|
|
1344325249U, // UMLALB_ZZZ_D
|
|
2220951169U, // UMLALB_ZZZ_H
|
|
2686535297U, // UMLALB_ZZZ_S
|
|
1688441552U, // UMLALL_MZZI_BtoS
|
|
1688425168U, // UMLALL_MZZI_HtoD
|
|
1688441552U, // UMLALL_MZZ_BtoS
|
|
1688425168U, // UMLALL_MZZ_HtoD
|
|
3835925200U, // UMLALL_VG2_M2Z2Z_BtoS
|
|
3835908816U, // UMLALL_VG2_M2Z2Z_HtoD
|
|
3835925200U, // UMLALL_VG2_M2ZZI_BtoS
|
|
3835908816U, // UMLALL_VG2_M2ZZI_HtoD
|
|
4104360656U, // UMLALL_VG2_M2ZZ_BtoS
|
|
4104344272U, // UMLALL_VG2_M2ZZ_HtoD
|
|
4104360656U, // UMLALL_VG4_M4Z4Z_BtoS
|
|
4104344272U, // UMLALL_VG4_M4Z4Z_HtoD
|
|
4104360656U, // UMLALL_VG4_M4ZZI_BtoS
|
|
4104344272U, // UMLALL_VG4_M4ZZI_HtoD
|
|
77828816U, // UMLALL_VG4_M4ZZ_BtoS
|
|
77812432U, // UMLALL_VG4_M4ZZ_HtoD
|
|
1344330691U, // UMLALT_ZZZI_D
|
|
2686540739U, // UMLALT_ZZZI_S
|
|
1344330691U, // UMLALT_ZZZ_D
|
|
2220956611U, // UMLALT_ZZZ_H
|
|
2686540739U, // UMLALT_ZZZ_S
|
|
1663275267U, // UMLAL_MZZI_HtoS
|
|
1663275267U, // UMLAL_MZZ_HtoS
|
|
3810758915U, // UMLAL_VG2_M2Z2Z_HtoS
|
|
3810758915U, // UMLAL_VG2_M2ZZI_S
|
|
3810758915U, // UMLAL_VG2_M2ZZ_HtoS
|
|
4079194371U, // UMLAL_VG4_M4Z4Z_HtoS
|
|
4079194371U, // UMLAL_VG4_M4ZZI_HtoS
|
|
4079194371U, // UMLAL_VG4_M4ZZ_HtoS
|
|
2969698566U, // UMLALv16i8_v8i16
|
|
2963411203U, // UMLALv2i32_indexed
|
|
2963411203U, // UMLALv2i32_v2i64
|
|
2967605507U, // UMLALv4i16_indexed
|
|
2967605507U, // UMLALv4i16_v4i32
|
|
2963407110U, // UMLALv4i32_indexed
|
|
2963407110U, // UMLALv4i32_v2i64
|
|
2967601414U, // UMLALv8i16_indexed
|
|
2967601414U, // UMLALv8i16_v4i32
|
|
2969702659U, // UMLALv8i8_v8i16
|
|
1344325547U, // UMLSLB_ZZZI_D
|
|
2686535595U, // UMLSLB_ZZZI_S
|
|
1344325547U, // UMLSLB_ZZZ_D
|
|
2220951467U, // UMLSLB_ZZZ_H
|
|
2686535595U, // UMLSLB_ZZZ_S
|
|
1688441582U, // UMLSLL_MZZI_BtoS
|
|
1688425198U, // UMLSLL_MZZI_HtoD
|
|
1688441582U, // UMLSLL_MZZ_BtoS
|
|
1688425198U, // UMLSLL_MZZ_HtoD
|
|
3835925230U, // UMLSLL_VG2_M2Z2Z_BtoS
|
|
3835908846U, // UMLSLL_VG2_M2Z2Z_HtoD
|
|
3835925230U, // UMLSLL_VG2_M2ZZI_BtoS
|
|
3835908846U, // UMLSLL_VG2_M2ZZI_HtoD
|
|
4104360686U, // UMLSLL_VG2_M2ZZ_BtoS
|
|
4104344302U, // UMLSLL_VG2_M2ZZ_HtoD
|
|
4104360686U, // UMLSLL_VG4_M4Z4Z_BtoS
|
|
4104344302U, // UMLSLL_VG4_M4Z4Z_HtoD
|
|
4104360686U, // UMLSLL_VG4_M4ZZI_BtoS
|
|
4104344302U, // UMLSLL_VG4_M4ZZI_HtoD
|
|
77828846U, // UMLSLL_VG4_M4ZZ_BtoS
|
|
77812462U, // UMLSLL_VG4_M4ZZ_HtoD
|
|
1344330866U, // UMLSLT_ZZZI_D
|
|
2686540914U, // UMLSLT_ZZZI_S
|
|
1344330866U, // UMLSLT_ZZZ_D
|
|
2220956786U, // UMLSLT_ZZZ_H
|
|
2686540914U, // UMLSLT_ZZZ_S
|
|
1663276034U, // UMLSL_MZZI_HtoS
|
|
1663276034U, // UMLSL_MZZ_HtoS
|
|
3810759682U, // UMLSL_VG2_M2Z2Z_HtoS
|
|
3810759682U, // UMLSL_VG2_M2ZZI_S
|
|
3810759682U, // UMLSL_VG2_M2ZZ_HtoS
|
|
4079195138U, // UMLSL_VG4_M4Z4Z_HtoS
|
|
4079195138U, // UMLSL_VG4_M4ZZI_HtoS
|
|
4079195138U, // UMLSL_VG4_M4ZZ_HtoS
|
|
2969698698U, // UMLSLv16i8_v8i16
|
|
2963411970U, // UMLSLv2i32_indexed
|
|
2963411970U, // UMLSLv2i32_v2i64
|
|
2967606274U, // UMLSLv4i16_indexed
|
|
2967606274U, // UMLSLv4i16_v4i32
|
|
2963407242U, // UMLSLv4i32_indexed
|
|
2963407242U, // UMLSLv4i32_v2i64
|
|
2967601546U, // UMLSLv8i16_indexed
|
|
2967601546U, // UMLSLv8i16_v4i32
|
|
2969703426U, // UMLSLv8i8_v8i16
|
|
2967602044U, // UMMLA
|
|
2418099068U, // UMMLA_ZZZ
|
|
54641595U, // UMOPA_MPPZZ_D
|
|
54641595U, // UMOPA_MPPZZ_HtoS
|
|
79807419U, // UMOPA_MPPZZ_S
|
|
54647471U, // UMOPS_MPPZZ_D
|
|
54647471U, // UMOPS_MPPZZ_HtoS
|
|
79813295U, // UMOPS_MPPZZ_S
|
|
807427827U, // UMOVvi16
|
|
807427827U, // UMOVvi16_idx0
|
|
807427827U, // UMOVvi32
|
|
807427827U, // UMOVvi32_idx0
|
|
807427827U, // UMOVvi64
|
|
807427827U, // UMOVvi64_idx0
|
|
807427827U, // UMOVvi8
|
|
807427827U, // UMOVvi8_idx0
|
|
2118174U, // UMSUBLrrr
|
|
3223359216U, // UMULH_ZPmZ_B
|
|
3223375600U, // UMULH_ZPmZ_D
|
|
3519090416U, // UMULH_ZPmZ_H
|
|
3223408368U, // UMULH_ZPmZ_S
|
|
2133744U, // UMULH_ZZZ_B
|
|
2418069232U, // UMULH_ZZZ_D
|
|
2189496048U, // UMULH_ZZZ_H
|
|
270618352U, // UMULH_ZZZ_S
|
|
2117360U, // UMULHrr
|
|
270583636U, // UMULLB_ZZZI_D
|
|
1881229140U, // UMULLB_ZZZI_S
|
|
270583636U, // UMULLB_ZZZ_D
|
|
2197882708U, // UMULLB_ZZZ_H
|
|
1881229140U, // UMULLB_ZZZ_S
|
|
270588993U, // UMULLT_ZZZI_D
|
|
1881234497U, // UMULLT_ZZZI_S
|
|
270588993U, // UMULLT_ZZZ_D
|
|
2197888065U, // UMULLT_ZZZ_H
|
|
1881234497U, // UMULLT_ZZZ_S
|
|
822182248U, // UMULLv16i8_v8i16
|
|
815895309U, // UMULLv2i32_indexed
|
|
815895309U, // UMULLv2i32_v2i64
|
|
820089613U, // UMULLv4i16_indexed
|
|
820089613U, // UMULLv4i16_v4i32
|
|
815890792U, // UMULLv4i32_indexed
|
|
815890792U, // UMULLv4i32_v2i64
|
|
820085096U, // UMULLv8i16_indexed
|
|
820085096U, // UMULLv8i16_v4i32
|
|
822186765U, // UMULLv8i8_v8i16
|
|
2132915U, // UQADD_ZI_B
|
|
2418068403U, // UQADD_ZI_D
|
|
2189495219U, // UQADD_ZI_H
|
|
270617523U, // UQADD_ZI_S
|
|
3223358387U, // UQADD_ZPmZ_B
|
|
3223374771U, // UQADD_ZPmZ_D
|
|
3519089587U, // UQADD_ZPmZ_H
|
|
3223407539U, // UQADD_ZPmZ_S
|
|
2132915U, // UQADD_ZZZ_B
|
|
2418068403U, // UQADD_ZZZ_D
|
|
2189495219U, // UQADD_ZZZ_H
|
|
270617523U, // UQADD_ZZZ_S
|
|
811699123U, // UQADDv16i8
|
|
2116531U, // UQADDv1i16
|
|
2116531U, // UQADDv1i32
|
|
2116531U, // UQADDv1i64
|
|
2116531U, // UQADDv1i8
|
|
813796275U, // UQADDv2i32
|
|
815893427U, // UQADDv2i64
|
|
817990579U, // UQADDv4i16
|
|
820087731U, // UQADDv4i32
|
|
822184883U, // UQADDv8i16
|
|
824282035U, // UQADDv8i8
|
|
1648432512U, // UQCVTN_Z2Z_StoH
|
|
1644238208U, // UQCVTN_Z4Z_DtoH
|
|
3223360896U, // UQCVTN_Z4Z_StoB
|
|
1648434664U, // UQCVT_Z2Z_StoH
|
|
1644240360U, // UQCVT_Z4Z_DtoH
|
|
3223363048U, // UQCVT_Z4Z_StoB
|
|
538985981U, // UQDECB_WPiI
|
|
538985981U, // UQDECB_XPiI
|
|
538987336U, // UQDECD_WPiI
|
|
538987336U, // UQDECD_XPiI
|
|
539020104U, // UQDECD_ZPiI
|
|
538988030U, // UQDECH_WPiI
|
|
538988030U, // UQDECH_XPiI
|
|
56692222U, // UQDECH_ZPiI
|
|
2119189U, // UQDECP_WP_B
|
|
2418038293U, // UQDECP_WP_D
|
|
1881167381U, // UQDECP_WP_H
|
|
270554645U, // UQDECP_WP_S
|
|
2119189U, // UQDECP_XP_B
|
|
2418038293U, // UQDECP_XP_D
|
|
1881167381U, // UQDECP_XP_H
|
|
270554645U, // UQDECP_XP_S
|
|
1075893781U, // UQDECP_ZP_D
|
|
1658918421U, // UQDECP_ZP_H
|
|
1344362005U, // UQDECP_ZP_S
|
|
538992613U, // UQDECW_WPiI
|
|
538992613U, // UQDECW_XPiI
|
|
539058149U, // UQDECW_ZPiI
|
|
538985997U, // UQINCB_WPiI
|
|
538985997U, // UQINCB_XPiI
|
|
538987352U, // UQINCD_WPiI
|
|
538987352U, // UQINCD_XPiI
|
|
539020120U, // UQINCD_ZPiI
|
|
538988046U, // UQINCH_WPiI
|
|
538988046U, // UQINCH_XPiI
|
|
56692238U, // UQINCH_ZPiI
|
|
2119205U, // UQINCP_WP_B
|
|
2418038309U, // UQINCP_WP_D
|
|
1881167397U, // UQINCP_WP_H
|
|
270554661U, // UQINCP_WP_S
|
|
2119205U, // UQINCP_XP_B
|
|
2418038309U, // UQINCP_XP_D
|
|
1881167397U, // UQINCP_XP_H
|
|
270554661U, // UQINCP_XP_S
|
|
1075893797U, // UQINCP_ZP_D
|
|
1658918437U, // UQINCP_ZP_H
|
|
1344362021U, // UQINCP_ZP_S
|
|
538992629U, // UQINCW_WPiI
|
|
538992629U, // UQINCW_XPiI
|
|
539058165U, // UQINCW_ZPiI
|
|
3223361756U, // UQRSHLR_ZPmZ_B
|
|
3223378140U, // UQRSHLR_ZPmZ_D
|
|
3519092956U, // UQRSHLR_ZPmZ_H
|
|
3223410908U, // UQRSHLR_ZPmZ_S
|
|
3223360156U, // UQRSHL_ZPmZ_B
|
|
3223376540U, // UQRSHL_ZPmZ_D
|
|
3519091356U, // UQRSHL_ZPmZ_H
|
|
3223409308U, // UQRSHL_ZPmZ_S
|
|
811700892U, // UQRSHLv16i8
|
|
2118300U, // UQRSHLv1i16
|
|
2118300U, // UQRSHLv1i32
|
|
2118300U, // UQRSHLv1i64
|
|
2118300U, // UQRSHLv1i8
|
|
813798044U, // UQRSHLv2i32
|
|
815895196U, // UQRSHLv2i64
|
|
817992348U, // UQRSHLv4i16
|
|
820089500U, // UQRSHLv4i32
|
|
822186652U, // UQRSHLv8i16
|
|
824283804U, // UQRSHLv8i8
|
|
1881180181U, // UQRSHRNB_ZZI_B
|
|
2172717077U, // UQRSHRNB_ZZI_H
|
|
2418100245U, // UQRSHRNB_ZZI_S
|
|
2686491875U, // UQRSHRNT_ZZI_B
|
|
2174819555U, // UQRSHRNT_ZZI_H
|
|
1075928291U, // UQRSHRNT_ZZI_S
|
|
3223360858U, // UQRSHRN_VG4_Z4ZI_B
|
|
2181109082U, // UQRSHRN_VG4_Z4ZI_H
|
|
2185303386U, // UQRSHRN_Z2ZI_StoH
|
|
2119002U, // UQRSHRNb
|
|
2119002U, // UQRSHRNh
|
|
2119002U, // UQRSHRNs
|
|
2959213020U, // UQRSHRNv16i8_shift
|
|
813798746U, // UQRSHRNv2i32_shift
|
|
817993050U, // UQRSHRNv4i16_shift
|
|
2967601628U, // UQRSHRNv4i32_shift
|
|
2969698780U, // UQRSHRNv8i16_shift
|
|
824284506U, // UQRSHRNv8i8_shift
|
|
2185304196U, // UQRSHR_VG2_Z2ZI_H
|
|
3223361668U, // UQRSHR_VG4_Z4ZI_B
|
|
2181109892U, // UQRSHR_VG4_Z4ZI_H
|
|
3223361739U, // UQSHLR_ZPmZ_B
|
|
3223378123U, // UQSHLR_ZPmZ_D
|
|
3519092939U, // UQSHLR_ZPmZ_H
|
|
3223410891U, // UQSHLR_ZPmZ_S
|
|
3223360141U, // UQSHL_ZPmI_B
|
|
3223376525U, // UQSHL_ZPmI_D
|
|
3519091341U, // UQSHL_ZPmI_H
|
|
3223409293U, // UQSHL_ZPmI_S
|
|
3223360141U, // UQSHL_ZPmZ_B
|
|
3223376525U, // UQSHL_ZPmZ_D
|
|
3519091341U, // UQSHL_ZPmZ_H
|
|
3223409293U, // UQSHL_ZPmZ_S
|
|
2118285U, // UQSHLb
|
|
2118285U, // UQSHLd
|
|
2118285U, // UQSHLh
|
|
2118285U, // UQSHLs
|
|
811700877U, // UQSHLv16i8
|
|
811700877U, // UQSHLv16i8_shift
|
|
2118285U, // UQSHLv1i16
|
|
2118285U, // UQSHLv1i32
|
|
2118285U, // UQSHLv1i64
|
|
2118285U, // UQSHLv1i8
|
|
813798029U, // UQSHLv2i32
|
|
813798029U, // UQSHLv2i32_shift
|
|
815895181U, // UQSHLv2i64
|
|
815895181U, // UQSHLv2i64_shift
|
|
817992333U, // UQSHLv4i16
|
|
817992333U, // UQSHLv4i16_shift
|
|
820089485U, // UQSHLv4i32
|
|
820089485U, // UQSHLv4i32_shift
|
|
822186637U, // UQSHLv8i16
|
|
822186637U, // UQSHLv8i16_shift
|
|
824283789U, // UQSHLv8i8
|
|
824283789U, // UQSHLv8i8_shift
|
|
1881180162U, // UQSHRNB_ZZI_B
|
|
2172717058U, // UQSHRNB_ZZI_H
|
|
2418100226U, // UQSHRNB_ZZI_S
|
|
2686491856U, // UQSHRNT_ZZI_B
|
|
2174819536U, // UQSHRNT_ZZI_H
|
|
1075928272U, // UQSHRNT_ZZI_S
|
|
2118985U, // UQSHRNb
|
|
2118985U, // UQSHRNh
|
|
2118985U, // UQSHRNs
|
|
2959213001U, // UQSHRNv16i8_shift
|
|
813798729U, // UQSHRNv2i32_shift
|
|
817993033U, // UQSHRNv4i16_shift
|
|
2967601609U, // UQSHRNv4i32_shift
|
|
2969698761U, // UQSHRNv8i16_shift
|
|
824284489U, // UQSHRNv8i8_shift
|
|
3223361620U, // UQSUBR_ZPmZ_B
|
|
3223378004U, // UQSUBR_ZPmZ_D
|
|
3519092820U, // UQSUBR_ZPmZ_H
|
|
3223410772U, // UQSUBR_ZPmZ_S
|
|
2132451U, // UQSUB_ZI_B
|
|
2418067939U, // UQSUB_ZI_D
|
|
2189494755U, // UQSUB_ZI_H
|
|
270617059U, // UQSUB_ZI_S
|
|
3223357923U, // UQSUB_ZPmZ_B
|
|
3223374307U, // UQSUB_ZPmZ_D
|
|
3519089123U, // UQSUB_ZPmZ_H
|
|
3223407075U, // UQSUB_ZPmZ_S
|
|
2132451U, // UQSUB_ZZZ_B
|
|
2418067939U, // UQSUB_ZZZ_D
|
|
2189494755U, // UQSUB_ZZZ_H
|
|
270617059U, // UQSUB_ZZZ_S
|
|
811698659U, // UQSUBv16i8
|
|
2116067U, // UQSUBv1i16
|
|
2116067U, // UQSUBv1i32
|
|
2116067U, // UQSUBv1i64
|
|
2116067U, // UQSUBv1i8
|
|
813795811U, // UQSUBv2i32
|
|
815892963U, // UQSUBv2i64
|
|
817990115U, // UQSUBv4i16
|
|
820087267U, // UQSUBv4i32
|
|
822184419U, // UQSUBv8i16
|
|
824281571U, // UQSUBv8i8
|
|
1881180207U, // UQXTNB_ZZ_B
|
|
1635846191U, // UQXTNB_ZZ_H
|
|
2418100271U, // UQXTNB_ZZ_S
|
|
2686491902U, // UQXTNT_ZZ_B
|
|
1637948670U, // UQXTNT_ZZ_H
|
|
1075928318U, // UQXTNT_ZZ_S
|
|
2959213053U, // UQXTNv16i8
|
|
2119055U, // UQXTNv1i16
|
|
2119055U, // UQXTNv1i32
|
|
2119055U, // UQXTNv1i8
|
|
813798799U, // UQXTNv2i32
|
|
817993103U, // UQXTNv4i16
|
|
2967601661U, // UQXTNv4i32
|
|
2969698813U, // UQXTNv8i16
|
|
824284559U, // UQXTNv8i8
|
|
270617702U, // URECPE_ZPmZ_S
|
|
813796454U, // URECPEv2i32
|
|
820087910U, // URECPEv4i32
|
|
3223358341U, // URHADD_ZPmZ_B
|
|
3223374725U, // URHADD_ZPmZ_D
|
|
3519089541U, // URHADD_ZPmZ_H
|
|
3223407493U, // URHADD_ZPmZ_S
|
|
811699077U, // URHADDv16i8
|
|
813796229U, // URHADDv2i32
|
|
817990533U, // URHADDv4i16
|
|
820087685U, // URHADDv4i32
|
|
822184837U, // URHADDv8i16
|
|
824281989U, // URHADDv8i8
|
|
3223361773U, // URSHLR_ZPmZ_B
|
|
3223378157U, // URSHLR_ZPmZ_D
|
|
3519092973U, // URSHLR_ZPmZ_H
|
|
3223410925U, // URSHLR_ZPmZ_S
|
|
2179093163U, // URSHL_VG2_2Z2Z_B
|
|
2181206699U, // URSHL_VG2_2Z2Z_D
|
|
2183320235U, // URSHL_VG2_2Z2Z_H
|
|
2185433771U, // URSHL_VG2_2Z2Z_S
|
|
2179093163U, // URSHL_VG2_2ZZ_B
|
|
2181206699U, // URSHL_VG2_2ZZ_D
|
|
2183320235U, // URSHL_VG2_2ZZ_H
|
|
2185433771U, // URSHL_VG2_2ZZ_S
|
|
2179093163U, // URSHL_VG4_4Z4Z_B
|
|
2181206699U, // URSHL_VG4_4Z4Z_D
|
|
2183320235U, // URSHL_VG4_4Z4Z_H
|
|
2185433771U, // URSHL_VG4_4Z4Z_S
|
|
2179093163U, // URSHL_VG4_4ZZ_B
|
|
2181206699U, // URSHL_VG4_4ZZ_D
|
|
2183320235U, // URSHL_VG4_4ZZ_H
|
|
2185433771U, // URSHL_VG4_4ZZ_S
|
|
3223360171U, // URSHL_ZPmZ_B
|
|
3223376555U, // URSHL_ZPmZ_D
|
|
3519091371U, // URSHL_ZPmZ_H
|
|
3223409323U, // URSHL_ZPmZ_S
|
|
811700907U, // URSHLv16i8
|
|
2118315U, // URSHLv1i64
|
|
813798059U, // URSHLv2i32
|
|
815895211U, // URSHLv2i64
|
|
817992363U, // URSHLv4i16
|
|
820089515U, // URSHLv4i32
|
|
822186667U, // URSHLv8i16
|
|
824283819U, // URSHLv8i8
|
|
3223361683U, // URSHR_ZPmI_B
|
|
3223378067U, // URSHR_ZPmI_D
|
|
3519092883U, // URSHR_ZPmI_H
|
|
3223410835U, // URSHR_ZPmI_S
|
|
2119827U, // URSHRd
|
|
811702419U, // URSHRv16i8_shift
|
|
813799571U, // URSHRv2i32_shift
|
|
815896723U, // URSHRv2i64_shift
|
|
817993875U, // URSHRv4i16_shift
|
|
820091027U, // URSHRv4i32_shift
|
|
822188179U, // URSHRv8i16_shift
|
|
824285331U, // URSHRv8i8_shift
|
|
270617748U, // URSQRTE_ZPmZ_S
|
|
813796500U, // URSQRTEv2i32
|
|
820087956U, // URSQRTEv4i32
|
|
2418050156U, // URSRA_ZZI_B
|
|
1075889260U, // URSRA_ZZI_D
|
|
2195784812U, // URSRA_ZZI_H
|
|
1344357484U, // URSRA_ZZI_S
|
|
807715948U, // URSRAd
|
|
2959213676U, // URSRAv16i8_shift
|
|
2961310828U, // URSRAv2i32_shift
|
|
2963407980U, // URSRAv2i64_shift
|
|
2965505132U, // URSRAv4i16_shift
|
|
2967602284U, // URSRAv4i32_shift
|
|
2969699436U, // URSRAv8i16_shift
|
|
2971796588U, // URSRAv8i8_shift
|
|
3798179130U, // USDOT_VG2_M2Z2Z_BToS
|
|
3798179130U, // USDOT_VG2_M2ZZI_BToS
|
|
3798179130U, // USDOT_VG2_M2ZZ_BToS
|
|
4066614586U, // USDOT_VG4_M4Z4Z_BToS
|
|
4066614586U, // USDOT_VG4_M4ZZI_BToS
|
|
4066614586U, // USDOT_VG4_M4ZZ_BToS
|
|
2418105658U, // USDOT_ZZZ
|
|
2418105658U, // USDOT_ZZZI
|
|
2967608634U, // USDOTlanev16i8
|
|
2961317178U, // USDOTlanev8i8
|
|
2967608634U, // USDOTv16i8
|
|
2961317178U, // USDOTv8i8
|
|
270583602U, // USHLLB_ZZI_D
|
|
2197882674U, // USHLLB_ZZI_H
|
|
1881229106U, // USHLLB_ZZI_S
|
|
270588959U, // USHLLT_ZZI_D
|
|
2197888031U, // USHLLT_ZZI_H
|
|
1881234463U, // USHLLT_ZZI_S
|
|
822182214U, // USHLLv16i8_shift
|
|
815895263U, // USHLLv2i32_shift
|
|
820089567U, // USHLLv4i16_shift
|
|
815890758U, // USHLLv4i32_shift
|
|
820085062U, // USHLLv8i16_shift
|
|
822186719U, // USHLLv8i8_shift
|
|
811700920U, // USHLv16i8
|
|
2118328U, // USHLv1i64
|
|
813798072U, // USHLv2i32
|
|
815895224U, // USHLv2i64
|
|
817992376U, // USHLv4i16
|
|
820089528U, // USHLv4i32
|
|
822186680U, // USHLv8i16
|
|
824283832U, // USHLv8i8
|
|
2119840U, // USHRd
|
|
811702432U, // USHRv16i8_shift
|
|
813799584U, // USHRv2i32_shift
|
|
815896736U, // USHRv2i64_shift
|
|
817993888U, // USHRv4i16_shift
|
|
820091040U, // USHRv4i32_shift
|
|
822188192U, // USHRv8i16_shift
|
|
824285344U, // USHRv8i8_shift
|
|
1688441542U, // USMLALL_MZZI_BtoS
|
|
1688441542U, // USMLALL_MZZ_BtoS
|
|
3835925190U, // USMLALL_VG2_M2Z2Z_BtoS
|
|
3835925190U, // USMLALL_VG2_M2ZZI_BtoS
|
|
4104360646U, // USMLALL_VG2_M2ZZ_BtoS
|
|
4104360646U, // USMLALL_VG4_M4Z4Z_BtoS
|
|
4104360646U, // USMLALL_VG4_M4ZZI_BtoS
|
|
77828806U, // USMLALL_VG4_M4ZZ_BtoS
|
|
2967602036U, // USMMLA
|
|
2418099060U, // USMMLA_ZZZ
|
|
54641586U, // USMOPA_MPPZZ_D
|
|
79807410U, // USMOPA_MPPZZ_S
|
|
54647462U, // USMOPS_MPPZZ_D
|
|
79813286U, // USMOPS_MPPZZ_S
|
|
3223358378U, // USQADD_ZPmZ_B
|
|
3223374762U, // USQADD_ZPmZ_D
|
|
3519089578U, // USQADD_ZPmZ_H
|
|
3223407530U, // USQADD_ZPmZ_S
|
|
2959215530U, // USQADDv16i8
|
|
807717802U, // USQADDv1i16
|
|
807717802U, // USQADDv1i32
|
|
807717802U, // USQADDv1i64
|
|
807717802U, // USQADDv1i8
|
|
2961312682U, // USQADDv2i32
|
|
2963409834U, // USQADDv2i64
|
|
2965506986U, // USQADDv4i16
|
|
2967604138U, // USQADDv4i32
|
|
2969701290U, // USQADDv8i16
|
|
2971798442U, // USQADDv8i8
|
|
2418050169U, // USRA_ZZI_B
|
|
1075889273U, // USRA_ZZI_D
|
|
2195784825U, // USRA_ZZI_H
|
|
1344357497U, // USRA_ZZI_S
|
|
807715961U, // USRAd
|
|
2959213689U, // USRAv16i8_shift
|
|
2961310841U, // USRAv2i32_shift
|
|
2963407993U, // USRAv2i64_shift
|
|
2965505145U, // USRAv4i16_shift
|
|
2967602297U, // USRAv4i32_shift
|
|
2969699449U, // USRAv8i16_shift
|
|
2971796601U, // USRAv8i8_shift
|
|
270583531U, // USUBLB_ZZZ_D
|
|
2197882603U, // USUBLB_ZZZ_H
|
|
1881229035U, // USUBLB_ZZZ_S
|
|
270588883U, // USUBLT_ZZZ_D
|
|
2197887955U, // USUBLT_ZZZ_H
|
|
1881234387U, // USUBLT_ZZZ_S
|
|
822182166U, // USUBLv16i8_v8i16
|
|
815895085U, // USUBLv2i32_v2i64
|
|
820089389U, // USUBLv4i16_v4i32
|
|
815890710U, // USUBLv4i32_v2i64
|
|
820085014U, // USUBLv8i16_v4i32
|
|
822186541U, // USUBLv8i8_v8i16
|
|
2418067960U, // USUBWB_ZZZ_D
|
|
2189494776U, // USUBWB_ZZZ_H
|
|
270617080U, // USUBWB_ZZZ_S
|
|
2418073085U, // USUBWT_ZZZ_D
|
|
2189499901U, // USUBWT_ZZZ_H
|
|
270622205U, // USUBWT_ZZZ_S
|
|
822182498U, // USUBWv16i8_v8i16
|
|
815898573U, // USUBWv2i32_v2i64
|
|
820092877U, // USUBWv4i16_v4i32
|
|
815891042U, // USUBWv4i32_v2i64
|
|
820085346U, // USUBWv8i16_v4i32
|
|
822190029U, // USUBWv8i8_v8i16
|
|
4066614608U, // USVDOT_VG4_M4ZZI_BToS
|
|
270585974U, // UUNPKHI_ZZ_D
|
|
1661014134U, // UUNPKHI_ZZ_H
|
|
1881231478U, // UUNPKHI_ZZ_S
|
|
270587363U, // UUNPKLO_ZZ_D
|
|
1661015523U, // UUNPKLO_ZZ_H
|
|
1881232867U, // UUNPKLO_ZZ_S
|
|
1635946690U, // UUNPK_VG2_2ZZ_D
|
|
1661128898U, // UUNPK_VG2_2ZZ_H
|
|
1652756674U, // UUNPK_VG2_2ZZ_S
|
|
1648529602U, // UUNPK_VG4_4Z2Z_D
|
|
1642254530U, // UUNPK_VG4_4Z2Z_H
|
|
1646465218U, // UUNPK_VG4_4Z2Z_S
|
|
3798179161U, // UVDOT_VG2_M2ZZI_HtoS
|
|
4066614617U, // UVDOT_VG4_M4ZZI_BtoS
|
|
4066598233U, // UVDOT_VG4_M4ZZI_HtoD
|
|
270584242U, // UXTB_ZPmZ_D
|
|
541133234U, // UXTB_ZPmZ_H
|
|
270617010U, // UXTB_ZPmZ_S
|
|
270585910U, // UXTH_ZPmZ_D
|
|
270618678U, // UXTH_ZPmZ_S
|
|
270590095U, // UXTW_ZPmZ_D
|
|
2129991U, // UZP1_PPP_B
|
|
2418065479U, // UZP1_PPP_D
|
|
2189492295U, // UZP1_PPP_H
|
|
270614599U, // UZP1_PPP_S
|
|
2129991U, // UZP1_ZZZ_B
|
|
2418065479U, // UZP1_ZZZ_D
|
|
2189492295U, // UZP1_ZZZ_H
|
|
2210873415U, // UZP1_ZZZ_Q
|
|
270614599U, // UZP1_ZZZ_S
|
|
811696199U, // UZP1v16i8
|
|
813793351U, // UZP1v2i32
|
|
815890503U, // UZP1v2i64
|
|
817987655U, // UZP1v4i16
|
|
820084807U, // UZP1v4i32
|
|
822181959U, // UZP1v8i16
|
|
824279111U, // UZP1v8i8
|
|
2130482U, // UZP2_PPP_B
|
|
2418065970U, // UZP2_PPP_D
|
|
2189492786U, // UZP2_PPP_H
|
|
270615090U, // UZP2_PPP_S
|
|
2130482U, // UZP2_ZZZ_B
|
|
2418065970U, // UZP2_ZZZ_D
|
|
2189492786U, // UZP2_ZZZ_H
|
|
2210873906U, // UZP2_ZZZ_Q
|
|
270615090U, // UZP2_ZZZ_S
|
|
811696690U, // UZP2v16i8
|
|
813793842U, // UZP2v2i32
|
|
815890994U, // UZP2v2i64
|
|
817988146U, // UZP2v4i16
|
|
820085298U, // UZP2v4i32
|
|
822182450U, // UZP2v8i16
|
|
824279602U, // UZP2v8i8
|
|
2130004U, // UZPQ1_ZZZ_B
|
|
2418065492U, // UZPQ1_ZZZ_D
|
|
2189492308U, // UZPQ1_ZZZ_H
|
|
270614612U, // UZPQ1_ZZZ_S
|
|
2130495U, // UZPQ2_ZZZ_B
|
|
2418065983U, // UZPQ2_ZZZ_D
|
|
2189492799U, // UZPQ2_ZZZ_H
|
|
270615103U, // UZPQ2_ZZZ_S
|
|
2197968807U, // UZP_VG2_2ZZZ_B
|
|
165844903U, // UZP_VG2_2ZZZ_D
|
|
2189612967U, // UZP_VG2_2ZZZ_H
|
|
2210895783U, // UZP_VG2_2ZZZ_Q
|
|
2172852135U, // UZP_VG2_2ZZZ_S
|
|
1642223527U, // UZP_VG4_4Z4Z_B
|
|
1644337063U, // UZP_VG4_4Z4Z_D
|
|
1646450599U, // UZP_VG4_4Z4Z_H
|
|
178755495U, // UZP_VG4_4Z4Z_Q
|
|
1648564135U, // UZP_VG4_4Z4Z_S
|
|
22079U, // VECFP
|
|
23729U, // VECINT
|
|
23364U, // WFET
|
|
23442U, // WFIT
|
|
2208451601U, // WHILEGE_2PXX_B
|
|
2208467985U, // WHILEGE_2PXX_D
|
|
2208484369U, // WHILEGE_2PXX_H
|
|
2208500753U, // WHILEGE_2PXX_S
|
|
3247121U, // WHILEGE_CXX_B
|
|
3263505U, // WHILEGE_CXX_D
|
|
3279889U, // WHILEGE_CXX_H
|
|
3296273U, // WHILEGE_CXX_S
|
|
2133009U, // WHILEGE_PWW_B
|
|
2149393U, // WHILEGE_PWW_D
|
|
2208369681U, // WHILEGE_PWW_H
|
|
2182161U, // WHILEGE_PWW_S
|
|
2133009U, // WHILEGE_PXX_B
|
|
2149393U, // WHILEGE_PXX_D
|
|
2208369681U, // WHILEGE_PXX_H
|
|
2182161U, // WHILEGE_PXX_S
|
|
2208455534U, // WHILEGT_2PXX_B
|
|
2208471918U, // WHILEGT_2PXX_D
|
|
2208488302U, // WHILEGT_2PXX_H
|
|
2208504686U, // WHILEGT_2PXX_S
|
|
3251054U, // WHILEGT_CXX_B
|
|
3267438U, // WHILEGT_CXX_D
|
|
3283822U, // WHILEGT_CXX_H
|
|
3300206U, // WHILEGT_CXX_S
|
|
2136942U, // WHILEGT_PWW_B
|
|
2153326U, // WHILEGT_PWW_D
|
|
2208373614U, // WHILEGT_PWW_H
|
|
2186094U, // WHILEGT_PWW_S
|
|
2136942U, // WHILEGT_PXX_B
|
|
2153326U, // WHILEGT_PXX_D
|
|
2208373614U, // WHILEGT_PXX_H
|
|
2186094U, // WHILEGT_PXX_S
|
|
2208452699U, // WHILEHI_2PXX_B
|
|
2208469083U, // WHILEHI_2PXX_D
|
|
2208485467U, // WHILEHI_2PXX_H
|
|
2208501851U, // WHILEHI_2PXX_S
|
|
3248219U, // WHILEHI_CXX_B
|
|
3264603U, // WHILEHI_CXX_D
|
|
3280987U, // WHILEHI_CXX_H
|
|
3297371U, // WHILEHI_CXX_S
|
|
2134107U, // WHILEHI_PWW_B
|
|
2150491U, // WHILEHI_PWW_D
|
|
2208370779U, // WHILEHI_PWW_H
|
|
2183259U, // WHILEHI_PWW_S
|
|
2134107U, // WHILEHI_PXX_B
|
|
2150491U, // WHILEHI_PXX_D
|
|
2208370779U, // WHILEHI_PXX_H
|
|
2183259U, // WHILEHI_PXX_S
|
|
2208455213U, // WHILEHS_2PXX_B
|
|
2208471597U, // WHILEHS_2PXX_D
|
|
2208487981U, // WHILEHS_2PXX_H
|
|
2208504365U, // WHILEHS_2PXX_S
|
|
3250733U, // WHILEHS_CXX_B
|
|
3267117U, // WHILEHS_CXX_D
|
|
3283501U, // WHILEHS_CXX_H
|
|
3299885U, // WHILEHS_CXX_S
|
|
2136621U, // WHILEHS_PWW_B
|
|
2153005U, // WHILEHS_PWW_D
|
|
2208373293U, // WHILEHS_PWW_H
|
|
2185773U, // WHILEHS_PWW_S
|
|
2136621U, // WHILEHS_PXX_B
|
|
2153005U, // WHILEHS_PXX_D
|
|
2208373293U, // WHILEHS_PXX_H
|
|
2185773U, // WHILEHS_PXX_S
|
|
2208451632U, // WHILELE_2PXX_B
|
|
2208468016U, // WHILELE_2PXX_D
|
|
2208484400U, // WHILELE_2PXX_H
|
|
2208500784U, // WHILELE_2PXX_S
|
|
3247152U, // WHILELE_CXX_B
|
|
3263536U, // WHILELE_CXX_D
|
|
3279920U, // WHILELE_CXX_H
|
|
3296304U, // WHILELE_CXX_S
|
|
2133040U, // WHILELE_PWW_B
|
|
2149424U, // WHILELE_PWW_D
|
|
2208369712U, // WHILELE_PWW_H
|
|
2182192U, // WHILELE_PWW_S
|
|
2133040U, // WHILELE_PXX_B
|
|
2149424U, // WHILELE_PXX_D
|
|
2208369712U, // WHILELE_PXX_H
|
|
2182192U, // WHILELE_PXX_S
|
|
2208454088U, // WHILELO_2PXX_B
|
|
2208470472U, // WHILELO_2PXX_D
|
|
2208486856U, // WHILELO_2PXX_H
|
|
2208503240U, // WHILELO_2PXX_S
|
|
3249608U, // WHILELO_CXX_B
|
|
3265992U, // WHILELO_CXX_D
|
|
3282376U, // WHILELO_CXX_H
|
|
3298760U, // WHILELO_CXX_S
|
|
2135496U, // WHILELO_PWW_B
|
|
2151880U, // WHILELO_PWW_D
|
|
2208372168U, // WHILELO_PWW_H
|
|
2184648U, // WHILELO_PWW_S
|
|
2135496U, // WHILELO_PXX_B
|
|
2151880U, // WHILELO_PXX_D
|
|
2208372168U, // WHILELO_PXX_H
|
|
2184648U, // WHILELO_PXX_S
|
|
2208455240U, // WHILELS_2PXX_B
|
|
2208471624U, // WHILELS_2PXX_D
|
|
2208488008U, // WHILELS_2PXX_H
|
|
2208504392U, // WHILELS_2PXX_S
|
|
3250760U, // WHILELS_CXX_B
|
|
3267144U, // WHILELS_CXX_D
|
|
3283528U, // WHILELS_CXX_H
|
|
3299912U, // WHILELS_CXX_S
|
|
2136648U, // WHILELS_PWW_B
|
|
2153032U, // WHILELS_PWW_D
|
|
2208373320U, // WHILELS_PWW_H
|
|
2185800U, // WHILELS_PWW_S
|
|
2136648U, // WHILELS_PXX_B
|
|
2153032U, // WHILELS_PXX_D
|
|
2208373320U, // WHILELS_PXX_H
|
|
2185800U, // WHILELS_PXX_S
|
|
2208455689U, // WHILELT_2PXX_B
|
|
2208472073U, // WHILELT_2PXX_D
|
|
2208488457U, // WHILELT_2PXX_H
|
|
2208504841U, // WHILELT_2PXX_S
|
|
3251209U, // WHILELT_CXX_B
|
|
3267593U, // WHILELT_CXX_D
|
|
3283977U, // WHILELT_CXX_H
|
|
3300361U, // WHILELT_CXX_S
|
|
2137097U, // WHILELT_PWW_B
|
|
2153481U, // WHILELT_PWW_D
|
|
2208373769U, // WHILELT_PWW_H
|
|
2186249U, // WHILELT_PWW_S
|
|
2137097U, // WHILELT_PXX_B
|
|
2153481U, // WHILELT_PXX_D
|
|
2208373769U, // WHILELT_PXX_H
|
|
2186249U, // WHILELT_PXX_S
|
|
2138152U, // WHILERW_PXX_B
|
|
2154536U, // WHILERW_PXX_D
|
|
2208374824U, // WHILERW_PXX_H
|
|
2187304U, // WHILERW_PXX_S
|
|
2136473U, // WHILEWR_PXX_B
|
|
2152857U, // WHILEWR_PXX_D
|
|
2208373145U, // WHILEWR_PXX_H
|
|
2185625U, // WHILEWR_PXX_S
|
|
807717464U, // WKDMC
|
|
807717824U, // WKDMD
|
|
39029U, // WRFFR
|
|
10339U, // XAFLAG
|
|
815896624U, // XAR
|
|
2136112U, // XAR_ZZZI_B
|
|
2418071600U, // XAR_ZZZI_D
|
|
2189498416U, // XAR_ZZZI_H
|
|
270620720U, // XAR_ZZZI_S
|
|
19257U, // XPACD
|
|
20564U, // XPACI
|
|
8957U, // XPACLRI
|
|
2959213047U, // XTNv16i8
|
|
813798794U, // XTNv2i32
|
|
817993098U, // XTNv4i16
|
|
2967601655U, // XTNv4i32
|
|
2969698807U, // XTNv8i16
|
|
824284554U, // XTNv8i8
|
|
1283571U, // ZERO_M
|
|
3005437427U, // ZERO_MXI_2Z
|
|
3030603251U, // ZERO_MXI_4Z
|
|
3810743795U, // ZERO_MXI_VG2_2Z
|
|
3835909619U, // ZERO_MXI_VG2_4Z
|
|
3798160883U, // ZERO_MXI_VG2_Z
|
|
4079179251U, // ZERO_MXI_VG4_2Z
|
|
4104345075U, // ZERO_MXI_VG4_4Z
|
|
4066596339U, // ZERO_MXI_VG4_Z
|
|
180380121U, // ZERO_T
|
|
2129985U, // ZIP1_PPP_B
|
|
2418065473U, // ZIP1_PPP_D
|
|
2189492289U, // ZIP1_PPP_H
|
|
270614593U, // ZIP1_PPP_S
|
|
2129985U, // ZIP1_ZZZ_B
|
|
2418065473U, // ZIP1_ZZZ_D
|
|
2189492289U, // ZIP1_ZZZ_H
|
|
2210873409U, // ZIP1_ZZZ_Q
|
|
270614593U, // ZIP1_ZZZ_S
|
|
811696193U, // ZIP1v16i8
|
|
813793345U, // ZIP1v2i32
|
|
815890497U, // ZIP1v2i64
|
|
817987649U, // ZIP1v4i16
|
|
820084801U, // ZIP1v4i32
|
|
822181953U, // ZIP1v8i16
|
|
824279105U, // ZIP1v8i8
|
|
2130476U, // ZIP2_PPP_B
|
|
2418065964U, // ZIP2_PPP_D
|
|
2189492780U, // ZIP2_PPP_H
|
|
270615084U, // ZIP2_PPP_S
|
|
2130476U, // ZIP2_ZZZ_B
|
|
2418065964U, // ZIP2_ZZZ_D
|
|
2189492780U, // ZIP2_ZZZ_H
|
|
2210873900U, // ZIP2_ZZZ_Q
|
|
270615084U, // ZIP2_ZZZ_S
|
|
811696684U, // ZIP2v16i8
|
|
813793836U, // ZIP2v2i32
|
|
815890988U, // ZIP2v2i64
|
|
817988140U, // ZIP2v4i16
|
|
820085292U, // ZIP2v4i32
|
|
822182444U, // ZIP2v8i16
|
|
824279596U, // ZIP2v8i8
|
|
2129997U, // ZIPQ1_ZZZ_B
|
|
2418065485U, // ZIPQ1_ZZZ_D
|
|
2189492301U, // ZIPQ1_ZZZ_H
|
|
270614605U, // ZIPQ1_ZZZ_S
|
|
2130488U, // ZIPQ2_ZZZ_B
|
|
2418065976U, // ZIPQ2_ZZZ_D
|
|
2189492792U, // ZIPQ2_ZZZ_H
|
|
270615096U, // ZIPQ2_ZZZ_S
|
|
2197968467U, // ZIP_VG2_2ZZZ_B
|
|
165844563U, // ZIP_VG2_2ZZZ_D
|
|
2189612627U, // ZIP_VG2_2ZZZ_H
|
|
2210895443U, // ZIP_VG2_2ZZZ_Q
|
|
2172851795U, // ZIP_VG2_2ZZZ_S
|
|
1642223187U, // ZIP_VG4_4Z4Z_B
|
|
1644336723U, // ZIP_VG4_4Z4Z_D
|
|
1646450259U, // ZIP_VG4_4Z4Z_H
|
|
178755155U, // ZIP_VG4_4Z4Z_Q
|
|
1648563795U, // ZIP_VG4_4Z4Z_S
|
|
};
|
|
|
|
static const uint32_t OpInfo1[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_VALUE_LIST
|
|
0U, // DBG_INSTR_REF
|
|
0U, // DBG_PHI
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ABS_ZPmZ_B_UNDEF
|
|
0U, // ABS_ZPmZ_D_UNDEF
|
|
0U, // ABS_ZPmZ_H_UNDEF
|
|
0U, // ABS_ZPmZ_S_UNDEF
|
|
0U, // ADDHA_MPPZ_D_PSEUDO_D
|
|
0U, // ADDHA_MPPZ_S_PSEUDO_S
|
|
0U, // ADDSWrr
|
|
0U, // ADDSXrr
|
|
0U, // ADDVA_MPPZ_D_PSEUDO_D
|
|
0U, // ADDVA_MPPZ_S_PSEUDO_S
|
|
0U, // ADDWrr
|
|
0U, // ADDXrr
|
|
0U, // ADD_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // ADD_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // ADD_VG2_M2ZZ_D_PSEUDO
|
|
0U, // ADD_VG2_M2ZZ_S_PSEUDO
|
|
0U, // ADD_VG2_M2Z_D_PSEUDO
|
|
0U, // ADD_VG2_M2Z_S_PSEUDO
|
|
0U, // ADD_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // ADD_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // ADD_VG4_M4ZZ_D_PSEUDO
|
|
0U, // ADD_VG4_M4ZZ_S_PSEUDO
|
|
0U, // ADD_VG4_M4Z_D_PSEUDO
|
|
0U, // ADD_VG4_M4Z_S_PSEUDO
|
|
0U, // ADD_ZPZZ_B_ZERO
|
|
0U, // ADD_ZPZZ_D_ZERO
|
|
0U, // ADD_ZPZZ_H_ZERO
|
|
0U, // ADD_ZPZZ_S_ZERO
|
|
0U, // ADDlowTLS
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // AESIMCrrTied
|
|
0U, // AESMCrrTied
|
|
0U, // ANDSWrr
|
|
0U, // ANDSXrr
|
|
0U, // ANDWrr
|
|
0U, // ANDXrr
|
|
0U, // AND_ZPZZ_B_ZERO
|
|
0U, // AND_ZPZZ_D_ZERO
|
|
0U, // AND_ZPZZ_H_ZERO
|
|
0U, // AND_ZPZZ_S_ZERO
|
|
0U, // ASRD_ZPZI_B_ZERO
|
|
0U, // ASRD_ZPZI_D_ZERO
|
|
0U, // ASRD_ZPZI_H_ZERO
|
|
0U, // ASRD_ZPZI_S_ZERO
|
|
0U, // ASR_ZPZI_B_UNDEF
|
|
0U, // ASR_ZPZI_B_ZERO
|
|
0U, // ASR_ZPZI_D_UNDEF
|
|
0U, // ASR_ZPZI_D_ZERO
|
|
0U, // ASR_ZPZI_H_UNDEF
|
|
0U, // ASR_ZPZI_H_ZERO
|
|
0U, // ASR_ZPZI_S_UNDEF
|
|
0U, // ASR_ZPZI_S_ZERO
|
|
0U, // ASR_ZPZZ_B_UNDEF
|
|
0U, // ASR_ZPZZ_B_ZERO
|
|
0U, // ASR_ZPZZ_D_UNDEF
|
|
0U, // ASR_ZPZZ_D_ZERO
|
|
0U, // ASR_ZPZZ_H_UNDEF
|
|
0U, // ASR_ZPZZ_H_ZERO
|
|
0U, // ASR_ZPZZ_S_UNDEF
|
|
0U, // ASR_ZPZZ_S_ZERO
|
|
0U, // BFADD_VG2_M2Z_H_PSEUDO
|
|
0U, // BFADD_VG4_M4Z_H_PSEUDO
|
|
0U, // BFADD_ZPZZ_UNDEF
|
|
0U, // BFADD_ZPZZ_ZERO
|
|
0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BFDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // BFDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // BFMAXNM_ZPZZ_UNDEF
|
|
0U, // BFMAXNM_ZPZZ_ZERO
|
|
0U, // BFMAX_ZPZZ_UNDEF
|
|
0U, // BFMAX_ZPZZ_ZERO
|
|
0U, // BFMINNM_ZPZZ_UNDEF
|
|
0U, // BFMINNM_ZPZZ_ZERO
|
|
0U, // BFMIN_ZPZZ_UNDEF
|
|
0U, // BFMIN_ZPZZ_ZERO
|
|
0U, // BFMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // BFMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // BFMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // BFMLA_VG2_M2Z2Z_PSEUDO
|
|
0U, // BFMLA_VG4_M4Z4Z_PSEUDO
|
|
0U, // BFMLA_ZPZZZ_UNDEF
|
|
0U, // BFMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // BFMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // BFMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // BFMLS_VG2_M2Z2Z_PSEUDO
|
|
0U, // BFMLS_VG4_M4Z4Z_PSEUDO
|
|
0U, // BFMLS_ZPZZZ_UNDEF
|
|
0U, // BFMOPA_MPPZZ_PSEUDO
|
|
0U, // BFMOPS_MPPZZ_PSEUDO
|
|
0U, // BFMUL_ZPZZ_UNDEF
|
|
0U, // BFMUL_ZPZZ_ZERO
|
|
0U, // BFSUB_VG2_M2Z_H_PSEUDO
|
|
0U, // BFSUB_VG4_M4Z_H_PSEUDO
|
|
0U, // BFSUB_ZPZZ_UNDEF
|
|
0U, // BFSUB_ZPZZ_ZERO
|
|
0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // BICSWrr
|
|
0U, // BICSXrr
|
|
0U, // BICWrr
|
|
0U, // BICXrr
|
|
0U, // BIC_ZPZZ_B_ZERO
|
|
0U, // BIC_ZPZZ_D_ZERO
|
|
0U, // BIC_ZPZZ_H_ZERO
|
|
0U, // BIC_ZPZZ_S_ZERO
|
|
0U, // BLRNoIP
|
|
0U, // BLR_BTI
|
|
0U, // BLR_RVMARKER
|
|
0U, // BLR_X16
|
|
0U, // BMOPA_MPPZZ_S_PSEUDO
|
|
0U, // BMOPS_MPPZZ_S_PSEUDO
|
|
0U, // BSPv16i8
|
|
0U, // BSPv8i8
|
|
0U, // CATCHRET
|
|
0U, // CLEANUPRET
|
|
0U, // CLS_ZPmZ_B_UNDEF
|
|
0U, // CLS_ZPmZ_D_UNDEF
|
|
0U, // CLS_ZPmZ_H_UNDEF
|
|
0U, // CLS_ZPmZ_S_UNDEF
|
|
0U, // CLZ_ZPmZ_B_UNDEF
|
|
0U, // CLZ_ZPmZ_D_UNDEF
|
|
0U, // CLZ_ZPmZ_H_UNDEF
|
|
0U, // CLZ_ZPmZ_S_UNDEF
|
|
0U, // CMP_SWAP_128
|
|
0U, // CMP_SWAP_128_ACQUIRE
|
|
0U, // CMP_SWAP_128_MONOTONIC
|
|
0U, // CMP_SWAP_128_RELEASE
|
|
0U, // CMP_SWAP_16
|
|
0U, // CMP_SWAP_32
|
|
0U, // CMP_SWAP_64
|
|
0U, // CMP_SWAP_8
|
|
0U, // CNOT_ZPmZ_B_UNDEF
|
|
0U, // CNOT_ZPmZ_D_UNDEF
|
|
0U, // CNOT_ZPmZ_H_UNDEF
|
|
0U, // CNOT_ZPmZ_S_UNDEF
|
|
0U, // CNT_ZPmZ_B_UNDEF
|
|
0U, // CNT_ZPmZ_D_UNDEF
|
|
0U, // CNT_ZPmZ_H_UNDEF
|
|
0U, // CNT_ZPmZ_S_UNDEF
|
|
0U, // COALESCER_BARRIER_FPR128
|
|
0U, // COALESCER_BARRIER_FPR16
|
|
0U, // COALESCER_BARRIER_FPR32
|
|
0U, // COALESCER_BARRIER_FPR64
|
|
0U, // EMITBKEY
|
|
0U, // EMITMTETAGGED
|
|
0U, // EONWrr
|
|
0U, // EONXrr
|
|
0U, // EORWrr
|
|
0U, // EORXrr
|
|
0U, // EOR_ZPZZ_B_ZERO
|
|
0U, // EOR_ZPZZ_D_ZERO
|
|
0U, // EOR_ZPZZ_H_ZERO
|
|
0U, // EOR_ZPZZ_S_ZERO
|
|
0U, // F128CSEL
|
|
0U, // FABD_ZPZZ_D_UNDEF
|
|
0U, // FABD_ZPZZ_D_ZERO
|
|
0U, // FABD_ZPZZ_H_UNDEF
|
|
0U, // FABD_ZPZZ_H_ZERO
|
|
0U, // FABD_ZPZZ_S_UNDEF
|
|
0U, // FABD_ZPZZ_S_ZERO
|
|
0U, // FABS_ZPmZ_D_UNDEF
|
|
0U, // FABS_ZPmZ_H_UNDEF
|
|
0U, // FABS_ZPmZ_S_UNDEF
|
|
0U, // FADD_VG2_M2Z_D_PSEUDO
|
|
0U, // FADD_VG2_M2Z_H_PSEUDO
|
|
0U, // FADD_VG2_M2Z_S_PSEUDO
|
|
0U, // FADD_VG4_M4Z_D_PSEUDO
|
|
0U, // FADD_VG4_M4Z_H_PSEUDO
|
|
0U, // FADD_VG4_M4Z_S_PSEUDO
|
|
0U, // FADD_ZPZI_D_UNDEF
|
|
0U, // FADD_ZPZI_D_ZERO
|
|
0U, // FADD_ZPZI_H_UNDEF
|
|
0U, // FADD_ZPZI_H_ZERO
|
|
0U, // FADD_ZPZI_S_UNDEF
|
|
0U, // FADD_ZPZI_S_ZERO
|
|
0U, // FADD_ZPZZ_D_UNDEF
|
|
0U, // FADD_ZPZZ_D_ZERO
|
|
0U, // FADD_ZPZZ_H_UNDEF
|
|
0U, // FADD_ZPZZ_H_ZERO
|
|
0U, // FADD_ZPZZ_S_UNDEF
|
|
0U, // FADD_ZPZZ_S_ZERO
|
|
0U, // FCVTZS_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoS_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoH_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_StoD_UNDEF
|
|
0U, // FCVT_ZPmZ_StoH_UNDEF
|
|
0U, // FDIVR_ZPZZ_D_ZERO
|
|
0U, // FDIVR_ZPZZ_H_ZERO
|
|
0U, // FDIVR_ZPZZ_S_ZERO
|
|
0U, // FDIV_ZPZZ_D_UNDEF
|
|
0U, // FDIV_ZPZZ_D_ZERO
|
|
0U, // FDIV_ZPZZ_H_UNDEF
|
|
0U, // FDIV_ZPZZ_H_ZERO
|
|
0U, // FDIV_ZPZZ_S_UNDEF
|
|
0U, // FDIV_ZPZZ_S_ZERO
|
|
0U, // FDOT_VG2_M2Z2Z_BtoH_PSEUDO
|
|
0U, // FDOT_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // FDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4Z4Z_BtoH_PSEUDO
|
|
0U, // FDOT_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // FDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // FLOGB_ZPZZ_D_ZERO
|
|
0U, // FLOGB_ZPZZ_H_ZERO
|
|
0U, // FLOGB_ZPZZ_S_ZERO
|
|
0U, // FMAXNM_ZPZI_D_UNDEF
|
|
0U, // FMAXNM_ZPZI_D_ZERO
|
|
0U, // FMAXNM_ZPZI_H_UNDEF
|
|
0U, // FMAXNM_ZPZI_H_ZERO
|
|
0U, // FMAXNM_ZPZI_S_UNDEF
|
|
0U, // FMAXNM_ZPZI_S_ZERO
|
|
0U, // FMAXNM_ZPZZ_D_UNDEF
|
|
0U, // FMAXNM_ZPZZ_D_ZERO
|
|
0U, // FMAXNM_ZPZZ_H_UNDEF
|
|
0U, // FMAXNM_ZPZZ_H_ZERO
|
|
0U, // FMAXNM_ZPZZ_S_UNDEF
|
|
0U, // FMAXNM_ZPZZ_S_ZERO
|
|
0U, // FMAX_ZPZI_D_UNDEF
|
|
0U, // FMAX_ZPZI_D_ZERO
|
|
0U, // FMAX_ZPZI_H_UNDEF
|
|
0U, // FMAX_ZPZI_H_ZERO
|
|
0U, // FMAX_ZPZI_S_UNDEF
|
|
0U, // FMAX_ZPZI_S_ZERO
|
|
0U, // FMAX_ZPZZ_D_UNDEF
|
|
0U, // FMAX_ZPZZ_D_ZERO
|
|
0U, // FMAX_ZPZZ_H_UNDEF
|
|
0U, // FMAX_ZPZZ_H_ZERO
|
|
0U, // FMAX_ZPZZ_S_UNDEF
|
|
0U, // FMAX_ZPZZ_S_ZERO
|
|
0U, // FMINNM_ZPZI_D_UNDEF
|
|
0U, // FMINNM_ZPZI_D_ZERO
|
|
0U, // FMINNM_ZPZI_H_UNDEF
|
|
0U, // FMINNM_ZPZI_H_ZERO
|
|
0U, // FMINNM_ZPZI_S_UNDEF
|
|
0U, // FMINNM_ZPZI_S_ZERO
|
|
0U, // FMINNM_ZPZZ_D_UNDEF
|
|
0U, // FMINNM_ZPZZ_D_ZERO
|
|
0U, // FMINNM_ZPZZ_H_UNDEF
|
|
0U, // FMINNM_ZPZZ_H_ZERO
|
|
0U, // FMINNM_ZPZZ_S_UNDEF
|
|
0U, // FMINNM_ZPZZ_S_ZERO
|
|
0U, // FMIN_ZPZI_D_UNDEF
|
|
0U, // FMIN_ZPZI_D_ZERO
|
|
0U, // FMIN_ZPZI_H_UNDEF
|
|
0U, // FMIN_ZPZI_H_ZERO
|
|
0U, // FMIN_ZPZI_S_UNDEF
|
|
0U, // FMIN_ZPZI_S_ZERO
|
|
0U, // FMIN_ZPZZ_D_UNDEF
|
|
0U, // FMIN_ZPZZ_D_ZERO
|
|
0U, // FMIN_ZPZZ_H_UNDEF
|
|
0U, // FMIN_ZPZZ_H_ZERO
|
|
0U, // FMIN_ZPZZ_S_UNDEF
|
|
0U, // FMIN_ZPZZ_S_ZERO
|
|
0U, // FMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // FMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // FMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // FMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // FMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // FMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // FMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // FMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // FMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // FMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // FMLAL_VG2_M2Z2Z_BtoH_PSEUDO
|
|
0U, // FMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // FMLAL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // FMLAL_VG2_M2ZZ_BtoH_PSEUDO
|
|
0U, // FMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // FMLAL_VG4_M4Z4Z_BtoH_PSEUDO
|
|
0U, // FMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // FMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // FMLAL_VG4_M4ZZ_BtoH_PSEUDO
|
|
0U, // FMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // FMLA_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // FMLA_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // FMLA_VG2_M2Z4Z_H_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZI_D_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZI_S_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZ_D_PSEUDO
|
|
0U, // FMLA_VG2_M2ZZ_S_PSEUDO
|
|
0U, // FMLA_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // FMLA_VG4_M4Z4Z_H_PSEUDO
|
|
0U, // FMLA_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZI_D_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZI_S_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZ_D_PSEUDO
|
|
0U, // FMLA_VG4_M4ZZ_S_PSEUDO
|
|
0U, // FMLA_ZPZZZ_D_UNDEF
|
|
0U, // FMLA_ZPZZZ_H_UNDEF
|
|
0U, // FMLA_ZPZZZ_S_UNDEF
|
|
0U, // FMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // FMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // FMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // FMLSL_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // FMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // FMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // FMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // FMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // FMLS_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // FMLS_VG2_M2Z2Z_H_PSEUDO
|
|
0U, // FMLS_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZI_D_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZI_S_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZ_D_PSEUDO
|
|
0U, // FMLS_VG2_M2ZZ_S_PSEUDO
|
|
0U, // FMLS_VG4_M4Z2Z_H_PSEUDO
|
|
0U, // FMLS_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // FMLS_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZI_D_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZI_S_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZ_D_PSEUDO
|
|
0U, // FMLS_VG4_M4ZZ_S_PSEUDO
|
|
0U, // FMLS_ZPZZZ_D_UNDEF
|
|
0U, // FMLS_ZPZZZ_H_UNDEF
|
|
0U, // FMLS_ZPZZZ_S_UNDEF
|
|
0U, // FMOPAL_MPPZZ_PSEUDO
|
|
0U, // FMOPA_MPPZZ_BtoS_PSEUDO
|
|
0U, // FMOPA_MPPZZ_D_PSEUDO
|
|
0U, // FMOPA_MPPZZ_S_PSEUDO
|
|
0U, // FMOPSL_MPPZZ_PSEUDO
|
|
0U, // FMOPS_MPPZZ_D_PSEUDO
|
|
0U, // FMOPS_MPPZZ_S_PSEUDO
|
|
0U, // FMOVD0
|
|
0U, // FMOVH0
|
|
0U, // FMOVS0
|
|
0U, // FMULX_ZPZZ_D_UNDEF
|
|
0U, // FMULX_ZPZZ_D_ZERO
|
|
0U, // FMULX_ZPZZ_H_UNDEF
|
|
0U, // FMULX_ZPZZ_H_ZERO
|
|
0U, // FMULX_ZPZZ_S_UNDEF
|
|
0U, // FMULX_ZPZZ_S_ZERO
|
|
0U, // FMUL_ZPZI_D_UNDEF
|
|
0U, // FMUL_ZPZI_D_ZERO
|
|
0U, // FMUL_ZPZI_H_UNDEF
|
|
0U, // FMUL_ZPZI_H_ZERO
|
|
0U, // FMUL_ZPZI_S_UNDEF
|
|
0U, // FMUL_ZPZI_S_ZERO
|
|
0U, // FMUL_ZPZZ_D_UNDEF
|
|
0U, // FMUL_ZPZZ_D_ZERO
|
|
0U, // FMUL_ZPZZ_H_UNDEF
|
|
0U, // FMUL_ZPZZ_H_ZERO
|
|
0U, // FMUL_ZPZZ_S_UNDEF
|
|
0U, // FMUL_ZPZZ_S_ZERO
|
|
0U, // FNEG_ZPmZ_D_UNDEF
|
|
0U, // FNEG_ZPmZ_H_UNDEF
|
|
0U, // FNEG_ZPmZ_S_UNDEF
|
|
0U, // FNMLA_ZPZZZ_D_UNDEF
|
|
0U, // FNMLA_ZPZZZ_H_UNDEF
|
|
0U, // FNMLA_ZPZZZ_S_UNDEF
|
|
0U, // FNMLS_ZPZZZ_D_UNDEF
|
|
0U, // FNMLS_ZPZZZ_H_UNDEF
|
|
0U, // FNMLS_ZPZZZ_S_UNDEF
|
|
0U, // FRECPX_ZPmZ_D_UNDEF
|
|
0U, // FRECPX_ZPmZ_H_UNDEF
|
|
0U, // FRECPX_ZPmZ_S_UNDEF
|
|
0U, // FRINTA_ZPmZ_D_UNDEF
|
|
0U, // FRINTA_ZPmZ_H_UNDEF
|
|
0U, // FRINTA_ZPmZ_S_UNDEF
|
|
0U, // FRINTI_ZPmZ_D_UNDEF
|
|
0U, // FRINTI_ZPmZ_H_UNDEF
|
|
0U, // FRINTI_ZPmZ_S_UNDEF
|
|
0U, // FRINTM_ZPmZ_D_UNDEF
|
|
0U, // FRINTM_ZPmZ_H_UNDEF
|
|
0U, // FRINTM_ZPmZ_S_UNDEF
|
|
0U, // FRINTN_ZPmZ_D_UNDEF
|
|
0U, // FRINTN_ZPmZ_H_UNDEF
|
|
0U, // FRINTN_ZPmZ_S_UNDEF
|
|
0U, // FRINTP_ZPmZ_D_UNDEF
|
|
0U, // FRINTP_ZPmZ_H_UNDEF
|
|
0U, // FRINTP_ZPmZ_S_UNDEF
|
|
0U, // FRINTX_ZPmZ_D_UNDEF
|
|
0U, // FRINTX_ZPmZ_H_UNDEF
|
|
0U, // FRINTX_ZPmZ_S_UNDEF
|
|
0U, // FRINTZ_ZPmZ_D_UNDEF
|
|
0U, // FRINTZ_ZPmZ_H_UNDEF
|
|
0U, // FRINTZ_ZPmZ_S_UNDEF
|
|
0U, // FSQRT_ZPmZ_D_UNDEF
|
|
0U, // FSQRT_ZPmZ_H_UNDEF
|
|
0U, // FSQRT_ZPmZ_S_UNDEF
|
|
0U, // FSUBR_ZPZI_D_UNDEF
|
|
0U, // FSUBR_ZPZI_D_ZERO
|
|
0U, // FSUBR_ZPZI_H_UNDEF
|
|
0U, // FSUBR_ZPZI_H_ZERO
|
|
0U, // FSUBR_ZPZI_S_UNDEF
|
|
0U, // FSUBR_ZPZI_S_ZERO
|
|
0U, // FSUBR_ZPZZ_D_ZERO
|
|
0U, // FSUBR_ZPZZ_H_ZERO
|
|
0U, // FSUBR_ZPZZ_S_ZERO
|
|
0U, // FSUB_VG2_M2Z_D_PSEUDO
|
|
0U, // FSUB_VG2_M2Z_H_PSEUDO
|
|
0U, // FSUB_VG2_M2Z_S_PSEUDO
|
|
0U, // FSUB_VG4_M4Z_D_PSEUDO
|
|
0U, // FSUB_VG4_M4Z_H_PSEUDO
|
|
0U, // FSUB_VG4_M4Z_S_PSEUDO
|
|
0U, // FSUB_ZPZI_D_UNDEF
|
|
0U, // FSUB_ZPZI_D_ZERO
|
|
0U, // FSUB_ZPZI_H_UNDEF
|
|
0U, // FSUB_ZPZI_H_ZERO
|
|
0U, // FSUB_ZPZI_S_UNDEF
|
|
0U, // FSUB_ZPZI_S_ZERO
|
|
0U, // FSUB_ZPZZ_D_UNDEF
|
|
0U, // FSUB_ZPZZ_D_ZERO
|
|
0U, // FSUB_ZPZZ_H_UNDEF
|
|
0U, // FSUB_ZPZZ_H_ZERO
|
|
0U, // FSUB_ZPZZ_S_UNDEF
|
|
0U, // FSUB_ZPZZ_S_ZERO
|
|
0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // GLD1B_D
|
|
0U, // GLD1B_D_IMM
|
|
0U, // GLD1B_D_SXTW
|
|
0U, // GLD1B_D_UXTW
|
|
0U, // GLD1B_S_IMM
|
|
0U, // GLD1B_S_SXTW
|
|
0U, // GLD1B_S_UXTW
|
|
0U, // GLD1D
|
|
0U, // GLD1D_IMM
|
|
0U, // GLD1D_SCALED
|
|
0U, // GLD1D_SXTW
|
|
0U, // GLD1D_SXTW_SCALED
|
|
0U, // GLD1D_UXTW
|
|
0U, // GLD1D_UXTW_SCALED
|
|
0U, // GLD1H_D
|
|
0U, // GLD1H_D_IMM
|
|
0U, // GLD1H_D_SCALED
|
|
0U, // GLD1H_D_SXTW
|
|
0U, // GLD1H_D_SXTW_SCALED
|
|
0U, // GLD1H_D_UXTW
|
|
0U, // GLD1H_D_UXTW_SCALED
|
|
0U, // GLD1H_S_IMM
|
|
0U, // GLD1H_S_SXTW
|
|
0U, // GLD1H_S_SXTW_SCALED
|
|
0U, // GLD1H_S_UXTW
|
|
0U, // GLD1H_S_UXTW_SCALED
|
|
0U, // GLD1SB_D
|
|
0U, // GLD1SB_D_IMM
|
|
0U, // GLD1SB_D_SXTW
|
|
0U, // GLD1SB_D_UXTW
|
|
0U, // GLD1SB_S_IMM
|
|
0U, // GLD1SB_S_SXTW
|
|
0U, // GLD1SB_S_UXTW
|
|
0U, // GLD1SH_D
|
|
0U, // GLD1SH_D_IMM
|
|
0U, // GLD1SH_D_SCALED
|
|
0U, // GLD1SH_D_SXTW
|
|
0U, // GLD1SH_D_SXTW_SCALED
|
|
0U, // GLD1SH_D_UXTW
|
|
0U, // GLD1SH_D_UXTW_SCALED
|
|
0U, // GLD1SH_S_IMM
|
|
0U, // GLD1SH_S_SXTW
|
|
0U, // GLD1SH_S_SXTW_SCALED
|
|
0U, // GLD1SH_S_UXTW
|
|
0U, // GLD1SH_S_UXTW_SCALED
|
|
0U, // GLD1SW_D
|
|
0U, // GLD1SW_D_IMM
|
|
0U, // GLD1SW_D_SCALED
|
|
0U, // GLD1SW_D_SXTW
|
|
0U, // GLD1SW_D_SXTW_SCALED
|
|
0U, // GLD1SW_D_UXTW
|
|
0U, // GLD1SW_D_UXTW_SCALED
|
|
0U, // GLD1W_D
|
|
0U, // GLD1W_D_IMM
|
|
0U, // GLD1W_D_SCALED
|
|
0U, // GLD1W_D_SXTW
|
|
0U, // GLD1W_D_SXTW_SCALED
|
|
0U, // GLD1W_D_UXTW
|
|
0U, // GLD1W_D_UXTW_SCALED
|
|
0U, // GLD1W_IMM
|
|
0U, // GLD1W_SXTW
|
|
0U, // GLD1W_SXTW_SCALED
|
|
0U, // GLD1W_UXTW
|
|
0U, // GLD1W_UXTW_SCALED
|
|
0U, // GLDFF1B_D
|
|
0U, // GLDFF1B_D_IMM
|
|
0U, // GLDFF1B_D_SXTW
|
|
0U, // GLDFF1B_D_UXTW
|
|
0U, // GLDFF1B_S_IMM
|
|
0U, // GLDFF1B_S_SXTW
|
|
0U, // GLDFF1B_S_UXTW
|
|
0U, // GLDFF1D
|
|
0U, // GLDFF1D_IMM
|
|
0U, // GLDFF1D_SCALED
|
|
0U, // GLDFF1D_SXTW
|
|
0U, // GLDFF1D_SXTW_SCALED
|
|
0U, // GLDFF1D_UXTW
|
|
0U, // GLDFF1D_UXTW_SCALED
|
|
0U, // GLDFF1H_D
|
|
0U, // GLDFF1H_D_IMM
|
|
0U, // GLDFF1H_D_SCALED
|
|
0U, // GLDFF1H_D_SXTW
|
|
0U, // GLDFF1H_D_SXTW_SCALED
|
|
0U, // GLDFF1H_D_UXTW
|
|
0U, // GLDFF1H_D_UXTW_SCALED
|
|
0U, // GLDFF1H_S_IMM
|
|
0U, // GLDFF1H_S_SXTW
|
|
0U, // GLDFF1H_S_SXTW_SCALED
|
|
0U, // GLDFF1H_S_UXTW
|
|
0U, // GLDFF1H_S_UXTW_SCALED
|
|
0U, // GLDFF1SB_D
|
|
0U, // GLDFF1SB_D_IMM
|
|
0U, // GLDFF1SB_D_SXTW
|
|
0U, // GLDFF1SB_D_UXTW
|
|
0U, // GLDFF1SB_S_IMM
|
|
0U, // GLDFF1SB_S_SXTW
|
|
0U, // GLDFF1SB_S_UXTW
|
|
0U, // GLDFF1SH_D
|
|
0U, // GLDFF1SH_D_IMM
|
|
0U, // GLDFF1SH_D_SCALED
|
|
0U, // GLDFF1SH_D_SXTW
|
|
0U, // GLDFF1SH_D_SXTW_SCALED
|
|
0U, // GLDFF1SH_D_UXTW
|
|
0U, // GLDFF1SH_D_UXTW_SCALED
|
|
0U, // GLDFF1SH_S_IMM
|
|
0U, // GLDFF1SH_S_SXTW
|
|
0U, // GLDFF1SH_S_SXTW_SCALED
|
|
0U, // GLDFF1SH_S_UXTW
|
|
0U, // GLDFF1SH_S_UXTW_SCALED
|
|
0U, // GLDFF1SW_D
|
|
0U, // GLDFF1SW_D_IMM
|
|
0U, // GLDFF1SW_D_SCALED
|
|
0U, // GLDFF1SW_D_SXTW
|
|
0U, // GLDFF1SW_D_SXTW_SCALED
|
|
0U, // GLDFF1SW_D_UXTW
|
|
0U, // GLDFF1SW_D_UXTW_SCALED
|
|
0U, // GLDFF1W_D
|
|
0U, // GLDFF1W_D_IMM
|
|
0U, // GLDFF1W_D_SCALED
|
|
0U, // GLDFF1W_D_SXTW
|
|
0U, // GLDFF1W_D_SXTW_SCALED
|
|
0U, // GLDFF1W_D_UXTW
|
|
0U, // GLDFF1W_D_UXTW_SCALED
|
|
0U, // GLDFF1W_IMM
|
|
0U, // GLDFF1W_SXTW
|
|
0U, // GLDFF1W_SXTW_SCALED
|
|
0U, // GLDFF1W_UXTW
|
|
0U, // GLDFF1W_UXTW_SCALED
|
|
0U, // G_AARCH64_PREFETCH
|
|
0U, // G_ADD_LOW
|
|
0U, // G_BSP
|
|
0U, // G_DUP
|
|
0U, // G_DUPLANE16
|
|
0U, // G_DUPLANE32
|
|
0U, // G_DUPLANE64
|
|
0U, // G_DUPLANE8
|
|
0U, // G_EXT
|
|
0U, // G_FCMEQ
|
|
0U, // G_FCMEQZ
|
|
0U, // G_FCMGE
|
|
0U, // G_FCMGEZ
|
|
0U, // G_FCMGT
|
|
0U, // G_FCMGTZ
|
|
0U, // G_FCMLEZ
|
|
0U, // G_FCMLTZ
|
|
0U, // G_REV16
|
|
0U, // G_REV32
|
|
0U, // G_REV64
|
|
0U, // G_SADDLP
|
|
0U, // G_SADDLV
|
|
0U, // G_SDOT
|
|
0U, // G_SITOF
|
|
0U, // G_SMULL
|
|
0U, // G_TRN1
|
|
0U, // G_TRN2
|
|
0U, // G_UADDLP
|
|
0U, // G_UADDLV
|
|
0U, // G_UDOT
|
|
0U, // G_UITOF
|
|
0U, // G_UMULL
|
|
0U, // G_UZP1
|
|
0U, // G_UZP2
|
|
0U, // G_VASHR
|
|
0U, // G_VLSHR
|
|
0U, // G_ZIP1
|
|
0U, // G_ZIP2
|
|
0U, // HOM_Epilog
|
|
0U, // HOM_Prolog
|
|
0U, // HWASAN_CHECK_MEMACCESS
|
|
0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_B
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_D
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_H
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_Q
|
|
0U, // INSERT_MXIPZ_H_PSEUDO_S
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_B
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_D
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_H
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_Q
|
|
0U, // INSERT_MXIPZ_V_PSEUDO_S
|
|
0U, // IRGstack
|
|
0U, // JumpTableDest16
|
|
0U, // JumpTableDest32
|
|
0U, // JumpTableDest8
|
|
0U, // KCFI_CHECK
|
|
0U, // LD1B_2Z_IMM_PSEUDO
|
|
0U, // LD1B_2Z_PSEUDO
|
|
0U, // LD1B_4Z_IMM_PSEUDO
|
|
0U, // LD1B_4Z_PSEUDO
|
|
0U, // LD1D_2Z_IMM_PSEUDO
|
|
0U, // LD1D_2Z_PSEUDO
|
|
0U, // LD1D_4Z_IMM_PSEUDO
|
|
0U, // LD1D_4Z_PSEUDO
|
|
0U, // LD1H_2Z_IMM_PSEUDO
|
|
0U, // LD1H_2Z_PSEUDO
|
|
0U, // LD1H_4Z_IMM_PSEUDO
|
|
0U, // LD1H_4Z_PSEUDO
|
|
0U, // LD1W_2Z_IMM_PSEUDO
|
|
0U, // LD1W_2Z_PSEUDO
|
|
0U, // LD1W_4Z_IMM_PSEUDO
|
|
0U, // LD1W_4Z_PSEUDO
|
|
0U, // LD1_MXIPXX_H_PSEUDO_B
|
|
0U, // LD1_MXIPXX_H_PSEUDO_D
|
|
0U, // LD1_MXIPXX_H_PSEUDO_H
|
|
0U, // LD1_MXIPXX_H_PSEUDO_Q
|
|
0U, // LD1_MXIPXX_H_PSEUDO_S
|
|
0U, // LD1_MXIPXX_V_PSEUDO_B
|
|
0U, // LD1_MXIPXX_V_PSEUDO_D
|
|
0U, // LD1_MXIPXX_V_PSEUDO_H
|
|
0U, // LD1_MXIPXX_V_PSEUDO_Q
|
|
0U, // LD1_MXIPXX_V_PSEUDO_S
|
|
0U, // LDFF1B
|
|
0U, // LDFF1B_D
|
|
0U, // LDFF1B_H
|
|
0U, // LDFF1B_S
|
|
0U, // LDFF1D
|
|
0U, // LDFF1H
|
|
0U, // LDFF1H_D
|
|
0U, // LDFF1H_S
|
|
0U, // LDFF1SB_D
|
|
0U, // LDFF1SB_H
|
|
0U, // LDFF1SB_S
|
|
0U, // LDFF1SH_D
|
|
0U, // LDFF1SH_S
|
|
0U, // LDFF1SW_D
|
|
0U, // LDFF1W
|
|
0U, // LDFF1W_D
|
|
0U, // LDNF1B_D_IMM
|
|
0U, // LDNF1B_H_IMM
|
|
0U, // LDNF1B_IMM
|
|
0U, // LDNF1B_S_IMM
|
|
0U, // LDNF1D_IMM
|
|
0U, // LDNF1H_D_IMM
|
|
0U, // LDNF1H_IMM
|
|
0U, // LDNF1H_S_IMM
|
|
0U, // LDNF1SB_D_IMM
|
|
0U, // LDNF1SB_H_IMM
|
|
0U, // LDNF1SB_S_IMM
|
|
0U, // LDNF1SH_D_IMM
|
|
0U, // LDNF1SH_S_IMM
|
|
0U, // LDNF1SW_D_IMM
|
|
0U, // LDNF1W_D_IMM
|
|
0U, // LDNF1W_IMM
|
|
0U, // LDNT1B_2Z_IMM_PSEUDO
|
|
0U, // LDNT1B_2Z_PSEUDO
|
|
0U, // LDNT1B_4Z_IMM_PSEUDO
|
|
0U, // LDNT1B_4Z_PSEUDO
|
|
0U, // LDNT1D_2Z_IMM_PSEUDO
|
|
0U, // LDNT1D_2Z_PSEUDO
|
|
0U, // LDNT1D_4Z_IMM_PSEUDO
|
|
0U, // LDNT1D_4Z_PSEUDO
|
|
0U, // LDNT1H_2Z_IMM_PSEUDO
|
|
0U, // LDNT1H_2Z_PSEUDO
|
|
0U, // LDNT1H_4Z_IMM_PSEUDO
|
|
0U, // LDNT1H_4Z_PSEUDO
|
|
0U, // LDNT1W_2Z_IMM_PSEUDO
|
|
0U, // LDNT1W_2Z_PSEUDO
|
|
0U, // LDNT1W_4Z_IMM_PSEUDO
|
|
0U, // LDNT1W_4Z_PSEUDO
|
|
0U, // LDR_PPXI
|
|
0U, // LDR_TX_PSEUDO
|
|
0U, // LDR_ZA_PSEUDO
|
|
0U, // LDR_ZZXI
|
|
0U, // LDR_ZZZXI
|
|
0U, // LDR_ZZZZXI
|
|
0U, // LOADgot
|
|
0U, // LSL_ZPZI_B_UNDEF
|
|
0U, // LSL_ZPZI_B_ZERO
|
|
0U, // LSL_ZPZI_D_UNDEF
|
|
0U, // LSL_ZPZI_D_ZERO
|
|
0U, // LSL_ZPZI_H_UNDEF
|
|
0U, // LSL_ZPZI_H_ZERO
|
|
0U, // LSL_ZPZI_S_UNDEF
|
|
0U, // LSL_ZPZI_S_ZERO
|
|
0U, // LSL_ZPZZ_B_UNDEF
|
|
0U, // LSL_ZPZZ_B_ZERO
|
|
0U, // LSL_ZPZZ_D_UNDEF
|
|
0U, // LSL_ZPZZ_D_ZERO
|
|
0U, // LSL_ZPZZ_H_UNDEF
|
|
0U, // LSL_ZPZZ_H_ZERO
|
|
0U, // LSL_ZPZZ_S_UNDEF
|
|
0U, // LSL_ZPZZ_S_ZERO
|
|
0U, // LSR_ZPZI_B_UNDEF
|
|
0U, // LSR_ZPZI_B_ZERO
|
|
0U, // LSR_ZPZI_D_UNDEF
|
|
0U, // LSR_ZPZI_D_ZERO
|
|
0U, // LSR_ZPZI_H_UNDEF
|
|
0U, // LSR_ZPZI_H_ZERO
|
|
0U, // LSR_ZPZI_S_UNDEF
|
|
0U, // LSR_ZPZI_S_ZERO
|
|
0U, // LSR_ZPZZ_B_UNDEF
|
|
0U, // LSR_ZPZZ_B_ZERO
|
|
0U, // LSR_ZPZZ_D_UNDEF
|
|
0U, // LSR_ZPZZ_D_ZERO
|
|
0U, // LSR_ZPZZ_H_UNDEF
|
|
0U, // LSR_ZPZZ_H_ZERO
|
|
0U, // LSR_ZPZZ_S_UNDEF
|
|
0U, // LSR_ZPZZ_S_ZERO
|
|
0U, // MLA_ZPZZZ_B_UNDEF
|
|
0U, // MLA_ZPZZZ_D_UNDEF
|
|
0U, // MLA_ZPZZZ_H_UNDEF
|
|
0U, // MLA_ZPZZZ_S_UNDEF
|
|
0U, // MLS_ZPZZZ_B_UNDEF
|
|
0U, // MLS_ZPZZZ_D_UNDEF
|
|
0U, // MLS_ZPZZZ_H_UNDEF
|
|
0U, // MLS_ZPZZZ_S_UNDEF
|
|
0U, // MOPSMemoryCopyPseudo
|
|
0U, // MOPSMemoryMovePseudo
|
|
0U, // MOPSMemorySetPseudo
|
|
0U, // MOPSMemorySetTaggingPseudo
|
|
0U, // MOVA_MXI2Z_H_B_PSEUDO
|
|
0U, // MOVA_MXI2Z_H_D_PSEUDO
|
|
0U, // MOVA_MXI2Z_H_H_PSEUDO
|
|
0U, // MOVA_MXI2Z_H_S_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_B_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_D_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_H_PSEUDO
|
|
0U, // MOVA_MXI2Z_V_S_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_B_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_D_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_H_PSEUDO
|
|
0U, // MOVA_MXI4Z_H_S_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_B_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_D_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_H_PSEUDO
|
|
0U, // MOVA_MXI4Z_V_S_PSEUDO
|
|
0U, // MOVA_VG2_MXI2Z_PSEUDO
|
|
0U, // MOVA_VG4_MXI4Z_PSEUDO
|
|
0U, // MOVMCSym
|
|
0U, // MOVaddr
|
|
0U, // MOVaddrBA
|
|
0U, // MOVaddrCP
|
|
0U, // MOVaddrEXT
|
|
0U, // MOVaddrJT
|
|
0U, // MOVaddrTLS
|
|
0U, // MOVbaseTLS
|
|
0U, // MOVi32imm
|
|
0U, // MOVi64imm
|
|
0U, // MRS_FPCR
|
|
0U, // MSR_FPCR
|
|
0U, // MSRpstatePseudo
|
|
0U, // MUL_ZPZZ_B_UNDEF
|
|
0U, // MUL_ZPZZ_D_UNDEF
|
|
0U, // MUL_ZPZZ_H_UNDEF
|
|
0U, // MUL_ZPZZ_S_UNDEF
|
|
0U, // NEG_ZPmZ_B_UNDEF
|
|
0U, // NEG_ZPmZ_D_UNDEF
|
|
0U, // NEG_ZPmZ_H_UNDEF
|
|
0U, // NEG_ZPmZ_S_UNDEF
|
|
0U, // NOT_ZPmZ_B_UNDEF
|
|
0U, // NOT_ZPmZ_D_UNDEF
|
|
0U, // NOT_ZPmZ_H_UNDEF
|
|
0U, // NOT_ZPmZ_S_UNDEF
|
|
0U, // ORNWrr
|
|
0U, // ORNXrr
|
|
0U, // ORRWrr
|
|
0U, // ORRXrr
|
|
0U, // ORR_ZPZZ_B_ZERO
|
|
0U, // ORR_ZPZZ_D_ZERO
|
|
0U, // ORR_ZPZZ_H_ZERO
|
|
0U, // ORR_ZPZZ_S_ZERO
|
|
0U, // PAUTH_EPILOGUE
|
|
0U, // PAUTH_PROLOGUE
|
|
0U, // PROBED_STACKALLOC
|
|
0U, // PROBED_STACKALLOC_DYN
|
|
0U, // PROBED_STACKALLOC_VAR
|
|
0U, // PTEST_PP_ANY
|
|
0U, // RDFFR_P
|
|
0U, // RDFFR_PPz
|
|
0U, // RET_ReallyLR
|
|
0U, // RestoreZAPseudo
|
|
0U, // SABD_ZPZZ_B_UNDEF
|
|
0U, // SABD_ZPZZ_D_UNDEF
|
|
0U, // SABD_ZPZZ_H_UNDEF
|
|
0U, // SABD_ZPZZ_S_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // SCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // SDIV_ZPZZ_D_UNDEF
|
|
0U, // SDIV_ZPZZ_S_UNDEF
|
|
0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // SDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // SDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // SEH_AddFP
|
|
0U, // SEH_EpilogEnd
|
|
0U, // SEH_EpilogStart
|
|
0U, // SEH_Nop
|
|
0U, // SEH_PACSignLR
|
|
0U, // SEH_PrologEnd
|
|
0U, // SEH_SaveAnyRegQP
|
|
0U, // SEH_SaveAnyRegQPX
|
|
0U, // SEH_SaveFPLR
|
|
0U, // SEH_SaveFPLR_X
|
|
0U, // SEH_SaveFReg
|
|
0U, // SEH_SaveFRegP
|
|
0U, // SEH_SaveFRegP_X
|
|
0U, // SEH_SaveFReg_X
|
|
0U, // SEH_SaveReg
|
|
0U, // SEH_SaveRegP
|
|
0U, // SEH_SaveRegP_X
|
|
0U, // SEH_SaveReg_X
|
|
0U, // SEH_SetFP
|
|
0U, // SEH_StackAlloc
|
|
0U, // SMAX_ZPZZ_B_UNDEF
|
|
0U, // SMAX_ZPZZ_D_UNDEF
|
|
0U, // SMAX_ZPZZ_H_UNDEF
|
|
0U, // SMAX_ZPZZ_S_UNDEF
|
|
0U, // SMIN_ZPZZ_B_UNDEF
|
|
0U, // SMIN_ZPZZ_D_UNDEF
|
|
0U, // SMIN_ZPZZ_H_UNDEF
|
|
0U, // SMIN_ZPZZ_S_UNDEF
|
|
0U, // SMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // SMLALL_MZZI_HtoD_PSEUDO
|
|
0U, // SMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // SMLALL_MZZ_HtoD_PSEUDO
|
|
0U, // SMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // SMLALL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SMLALL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // SMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // SMLALL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SMLALL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // SMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // SMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // SMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // SMLAL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // SMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // SMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // SMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // SMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // SMLSLL_MZZI_BtoS_PSEUDO
|
|
0U, // SMLSLL_MZZI_HtoD_PSEUDO
|
|
0U, // SMLSLL_MZZ_BtoS_PSEUDO
|
|
0U, // SMLSLL_MZZ_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SMLSLL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // SMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // SMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // SMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // SMLSL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // SMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // SMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // SMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // SMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // SMOPA_MPPZZ_D_PSEUDO
|
|
0U, // SMOPA_MPPZZ_HtoS_PSEUDO
|
|
0U, // SMOPA_MPPZZ_S_PSEUDO
|
|
0U, // SMOPS_MPPZZ_D_PSEUDO
|
|
0U, // SMOPS_MPPZZ_HtoS_PSEUDO
|
|
0U, // SMOPS_MPPZZ_S_PSEUDO
|
|
0U, // SMULH_ZPZZ_B_UNDEF
|
|
0U, // SMULH_ZPZZ_D_UNDEF
|
|
0U, // SMULH_ZPZZ_H_UNDEF
|
|
0U, // SMULH_ZPZZ_S_UNDEF
|
|
0U, // SPACE
|
|
0U, // SQABS_ZPmZ_B_UNDEF
|
|
0U, // SQABS_ZPmZ_D_UNDEF
|
|
0U, // SQABS_ZPmZ_H_UNDEF
|
|
0U, // SQABS_ZPmZ_S_UNDEF
|
|
0U, // SQNEG_ZPmZ_B_UNDEF
|
|
0U, // SQNEG_ZPmZ_D_UNDEF
|
|
0U, // SQNEG_ZPmZ_H_UNDEF
|
|
0U, // SQNEG_ZPmZ_S_UNDEF
|
|
0U, // SQRSHL_ZPZZ_B_UNDEF
|
|
0U, // SQRSHL_ZPZZ_D_UNDEF
|
|
0U, // SQRSHL_ZPZZ_H_UNDEF
|
|
0U, // SQRSHL_ZPZZ_S_UNDEF
|
|
0U, // SQSHLU_ZPZI_B_ZERO
|
|
0U, // SQSHLU_ZPZI_D_ZERO
|
|
0U, // SQSHLU_ZPZI_H_ZERO
|
|
0U, // SQSHLU_ZPZI_S_ZERO
|
|
0U, // SQSHL_ZPZI_B_ZERO
|
|
0U, // SQSHL_ZPZI_D_ZERO
|
|
0U, // SQSHL_ZPZI_H_ZERO
|
|
0U, // SQSHL_ZPZI_S_ZERO
|
|
0U, // SQSHL_ZPZZ_B_UNDEF
|
|
0U, // SQSHL_ZPZZ_D_UNDEF
|
|
0U, // SQSHL_ZPZZ_H_UNDEF
|
|
0U, // SQSHL_ZPZZ_S_UNDEF
|
|
0U, // SRSHL_ZPZZ_B_UNDEF
|
|
0U, // SRSHL_ZPZZ_D_UNDEF
|
|
0U, // SRSHL_ZPZZ_H_UNDEF
|
|
0U, // SRSHL_ZPZZ_S_UNDEF
|
|
0U, // SRSHR_ZPZI_B_ZERO
|
|
0U, // SRSHR_ZPZI_D_ZERO
|
|
0U, // SRSHR_ZPZI_H_ZERO
|
|
0U, // SRSHR_ZPZI_S_ZERO
|
|
0U, // STGloop
|
|
0U, // STGloop_wback
|
|
0U, // STR_PPXI
|
|
0U, // STR_TX_PSEUDO
|
|
0U, // STR_ZZXI
|
|
0U, // STR_ZZZXI
|
|
0U, // STR_ZZZZXI
|
|
0U, // STZGloop
|
|
0U, // STZGloop_wback
|
|
0U, // SUBR_ZPZZ_B_ZERO
|
|
0U, // SUBR_ZPZZ_D_ZERO
|
|
0U, // SUBR_ZPZZ_H_ZERO
|
|
0U, // SUBR_ZPZZ_S_ZERO
|
|
0U, // SUBSWrr
|
|
0U, // SUBSXrr
|
|
0U, // SUBWrr
|
|
0U, // SUBXrr
|
|
0U, // SUB_VG2_M2Z2Z_D_PSEUDO
|
|
0U, // SUB_VG2_M2Z2Z_S_PSEUDO
|
|
0U, // SUB_VG2_M2ZZ_D_PSEUDO
|
|
0U, // SUB_VG2_M2ZZ_S_PSEUDO
|
|
0U, // SUB_VG2_M2Z_D_PSEUDO
|
|
0U, // SUB_VG2_M2Z_S_PSEUDO
|
|
0U, // SUB_VG4_M4Z4Z_D_PSEUDO
|
|
0U, // SUB_VG4_M4Z4Z_S_PSEUDO
|
|
0U, // SUB_VG4_M4ZZ_D_PSEUDO
|
|
0U, // SUB_VG4_M4ZZ_S_PSEUDO
|
|
0U, // SUB_VG4_M4Z_D_PSEUDO
|
|
0U, // SUB_VG4_M4Z_S_PSEUDO
|
|
0U, // SUB_ZPZZ_B_ZERO
|
|
0U, // SUB_ZPZZ_D_ZERO
|
|
0U, // SUB_ZPZZ_H_ZERO
|
|
0U, // SUB_ZPZZ_S_ZERO
|
|
0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // SUDOT_VG2_M2ZZ_BToS_PSEUDO
|
|
0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // SUDOT_VG4_M4ZZ_BToS_PSEUDO
|
|
0U, // SUMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SUMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // SUMOPA_MPPZZ_D_PSEUDO
|
|
0U, // SUMOPA_MPPZZ_S_PSEUDO
|
|
0U, // SUMOPS_MPPZZ_D_PSEUDO
|
|
0U, // SUMOPS_MPPZZ_S_PSEUDO
|
|
0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // SXTB_ZPmZ_D_UNDEF
|
|
0U, // SXTB_ZPmZ_H_UNDEF
|
|
0U, // SXTB_ZPmZ_S_UNDEF
|
|
0U, // SXTH_ZPmZ_D_UNDEF
|
|
0U, // SXTH_ZPmZ_S_UNDEF
|
|
0U, // SXTW_ZPmZ_D_UNDEF
|
|
0U, // SpeculationBarrierISBDSBEndBB
|
|
0U, // SpeculationBarrierSBEndBB
|
|
0U, // SpeculationSafeValueW
|
|
0U, // SpeculationSafeValueX
|
|
0U, // StoreSwiftAsyncContext
|
|
0U, // TAGPstack
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNriALL
|
|
0U, // TCRETURNriBTI
|
|
0U, // TLSDESCCALL
|
|
0U, // TLSDESC_CALLSEQ
|
|
0U, // UABD_ZPZZ_B_UNDEF
|
|
0U, // UABD_ZPZZ_D_UNDEF
|
|
0U, // UABD_ZPZZ_H_UNDEF
|
|
0U, // UABD_ZPZZ_S_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // UCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // UDIV_ZPZZ_D_UNDEF
|
|
0U, // UDIV_ZPZZ_S_UNDEF
|
|
0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // UDOT_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // UDOT_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // UMAX_ZPZZ_B_UNDEF
|
|
0U, // UMAX_ZPZZ_D_UNDEF
|
|
0U, // UMAX_ZPZZ_H_UNDEF
|
|
0U, // UMAX_ZPZZ_S_UNDEF
|
|
0U, // UMIN_ZPZZ_B_UNDEF
|
|
0U, // UMIN_ZPZZ_D_UNDEF
|
|
0U, // UMIN_ZPZZ_H_UNDEF
|
|
0U, // UMIN_ZPZZ_S_UNDEF
|
|
0U, // UMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // UMLALL_MZZI_HtoD_PSEUDO
|
|
0U, // UMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // UMLALL_MZZ_HtoD_PSEUDO
|
|
0U, // UMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // UMLALL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // UMLALL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // UMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // UMLALL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // UMLALL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // UMLAL_MZZI_HtoS_PSEUDO
|
|
0U, // UMLAL_MZZ_HtoS_PSEUDO
|
|
0U, // UMLAL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // UMLAL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // UMLAL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // UMLAL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // UMLAL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // UMLAL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // UMLSLL_MZZI_BtoS_PSEUDO
|
|
0U, // UMLSLL_MZZI_HtoD_PSEUDO
|
|
0U, // UMLSLL_MZZ_BtoS_PSEUDO
|
|
0U, // UMLSLL_MZZ_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG2_M2Z2Z_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZI_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG2_M2ZZ_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG4_M4Z4Z_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // UMLSLL_VG4_M4ZZ_HtoD_PSEUDO
|
|
0U, // UMLSL_MZZI_HtoS_PSEUDO
|
|
0U, // UMLSL_MZZ_HtoS_PSEUDO
|
|
0U, // UMLSL_VG2_M2Z2Z_HtoS_PSEUDO
|
|
0U, // UMLSL_VG2_M2ZZI_S_PSEUDO
|
|
0U, // UMLSL_VG2_M2ZZ_HtoS_PSEUDO
|
|
0U, // UMLSL_VG4_M4Z4Z_HtoS_PSEUDO
|
|
0U, // UMLSL_VG4_M4ZZI_HtoS_PSEUDO
|
|
0U, // UMLSL_VG4_M4ZZ_HtoS_PSEUDO
|
|
0U, // UMOPA_MPPZZ_D_PSEUDO
|
|
0U, // UMOPA_MPPZZ_HtoS_PSEUDO
|
|
0U, // UMOPA_MPPZZ_S_PSEUDO
|
|
0U, // UMOPS_MPPZZ_D_PSEUDO
|
|
0U, // UMOPS_MPPZZ_HtoS_PSEUDO
|
|
0U, // UMOPS_MPPZZ_S_PSEUDO
|
|
0U, // UMULH_ZPZZ_B_UNDEF
|
|
0U, // UMULH_ZPZZ_D_UNDEF
|
|
0U, // UMULH_ZPZZ_H_UNDEF
|
|
0U, // UMULH_ZPZZ_S_UNDEF
|
|
0U, // UQRSHL_ZPZZ_B_UNDEF
|
|
0U, // UQRSHL_ZPZZ_D_UNDEF
|
|
0U, // UQRSHL_ZPZZ_H_UNDEF
|
|
0U, // UQRSHL_ZPZZ_S_UNDEF
|
|
0U, // UQSHL_ZPZI_B_ZERO
|
|
0U, // UQSHL_ZPZI_D_ZERO
|
|
0U, // UQSHL_ZPZI_H_ZERO
|
|
0U, // UQSHL_ZPZI_S_ZERO
|
|
0U, // UQSHL_ZPZZ_B_UNDEF
|
|
0U, // UQSHL_ZPZZ_D_UNDEF
|
|
0U, // UQSHL_ZPZZ_H_UNDEF
|
|
0U, // UQSHL_ZPZZ_S_UNDEF
|
|
0U, // URECPE_ZPmZ_S_UNDEF
|
|
0U, // URSHL_ZPZZ_B_UNDEF
|
|
0U, // URSHL_ZPZZ_D_UNDEF
|
|
0U, // URSHL_ZPZZ_H_UNDEF
|
|
0U, // URSHL_ZPZZ_S_UNDEF
|
|
0U, // URSHR_ZPZI_B_ZERO
|
|
0U, // URSHR_ZPZI_D_ZERO
|
|
0U, // URSHR_ZPZI_H_ZERO
|
|
0U, // URSHR_ZPZI_S_ZERO
|
|
0U, // URSQRTE_ZPmZ_S_UNDEF
|
|
0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO
|
|
0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO
|
|
0U, // USDOT_VG2_M2ZZ_BToS_PSEUDO
|
|
0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO
|
|
0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // USDOT_VG4_M4ZZ_BToS_PSEUDO
|
|
0U, // USMLALL_MZZI_BtoS_PSEUDO
|
|
0U, // USMLALL_MZZ_BtoS_PSEUDO
|
|
0U, // USMLALL_VG2_M2Z2Z_BtoS_PSEUDO
|
|
0U, // USMLALL_VG2_M2ZZI_BtoS_PSEUDO
|
|
0U, // USMLALL_VG2_M2ZZ_BtoS_PSEUDO
|
|
0U, // USMLALL_VG4_M4Z4Z_BtoS_PSEUDO
|
|
0U, // USMLALL_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // USMLALL_VG4_M4ZZ_BtoS_PSEUDO
|
|
0U, // USMOPA_MPPZZ_D_PSEUDO
|
|
0U, // USMOPA_MPPZZ_S_PSEUDO
|
|
0U, // USMOPS_MPPZZ_D_PSEUDO
|
|
0U, // USMOPS_MPPZZ_S_PSEUDO
|
|
0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO
|
|
0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO
|
|
0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO
|
|
0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO
|
|
0U, // UXTB_ZPmZ_D_UNDEF
|
|
0U, // UXTB_ZPmZ_H_UNDEF
|
|
0U, // UXTB_ZPmZ_S_UNDEF
|
|
0U, // UXTH_ZPmZ_D_UNDEF
|
|
0U, // UXTH_ZPmZ_S_UNDEF
|
|
0U, // UXTW_ZPmZ_D_UNDEF
|
|
0U, // ZERO_M_PSEUDO
|
|
0U, // ZERO_T_PSEUDO
|
|
0U, // ABSWr
|
|
0U, // ABSXr
|
|
8U, // ABS_ZPmZ_B
|
|
16U, // ABS_ZPmZ_D
|
|
0U, // ABS_ZPmZ_H
|
|
24U, // ABS_ZPmZ_S
|
|
32U, // ABSv16i8
|
|
0U, // ABSv1i64
|
|
40U, // ABSv2i32
|
|
48U, // ABSv2i64
|
|
56U, // ABSv4i16
|
|
64U, // ABSv4i32
|
|
72U, // ABSv8i16
|
|
80U, // ABSv8i8
|
|
1112U, // ADCLB_ZZZ_D
|
|
2136U, // ADCLB_ZZZ_S
|
|
1112U, // ADCLT_ZZZ_D
|
|
2136U, // ADCLT_ZZZ_S
|
|
3160U, // ADCSWr
|
|
3160U, // ADCSXr
|
|
3160U, // ADCWr
|
|
3160U, // ADCXr
|
|
135256U, // ADDG
|
|
0U, // ADDHA_MPPZ_D
|
|
0U, // ADDHA_MPPZ_S
|
|
5208U, // ADDHNB_ZZZ_B
|
|
96U, // ADDHNB_ZZZ_H
|
|
6232U, // ADDHNB_ZZZ_S
|
|
7256U, // ADDHNT_ZZZ_B
|
|
24U, // ADDHNT_ZZZ_H
|
|
1112U, // ADDHNT_ZZZ_S
|
|
270440U, // ADDHNv2i64_v2i32
|
|
271464U, // ADDHNv2i64_v4i32
|
|
401520U, // ADDHNv4i32_v4i16
|
|
402544U, // ADDHNv4i32_v8i16
|
|
533624U, // ADDHNv8i16_v16i8
|
|
532600U, // ADDHNv8i16_v8i8
|
|
3160U, // ADDPL_XXI
|
|
658520U, // ADDPT_shift
|
|
16918656U, // ADDP_ZPmZ_B
|
|
33691776U, // ADDP_ZPmZ_D
|
|
51129480U, // ADDP_ZPmZ_H
|
|
67252352U, // ADDP_ZPmZ_S
|
|
925840U, // ADDPv16i8
|
|
1056920U, // ADDPv2i32
|
|
270440U, // ADDPv2i64
|
|
48U, // ADDPv2i64p
|
|
1188000U, // ADDPv4i16
|
|
401520U, // ADDPv4i32
|
|
532600U, // ADDPv8i16
|
|
1319080U, // ADDPv8i8
|
|
10328U, // ADDQV_VPZ_B
|
|
6232U, // ADDQV_VPZ_D
|
|
5208U, // ADDQV_VPZ_H
|
|
12376U, // ADDQV_VPZ_S
|
|
3160U, // ADDSPL_XXI
|
|
3160U, // ADDSVL_XXI
|
|
13400U, // ADDSWri
|
|
14424U, // ADDSWrs
|
|
15448U, // ADDSWrx
|
|
13400U, // ADDSXri
|
|
14424U, // ADDSXrs
|
|
15448U, // ADDSXrx
|
|
1444952U, // ADDSXrx64
|
|
0U, // ADDVA_MPPZ_D
|
|
0U, // ADDVA_MPPZ_S
|
|
3160U, // ADDVL_XXI
|
|
32U, // ADDVv16i8v
|
|
56U, // ADDVv4i16v
|
|
64U, // ADDVv4i32v
|
|
72U, // ADDVv8i16v
|
|
80U, // ADDVv8i8v
|
|
13400U, // ADDWri
|
|
14424U, // ADDWrs
|
|
15448U, // ADDWrx
|
|
13400U, // ADDXri
|
|
14424U, // ADDXrs
|
|
15448U, // ADDXrx
|
|
1444952U, // ADDXrx64
|
|
176U, // ADD_VG2_2ZZ_B
|
|
184U, // ADD_VG2_2ZZ_D
|
|
136U, // ADD_VG2_2ZZ_H
|
|
96U, // ADD_VG2_2ZZ_S
|
|
1584320U, // ADD_VG2_M2Z2Z_D
|
|
1715400U, // ADD_VG2_M2Z2Z_S
|
|
52178112U, // ADD_VG2_M2ZZ_D
|
|
52309192U, // ADD_VG2_M2ZZ_S
|
|
192U, // ADD_VG2_M2Z_D
|
|
200U, // ADD_VG2_M2Z_S
|
|
176U, // ADD_VG4_4ZZ_B
|
|
184U, // ADD_VG4_4ZZ_D
|
|
136U, // ADD_VG4_4ZZ_H
|
|
96U, // ADD_VG4_4ZZ_S
|
|
1584320U, // ADD_VG4_M4Z4Z_D
|
|
1715400U, // ADD_VG4_M4Z4Z_S
|
|
52178112U, // ADD_VG4_M4ZZ_D
|
|
52309192U, // ADD_VG4_M4ZZ_S
|
|
192U, // ADD_VG4_M4Z_D
|
|
200U, // ADD_VG4_M4Z_S
|
|
16473U, // ADD_ZI_B
|
|
17496U, // ADD_ZI_D
|
|
208U, // ADD_ZI_H
|
|
18521U, // ADD_ZI_S
|
|
16918656U, // ADD_ZPmZ_B
|
|
33691776U, // ADD_ZPmZ_CPA
|
|
33691776U, // ADD_ZPmZ_D
|
|
51129480U, // ADD_ZPmZ_H
|
|
67252352U, // ADD_ZPmZ_S
|
|
10329U, // ADD_ZZZ_B
|
|
6232U, // ADD_ZZZ_CPA
|
|
6232U, // ADD_ZZZ_D
|
|
136U, // ADD_ZZZ_H
|
|
12377U, // ADD_ZZZ_S
|
|
925840U, // ADDv16i8
|
|
3160U, // ADDv1i64
|
|
1056920U, // ADDv2i32
|
|
270440U, // ADDv2i64
|
|
1188000U, // ADDv4i16
|
|
401520U, // ADDv4i32
|
|
532600U, // ADDv8i16
|
|
1319080U, // ADDv8i8
|
|
1U, // ADR
|
|
1U, // ADRP
|
|
19544U, // ADR_LSL_ZZZ_D_0
|
|
20568U, // ADR_LSL_ZZZ_D_1
|
|
21592U, // ADR_LSL_ZZZ_D_2
|
|
22616U, // ADR_LSL_ZZZ_D_3
|
|
23641U, // ADR_LSL_ZZZ_S_0
|
|
24665U, // ADR_LSL_ZZZ_S_1
|
|
25689U, // ADR_LSL_ZZZ_S_2
|
|
26713U, // ADR_LSL_ZZZ_S_3
|
|
27736U, // ADR_SXTW_ZZZ_D_0
|
|
28760U, // ADR_SXTW_ZZZ_D_1
|
|
29784U, // ADR_SXTW_ZZZ_D_2
|
|
30808U, // ADR_SXTW_ZZZ_D_3
|
|
31832U, // ADR_UXTW_ZZZ_D_0
|
|
32856U, // ADR_UXTW_ZZZ_D_1
|
|
33880U, // ADR_UXTW_ZZZ_D_2
|
|
34904U, // ADR_UXTW_ZZZ_D_3
|
|
10329U, // AESD_ZZZ_B
|
|
32U, // AESDrr
|
|
10329U, // AESE_ZZZ_B
|
|
32U, // AESErr
|
|
1U, // AESIMC_ZZ_B
|
|
32U, // AESIMCrr
|
|
1U, // AESMC_ZZ_B
|
|
32U, // AESMCrr
|
|
10328U, // ANDQV_VPZ_B
|
|
6232U, // ANDQV_VPZ_D
|
|
5208U, // ANDQV_VPZ_H
|
|
12376U, // ANDQV_VPZ_S
|
|
35928U, // ANDSWri
|
|
14424U, // ANDSWrs
|
|
36952U, // ANDSXri
|
|
14424U, // ANDSXrs
|
|
16918744U, // ANDS_PPzPP
|
|
0U, // ANDV_VPZ_B
|
|
0U, // ANDV_VPZ_D
|
|
0U, // ANDV_VPZ_H
|
|
0U, // ANDV_VPZ_S
|
|
35928U, // ANDWri
|
|
14424U, // ANDWrs
|
|
36952U, // ANDXri
|
|
14424U, // ANDXrs
|
|
16918744U, // AND_PPzPP
|
|
36952U, // AND_ZI
|
|
16918656U, // AND_ZPmZ_B
|
|
33691776U, // AND_ZPmZ_D
|
|
51129480U, // AND_ZPmZ_H
|
|
67252352U, // AND_ZPmZ_S
|
|
6232U, // AND_ZZZ
|
|
925840U, // ANDv16i8
|
|
1319080U, // ANDv8i8
|
|
141440U, // ASRD_ZPmI_B
|
|
137344U, // ASRD_ZPmI_D
|
|
52440200U, // ASRD_ZPmI_H
|
|
143488U, // ASRD_ZPmI_S
|
|
16918656U, // ASRR_ZPmZ_B
|
|
33691776U, // ASRR_ZPmZ_D
|
|
51129480U, // ASRR_ZPmZ_H
|
|
67252352U, // ASRR_ZPmZ_S
|
|
3160U, // ASRVWr
|
|
3160U, // ASRVXr
|
|
33695872U, // ASR_WIDE_ZPmZ_B
|
|
2239624U, // ASR_WIDE_ZPmZ_H
|
|
33697920U, // ASR_WIDE_ZPmZ_S
|
|
6233U, // ASR_WIDE_ZZZ_B
|
|
184U, // ASR_WIDE_ZZZ_H
|
|
6233U, // ASR_WIDE_ZZZ_S
|
|
141440U, // ASR_ZPmI_B
|
|
137344U, // ASR_ZPmI_D
|
|
52440200U, // ASR_ZPmI_H
|
|
143488U, // ASR_ZPmI_S
|
|
16918656U, // ASR_ZPmZ_B
|
|
33691776U, // ASR_ZPmZ_D
|
|
51129480U, // ASR_ZPmZ_H
|
|
67252352U, // ASR_ZPmZ_S
|
|
3161U, // ASR_ZZI_B
|
|
3160U, // ASR_ZZI_D
|
|
224U, // ASR_ZZI_H
|
|
3161U, // ASR_ZZI_S
|
|
0U, // AT_AS1ELX
|
|
1U, // AUTDA
|
|
1U, // AUTDB
|
|
0U, // AUTDZA
|
|
0U, // AUTDZB
|
|
1U, // AUTIA
|
|
0U, // AUTIA1716
|
|
0U, // AUTIA171615
|
|
0U, // AUTIASP
|
|
0U, // AUTIASPPCi
|
|
0U, // AUTIASPPCr
|
|
0U, // AUTIAZ
|
|
1U, // AUTIB
|
|
0U, // AUTIB1716
|
|
0U, // AUTIB171615
|
|
0U, // AUTIBSP
|
|
0U, // AUTIBSPPCi
|
|
0U, // AUTIBSPPCr
|
|
0U, // AUTIBZ
|
|
0U, // AUTIZA
|
|
0U, // AUTIZB
|
|
0U, // AXFLAG
|
|
0U, // B
|
|
86253712U, // BCAX
|
|
33691736U, // BCAX_ZZZZ
|
|
0U, // BCcc
|
|
10329U, // BDEP_ZZZ_B
|
|
6232U, // BDEP_ZZZ_D
|
|
136U, // BDEP_ZZZ_H
|
|
12377U, // BDEP_ZZZ_S
|
|
10329U, // BEXT_ZZZ_B
|
|
6232U, // BEXT_ZZZ_D
|
|
136U, // BEXT_ZZZ_H
|
|
12377U, // BEXT_ZZZ_S
|
|
2499744U, // BF16DOTlanev4bf16
|
|
2499704U, // BF16DOTlanev8bf16
|
|
32U, // BF1CVTL2v8f16
|
|
0U, // BF1CVTLT_ZZ_BtoH
|
|
0U, // BF1CVTL_2ZZ_BtoH_NAME
|
|
80U, // BF1CVTLv8f16
|
|
0U, // BF1CVT_2ZZ_BtoH_NAME
|
|
0U, // BF1CVT_ZZ_BtoH
|
|
32U, // BF2CVTL2v8f16
|
|
0U, // BF2CVTLT_ZZ_BtoH
|
|
0U, // BF2CVTL_2ZZ_BtoH_NAME
|
|
80U, // BF2CVTLv8f16
|
|
0U, // BF2CVT_2ZZ_BtoH_NAME
|
|
0U, // BF2CVT_ZZ_BtoH
|
|
232U, // BFADD_VG2_M2Z_H
|
|
232U, // BFADD_VG4_M4Z_H
|
|
51129480U, // BFADD_ZPmZZ
|
|
136U, // BFADD_ZZZ
|
|
240U, // BFCLAMP_VG2_2ZZZ_H
|
|
240U, // BFCLAMP_VG4_4ZZZ_H
|
|
240U, // BFCLAMP_ZZZ
|
|
0U, // BFCVT
|
|
64U, // BFCVTN
|
|
64U, // BFCVTN2
|
|
1U, // BFCVTNT_ZPmZ
|
|
1U, // BFCVTN_Z2Z_HtoB
|
|
0U, // BFCVTN_Z2Z_StoH
|
|
1U, // BFCVT_Z2Z_HtoB
|
|
0U, // BFCVT_Z2Z_StoH
|
|
1U, // BFCVT_ZPmZ
|
|
2632936U, // BFDOT_VG2_M2Z2Z_HtoS
|
|
103427304U, // BFDOT_VG2_M2ZZI_HtoS
|
|
53095656U, // BFDOT_VG2_M2ZZ_HtoS
|
|
2632936U, // BFDOT_VG4_M4Z4Z_HtoS
|
|
103427304U, // BFDOT_VG4_M4ZZI_HtoS
|
|
53095656U, // BFDOT_VG4_M4ZZ_HtoS
|
|
53222488U, // BFDOT_ZZI
|
|
7256U, // BFDOT_ZZZ
|
|
1189024U, // BFDOTv4bf16
|
|
533624U, // BFDOTv8bf16
|
|
248U, // BFMAXNM_VG2_2Z2Z_H
|
|
136U, // BFMAXNM_VG2_2ZZ_H
|
|
248U, // BFMAXNM_VG4_4Z2Z_H
|
|
136U, // BFMAXNM_VG4_4ZZ_H
|
|
51129480U, // BFMAXNM_ZPmZZ
|
|
248U, // BFMAX_VG2_2Z2Z_H
|
|
136U, // BFMAX_VG2_2ZZ_H
|
|
248U, // BFMAX_VG4_4Z2Z_H
|
|
136U, // BFMAX_VG4_4ZZ_H
|
|
51129480U, // BFMAX_ZPmZZ
|
|
248U, // BFMINNM_VG2_2Z2Z_H
|
|
136U, // BFMINNM_VG2_2ZZ_H
|
|
248U, // BFMINNM_VG4_4Z2Z_H
|
|
136U, // BFMINNM_VG4_4ZZ_H
|
|
51129480U, // BFMINNM_ZPmZZ
|
|
248U, // BFMIN_VG2_2Z2Z_H
|
|
136U, // BFMIN_VG2_2ZZ_H
|
|
248U, // BFMIN_VG4_4Z2Z_H
|
|
136U, // BFMIN_VG4_4ZZ_H
|
|
51129480U, // BFMIN_ZPmZZ
|
|
533624U, // BFMLALB
|
|
120464504U, // BFMLALBIdx
|
|
7256U, // BFMLALB_ZZZ
|
|
53222488U, // BFMLALB_ZZZI
|
|
533624U, // BFMLALT
|
|
120464504U, // BFMLALTIdx
|
|
7256U, // BFMLALT_ZZZ
|
|
53222488U, // BFMLALT_ZZZI
|
|
38145U, // BFMLAL_MZZI_HtoS
|
|
257U, // BFMLAL_MZZ_HtoS
|
|
2632936U, // BFMLAL_VG2_M2Z2Z_HtoS
|
|
103427304U, // BFMLAL_VG2_M2ZZI_HtoS
|
|
53095656U, // BFMLAL_VG2_M2ZZ_HtoS
|
|
2632936U, // BFMLAL_VG4_M4Z4Z_HtoS
|
|
103427304U, // BFMLAL_VG4_M4ZZI_HtoS
|
|
53095656U, // BFMLAL_VG4_M4ZZ_HtoS
|
|
2632936U, // BFMLA_VG2_M2Z2Z
|
|
53095656U, // BFMLA_VG2_M2ZZ
|
|
103427304U, // BFMLA_VG2_M2ZZI
|
|
2632936U, // BFMLA_VG4_M4Z4Z
|
|
53095656U, // BFMLA_VG4_M4ZZ
|
|
103427304U, // BFMLA_VG4_M4ZZI
|
|
53488880U, // BFMLA_ZPmZZ
|
|
39152U, // BFMLA_ZZZI
|
|
53222488U, // BFMLSLB_ZZZI_S
|
|
7256U, // BFMLSLB_ZZZ_S
|
|
53222488U, // BFMLSLT_ZZZI_S
|
|
7256U, // BFMLSLT_ZZZ_S
|
|
38145U, // BFMLSL_MZZI_HtoS
|
|
257U, // BFMLSL_MZZ_HtoS
|
|
2632936U, // BFMLSL_VG2_M2Z2Z_HtoS
|
|
103427304U, // BFMLSL_VG2_M2ZZI_HtoS
|
|
53095656U, // BFMLSL_VG2_M2ZZ_HtoS
|
|
2632936U, // BFMLSL_VG4_M4Z4Z_HtoS
|
|
103427304U, // BFMLSL_VG4_M4ZZI_HtoS
|
|
53095656U, // BFMLSL_VG4_M4ZZ_HtoS
|
|
2632936U, // BFMLS_VG2_M2Z2Z
|
|
53095656U, // BFMLS_VG2_M2ZZ
|
|
103427304U, // BFMLS_VG2_M2ZZI
|
|
2632936U, // BFMLS_VG4_M4Z4Z
|
|
53095656U, // BFMLS_VG4_M4ZZ
|
|
103427304U, // BFMLS_VG4_M4ZZI
|
|
53488880U, // BFMLS_ZPmZZ
|
|
39152U, // BFMLS_ZZZI
|
|
533624U, // BFMMLA
|
|
7256U, // BFMMLA_ZZZ
|
|
0U, // BFMOPA_MPPZZ
|
|
0U, // BFMOPA_MPPZZ_H
|
|
0U, // BFMOPS_MPPZZ
|
|
0U, // BFMOPS_MPPZZ_H
|
|
51129480U, // BFMUL_ZPmZZ
|
|
136U, // BFMUL_ZZZ
|
|
40072U, // BFMUL_ZZZI
|
|
134389849U, // BFMWri
|
|
134389849U, // BFMXri
|
|
232U, // BFSUB_VG2_M2Z_H
|
|
232U, // BFSUB_VG4_M4Z_H
|
|
51129480U, // BFSUB_ZPmZZ
|
|
136U, // BFSUB_ZZZ
|
|
103427304U, // BFVDOT_VG2_M2ZZI_HtoS
|
|
10329U, // BGRP_ZZZ_B
|
|
6232U, // BGRP_ZZZ_D
|
|
136U, // BGRP_ZZZ_H
|
|
12377U, // BGRP_ZZZ_S
|
|
14424U, // BICSWrs
|
|
14424U, // BICSXrs
|
|
16918744U, // BICS_PPzPP
|
|
14424U, // BICWrs
|
|
14424U, // BICXrs
|
|
16918744U, // BIC_PPzPP
|
|
16918656U, // BIC_ZPmZ_B
|
|
33691776U, // BIC_ZPmZ_D
|
|
51129480U, // BIC_ZPmZ_H
|
|
67252352U, // BIC_ZPmZ_S
|
|
6232U, // BIC_ZZZ
|
|
925840U, // BICv16i8
|
|
1U, // BICv2i32
|
|
1U, // BICv4i16
|
|
1U, // BICv4i32
|
|
1U, // BICv8i16
|
|
1319080U, // BICv8i8
|
|
926864U, // BIFv16i8
|
|
1320104U, // BIFv8i8
|
|
926864U, // BITv16i8
|
|
1320104U, // BITv8i8
|
|
0U, // BL
|
|
0U, // BLR
|
|
0U, // BLRAA
|
|
0U, // BLRAAZ
|
|
0U, // BLRAB
|
|
0U, // BLRABZ
|
|
264U, // BMOPA_MPPZZ_S
|
|
264U, // BMOPS_MPPZZ_S
|
|
0U, // BR
|
|
0U, // BRAA
|
|
0U, // BRAAZ
|
|
0U, // BRAB
|
|
0U, // BRABZ
|
|
0U, // BRB_IALL
|
|
0U, // BRB_INJ
|
|
0U, // BRK
|
|
10456U, // BRKAS_PPzP
|
|
8U, // BRKA_PPmP
|
|
10456U, // BRKA_PPzP
|
|
10456U, // BRKBS_PPzP
|
|
8U, // BRKB_PPmP
|
|
10456U, // BRKB_PPzP
|
|
16918744U, // BRKNS_PPzP
|
|
16918744U, // BRKN_PPzP
|
|
16918744U, // BRKPAS_PPzPP
|
|
16918744U, // BRKPA_PPzPP
|
|
16918744U, // BRKPBS_PPzPP
|
|
16918744U, // BRKPB_PPzPP
|
|
33691736U, // BSL1N_ZZZZ
|
|
33691736U, // BSL2N_ZZZZ
|
|
33691736U, // BSL_ZZZZ
|
|
926864U, // BSLv16i8
|
|
1320104U, // BSLv8i8
|
|
0U, // Bcc
|
|
151136345U, // CADD_ZZI_B
|
|
151132248U, // CADD_ZZI_D
|
|
3288200U, // CADD_ZZI_H
|
|
151138393U, // CADD_ZZI_S
|
|
3449105U, // CASAB
|
|
3449105U, // CASAH
|
|
3449105U, // CASALB
|
|
3449105U, // CASALH
|
|
3449105U, // CASALW
|
|
3449105U, // CASALX
|
|
3449105U, // CASAW
|
|
3449105U, // CASAX
|
|
3449105U, // CASB
|
|
3449105U, // CASH
|
|
3449105U, // CASLB
|
|
3449105U, // CASLH
|
|
3449105U, // CASLW
|
|
3449105U, // CASLX
|
|
0U, // CASPALW
|
|
0U, // CASPALX
|
|
0U, // CASPAW
|
|
0U, // CASPAX
|
|
0U, // CASPLW
|
|
0U, // CASPLX
|
|
0U, // CASPW
|
|
0U, // CASPX
|
|
3449105U, // CASW
|
|
3449105U, // CASX
|
|
1U, // CBNZW
|
|
1U, // CBNZX
|
|
1U, // CBZW
|
|
1U, // CBZX
|
|
167906392U, // CCMNWi
|
|
167906392U, // CCMNWr
|
|
167906392U, // CCMNXi
|
|
167906392U, // CCMNXr
|
|
167906392U, // CCMPWi
|
|
167906392U, // CCMPWr
|
|
167906392U, // CCMPXi
|
|
167906392U, // CCMPXr
|
|
187440216U, // CDOT_ZZZI_D
|
|
201496585U, // CDOT_ZZZI_S
|
|
218242136U, // CDOT_ZZZ_D
|
|
3550217U, // CDOT_ZZZ_S
|
|
0U, // CFINV
|
|
0U, // CHKFEAT
|
|
16911448U, // CLASTA_RPZ_B
|
|
33688664U, // CLASTA_RPZ_D
|
|
235015256U, // CLASTA_RPZ_H
|
|
67243096U, // CLASTA_RPZ_S
|
|
16911448U, // CLASTA_VPZ_B
|
|
33688664U, // CLASTA_VPZ_D
|
|
235015256U, // CLASTA_VPZ_H
|
|
67243096U, // CLASTA_VPZ_S
|
|
16918616U, // CLASTA_ZPZ_B
|
|
33691736U, // CLASTA_ZPZ_D
|
|
51129480U, // CLASTA_ZPZ_H
|
|
67252312U, // CLASTA_ZPZ_S
|
|
16911448U, // CLASTB_RPZ_B
|
|
33688664U, // CLASTB_RPZ_D
|
|
235015256U, // CLASTB_RPZ_H
|
|
67243096U, // CLASTB_RPZ_S
|
|
16911448U, // CLASTB_VPZ_B
|
|
33688664U, // CLASTB_VPZ_D
|
|
235015256U, // CLASTB_VPZ_H
|
|
67243096U, // CLASTB_VPZ_S
|
|
16918616U, // CLASTB_ZPZ_B
|
|
33691736U, // CLASTB_ZPZ_D
|
|
51129480U, // CLASTB_ZPZ_H
|
|
67252312U, // CLASTB_ZPZ_S
|
|
0U, // CLR
|
|
0U, // CLREX
|
|
0U, // CLSWr
|
|
0U, // CLSXr
|
|
8U, // CLS_ZPmZ_B
|
|
16U, // CLS_ZPmZ_D
|
|
0U, // CLS_ZPmZ_H
|
|
24U, // CLS_ZPmZ_S
|
|
32U, // CLSv16i8
|
|
40U, // CLSv2i32
|
|
56U, // CLSv4i16
|
|
64U, // CLSv4i32
|
|
72U, // CLSv8i16
|
|
80U, // CLSv8i8
|
|
0U, // CLZWr
|
|
0U, // CLZXr
|
|
8U, // CLZ_ZPmZ_B
|
|
16U, // CLZ_ZPmZ_D
|
|
0U, // CLZ_ZPmZ_H
|
|
24U, // CLZ_ZPmZ_S
|
|
32U, // CLZv16i8
|
|
40U, // CLZv2i32
|
|
56U, // CLZv4i16
|
|
64U, // CLZv4i32
|
|
72U, // CLZv8i16
|
|
80U, // CLZv8i8
|
|
925840U, // CMEQv16i8
|
|
280U, // CMEQv16i8rz
|
|
3160U, // CMEQv1i64
|
|
288U, // CMEQv1i64rz
|
|
1056920U, // CMEQv2i32
|
|
296U, // CMEQv2i32rz
|
|
270440U, // CMEQv2i64
|
|
304U, // CMEQv2i64rz
|
|
1188000U, // CMEQv4i16
|
|
312U, // CMEQv4i16rz
|
|
401520U, // CMEQv4i32
|
|
320U, // CMEQv4i32rz
|
|
532600U, // CMEQv8i16
|
|
328U, // CMEQv8i16rz
|
|
1319080U, // CMEQv8i8
|
|
336U, // CMEQv8i8rz
|
|
925840U, // CMGEv16i8
|
|
280U, // CMGEv16i8rz
|
|
3160U, // CMGEv1i64
|
|
288U, // CMGEv1i64rz
|
|
1056920U, // CMGEv2i32
|
|
296U, // CMGEv2i32rz
|
|
270440U, // CMGEv2i64
|
|
304U, // CMGEv2i64rz
|
|
1188000U, // CMGEv4i16
|
|
312U, // CMGEv4i16rz
|
|
401520U, // CMGEv4i32
|
|
320U, // CMGEv4i32rz
|
|
532600U, // CMGEv8i16
|
|
328U, // CMGEv8i16rz
|
|
1319080U, // CMGEv8i8
|
|
336U, // CMGEv8i8rz
|
|
925840U, // CMGTv16i8
|
|
280U, // CMGTv16i8rz
|
|
3160U, // CMGTv1i64
|
|
288U, // CMGTv1i64rz
|
|
1056920U, // CMGTv2i32
|
|
296U, // CMGTv2i32rz
|
|
270440U, // CMGTv2i64
|
|
304U, // CMGTv2i64rz
|
|
1188000U, // CMGTv4i16
|
|
312U, // CMGTv4i16rz
|
|
401520U, // CMGTv4i32
|
|
320U, // CMGTv4i32rz
|
|
532600U, // CMGTv8i16
|
|
328U, // CMGTv8i16rz
|
|
1319080U, // CMGTv8i8
|
|
336U, // CMGTv8i8rz
|
|
925840U, // CMHIv16i8
|
|
3160U, // CMHIv1i64
|
|
1056920U, // CMHIv2i32
|
|
270440U, // CMHIv2i64
|
|
1188000U, // CMHIv4i16
|
|
401520U, // CMHIv4i32
|
|
532600U, // CMHIv8i16
|
|
1319080U, // CMHIv8i8
|
|
925840U, // CMHSv16i8
|
|
3160U, // CMHSv1i64
|
|
1056920U, // CMHSv2i32
|
|
270440U, // CMHSv2i64
|
|
1188000U, // CMHSv4i16
|
|
401520U, // CMHSv4i32
|
|
532600U, // CMHSv8i16
|
|
1319080U, // CMHSv8i8
|
|
201496816U, // CMLA_ZZZI_H
|
|
187435096U, // CMLA_ZZZI_S
|
|
3550217U, // CMLA_ZZZ_B
|
|
218235992U, // CMLA_ZZZ_D
|
|
3550448U, // CMLA_ZZZ_H
|
|
218237016U, // CMLA_ZZZ_S
|
|
280U, // CMLEv16i8rz
|
|
288U, // CMLEv1i64rz
|
|
296U, // CMLEv2i32rz
|
|
304U, // CMLEv2i64rz
|
|
312U, // CMLEv4i16rz
|
|
320U, // CMLEv4i32rz
|
|
328U, // CMLEv8i16rz
|
|
336U, // CMLEv8i8rz
|
|
280U, // CMLTv16i8rz
|
|
288U, // CMLTv1i64rz
|
|
296U, // CMLTv2i32rz
|
|
304U, // CMLTv2i64rz
|
|
312U, // CMLTv4i16rz
|
|
320U, // CMLTv4i32rz
|
|
328U, // CMLTv8i16rz
|
|
336U, // CMLTv8i8rz
|
|
141528U, // CMPEQ_PPzZI_B
|
|
137432U, // CMPEQ_PPzZI_D
|
|
52440201U, // CMPEQ_PPzZI_H
|
|
143576U, // CMPEQ_PPzZI_S
|
|
16918744U, // CMPEQ_PPzZZ_B
|
|
33691864U, // CMPEQ_PPzZZ_D
|
|
51129481U, // CMPEQ_PPzZZ_H
|
|
67252440U, // CMPEQ_PPzZZ_S
|
|
33695960U, // CMPEQ_WIDE_PPzZZ_B
|
|
2239625U, // CMPEQ_WIDE_PPzZZ_H
|
|
33698008U, // CMPEQ_WIDE_PPzZZ_S
|
|
141528U, // CMPGE_PPzZI_B
|
|
137432U, // CMPGE_PPzZI_D
|
|
52440201U, // CMPGE_PPzZI_H
|
|
143576U, // CMPGE_PPzZI_S
|
|
16918744U, // CMPGE_PPzZZ_B
|
|
33691864U, // CMPGE_PPzZZ_D
|
|
51129481U, // CMPGE_PPzZZ_H
|
|
67252440U, // CMPGE_PPzZZ_S
|
|
33695960U, // CMPGE_WIDE_PPzZZ_B
|
|
2239625U, // CMPGE_WIDE_PPzZZ_H
|
|
33698008U, // CMPGE_WIDE_PPzZZ_S
|
|
141528U, // CMPGT_PPzZI_B
|
|
137432U, // CMPGT_PPzZI_D
|
|
52440201U, // CMPGT_PPzZI_H
|
|
143576U, // CMPGT_PPzZI_S
|
|
16918744U, // CMPGT_PPzZZ_B
|
|
33691864U, // CMPGT_PPzZZ_D
|
|
51129481U, // CMPGT_PPzZZ_H
|
|
67252440U, // CMPGT_PPzZZ_S
|
|
33695960U, // CMPGT_WIDE_PPzZZ_B
|
|
2239625U, // CMPGT_WIDE_PPzZZ_H
|
|
33698008U, // CMPGT_WIDE_PPzZZ_S
|
|
251799768U, // CMPHI_PPzZI_B
|
|
251795672U, // CMPHI_PPzZI_D
|
|
3681417U, // CMPHI_PPzZI_H
|
|
251801816U, // CMPHI_PPzZI_S
|
|
16918744U, // CMPHI_PPzZZ_B
|
|
33691864U, // CMPHI_PPzZZ_D
|
|
51129481U, // CMPHI_PPzZZ_H
|
|
67252440U, // CMPHI_PPzZZ_S
|
|
33695960U, // CMPHI_WIDE_PPzZZ_B
|
|
2239625U, // CMPHI_WIDE_PPzZZ_H
|
|
33698008U, // CMPHI_WIDE_PPzZZ_S
|
|
251799768U, // CMPHS_PPzZI_B
|
|
251795672U, // CMPHS_PPzZI_D
|
|
3681417U, // CMPHS_PPzZI_H
|
|
251801816U, // CMPHS_PPzZI_S
|
|
16918744U, // CMPHS_PPzZZ_B
|
|
33691864U, // CMPHS_PPzZZ_D
|
|
51129481U, // CMPHS_PPzZZ_H
|
|
67252440U, // CMPHS_PPzZZ_S
|
|
33695960U, // CMPHS_WIDE_PPzZZ_B
|
|
2239625U, // CMPHS_WIDE_PPzZZ_H
|
|
33698008U, // CMPHS_WIDE_PPzZZ_S
|
|
141528U, // CMPLE_PPzZI_B
|
|
137432U, // CMPLE_PPzZI_D
|
|
52440201U, // CMPLE_PPzZI_H
|
|
143576U, // CMPLE_PPzZI_S
|
|
33695960U, // CMPLE_WIDE_PPzZZ_B
|
|
2239625U, // CMPLE_WIDE_PPzZZ_H
|
|
33698008U, // CMPLE_WIDE_PPzZZ_S
|
|
251799768U, // CMPLO_PPzZI_B
|
|
251795672U, // CMPLO_PPzZI_D
|
|
3681417U, // CMPLO_PPzZI_H
|
|
251801816U, // CMPLO_PPzZI_S
|
|
33695960U, // CMPLO_WIDE_PPzZZ_B
|
|
2239625U, // CMPLO_WIDE_PPzZZ_H
|
|
33698008U, // CMPLO_WIDE_PPzZZ_S
|
|
251799768U, // CMPLS_PPzZI_B
|
|
251795672U, // CMPLS_PPzZI_D
|
|
3681417U, // CMPLS_PPzZI_H
|
|
251801816U, // CMPLS_PPzZI_S
|
|
33695960U, // CMPLS_WIDE_PPzZZ_B
|
|
2239625U, // CMPLS_WIDE_PPzZZ_H
|
|
33698008U, // CMPLS_WIDE_PPzZZ_S
|
|
141528U, // CMPLT_PPzZI_B
|
|
137432U, // CMPLT_PPzZI_D
|
|
52440201U, // CMPLT_PPzZI_H
|
|
143576U, // CMPLT_PPzZI_S
|
|
33695960U, // CMPLT_WIDE_PPzZZ_B
|
|
2239625U, // CMPLT_WIDE_PPzZZ_H
|
|
33698008U, // CMPLT_WIDE_PPzZZ_S
|
|
141528U, // CMPNE_PPzZI_B
|
|
137432U, // CMPNE_PPzZI_D
|
|
52440201U, // CMPNE_PPzZI_H
|
|
143576U, // CMPNE_PPzZI_S
|
|
16918744U, // CMPNE_PPzZZ_B
|
|
33691864U, // CMPNE_PPzZZ_D
|
|
51129481U, // CMPNE_PPzZZ_H
|
|
67252440U, // CMPNE_PPzZZ_S
|
|
33695960U, // CMPNE_WIDE_PPzZZ_B
|
|
2239625U, // CMPNE_WIDE_PPzZZ_H
|
|
33698008U, // CMPNE_WIDE_PPzZZ_S
|
|
925840U, // CMTSTv16i8
|
|
3160U, // CMTSTv1i64
|
|
1056920U, // CMTSTv2i32
|
|
270440U, // CMTSTv2i64
|
|
1188000U, // CMTSTv4i16
|
|
401520U, // CMTSTv4i32
|
|
532600U, // CMTSTv8i16
|
|
1319080U, // CMTSTv8i8
|
|
8U, // CNOT_ZPmZ_B
|
|
16U, // CNOT_ZPmZ_D
|
|
0U, // CNOT_ZPmZ_H
|
|
24U, // CNOT_ZPmZ_S
|
|
345U, // CNTB_XPiI
|
|
345U, // CNTD_XPiI
|
|
345U, // CNTH_XPiI
|
|
1U, // CNTP_XCI_B
|
|
1U, // CNTP_XCI_D
|
|
1U, // CNTP_XCI_H
|
|
1U, // CNTP_XCI_S
|
|
10328U, // CNTP_XPP_B
|
|
6232U, // CNTP_XPP_D
|
|
5208U, // CNTP_XPP_H
|
|
12376U, // CNTP_XPP_S
|
|
345U, // CNTW_XPiI
|
|
0U, // CNTWr
|
|
0U, // CNTXr
|
|
8U, // CNT_ZPmZ_B
|
|
16U, // CNT_ZPmZ_D
|
|
0U, // CNT_ZPmZ_H
|
|
24U, // CNT_ZPmZ_S
|
|
32U, // CNTv16i8
|
|
80U, // CNTv8i8
|
|
6232U, // COMPACT_ZPZ_D
|
|
12376U, // COMPACT_ZPZ_S
|
|
0U, // CPYE
|
|
0U, // CPYEN
|
|
0U, // CPYERN
|
|
0U, // CPYERT
|
|
0U, // CPYERTN
|
|
0U, // CPYERTRN
|
|
0U, // CPYERTWN
|
|
0U, // CPYET
|
|
0U, // CPYETN
|
|
0U, // CPYETRN
|
|
0U, // CPYETWN
|
|
0U, // CPYEWN
|
|
0U, // CPYEWT
|
|
0U, // CPYEWTN
|
|
0U, // CPYEWTRN
|
|
0U, // CPYEWTWN
|
|
0U, // CPYFE
|
|
0U, // CPYFEN
|
|
0U, // CPYFERN
|
|
0U, // CPYFERT
|
|
0U, // CPYFERTN
|
|
0U, // CPYFERTRN
|
|
0U, // CPYFERTWN
|
|
0U, // CPYFET
|
|
0U, // CPYFETN
|
|
0U, // CPYFETRN
|
|
0U, // CPYFETWN
|
|
0U, // CPYFEWN
|
|
0U, // CPYFEWT
|
|
0U, // CPYFEWTN
|
|
0U, // CPYFEWTRN
|
|
0U, // CPYFEWTWN
|
|
0U, // CPYFM
|
|
0U, // CPYFMN
|
|
0U, // CPYFMRN
|
|
0U, // CPYFMRT
|
|
0U, // CPYFMRTN
|
|
0U, // CPYFMRTRN
|
|
0U, // CPYFMRTWN
|
|
0U, // CPYFMT
|
|
0U, // CPYFMTN
|
|
0U, // CPYFMTRN
|
|
0U, // CPYFMTWN
|
|
0U, // CPYFMWN
|
|
0U, // CPYFMWT
|
|
0U, // CPYFMWTN
|
|
0U, // CPYFMWTRN
|
|
0U, // CPYFMWTWN
|
|
0U, // CPYFP
|
|
0U, // CPYFPN
|
|
0U, // CPYFPRN
|
|
0U, // CPYFPRT
|
|
0U, // CPYFPRTN
|
|
0U, // CPYFPRTRN
|
|
0U, // CPYFPRTWN
|
|
0U, // CPYFPT
|
|
0U, // CPYFPTN
|
|
0U, // CPYFPTRN
|
|
0U, // CPYFPTWN
|
|
0U, // CPYFPWN
|
|
0U, // CPYFPWT
|
|
0U, // CPYFPWTN
|
|
0U, // CPYFPWTRN
|
|
0U, // CPYFPWTWN
|
|
0U, // CPYM
|
|
0U, // CPYMN
|
|
0U, // CPYMRN
|
|
0U, // CPYMRT
|
|
0U, // CPYMRTN
|
|
0U, // CPYMRTRN
|
|
0U, // CPYMRTWN
|
|
0U, // CPYMT
|
|
0U, // CPYMTN
|
|
0U, // CPYMTRN
|
|
0U, // CPYMTWN
|
|
0U, // CPYMWN
|
|
0U, // CPYMWT
|
|
0U, // CPYMWTN
|
|
0U, // CPYMWTRN
|
|
0U, // CPYMWTWN
|
|
0U, // CPYP
|
|
0U, // CPYPN
|
|
0U, // CPYPRN
|
|
0U, // CPYPRT
|
|
0U, // CPYPRTN
|
|
0U, // CPYPRTRN
|
|
0U, // CPYPRTWN
|
|
0U, // CPYPT
|
|
0U, // CPYPTN
|
|
0U, // CPYPTRN
|
|
0U, // CPYPTWN
|
|
0U, // CPYPWN
|
|
0U, // CPYPWT
|
|
0U, // CPYPWTN
|
|
0U, // CPYPWTRN
|
|
0U, // CPYPWTWN
|
|
352U, // CPY_ZPmI_B
|
|
360U, // CPY_ZPmI_D
|
|
2U, // CPY_ZPmI_H
|
|
368U, // CPY_ZPmI_S
|
|
376U, // CPY_ZPmR_B
|
|
376U, // CPY_ZPmR_D
|
|
2U, // CPY_ZPmR_H
|
|
376U, // CPY_ZPmR_S
|
|
376U, // CPY_ZPmV_B
|
|
376U, // CPY_ZPmV_D
|
|
2U, // CPY_ZPmV_H
|
|
376U, // CPY_ZPmV_S
|
|
42200U, // CPY_ZPzI_B
|
|
43224U, // CPY_ZPzI_D
|
|
385U, // CPY_ZPzI_H
|
|
44248U, // CPY_ZPzI_S
|
|
3160U, // CRC32Brr
|
|
3160U, // CRC32CBrr
|
|
3160U, // CRC32CHrr
|
|
3160U, // CRC32CWrr
|
|
3160U, // CRC32CXrr
|
|
3160U, // CRC32Hrr
|
|
3160U, // CRC32Wrr
|
|
3160U, // CRC32Xrr
|
|
167906392U, // CSELWr
|
|
167906392U, // CSELXr
|
|
167906392U, // CSINCWr
|
|
167906392U, // CSINCXr
|
|
167906392U, // CSINVWr
|
|
167906392U, // CSINVXr
|
|
167906392U, // CSNEGWr
|
|
167906392U, // CSNEGXr
|
|
0U, // CTERMEQ_WW
|
|
0U, // CTERMEQ_XX
|
|
0U, // CTERMNE_WW
|
|
0U, // CTERMNE_XX
|
|
0U, // CTZWr
|
|
0U, // CTZXr
|
|
0U, // DCPS1
|
|
0U, // DCPS2
|
|
0U, // DCPS3
|
|
2U, // DECB_XPiI
|
|
2U, // DECD_XPiI
|
|
2U, // DECD_ZPiI
|
|
2U, // DECH_XPiI
|
|
0U, // DECH_ZPiI
|
|
1U, // DECP_XP_B
|
|
0U, // DECP_XP_D
|
|
0U, // DECP_XP_H
|
|
1U, // DECP_XP_S
|
|
0U, // DECP_ZP_D
|
|
0U, // DECP_ZP_H
|
|
0U, // DECP_ZP_S
|
|
2U, // DECW_XPiI
|
|
2U, // DECW_ZPiI
|
|
0U, // DMB
|
|
0U, // DRPS
|
|
0U, // DSB
|
|
0U, // DSBnXS
|
|
2U, // DUPM_ZI
|
|
393U, // DUPQ_ZZI_B
|
|
392U, // DUPQ_ZZI_D
|
|
2U, // DUPQ_ZZI_H
|
|
393U, // DUPQ_ZZI_S
|
|
2U, // DUP_ZI_B
|
|
2U, // DUP_ZI_D
|
|
0U, // DUP_ZI_H
|
|
2U, // DUP_ZI_S
|
|
0U, // DUP_ZR_B
|
|
0U, // DUP_ZR_D
|
|
0U, // DUP_ZR_H
|
|
0U, // DUP_ZR_S
|
|
393U, // DUP_ZZI_B
|
|
392U, // DUP_ZZI_D
|
|
2U, // DUP_ZZI_H
|
|
2U, // DUP_ZZI_Q
|
|
393U, // DUP_ZZI_S
|
|
45456U, // DUPi16
|
|
45464U, // DUPi32
|
|
45472U, // DUPi64
|
|
45480U, // DUPi8
|
|
0U, // DUPv16i8gpr
|
|
45480U, // DUPv16i8lane
|
|
0U, // DUPv2i32gpr
|
|
45464U, // DUPv2i32lane
|
|
0U, // DUPv2i64gpr
|
|
45472U, // DUPv2i64lane
|
|
0U, // DUPv4i16gpr
|
|
45456U, // DUPv4i16lane
|
|
0U, // DUPv4i32gpr
|
|
45464U, // DUPv4i32lane
|
|
0U, // DUPv8i16gpr
|
|
45456U, // DUPv8i16lane
|
|
0U, // DUPv8i8gpr
|
|
45480U, // DUPv8i8lane
|
|
14424U, // EONWrs
|
|
14424U, // EONXrs
|
|
86253712U, // EOR3
|
|
33691736U, // EOR3_ZZZZ
|
|
9U, // EORBT_ZZZ_B
|
|
1112U, // EORBT_ZZZ_D
|
|
240U, // EORBT_ZZZ_H
|
|
2136U, // EORBT_ZZZ_S
|
|
10328U, // EORQV_VPZ_B
|
|
6232U, // EORQV_VPZ_D
|
|
5208U, // EORQV_VPZ_H
|
|
12376U, // EORQV_VPZ_S
|
|
16918744U, // EORS_PPzPP
|
|
9U, // EORTB_ZZZ_B
|
|
1112U, // EORTB_ZZZ_D
|
|
240U, // EORTB_ZZZ_H
|
|
2136U, // EORTB_ZZZ_S
|
|
0U, // EORV_VPZ_B
|
|
0U, // EORV_VPZ_D
|
|
0U, // EORV_VPZ_H
|
|
0U, // EORV_VPZ_S
|
|
35928U, // EORWri
|
|
14424U, // EORWrs
|
|
36952U, // EORXri
|
|
14424U, // EORXrs
|
|
16918744U, // EOR_PPzPP
|
|
36952U, // EOR_ZI
|
|
16918656U, // EOR_ZPmZ_B
|
|
33691776U, // EOR_ZPmZ_D
|
|
51129480U, // EOR_ZPmZ_H
|
|
67252352U, // EOR_ZPmZ_S
|
|
6232U, // EOR_ZZZ
|
|
925840U, // EORv16i8
|
|
1319080U, // EORv8i8
|
|
0U, // ERET
|
|
0U, // ERETAA
|
|
0U, // ERETAB
|
|
141401U, // EXTQ_ZZI
|
|
432U, // EXTRACT_ZPMXI_H_B
|
|
432U, // EXTRACT_ZPMXI_H_D
|
|
2U, // EXTRACT_ZPMXI_H_H
|
|
2U, // EXTRACT_ZPMXI_H_Q
|
|
432U, // EXTRACT_ZPMXI_H_S
|
|
440U, // EXTRACT_ZPMXI_V_B
|
|
440U, // EXTRACT_ZPMXI_V_D
|
|
2U, // EXTRACT_ZPMXI_V_H
|
|
2U, // EXTRACT_ZPMXI_V_Q
|
|
440U, // EXTRACT_ZPMXI_V_S
|
|
134232U, // EXTRWrri
|
|
0U, // EXTRX
|
|
134232U, // EXTRXrri
|
|
0U, // EXTRY
|
|
251799641U, // EXT_ZZI
|
|
450U, // EXT_ZZI_B
|
|
2367632U, // EXTv16i8
|
|
3809448U, // EXTv8i8
|
|
32U, // F1CVTL2v8f16
|
|
0U, // F1CVTLT_ZZ_BtoH
|
|
0U, // F1CVTL_2ZZ_BtoH_NAME
|
|
80U, // F1CVTLv8f16
|
|
0U, // F1CVT_2ZZ_BtoH_NAME
|
|
0U, // F1CVT_ZZ_BtoH
|
|
32U, // F2CVTL2v8f16
|
|
0U, // F2CVTLT_ZZ_BtoH
|
|
0U, // F2CVTL_2ZZ_BtoH_NAME
|
|
80U, // F2CVTLv8f16
|
|
0U, // F2CVT_2ZZ_BtoH_NAME
|
|
0U, // F2CVT_ZZ_BtoH
|
|
3160U, // FABD16
|
|
3160U, // FABD32
|
|
3160U, // FABD64
|
|
33691776U, // FABD_ZPmZ_D
|
|
51129480U, // FABD_ZPmZ_H
|
|
67252352U, // FABD_ZPmZ_S
|
|
1056920U, // FABDv2f32
|
|
270440U, // FABDv2f64
|
|
1188000U, // FABDv4f16
|
|
401520U, // FABDv4f32
|
|
532600U, // FABDv8f16
|
|
0U, // FABSDr
|
|
0U, // FABSHr
|
|
0U, // FABSSr
|
|
16U, // FABS_ZPmZ_D
|
|
0U, // FABS_ZPmZ_H
|
|
24U, // FABS_ZPmZ_S
|
|
40U, // FABSv2f32
|
|
48U, // FABSv2f64
|
|
56U, // FABSv4f16
|
|
64U, // FABSv4f32
|
|
72U, // FABSv8f16
|
|
3160U, // FACGE16
|
|
3160U, // FACGE32
|
|
3160U, // FACGE64
|
|
33691864U, // FACGE_PPzZZ_D
|
|
51129481U, // FACGE_PPzZZ_H
|
|
67252440U, // FACGE_PPzZZ_S
|
|
1056920U, // FACGEv2f32
|
|
270440U, // FACGEv2f64
|
|
1188000U, // FACGEv4f16
|
|
401520U, // FACGEv4f32
|
|
532600U, // FACGEv8f16
|
|
3160U, // FACGT16
|
|
3160U, // FACGT32
|
|
3160U, // FACGT64
|
|
33691864U, // FACGT_PPzZZ_D
|
|
51129481U, // FACGT_PPzZZ_H
|
|
67252440U, // FACGT_PPzZZ_S
|
|
1056920U, // FACGTv2f32
|
|
270440U, // FACGTv2f64
|
|
1188000U, // FACGTv4f16
|
|
401520U, // FACGTv4f32
|
|
532600U, // FACGTv8f16
|
|
0U, // FADDA_VPZ_D
|
|
240U, // FADDA_VPZ_H
|
|
0U, // FADDA_VPZ_S
|
|
3160U, // FADDDrr
|
|
3160U, // FADDHrr
|
|
33691776U, // FADDP_ZPmZZ_D
|
|
51129480U, // FADDP_ZPmZZ_H
|
|
67252352U, // FADDP_ZPmZZ_S
|
|
1056920U, // FADDPv2f32
|
|
270440U, // FADDPv2f64
|
|
456U, // FADDPv2i16p
|
|
40U, // FADDPv2i32p
|
|
48U, // FADDPv2i64p
|
|
1188000U, // FADDPv4f16
|
|
401520U, // FADDPv4f32
|
|
532600U, // FADDPv8f16
|
|
6232U, // FADDQV_D
|
|
5208U, // FADDQV_H
|
|
12376U, // FADDQV_S
|
|
3160U, // FADDSrr
|
|
0U, // FADDV_VPZ_D
|
|
0U, // FADDV_VPZ_H
|
|
0U, // FADDV_VPZ_S
|
|
192U, // FADD_VG2_M2Z_D
|
|
232U, // FADD_VG2_M2Z_H
|
|
200U, // FADD_VG2_M2Z_S
|
|
192U, // FADD_VG4_M4Z_D
|
|
232U, // FADD_VG4_M4Z_H
|
|
200U, // FADD_VG4_M4Z_S
|
|
268572800U, // FADD_ZPmI_D
|
|
3943560U, // FADD_ZPmI_H
|
|
268578944U, // FADD_ZPmI_S
|
|
33691776U, // FADD_ZPmZ_D
|
|
51129480U, // FADD_ZPmZ_H
|
|
67252352U, // FADD_ZPmZ_S
|
|
6232U, // FADD_ZZZ_D
|
|
136U, // FADD_ZZZ_H
|
|
12377U, // FADD_ZZZ_S
|
|
1056920U, // FADDv2f32
|
|
270440U, // FADDv2f64
|
|
1188000U, // FADDv4f16
|
|
401520U, // FADDv4f32
|
|
532600U, // FADDv8f16
|
|
464U, // FAMAX_2Z2Z_D
|
|
248U, // FAMAX_2Z2Z_H
|
|
472U, // FAMAX_2Z2Z_S
|
|
464U, // FAMAX_4Z4Z_D
|
|
248U, // FAMAX_4Z4Z_H
|
|
472U, // FAMAX_4Z4Z_S
|
|
33691776U, // FAMAX_ZPmZ_D
|
|
51129480U, // FAMAX_ZPmZ_H
|
|
67252352U, // FAMAX_ZPmZ_S
|
|
1056920U, // FAMAXv2f32
|
|
270440U, // FAMAXv2f64
|
|
1188000U, // FAMAXv4f16
|
|
401520U, // FAMAXv4f32
|
|
532600U, // FAMAXv8f16
|
|
464U, // FAMIN_2Z2Z_D
|
|
248U, // FAMIN_2Z2Z_H
|
|
472U, // FAMIN_2Z2Z_S
|
|
464U, // FAMIN_4Z4Z_D
|
|
248U, // FAMIN_4Z4Z_H
|
|
472U, // FAMIN_4Z4Z_S
|
|
33691776U, // FAMIN_ZPmZ_D
|
|
51129480U, // FAMIN_ZPmZ_H
|
|
67252352U, // FAMIN_ZPmZ_S
|
|
1056920U, // FAMINv2f32
|
|
270440U, // FAMINv2f64
|
|
1188000U, // FAMINv4f16
|
|
401520U, // FAMINv4f32
|
|
532600U, // FAMINv8f16
|
|
33691776U, // FCADD_ZPmZ_D
|
|
185347208U, // FCADD_ZPmZ_H
|
|
67252352U, // FCADD_ZPmZ_S
|
|
155066520U, // FCADDv2f32
|
|
155197544U, // FCADDv2f64
|
|
155328672U, // FCADDv4f16
|
|
155459696U, // FCADDv4f32
|
|
155590776U, // FCADDv8f16
|
|
167906392U, // FCCMPDrr
|
|
167906392U, // FCCMPEDrr
|
|
167906392U, // FCCMPEHrr
|
|
167906392U, // FCCMPESrr
|
|
167906392U, // FCCMPHrr
|
|
167906392U, // FCCMPSrr
|
|
16U, // FCLAMP_VG2_2Z2Z_D
|
|
240U, // FCLAMP_VG2_2Z2Z_H
|
|
24U, // FCLAMP_VG2_2Z2Z_S
|
|
16U, // FCLAMP_VG4_4Z4Z_D
|
|
240U, // FCLAMP_VG4_4Z4Z_H
|
|
24U, // FCLAMP_VG4_4Z4Z_S
|
|
1112U, // FCLAMP_ZZZ_D
|
|
240U, // FCLAMP_ZZZ_H
|
|
2136U, // FCLAMP_ZZZ_S
|
|
3160U, // FCMEQ16
|
|
3160U, // FCMEQ32
|
|
3160U, // FCMEQ64
|
|
4724952U, // FCMEQ_PPzZ0_D
|
|
46217U, // FCMEQ_PPzZ0_H
|
|
4731096U, // FCMEQ_PPzZ0_S
|
|
33691864U, // FCMEQ_PPzZZ_D
|
|
51129481U, // FCMEQ_PPzZZ_H
|
|
67252440U, // FCMEQ_PPzZZ_S
|
|
480U, // FCMEQv1i16rz
|
|
480U, // FCMEQv1i32rz
|
|
480U, // FCMEQv1i64rz
|
|
1056920U, // FCMEQv2f32
|
|
270440U, // FCMEQv2f64
|
|
488U, // FCMEQv2i32rz
|
|
496U, // FCMEQv2i64rz
|
|
1188000U, // FCMEQv4f16
|
|
401520U, // FCMEQv4f32
|
|
504U, // FCMEQv4i16rz
|
|
512U, // FCMEQv4i32rz
|
|
532600U, // FCMEQv8f16
|
|
520U, // FCMEQv8i16rz
|
|
3160U, // FCMGE16
|
|
3160U, // FCMGE32
|
|
3160U, // FCMGE64
|
|
4724952U, // FCMGE_PPzZ0_D
|
|
46217U, // FCMGE_PPzZ0_H
|
|
4731096U, // FCMGE_PPzZ0_S
|
|
33691864U, // FCMGE_PPzZZ_D
|
|
51129481U, // FCMGE_PPzZZ_H
|
|
67252440U, // FCMGE_PPzZZ_S
|
|
480U, // FCMGEv1i16rz
|
|
480U, // FCMGEv1i32rz
|
|
480U, // FCMGEv1i64rz
|
|
1056920U, // FCMGEv2f32
|
|
270440U, // FCMGEv2f64
|
|
488U, // FCMGEv2i32rz
|
|
496U, // FCMGEv2i64rz
|
|
1188000U, // FCMGEv4f16
|
|
401520U, // FCMGEv4f32
|
|
504U, // FCMGEv4i16rz
|
|
512U, // FCMGEv4i32rz
|
|
532600U, // FCMGEv8f16
|
|
520U, // FCMGEv8i16rz
|
|
3160U, // FCMGT16
|
|
3160U, // FCMGT32
|
|
3160U, // FCMGT64
|
|
4724952U, // FCMGT_PPzZ0_D
|
|
46217U, // FCMGT_PPzZ0_H
|
|
4731096U, // FCMGT_PPzZ0_S
|
|
33691864U, // FCMGT_PPzZZ_D
|
|
51129481U, // FCMGT_PPzZZ_H
|
|
67252440U, // FCMGT_PPzZZ_S
|
|
480U, // FCMGTv1i16rz
|
|
480U, // FCMGTv1i32rz
|
|
480U, // FCMGTv1i64rz
|
|
1056920U, // FCMGTv2f32
|
|
270440U, // FCMGTv2f64
|
|
488U, // FCMGTv2i32rz
|
|
496U, // FCMGTv2i64rz
|
|
1188000U, // FCMGTv4f16
|
|
401520U, // FCMGTv4f32
|
|
504U, // FCMGTv4i16rz
|
|
512U, // FCMGTv4i32rz
|
|
532600U, // FCMGTv8f16
|
|
520U, // FCMGTv8i16rz
|
|
285344896U, // FCMLA_ZPmZZ_D
|
|
187706608U, // FCMLA_ZPmZZ_H
|
|
302123136U, // FCMLA_ZPmZZ_S
|
|
201496816U, // FCMLA_ZZZI_H
|
|
187435096U, // FCMLA_ZZZI_S
|
|
222176408U, // FCMLAv2f32
|
|
222307432U, // FCMLAv2f64
|
|
222438560U, // FCMLAv4f16
|
|
120464544U, // FCMLAv4f16_indexed
|
|
222569584U, // FCMLAv4f32
|
|
122299504U, // FCMLAv4f32_indexed
|
|
222700664U, // FCMLAv8f16
|
|
120464504U, // FCMLAv8f16_indexed
|
|
4724952U, // FCMLE_PPzZ0_D
|
|
46217U, // FCMLE_PPzZ0_H
|
|
4731096U, // FCMLE_PPzZ0_S
|
|
480U, // FCMLEv1i16rz
|
|
480U, // FCMLEv1i32rz
|
|
480U, // FCMLEv1i64rz
|
|
488U, // FCMLEv2i32rz
|
|
496U, // FCMLEv2i64rz
|
|
504U, // FCMLEv4i16rz
|
|
512U, // FCMLEv4i32rz
|
|
520U, // FCMLEv8i16rz
|
|
4724952U, // FCMLT_PPzZ0_D
|
|
46217U, // FCMLT_PPzZ0_H
|
|
4731096U, // FCMLT_PPzZ0_S
|
|
480U, // FCMLTv1i16rz
|
|
480U, // FCMLTv1i32rz
|
|
480U, // FCMLTv1i64rz
|
|
488U, // FCMLTv2i32rz
|
|
496U, // FCMLTv2i64rz
|
|
504U, // FCMLTv4i16rz
|
|
512U, // FCMLTv4i32rz
|
|
520U, // FCMLTv8i16rz
|
|
4724952U, // FCMNE_PPzZ0_D
|
|
46217U, // FCMNE_PPzZ0_H
|
|
4731096U, // FCMNE_PPzZ0_S
|
|
33691864U, // FCMNE_PPzZZ_D
|
|
51129481U, // FCMNE_PPzZZ_H
|
|
67252440U, // FCMNE_PPzZZ_S
|
|
0U, // FCMPDri
|
|
0U, // FCMPDrr
|
|
0U, // FCMPEDri
|
|
0U, // FCMPEDrr
|
|
0U, // FCMPEHri
|
|
0U, // FCMPEHrr
|
|
0U, // FCMPESri
|
|
0U, // FCMPESrr
|
|
0U, // FCMPHri
|
|
0U, // FCMPHrr
|
|
0U, // FCMPSri
|
|
0U, // FCMPSrr
|
|
33691864U, // FCMUO_PPzZZ_D
|
|
51129481U, // FCMUO_PPzZZ_H
|
|
67252440U, // FCMUO_PPzZZ_S
|
|
528U, // FCPY_ZPmI_D
|
|
2U, // FCPY_ZPmI_H
|
|
528U, // FCPY_ZPmI_S
|
|
167906392U, // FCSELDrrr
|
|
167906392U, // FCSELHrrr
|
|
167906392U, // FCSELSrrr
|
|
0U, // FCVTASUWDr
|
|
0U, // FCVTASUWHr
|
|
0U, // FCVTASUWSr
|
|
0U, // FCVTASUXDr
|
|
0U, // FCVTASUXHr
|
|
0U, // FCVTASUXSr
|
|
0U, // FCVTASv1f16
|
|
0U, // FCVTASv1i32
|
|
0U, // FCVTASv1i64
|
|
40U, // FCVTASv2f32
|
|
48U, // FCVTASv2f64
|
|
56U, // FCVTASv4f16
|
|
64U, // FCVTASv4f32
|
|
72U, // FCVTASv8f16
|
|
0U, // FCVTAUUWDr
|
|
0U, // FCVTAUUWHr
|
|
0U, // FCVTAUUWSr
|
|
0U, // FCVTAUUXDr
|
|
0U, // FCVTAUUXHr
|
|
0U, // FCVTAUUXSr
|
|
0U, // FCVTAUv1f16
|
|
0U, // FCVTAUv1i32
|
|
0U, // FCVTAUv1i64
|
|
40U, // FCVTAUv2f32
|
|
48U, // FCVTAUv2f64
|
|
56U, // FCVTAUv4f16
|
|
64U, // FCVTAUv4f32
|
|
72U, // FCVTAUv8f16
|
|
0U, // FCVTDHr
|
|
0U, // FCVTDSr
|
|
0U, // FCVTHDr
|
|
0U, // FCVTHSr
|
|
240U, // FCVTLT_ZPmZ_HtoS
|
|
24U, // FCVTLT_ZPmZ_StoD
|
|
0U, // FCVTL_2ZZ_H_S
|
|
40U, // FCVTLv2i32
|
|
56U, // FCVTLv4i16
|
|
64U, // FCVTLv4i32
|
|
72U, // FCVTLv8i16
|
|
0U, // FCVTMSUWDr
|
|
0U, // FCVTMSUWHr
|
|
0U, // FCVTMSUWSr
|
|
0U, // FCVTMSUXDr
|
|
0U, // FCVTMSUXHr
|
|
0U, // FCVTMSUXSr
|
|
0U, // FCVTMSv1f16
|
|
0U, // FCVTMSv1i32
|
|
0U, // FCVTMSv1i64
|
|
40U, // FCVTMSv2f32
|
|
48U, // FCVTMSv2f64
|
|
56U, // FCVTMSv4f16
|
|
64U, // FCVTMSv4f32
|
|
72U, // FCVTMSv8f16
|
|
0U, // FCVTMUUWDr
|
|
0U, // FCVTMUUWHr
|
|
0U, // FCVTMUUWSr
|
|
0U, // FCVTMUUXDr
|
|
0U, // FCVTMUUXHr
|
|
0U, // FCVTMUUXSr
|
|
0U, // FCVTMUv1f16
|
|
0U, // FCVTMUv1i32
|
|
0U, // FCVTMUv1i64
|
|
40U, // FCVTMUv2f32
|
|
48U, // FCVTMUv2f64
|
|
56U, // FCVTMUv4f16
|
|
64U, // FCVTMUv4f32
|
|
72U, // FCVTMUv8f16
|
|
2U, // FCVTNB_Z2Z_StoB
|
|
0U, // FCVTNSUWDr
|
|
0U, // FCVTNSUWHr
|
|
0U, // FCVTNSUWSr
|
|
0U, // FCVTNSUXDr
|
|
0U, // FCVTNSUXHr
|
|
0U, // FCVTNSUXSr
|
|
0U, // FCVTNSv1f16
|
|
0U, // FCVTNSv1i32
|
|
0U, // FCVTNSv1i64
|
|
40U, // FCVTNSv2f32
|
|
48U, // FCVTNSv2f64
|
|
56U, // FCVTNSv4f16
|
|
64U, // FCVTNSv4f32
|
|
72U, // FCVTNSv8f16
|
|
2U, // FCVTNT_Z2Z_StoB
|
|
16U, // FCVTNT_ZPmZ_DtoS
|
|
1U, // FCVTNT_ZPmZ_StoH
|
|
0U, // FCVTNUUWDr
|
|
0U, // FCVTNUUWHr
|
|
0U, // FCVTNUUWSr
|
|
0U, // FCVTNUUXDr
|
|
0U, // FCVTNUUXHr
|
|
0U, // FCVTNUUXSr
|
|
0U, // FCVTNUv1f16
|
|
0U, // FCVTNUv1i32
|
|
0U, // FCVTNUv1i64
|
|
40U, // FCVTNUv2f32
|
|
48U, // FCVTNUv2f64
|
|
56U, // FCVTNUv4f16
|
|
64U, // FCVTNUv4f32
|
|
72U, // FCVTNUv8f16
|
|
532600U, // FCVTN_F16_F8v16f8
|
|
1188000U, // FCVTN_F16_F8v8f8
|
|
402544U, // FCVTN_F32_F82v16f8
|
|
401520U, // FCVTN_F32_F8v8f8
|
|
1U, // FCVTN_Z2Z_HtoB
|
|
0U, // FCVTN_Z2Z_StoH
|
|
2U, // FCVTN_Z4Z_StoB_NAME
|
|
48U, // FCVTNv2i32
|
|
64U, // FCVTNv4i16
|
|
48U, // FCVTNv4i32
|
|
64U, // FCVTNv8i16
|
|
0U, // FCVTPSUWDr
|
|
0U, // FCVTPSUWHr
|
|
0U, // FCVTPSUWSr
|
|
0U, // FCVTPSUXDr
|
|
0U, // FCVTPSUXHr
|
|
0U, // FCVTPSUXSr
|
|
0U, // FCVTPSv1f16
|
|
0U, // FCVTPSv1i32
|
|
0U, // FCVTPSv1i64
|
|
40U, // FCVTPSv2f32
|
|
48U, // FCVTPSv2f64
|
|
56U, // FCVTPSv4f16
|
|
64U, // FCVTPSv4f32
|
|
72U, // FCVTPSv8f16
|
|
0U, // FCVTPUUWDr
|
|
0U, // FCVTPUUWHr
|
|
0U, // FCVTPUUWSr
|
|
0U, // FCVTPUUXDr
|
|
0U, // FCVTPUUXHr
|
|
0U, // FCVTPUUXSr
|
|
0U, // FCVTPUv1f16
|
|
0U, // FCVTPUv1i32
|
|
0U, // FCVTPUv1i64
|
|
40U, // FCVTPUv2f32
|
|
48U, // FCVTPUv2f64
|
|
56U, // FCVTPUv4f16
|
|
64U, // FCVTPUv4f32
|
|
72U, // FCVTPUv8f16
|
|
0U, // FCVTSDr
|
|
0U, // FCVTSHr
|
|
16U, // FCVTXNT_ZPmZ_DtoS
|
|
0U, // FCVTXNv1i64
|
|
48U, // FCVTXNv2f32
|
|
48U, // FCVTXNv4f32
|
|
16U, // FCVTX_ZPmZ_DtoS
|
|
3160U, // FCVTZSSWDri
|
|
3160U, // FCVTZSSWHri
|
|
3160U, // FCVTZSSWSri
|
|
3160U, // FCVTZSSXDri
|
|
3160U, // FCVTZSSXHri
|
|
3160U, // FCVTZSSXSri
|
|
0U, // FCVTZSUWDr
|
|
0U, // FCVTZSUWHr
|
|
0U, // FCVTZSUWSr
|
|
0U, // FCVTZSUXDr
|
|
0U, // FCVTZSUXHr
|
|
0U, // FCVTZSUXSr
|
|
0U, // FCVTZS_2Z2Z_StoS
|
|
0U, // FCVTZS_4Z4Z_StoS
|
|
16U, // FCVTZS_ZPmZ_DtoD
|
|
16U, // FCVTZS_ZPmZ_DtoS
|
|
240U, // FCVTZS_ZPmZ_HtoD
|
|
0U, // FCVTZS_ZPmZ_HtoH
|
|
240U, // FCVTZS_ZPmZ_HtoS
|
|
24U, // FCVTZS_ZPmZ_StoD
|
|
24U, // FCVTZS_ZPmZ_StoS
|
|
3160U, // FCVTZSd
|
|
3160U, // FCVTZSh
|
|
3160U, // FCVTZSs
|
|
0U, // FCVTZSv1f16
|
|
0U, // FCVTZSv1i32
|
|
0U, // FCVTZSv1i64
|
|
40U, // FCVTZSv2f32
|
|
48U, // FCVTZSv2f64
|
|
3224U, // FCVTZSv2i32_shift
|
|
3176U, // FCVTZSv2i64_shift
|
|
56U, // FCVTZSv4f16
|
|
64U, // FCVTZSv4f32
|
|
3232U, // FCVTZSv4i16_shift
|
|
3184U, // FCVTZSv4i32_shift
|
|
72U, // FCVTZSv8f16
|
|
3192U, // FCVTZSv8i16_shift
|
|
3160U, // FCVTZUSWDri
|
|
3160U, // FCVTZUSWHri
|
|
3160U, // FCVTZUSWSri
|
|
3160U, // FCVTZUSXDri
|
|
3160U, // FCVTZUSXHri
|
|
3160U, // FCVTZUSXSri
|
|
0U, // FCVTZUUWDr
|
|
0U, // FCVTZUUWHr
|
|
0U, // FCVTZUUWSr
|
|
0U, // FCVTZUUXDr
|
|
0U, // FCVTZUUXHr
|
|
0U, // FCVTZUUXSr
|
|
0U, // FCVTZU_2Z2Z_StoS
|
|
0U, // FCVTZU_4Z4Z_StoS
|
|
16U, // FCVTZU_ZPmZ_DtoD
|
|
16U, // FCVTZU_ZPmZ_DtoS
|
|
240U, // FCVTZU_ZPmZ_HtoD
|
|
0U, // FCVTZU_ZPmZ_HtoH
|
|
240U, // FCVTZU_ZPmZ_HtoS
|
|
24U, // FCVTZU_ZPmZ_StoD
|
|
24U, // FCVTZU_ZPmZ_StoS
|
|
3160U, // FCVTZUd
|
|
3160U, // FCVTZUh
|
|
3160U, // FCVTZUs
|
|
0U, // FCVTZUv1f16
|
|
0U, // FCVTZUv1i32
|
|
0U, // FCVTZUv1i64
|
|
40U, // FCVTZUv2f32
|
|
48U, // FCVTZUv2f64
|
|
3224U, // FCVTZUv2i32_shift
|
|
3176U, // FCVTZUv2i64_shift
|
|
56U, // FCVTZUv4f16
|
|
64U, // FCVTZUv4f32
|
|
3232U, // FCVTZUv4i16_shift
|
|
3184U, // FCVTZUv4i32_shift
|
|
72U, // FCVTZUv8f16
|
|
3192U, // FCVTZUv8i16_shift
|
|
0U, // FCVT_2ZZ_H_S
|
|
1U, // FCVT_Z2Z_HtoB
|
|
0U, // FCVT_Z2Z_StoH
|
|
2U, // FCVT_Z4Z_StoB_NAME
|
|
2U, // FCVT_ZPmZ_DtoH
|
|
16U, // FCVT_ZPmZ_DtoS
|
|
240U, // FCVT_ZPmZ_HtoD
|
|
240U, // FCVT_ZPmZ_HtoS
|
|
24U, // FCVT_ZPmZ_StoD
|
|
1U, // FCVT_ZPmZ_StoH
|
|
3160U, // FDIVDrr
|
|
3160U, // FDIVHrr
|
|
33691776U, // FDIVR_ZPmZ_D
|
|
51129480U, // FDIVR_ZPmZ_H
|
|
67252352U, // FDIVR_ZPmZ_S
|
|
3160U, // FDIVSrr
|
|
33691776U, // FDIV_ZPmZ_D
|
|
51129480U, // FDIV_ZPmZ_H
|
|
67252352U, // FDIV_ZPmZ_S
|
|
1056920U, // FDIVv2f32
|
|
270440U, // FDIVv2f64
|
|
1188000U, // FDIVv4f16
|
|
401520U, // FDIVv4f32
|
|
532600U, // FDIVv8f16
|
|
47640U, // FDOT_VG2_M2Z2Z_BtoH
|
|
47640U, // FDOT_VG2_M2Z2Z_BtoS
|
|
2632936U, // FDOT_VG2_M2Z2Z_HtoS
|
|
5029400U, // FDOT_VG2_M2ZZI_BtoH
|
|
5029400U, // FDOT_VG2_M2ZZI_BtoS
|
|
103427304U, // FDOT_VG2_M2ZZI_HtoS
|
|
48664U, // FDOT_VG2_M2ZZ_BtoH
|
|
48664U, // FDOT_VG2_M2ZZ_BtoS
|
|
53095656U, // FDOT_VG2_M2ZZ_HtoS
|
|
47640U, // FDOT_VG4_M4Z4Z_BtoH
|
|
47640U, // FDOT_VG4_M4Z4Z_BtoS
|
|
2632936U, // FDOT_VG4_M4Z4Z_HtoS
|
|
5029400U, // FDOT_VG4_M4ZZI_BtoH
|
|
5029400U, // FDOT_VG4_M4ZZI_BtoS
|
|
103427304U, // FDOT_VG4_M4ZZI_HtoS
|
|
48664U, // FDOT_VG4_M4ZZ_BtoH
|
|
48664U, // FDOT_VG4_M4ZZ_BtoS
|
|
53095656U, // FDOT_VG4_M4ZZ_HtoS
|
|
38920U, // FDOT_ZZZI_BtoH
|
|
38921U, // FDOT_ZZZI_BtoS
|
|
53222488U, // FDOT_ZZZI_S
|
|
8U, // FDOT_ZZZ_BtoH
|
|
9U, // FDOT_ZZZ_BtoS
|
|
7256U, // FDOT_ZZZ_S
|
|
5121168U, // FDOTlanev16f8
|
|
5252264U, // FDOTlanev4f16
|
|
5252240U, // FDOTlanev8f16
|
|
5121192U, // FDOTlanev8f8
|
|
1320104U, // FDOTv2f32
|
|
1320104U, // FDOTv4f16
|
|
926864U, // FDOTv4f32
|
|
926864U, // FDOTv8f16
|
|
2U, // FDUP_ZI_D
|
|
0U, // FDUP_ZI_H
|
|
2U, // FDUP_ZI_S
|
|
0U, // FEXPA_ZZ_D
|
|
0U, // FEXPA_ZZ_H
|
|
1U, // FEXPA_ZZ_S
|
|
0U, // FJCVTZS
|
|
16U, // FLOGB_ZPmZ_D
|
|
0U, // FLOGB_ZPmZ_H
|
|
24U, // FLOGB_ZPmZ_S
|
|
0U, // FMA16
|
|
0U, // FMA32
|
|
0U, // FMA64
|
|
134232U, // FMADDDrrr
|
|
134232U, // FMADDHrrr
|
|
134232U, // FMADDSrrr
|
|
285344896U, // FMAD_ZPmZZ_D
|
|
53488880U, // FMAD_ZPmZZ_H
|
|
302123136U, // FMAD_ZPmZZ_S
|
|
3160U, // FMAXDrr
|
|
3160U, // FMAXHrr
|
|
3160U, // FMAXNMDrr
|
|
3160U, // FMAXNMHrr
|
|
33691776U, // FMAXNMP_ZPmZZ_D
|
|
51129480U, // FMAXNMP_ZPmZZ_H
|
|
67252352U, // FMAXNMP_ZPmZZ_S
|
|
1056920U, // FMAXNMPv2f32
|
|
270440U, // FMAXNMPv2f64
|
|
456U, // FMAXNMPv2i16p
|
|
40U, // FMAXNMPv2i32p
|
|
48U, // FMAXNMPv2i64p
|
|
1188000U, // FMAXNMPv4f16
|
|
401520U, // FMAXNMPv4f32
|
|
532600U, // FMAXNMPv8f16
|
|
6232U, // FMAXNMQV_D
|
|
5208U, // FMAXNMQV_H
|
|
12376U, // FMAXNMQV_S
|
|
3160U, // FMAXNMSrr
|
|
0U, // FMAXNMV_VPZ_D
|
|
0U, // FMAXNMV_VPZ_H
|
|
0U, // FMAXNMV_VPZ_S
|
|
56U, // FMAXNMVv4i16v
|
|
64U, // FMAXNMVv4i32v
|
|
72U, // FMAXNMVv8i16v
|
|
464U, // FMAXNM_VG2_2Z2Z_D
|
|
248U, // FMAXNM_VG2_2Z2Z_H
|
|
472U, // FMAXNM_VG2_2Z2Z_S
|
|
184U, // FMAXNM_VG2_2ZZ_D
|
|
136U, // FMAXNM_VG2_2ZZ_H
|
|
96U, // FMAXNM_VG2_2ZZ_S
|
|
464U, // FMAXNM_VG4_4Z4Z_D
|
|
248U, // FMAXNM_VG4_4Z4Z_H
|
|
472U, // FMAXNM_VG4_4Z4Z_S
|
|
184U, // FMAXNM_VG4_4ZZ_D
|
|
136U, // FMAXNM_VG4_4ZZ_H
|
|
96U, // FMAXNM_VG4_4ZZ_S
|
|
318904448U, // FMAXNM_ZPmI_D
|
|
5385352U, // FMAXNM_ZPmI_H
|
|
318910592U, // FMAXNM_ZPmI_S
|
|
33691776U, // FMAXNM_ZPmZ_D
|
|
51129480U, // FMAXNM_ZPmZ_H
|
|
67252352U, // FMAXNM_ZPmZ_S
|
|
1056920U, // FMAXNMv2f32
|
|
270440U, // FMAXNMv2f64
|
|
1188000U, // FMAXNMv4f16
|
|
401520U, // FMAXNMv4f32
|
|
532600U, // FMAXNMv8f16
|
|
33691776U, // FMAXP_ZPmZZ_D
|
|
51129480U, // FMAXP_ZPmZZ_H
|
|
67252352U, // FMAXP_ZPmZZ_S
|
|
1056920U, // FMAXPv2f32
|
|
270440U, // FMAXPv2f64
|
|
456U, // FMAXPv2i16p
|
|
40U, // FMAXPv2i32p
|
|
48U, // FMAXPv2i64p
|
|
1188000U, // FMAXPv4f16
|
|
401520U, // FMAXPv4f32
|
|
532600U, // FMAXPv8f16
|
|
6232U, // FMAXQV_D
|
|
5208U, // FMAXQV_H
|
|
12376U, // FMAXQV_S
|
|
3160U, // FMAXSrr
|
|
0U, // FMAXV_VPZ_D
|
|
0U, // FMAXV_VPZ_H
|
|
0U, // FMAXV_VPZ_S
|
|
56U, // FMAXVv4i16v
|
|
64U, // FMAXVv4i32v
|
|
72U, // FMAXVv8i16v
|
|
464U, // FMAX_VG2_2Z2Z_D
|
|
248U, // FMAX_VG2_2Z2Z_H
|
|
472U, // FMAX_VG2_2Z2Z_S
|
|
184U, // FMAX_VG2_2ZZ_D
|
|
136U, // FMAX_VG2_2ZZ_H
|
|
96U, // FMAX_VG2_2ZZ_S
|
|
464U, // FMAX_VG4_4Z4Z_D
|
|
248U, // FMAX_VG4_4Z4Z_H
|
|
472U, // FMAX_VG4_4Z4Z_S
|
|
184U, // FMAX_VG4_4ZZ_D
|
|
136U, // FMAX_VG4_4ZZ_H
|
|
96U, // FMAX_VG4_4ZZ_S
|
|
318904448U, // FMAX_ZPmI_D
|
|
5385352U, // FMAX_ZPmI_H
|
|
318910592U, // FMAX_ZPmI_S
|
|
33691776U, // FMAX_ZPmZ_D
|
|
51129480U, // FMAX_ZPmZ_H
|
|
67252352U, // FMAX_ZPmZ_S
|
|
1056920U, // FMAXv2f32
|
|
270440U, // FMAXv2f64
|
|
1188000U, // FMAXv4f16
|
|
401520U, // FMAXv4f32
|
|
532600U, // FMAXv8f16
|
|
3160U, // FMINDrr
|
|
3160U, // FMINHrr
|
|
3160U, // FMINNMDrr
|
|
3160U, // FMINNMHrr
|
|
33691776U, // FMINNMP_ZPmZZ_D
|
|
51129480U, // FMINNMP_ZPmZZ_H
|
|
67252352U, // FMINNMP_ZPmZZ_S
|
|
1056920U, // FMINNMPv2f32
|
|
270440U, // FMINNMPv2f64
|
|
456U, // FMINNMPv2i16p
|
|
40U, // FMINNMPv2i32p
|
|
48U, // FMINNMPv2i64p
|
|
1188000U, // FMINNMPv4f16
|
|
401520U, // FMINNMPv4f32
|
|
532600U, // FMINNMPv8f16
|
|
6232U, // FMINNMQV_D
|
|
5208U, // FMINNMQV_H
|
|
12376U, // FMINNMQV_S
|
|
3160U, // FMINNMSrr
|
|
0U, // FMINNMV_VPZ_D
|
|
0U, // FMINNMV_VPZ_H
|
|
0U, // FMINNMV_VPZ_S
|
|
56U, // FMINNMVv4i16v
|
|
64U, // FMINNMVv4i32v
|
|
72U, // FMINNMVv8i16v
|
|
464U, // FMINNM_VG2_2Z2Z_D
|
|
248U, // FMINNM_VG2_2Z2Z_H
|
|
472U, // FMINNM_VG2_2Z2Z_S
|
|
184U, // FMINNM_VG2_2ZZ_D
|
|
136U, // FMINNM_VG2_2ZZ_H
|
|
96U, // FMINNM_VG2_2ZZ_S
|
|
464U, // FMINNM_VG4_4Z4Z_D
|
|
248U, // FMINNM_VG4_4Z4Z_H
|
|
472U, // FMINNM_VG4_4Z4Z_S
|
|
184U, // FMINNM_VG4_4ZZ_D
|
|
136U, // FMINNM_VG4_4ZZ_H
|
|
96U, // FMINNM_VG4_4ZZ_S
|
|
318904448U, // FMINNM_ZPmI_D
|
|
5385352U, // FMINNM_ZPmI_H
|
|
318910592U, // FMINNM_ZPmI_S
|
|
33691776U, // FMINNM_ZPmZ_D
|
|
51129480U, // FMINNM_ZPmZ_H
|
|
67252352U, // FMINNM_ZPmZ_S
|
|
1056920U, // FMINNMv2f32
|
|
270440U, // FMINNMv2f64
|
|
1188000U, // FMINNMv4f16
|
|
401520U, // FMINNMv4f32
|
|
532600U, // FMINNMv8f16
|
|
33691776U, // FMINP_ZPmZZ_D
|
|
51129480U, // FMINP_ZPmZZ_H
|
|
67252352U, // FMINP_ZPmZZ_S
|
|
1056920U, // FMINPv2f32
|
|
270440U, // FMINPv2f64
|
|
456U, // FMINPv2i16p
|
|
40U, // FMINPv2i32p
|
|
48U, // FMINPv2i64p
|
|
1188000U, // FMINPv4f16
|
|
401520U, // FMINPv4f32
|
|
532600U, // FMINPv8f16
|
|
6232U, // FMINQV_D
|
|
5208U, // FMINQV_H
|
|
12376U, // FMINQV_S
|
|
3160U, // FMINSrr
|
|
0U, // FMINV_VPZ_D
|
|
0U, // FMINV_VPZ_H
|
|
0U, // FMINV_VPZ_S
|
|
56U, // FMINVv4i16v
|
|
64U, // FMINVv4i32v
|
|
72U, // FMINVv8i16v
|
|
464U, // FMIN_VG2_2Z2Z_D
|
|
248U, // FMIN_VG2_2Z2Z_H
|
|
472U, // FMIN_VG2_2Z2Z_S
|
|
184U, // FMIN_VG2_2ZZ_D
|
|
136U, // FMIN_VG2_2ZZ_H
|
|
96U, // FMIN_VG2_2ZZ_S
|
|
464U, // FMIN_VG4_4Z4Z_D
|
|
248U, // FMIN_VG4_4Z4Z_H
|
|
472U, // FMIN_VG4_4Z4Z_S
|
|
184U, // FMIN_VG4_4ZZ_D
|
|
136U, // FMIN_VG4_4ZZ_H
|
|
96U, // FMIN_VG4_4ZZ_S
|
|
318904448U, // FMIN_ZPmI_D
|
|
5385352U, // FMIN_ZPmI_H
|
|
318910592U, // FMIN_ZPmI_S
|
|
33691776U, // FMIN_ZPmZ_D
|
|
51129480U, // FMIN_ZPmZ_H
|
|
67252352U, // FMIN_ZPmZ_S
|
|
1056920U, // FMINv2f32
|
|
270440U, // FMINv2f64
|
|
1188000U, // FMINv4f16
|
|
401520U, // FMINv4f32
|
|
532600U, // FMINv8f16
|
|
49696U, // FMLAL2lanev4f16
|
|
120464544U, // FMLAL2lanev8f16
|
|
50720U, // FMLAL2v4f16
|
|
1189024U, // FMLAL2v8f16
|
|
8U, // FMLALB_ZZZ
|
|
38920U, // FMLALB_ZZZI
|
|
53222488U, // FMLALB_ZZZI_SHH
|
|
7256U, // FMLALB_ZZZ_SHH
|
|
5514384U, // FMLALBlanev8f16
|
|
926864U, // FMLALBv8f16
|
|
9U, // FMLALLBB_ZZZ
|
|
38921U, // FMLALLBB_ZZZI
|
|
5514384U, // FMLALLBBlanev4f32
|
|
926864U, // FMLALLBBv4f32
|
|
9U, // FMLALLBT_ZZZ
|
|
38921U, // FMLALLBT_ZZZI
|
|
5514384U, // FMLALLBTlanev4f32
|
|
926864U, // FMLALLBTv4f32
|
|
9U, // FMLALLTB_ZZZ
|
|
38921U, // FMLALLTB_ZZZI
|
|
5514384U, // FMLALLTBlanev4f32
|
|
926864U, // FMLALLTBv4f32
|
|
9U, // FMLALLTT_ZZZ
|
|
38921U, // FMLALLTT_ZZZI
|
|
5514384U, // FMLALLTTlanev4f32
|
|
926864U, // FMLALLTTv4f32
|
|
38441U, // FMLALL_MZZI_BtoS
|
|
553U, // FMLALL_MZZ_BtoS
|
|
47640U, // FMLALL_VG2_M2Z2Z_BtoS
|
|
5029400U, // FMLALL_VG2_M2ZZI_BtoS
|
|
48666U, // FMLALL_VG2_M2ZZ_BtoS
|
|
47640U, // FMLALL_VG4_M4Z4Z_BtoS
|
|
5029400U, // FMLALL_VG4_M4ZZI_BtoS
|
|
48667U, // FMLALL_VG4_M4ZZ_BtoS
|
|
8U, // FMLALT_ZZZ
|
|
38920U, // FMLALT_ZZZI
|
|
53222488U, // FMLALT_ZZZI_SHH
|
|
7256U, // FMLALT_ZZZ_SHH
|
|
5514384U, // FMLALTlanev8f16
|
|
926864U, // FMLALTv8f16
|
|
38441U, // FMLAL_MZZI_BtoH
|
|
38145U, // FMLAL_MZZI_HtoS
|
|
257U, // FMLAL_MZZ_HtoS
|
|
47640U, // FMLAL_VG2_M2Z2Z_BtoH
|
|
2632936U, // FMLAL_VG2_M2Z2Z_HtoS
|
|
5029400U, // FMLAL_VG2_M2ZZI_BtoH
|
|
103427304U, // FMLAL_VG2_M2ZZI_HtoS
|
|
48664U, // FMLAL_VG2_M2ZZ_BtoH
|
|
53095656U, // FMLAL_VG2_M2ZZ_HtoS
|
|
553U, // FMLAL_VG2_MZZ_BtoH
|
|
47640U, // FMLAL_VG4_M4Z4Z_BtoH
|
|
2632936U, // FMLAL_VG4_M4Z4Z_HtoS
|
|
5029400U, // FMLAL_VG4_M4ZZI_BtoH
|
|
103427304U, // FMLAL_VG4_M4ZZI_HtoS
|
|
48664U, // FMLAL_VG4_M4ZZ_BtoH
|
|
53095656U, // FMLAL_VG4_M4ZZ_HtoS
|
|
49696U, // FMLALlanev4f16
|
|
120464544U, // FMLALlanev8f16
|
|
50720U, // FMLALv4f16
|
|
1189024U, // FMLALv8f16
|
|
1584320U, // FMLA_VG2_M2Z2Z_D
|
|
1715400U, // FMLA_VG2_M2Z2Z_S
|
|
2632936U, // FMLA_VG2_M2Z4Z_H
|
|
102509760U, // FMLA_VG2_M2ZZI_D
|
|
103427304U, // FMLA_VG2_M2ZZI_H
|
|
102640840U, // FMLA_VG2_M2ZZI_S
|
|
52178112U, // FMLA_VG2_M2ZZ_D
|
|
53095656U, // FMLA_VG2_M2ZZ_H
|
|
52309192U, // FMLA_VG2_M2ZZ_S
|
|
1584320U, // FMLA_VG4_M4Z4Z_D
|
|
2632936U, // FMLA_VG4_M4Z4Z_H
|
|
1715400U, // FMLA_VG4_M4Z4Z_S
|
|
102509760U, // FMLA_VG4_M4ZZI_D
|
|
103427304U, // FMLA_VG4_M4ZZI_H
|
|
102640840U, // FMLA_VG4_M4ZZI_S
|
|
52178112U, // FMLA_VG4_M4ZZ_D
|
|
53095656U, // FMLA_VG4_M4ZZ_H
|
|
52309192U, // FMLA_VG4_M4ZZ_S
|
|
285344896U, // FMLA_ZPmZZ_D
|
|
53488880U, // FMLA_ZPmZZ_H
|
|
302123136U, // FMLA_ZPmZZ_S
|
|
53216344U, // FMLA_ZZZI_D
|
|
39152U, // FMLA_ZZZI_H
|
|
53217368U, // FMLA_ZZZI_S
|
|
120464473U, // FMLAv1i16_indexed
|
|
122299481U, // FMLAv1i32_indexed
|
|
123085913U, // FMLAv1i64_indexed
|
|
1057944U, // FMLAv2f32
|
|
271464U, // FMLAv2f64
|
|
122299544U, // FMLAv2i32_indexed
|
|
123085928U, // FMLAv2i64_indexed
|
|
1189024U, // FMLAv4f16
|
|
402544U, // FMLAv4f32
|
|
120464544U, // FMLAv4i16_indexed
|
|
122299504U, // FMLAv4i32_indexed
|
|
533624U, // FMLAv8f16
|
|
120464504U, // FMLAv8i16_indexed
|
|
49696U, // FMLSL2lanev4f16
|
|
120464544U, // FMLSL2lanev8f16
|
|
50720U, // FMLSL2v4f16
|
|
1189024U, // FMLSL2v8f16
|
|
53222488U, // FMLSLB_ZZZI_SHH
|
|
7256U, // FMLSLB_ZZZ_SHH
|
|
53222488U, // FMLSLT_ZZZI_SHH
|
|
7256U, // FMLSLT_ZZZ_SHH
|
|
38145U, // FMLSL_MZZI_HtoS
|
|
257U, // FMLSL_MZZ_HtoS
|
|
2632936U, // FMLSL_VG2_M2Z2Z_HtoS
|
|
103427304U, // FMLSL_VG2_M2ZZI_HtoS
|
|
53095656U, // FMLSL_VG2_M2ZZ_HtoS
|
|
2632936U, // FMLSL_VG4_M4Z4Z_HtoS
|
|
103427304U, // FMLSL_VG4_M4ZZI_HtoS
|
|
53095656U, // FMLSL_VG4_M4ZZ_HtoS
|
|
49696U, // FMLSLlanev4f16
|
|
120464544U, // FMLSLlanev8f16
|
|
50720U, // FMLSLv4f16
|
|
1189024U, // FMLSLv8f16
|
|
1584320U, // FMLS_VG2_M2Z2Z_D
|
|
2632936U, // FMLS_VG2_M2Z2Z_H
|
|
1715400U, // FMLS_VG2_M2Z2Z_S
|
|
102509760U, // FMLS_VG2_M2ZZI_D
|
|
103427304U, // FMLS_VG2_M2ZZI_H
|
|
102640840U, // FMLS_VG2_M2ZZI_S
|
|
52178112U, // FMLS_VG2_M2ZZ_D
|
|
53095656U, // FMLS_VG2_M2ZZ_H
|
|
52309192U, // FMLS_VG2_M2ZZ_S
|
|
2632936U, // FMLS_VG4_M4Z2Z_H
|
|
1584320U, // FMLS_VG4_M4Z4Z_D
|
|
1715400U, // FMLS_VG4_M4Z4Z_S
|
|
102509760U, // FMLS_VG4_M4ZZI_D
|
|
103427304U, // FMLS_VG4_M4ZZI_H
|
|
102640840U, // FMLS_VG4_M4ZZI_S
|
|
52178112U, // FMLS_VG4_M4ZZ_D
|
|
53095656U, // FMLS_VG4_M4ZZ_H
|
|
52309192U, // FMLS_VG4_M4ZZ_S
|
|
285344896U, // FMLS_ZPmZZ_D
|
|
53488880U, // FMLS_ZPmZZ_H
|
|
302123136U, // FMLS_ZPmZZ_S
|
|
53216344U, // FMLS_ZZZI_D
|
|
39152U, // FMLS_ZZZI_H
|
|
53217368U, // FMLS_ZZZI_S
|
|
120464473U, // FMLSv1i16_indexed
|
|
122299481U, // FMLSv1i32_indexed
|
|
123085913U, // FMLSv1i64_indexed
|
|
1057944U, // FMLSv2f32
|
|
271464U, // FMLSv2f64
|
|
122299544U, // FMLSv2i32_indexed
|
|
123085928U, // FMLSv2i64_indexed
|
|
1189024U, // FMLSv4f16
|
|
402544U, // FMLSv4f32
|
|
120464544U, // FMLSv4i16_indexed
|
|
122299504U, // FMLSv4i32_indexed
|
|
533624U, // FMLSv8f16
|
|
120464504U, // FMLSv8i16_indexed
|
|
1112U, // FMMLA_ZZZ_D
|
|
2136U, // FMMLA_ZZZ_S
|
|
0U, // FMOPAL_MPPZZ
|
|
0U, // FMOPA_MPPZZ_BtoH
|
|
0U, // FMOPA_MPPZZ_BtoS
|
|
560U, // FMOPA_MPPZZ_D
|
|
0U, // FMOPA_MPPZZ_H
|
|
264U, // FMOPA_MPPZZ_S
|
|
0U, // FMOPSL_MPPZZ
|
|
560U, // FMOPS_MPPZZ_D
|
|
0U, // FMOPS_MPPZZ_H
|
|
264U, // FMOPS_MPPZZ_S
|
|
45472U, // FMOVDXHighr
|
|
0U, // FMOVDXr
|
|
2U, // FMOVDi
|
|
0U, // FMOVDr
|
|
0U, // FMOVHWr
|
|
0U, // FMOVHXr
|
|
2U, // FMOVHi
|
|
0U, // FMOVHr
|
|
0U, // FMOVSWr
|
|
2U, // FMOVSi
|
|
0U, // FMOVSr
|
|
0U, // FMOVWHr
|
|
0U, // FMOVWSr
|
|
0U, // FMOVXDHighr
|
|
0U, // FMOVXDr
|
|
0U, // FMOVXHr
|
|
2U, // FMOVv2f32_ns
|
|
2U, // FMOVv2f64_ns
|
|
2U, // FMOVv4f16_ns
|
|
2U, // FMOVv4f32_ns
|
|
2U, // FMOVv8f16_ns
|
|
0U, // FMS16
|
|
0U, // FMS32
|
|
0U, // FMS64
|
|
285344896U, // FMSB_ZPmZZ_D
|
|
53488880U, // FMSB_ZPmZZ_H
|
|
302123136U, // FMSB_ZPmZZ_S
|
|
134232U, // FMSUBDrrr
|
|
134232U, // FMSUBHrrr
|
|
134232U, // FMSUBSrrr
|
|
3160U, // FMULDrr
|
|
3160U, // FMULHrr
|
|
3160U, // FMULSrr
|
|
3160U, // FMULX16
|
|
3160U, // FMULX32
|
|
3160U, // FMULX64
|
|
33691776U, // FMULX_ZPmZ_D
|
|
51129480U, // FMULX_ZPmZ_H
|
|
67252352U, // FMULX_ZPmZ_S
|
|
338567256U, // FMULXv1i16_indexed
|
|
340402264U, // FMULXv1i32_indexed
|
|
341188696U, // FMULXv1i64_indexed
|
|
1056920U, // FMULXv2f32
|
|
270440U, // FMULXv2f64
|
|
340402328U, // FMULXv2i32_indexed
|
|
341188712U, // FMULXv2i64_indexed
|
|
1188000U, // FMULXv4f16
|
|
401520U, // FMULXv4f32
|
|
338567328U, // FMULXv4i16_indexed
|
|
340402288U, // FMULXv4i32_indexed
|
|
532600U, // FMULXv8f16
|
|
338567288U, // FMULXv8i16_indexed
|
|
352458880U, // FMUL_ZPmI_D
|
|
5778568U, // FMUL_ZPmI_H
|
|
352465024U, // FMUL_ZPmI_S
|
|
33691776U, // FMUL_ZPmZ_D
|
|
51129480U, // FMUL_ZPmZ_H
|
|
67252352U, // FMUL_ZPmZ_S
|
|
5904472U, // FMUL_ZZZI_D
|
|
40072U, // FMUL_ZZZI_H
|
|
5910617U, // FMUL_ZZZI_S
|
|
6232U, // FMUL_ZZZ_D
|
|
136U, // FMUL_ZZZ_H
|
|
12377U, // FMUL_ZZZ_S
|
|
338567256U, // FMULv1i16_indexed
|
|
340402264U, // FMULv1i32_indexed
|
|
341188696U, // FMULv1i64_indexed
|
|
1056920U, // FMULv2f32
|
|
270440U, // FMULv2f64
|
|
340402328U, // FMULv2i32_indexed
|
|
341188712U, // FMULv2i64_indexed
|
|
1188000U, // FMULv4f16
|
|
401520U, // FMULv4f32
|
|
338567328U, // FMULv4i16_indexed
|
|
340402288U, // FMULv4i32_indexed
|
|
532600U, // FMULv8f16
|
|
338567288U, // FMULv8i16_indexed
|
|
0U, // FNEGDr
|
|
0U, // FNEGHr
|
|
0U, // FNEGSr
|
|
16U, // FNEG_ZPmZ_D
|
|
0U, // FNEG_ZPmZ_H
|
|
24U, // FNEG_ZPmZ_S
|
|
40U, // FNEGv2f32
|
|
48U, // FNEGv2f64
|
|
56U, // FNEGv4f16
|
|
64U, // FNEGv4f32
|
|
72U, // FNEGv8f16
|
|
134232U, // FNMADDDrrr
|
|
134232U, // FNMADDHrrr
|
|
134232U, // FNMADDSrrr
|
|
285344896U, // FNMAD_ZPmZZ_D
|
|
53488880U, // FNMAD_ZPmZZ_H
|
|
302123136U, // FNMAD_ZPmZZ_S
|
|
285344896U, // FNMLA_ZPmZZ_D
|
|
53488880U, // FNMLA_ZPmZZ_H
|
|
302123136U, // FNMLA_ZPmZZ_S
|
|
285344896U, // FNMLS_ZPmZZ_D
|
|
53488880U, // FNMLS_ZPmZZ_H
|
|
302123136U, // FNMLS_ZPmZZ_S
|
|
285344896U, // FNMSB_ZPmZZ_D
|
|
53488880U, // FNMSB_ZPmZZ_H
|
|
302123136U, // FNMSB_ZPmZZ_S
|
|
134232U, // FNMSUBDrrr
|
|
134232U, // FNMSUBHrrr
|
|
134232U, // FNMSUBSrrr
|
|
3160U, // FNMULDrr
|
|
3160U, // FNMULHrr
|
|
3160U, // FNMULSrr
|
|
0U, // FRECPE_ZZ_D
|
|
0U, // FRECPE_ZZ_H
|
|
1U, // FRECPE_ZZ_S
|
|
0U, // FRECPEv1f16
|
|
0U, // FRECPEv1i32
|
|
0U, // FRECPEv1i64
|
|
40U, // FRECPEv2f32
|
|
48U, // FRECPEv2f64
|
|
56U, // FRECPEv4f16
|
|
64U, // FRECPEv4f32
|
|
72U, // FRECPEv8f16
|
|
3160U, // FRECPS16
|
|
3160U, // FRECPS32
|
|
3160U, // FRECPS64
|
|
6232U, // FRECPS_ZZZ_D
|
|
136U, // FRECPS_ZZZ_H
|
|
12377U, // FRECPS_ZZZ_S
|
|
1056920U, // FRECPSv2f32
|
|
270440U, // FRECPSv2f64
|
|
1188000U, // FRECPSv4f16
|
|
401520U, // FRECPSv4f32
|
|
532600U, // FRECPSv8f16
|
|
16U, // FRECPX_ZPmZ_D
|
|
0U, // FRECPX_ZPmZ_H
|
|
24U, // FRECPX_ZPmZ_S
|
|
0U, // FRECPXv1f16
|
|
0U, // FRECPXv1i32
|
|
0U, // FRECPXv1i64
|
|
0U, // FRINT32XDr
|
|
0U, // FRINT32XSr
|
|
40U, // FRINT32Xv2f32
|
|
48U, // FRINT32Xv2f64
|
|
64U, // FRINT32Xv4f32
|
|
0U, // FRINT32ZDr
|
|
0U, // FRINT32ZSr
|
|
40U, // FRINT32Zv2f32
|
|
48U, // FRINT32Zv2f64
|
|
64U, // FRINT32Zv4f32
|
|
0U, // FRINT64XDr
|
|
0U, // FRINT64XSr
|
|
40U, // FRINT64Xv2f32
|
|
48U, // FRINT64Xv2f64
|
|
64U, // FRINT64Xv4f32
|
|
0U, // FRINT64ZDr
|
|
0U, // FRINT64ZSr
|
|
40U, // FRINT64Zv2f32
|
|
48U, // FRINT64Zv2f64
|
|
64U, // FRINT64Zv4f32
|
|
0U, // FRINTADr
|
|
0U, // FRINTAHr
|
|
0U, // FRINTASr
|
|
0U, // FRINTA_2Z2Z_S
|
|
0U, // FRINTA_4Z4Z_S
|
|
16U, // FRINTA_ZPmZ_D
|
|
0U, // FRINTA_ZPmZ_H
|
|
24U, // FRINTA_ZPmZ_S
|
|
40U, // FRINTAv2f32
|
|
48U, // FRINTAv2f64
|
|
56U, // FRINTAv4f16
|
|
64U, // FRINTAv4f32
|
|
72U, // FRINTAv8f16
|
|
0U, // FRINTIDr
|
|
0U, // FRINTIHr
|
|
0U, // FRINTISr
|
|
16U, // FRINTI_ZPmZ_D
|
|
0U, // FRINTI_ZPmZ_H
|
|
24U, // FRINTI_ZPmZ_S
|
|
40U, // FRINTIv2f32
|
|
48U, // FRINTIv2f64
|
|
56U, // FRINTIv4f16
|
|
64U, // FRINTIv4f32
|
|
72U, // FRINTIv8f16
|
|
0U, // FRINTMDr
|
|
0U, // FRINTMHr
|
|
0U, // FRINTMSr
|
|
0U, // FRINTM_2Z2Z_S
|
|
0U, // FRINTM_4Z4Z_S
|
|
16U, // FRINTM_ZPmZ_D
|
|
0U, // FRINTM_ZPmZ_H
|
|
24U, // FRINTM_ZPmZ_S
|
|
40U, // FRINTMv2f32
|
|
48U, // FRINTMv2f64
|
|
56U, // FRINTMv4f16
|
|
64U, // FRINTMv4f32
|
|
72U, // FRINTMv8f16
|
|
0U, // FRINTNDr
|
|
0U, // FRINTNHr
|
|
0U, // FRINTNSr
|
|
0U, // FRINTN_2Z2Z_S
|
|
0U, // FRINTN_4Z4Z_S
|
|
16U, // FRINTN_ZPmZ_D
|
|
0U, // FRINTN_ZPmZ_H
|
|
24U, // FRINTN_ZPmZ_S
|
|
40U, // FRINTNv2f32
|
|
48U, // FRINTNv2f64
|
|
56U, // FRINTNv4f16
|
|
64U, // FRINTNv4f32
|
|
72U, // FRINTNv8f16
|
|
0U, // FRINTPDr
|
|
0U, // FRINTPHr
|
|
0U, // FRINTPSr
|
|
0U, // FRINTP_2Z2Z_S
|
|
0U, // FRINTP_4Z4Z_S
|
|
16U, // FRINTP_ZPmZ_D
|
|
0U, // FRINTP_ZPmZ_H
|
|
24U, // FRINTP_ZPmZ_S
|
|
40U, // FRINTPv2f32
|
|
48U, // FRINTPv2f64
|
|
56U, // FRINTPv4f16
|
|
64U, // FRINTPv4f32
|
|
72U, // FRINTPv8f16
|
|
0U, // FRINTXDr
|
|
0U, // FRINTXHr
|
|
0U, // FRINTXSr
|
|
16U, // FRINTX_ZPmZ_D
|
|
0U, // FRINTX_ZPmZ_H
|
|
24U, // FRINTX_ZPmZ_S
|
|
40U, // FRINTXv2f32
|
|
48U, // FRINTXv2f64
|
|
56U, // FRINTXv4f16
|
|
64U, // FRINTXv4f32
|
|
72U, // FRINTXv8f16
|
|
0U, // FRINTZDr
|
|
0U, // FRINTZHr
|
|
0U, // FRINTZSr
|
|
16U, // FRINTZ_ZPmZ_D
|
|
0U, // FRINTZ_ZPmZ_H
|
|
24U, // FRINTZ_ZPmZ_S
|
|
40U, // FRINTZv2f32
|
|
48U, // FRINTZv2f64
|
|
56U, // FRINTZv4f16
|
|
64U, // FRINTZv4f32
|
|
72U, // FRINTZv8f16
|
|
0U, // FRSQRTE_ZZ_D
|
|
0U, // FRSQRTE_ZZ_H
|
|
1U, // FRSQRTE_ZZ_S
|
|
0U, // FRSQRTEv1f16
|
|
0U, // FRSQRTEv1i32
|
|
0U, // FRSQRTEv1i64
|
|
40U, // FRSQRTEv2f32
|
|
48U, // FRSQRTEv2f64
|
|
56U, // FRSQRTEv4f16
|
|
64U, // FRSQRTEv4f32
|
|
72U, // FRSQRTEv8f16
|
|
3160U, // FRSQRTS16
|
|
3160U, // FRSQRTS32
|
|
3160U, // FRSQRTS64
|
|
6232U, // FRSQRTS_ZZZ_D
|
|
136U, // FRSQRTS_ZZZ_H
|
|
12377U, // FRSQRTS_ZZZ_S
|
|
1056920U, // FRSQRTSv2f32
|
|
270440U, // FRSQRTSv2f64
|
|
1188000U, // FRSQRTSv4f16
|
|
401520U, // FRSQRTSv4f32
|
|
532600U, // FRSQRTSv8f16
|
|
464U, // FSCALE_2Z2Z_D
|
|
248U, // FSCALE_2Z2Z_H
|
|
472U, // FSCALE_2Z2Z_S
|
|
184U, // FSCALE_2ZZ_D
|
|
136U, // FSCALE_2ZZ_H
|
|
96U, // FSCALE_2ZZ_S
|
|
464U, // FSCALE_4Z4Z_D
|
|
248U, // FSCALE_4Z4Z_H
|
|
472U, // FSCALE_4Z4Z_S
|
|
184U, // FSCALE_4ZZ_D
|
|
136U, // FSCALE_4ZZ_H
|
|
96U, // FSCALE_4ZZ_S
|
|
33691776U, // FSCALE_ZPmZ_D
|
|
51129480U, // FSCALE_ZPmZ_H
|
|
67252352U, // FSCALE_ZPmZ_S
|
|
1056920U, // FSCALEv2f32
|
|
270440U, // FSCALEv2f64
|
|
1188000U, // FSCALEv4f16
|
|
401520U, // FSCALEv4f32
|
|
532600U, // FSCALEv8f16
|
|
0U, // FSQRTDr
|
|
0U, // FSQRTHr
|
|
0U, // FSQRTSr
|
|
16U, // FSQRT_ZPmZ_D
|
|
0U, // FSQRT_ZPmZ_H
|
|
24U, // FSQRT_ZPmZ_S
|
|
40U, // FSQRTv2f32
|
|
48U, // FSQRTv2f64
|
|
56U, // FSQRTv4f16
|
|
64U, // FSQRTv4f32
|
|
72U, // FSQRTv8f16
|
|
3160U, // FSUBDrr
|
|
3160U, // FSUBHrr
|
|
268572800U, // FSUBR_ZPmI_D
|
|
3943560U, // FSUBR_ZPmI_H
|
|
268578944U, // FSUBR_ZPmI_S
|
|
33691776U, // FSUBR_ZPmZ_D
|
|
51129480U, // FSUBR_ZPmZ_H
|
|
67252352U, // FSUBR_ZPmZ_S
|
|
3160U, // FSUBSrr
|
|
192U, // FSUB_VG2_M2Z_D
|
|
232U, // FSUB_VG2_M2Z_H
|
|
200U, // FSUB_VG2_M2Z_S
|
|
192U, // FSUB_VG4_M4Z_D
|
|
232U, // FSUB_VG4_M4Z_H
|
|
200U, // FSUB_VG4_M4Z_S
|
|
268572800U, // FSUB_ZPmI_D
|
|
3943560U, // FSUB_ZPmI_H
|
|
268578944U, // FSUB_ZPmI_S
|
|
33691776U, // FSUB_ZPmZ_D
|
|
51129480U, // FSUB_ZPmZ_H
|
|
67252352U, // FSUB_ZPmZ_S
|
|
6232U, // FSUB_ZZZ_D
|
|
136U, // FSUB_ZZZ_H
|
|
12377U, // FSUB_ZZZ_S
|
|
1056920U, // FSUBv2f32
|
|
270440U, // FSUBv2f64
|
|
1188000U, // FSUBv4f16
|
|
401520U, // FSUBv4f32
|
|
532600U, // FSUBv8f16
|
|
137304U, // FTMAD_ZZI_D
|
|
52440200U, // FTMAD_ZZI_H
|
|
143449U, // FTMAD_ZZI_S
|
|
6232U, // FTSMUL_ZZZ_D
|
|
136U, // FTSMUL_ZZZ_H
|
|
12377U, // FTSMUL_ZZZ_S
|
|
6232U, // FTSSEL_ZZZ_D
|
|
136U, // FTSSEL_ZZZ_H
|
|
12377U, // FTSSEL_ZZZ_S
|
|
5029400U, // FVDOTB_VG4_M2ZZI_BtoS
|
|
5029400U, // FVDOTT_VG4_M2ZZI_BtoS
|
|
5029400U, // FVDOT_VG2_M2ZZI_BtoH
|
|
103427304U, // FVDOT_VG2_M2ZZI_HtoS
|
|
0U, // GCSPOPCX
|
|
0U, // GCSPOPM
|
|
0U, // GCSPOPX
|
|
0U, // GCSPUSHM
|
|
0U, // GCSPUSHX
|
|
0U, // GCSSS1
|
|
0U, // GCSSS2
|
|
0U, // GCSSTR
|
|
0U, // GCSSTTR
|
|
0U, // GENLUT
|
|
0U, // GENTER
|
|
0U, // GEXIT
|
|
371207355U, // GLD1B_D_IMM_REAL
|
|
6040803U, // GLD1B_D_REAL
|
|
6171875U, // GLD1B_D_SXTW_REAL
|
|
6302947U, // GLD1B_D_UXTW_REAL
|
|
371207267U, // GLD1B_S_IMM_REAL
|
|
6434019U, // GLD1B_S_SXTW_REAL
|
|
6565091U, // GLD1B_S_UXTW_REAL
|
|
6696123U, // GLD1D_IMM_REAL
|
|
6040803U, // GLD1D_REAL
|
|
6827235U, // GLD1D_SCALED_REAL
|
|
6171875U, // GLD1D_SXTW_REAL
|
|
6958307U, // GLD1D_SXTW_SCALED_REAL
|
|
6302947U, // GLD1D_UXTW_REAL
|
|
7089379U, // GLD1D_UXTW_SCALED_REAL
|
|
376319163U, // GLD1H_D_IMM_REAL
|
|
6040803U, // GLD1H_D_REAL
|
|
7351523U, // GLD1H_D_SCALED_REAL
|
|
6171875U, // GLD1H_D_SXTW_REAL
|
|
7482595U, // GLD1H_D_SXTW_SCALED_REAL
|
|
6302947U, // GLD1H_D_UXTW_REAL
|
|
7613667U, // GLD1H_D_UXTW_SCALED_REAL
|
|
376319075U, // GLD1H_S_IMM_REAL
|
|
6434019U, // GLD1H_S_SXTW_REAL
|
|
7744739U, // GLD1H_S_SXTW_SCALED_REAL
|
|
6565091U, // GLD1H_S_UXTW_REAL
|
|
7875811U, // GLD1H_S_UXTW_SCALED_REAL
|
|
371207355U, // GLD1Q
|
|
371207355U, // GLD1SB_D_IMM_REAL
|
|
6040803U, // GLD1SB_D_REAL
|
|
6171875U, // GLD1SB_D_SXTW_REAL
|
|
6302947U, // GLD1SB_D_UXTW_REAL
|
|
371207267U, // GLD1SB_S_IMM_REAL
|
|
6434019U, // GLD1SB_S_SXTW_REAL
|
|
6565091U, // GLD1SB_S_UXTW_REAL
|
|
376319163U, // GLD1SH_D_IMM_REAL
|
|
6040803U, // GLD1SH_D_REAL
|
|
7351523U, // GLD1SH_D_SCALED_REAL
|
|
6171875U, // GLD1SH_D_SXTW_REAL
|
|
7482595U, // GLD1SH_D_SXTW_SCALED_REAL
|
|
6302947U, // GLD1SH_D_UXTW_REAL
|
|
7613667U, // GLD1SH_D_UXTW_SCALED_REAL
|
|
376319075U, // GLD1SH_S_IMM_REAL
|
|
6434019U, // GLD1SH_S_SXTW_REAL
|
|
7744739U, // GLD1SH_S_SXTW_SCALED_REAL
|
|
6565091U, // GLD1SH_S_UXTW_REAL
|
|
7875811U, // GLD1SH_S_UXTW_SCALED_REAL
|
|
377105595U, // GLD1SW_D_IMM_REAL
|
|
6040803U, // GLD1SW_D_REAL
|
|
8137955U, // GLD1SW_D_SCALED_REAL
|
|
6171875U, // GLD1SW_D_SXTW_REAL
|
|
8269027U, // GLD1SW_D_SXTW_SCALED_REAL
|
|
6302947U, // GLD1SW_D_UXTW_REAL
|
|
8400099U, // GLD1SW_D_UXTW_SCALED_REAL
|
|
377105595U, // GLD1W_D_IMM_REAL
|
|
6040803U, // GLD1W_D_REAL
|
|
8137955U, // GLD1W_D_SCALED_REAL
|
|
6171875U, // GLD1W_D_SXTW_REAL
|
|
8269027U, // GLD1W_D_SXTW_SCALED_REAL
|
|
6302947U, // GLD1W_D_UXTW_REAL
|
|
8400099U, // GLD1W_D_UXTW_SCALED_REAL
|
|
377105507U, // GLD1W_IMM_REAL
|
|
6434019U, // GLD1W_SXTW_REAL
|
|
8531171U, // GLD1W_SXTW_SCALED_REAL
|
|
6565091U, // GLD1W_UXTW_REAL
|
|
8662243U, // GLD1W_UXTW_SCALED_REAL
|
|
371207355U, // GLDFF1B_D_IMM_REAL
|
|
6040803U, // GLDFF1B_D_REAL
|
|
6171875U, // GLDFF1B_D_SXTW_REAL
|
|
6302947U, // GLDFF1B_D_UXTW_REAL
|
|
371207267U, // GLDFF1B_S_IMM_REAL
|
|
6434019U, // GLDFF1B_S_SXTW_REAL
|
|
6565091U, // GLDFF1B_S_UXTW_REAL
|
|
6696123U, // GLDFF1D_IMM_REAL
|
|
6040803U, // GLDFF1D_REAL
|
|
6827235U, // GLDFF1D_SCALED_REAL
|
|
6171875U, // GLDFF1D_SXTW_REAL
|
|
6958307U, // GLDFF1D_SXTW_SCALED_REAL
|
|
6302947U, // GLDFF1D_UXTW_REAL
|
|
7089379U, // GLDFF1D_UXTW_SCALED_REAL
|
|
376319163U, // GLDFF1H_D_IMM_REAL
|
|
6040803U, // GLDFF1H_D_REAL
|
|
7351523U, // GLDFF1H_D_SCALED_REAL
|
|
6171875U, // GLDFF1H_D_SXTW_REAL
|
|
7482595U, // GLDFF1H_D_SXTW_SCALED_REAL
|
|
6302947U, // GLDFF1H_D_UXTW_REAL
|
|
7613667U, // GLDFF1H_D_UXTW_SCALED_REAL
|
|
376319075U, // GLDFF1H_S_IMM_REAL
|
|
6434019U, // GLDFF1H_S_SXTW_REAL
|
|
7744739U, // GLDFF1H_S_SXTW_SCALED_REAL
|
|
6565091U, // GLDFF1H_S_UXTW_REAL
|
|
7875811U, // GLDFF1H_S_UXTW_SCALED_REAL
|
|
371207355U, // GLDFF1SB_D_IMM_REAL
|
|
6040803U, // GLDFF1SB_D_REAL
|
|
6171875U, // GLDFF1SB_D_SXTW_REAL
|
|
6302947U, // GLDFF1SB_D_UXTW_REAL
|
|
371207267U, // GLDFF1SB_S_IMM_REAL
|
|
6434019U, // GLDFF1SB_S_SXTW_REAL
|
|
6565091U, // GLDFF1SB_S_UXTW_REAL
|
|
376319163U, // GLDFF1SH_D_IMM_REAL
|
|
6040803U, // GLDFF1SH_D_REAL
|
|
7351523U, // GLDFF1SH_D_SCALED_REAL
|
|
6171875U, // GLDFF1SH_D_SXTW_REAL
|
|
7482595U, // GLDFF1SH_D_SXTW_SCALED_REAL
|
|
6302947U, // GLDFF1SH_D_UXTW_REAL
|
|
7613667U, // GLDFF1SH_D_UXTW_SCALED_REAL
|
|
376319075U, // GLDFF1SH_S_IMM_REAL
|
|
6434019U, // GLDFF1SH_S_SXTW_REAL
|
|
7744739U, // GLDFF1SH_S_SXTW_SCALED_REAL
|
|
6565091U, // GLDFF1SH_S_UXTW_REAL
|
|
7875811U, // GLDFF1SH_S_UXTW_SCALED_REAL
|
|
377105595U, // GLDFF1SW_D_IMM_REAL
|
|
6040803U, // GLDFF1SW_D_REAL
|
|
8137955U, // GLDFF1SW_D_SCALED_REAL
|
|
6171875U, // GLDFF1SW_D_SXTW_REAL
|
|
8269027U, // GLDFF1SW_D_SXTW_SCALED_REAL
|
|
6302947U, // GLDFF1SW_D_UXTW_REAL
|
|
8400099U, // GLDFF1SW_D_UXTW_SCALED_REAL
|
|
377105595U, // GLDFF1W_D_IMM_REAL
|
|
6040803U, // GLDFF1W_D_REAL
|
|
8137955U, // GLDFF1W_D_SCALED_REAL
|
|
6171875U, // GLDFF1W_D_SXTW_REAL
|
|
8269027U, // GLDFF1W_D_SXTW_SCALED_REAL
|
|
6302947U, // GLDFF1W_D_UXTW_REAL
|
|
8400099U, // GLDFF1W_D_UXTW_SCALED_REAL
|
|
377105507U, // GLDFF1W_IMM_REAL
|
|
6434019U, // GLDFF1W_SXTW_REAL
|
|
8531171U, // GLDFF1W_SXTW_SCALED_REAL
|
|
6565091U, // GLDFF1W_UXTW_REAL
|
|
8662243U, // GLDFF1W_UXTW_SCALED_REAL
|
|
3160U, // GMI
|
|
0U, // HINT
|
|
33691864U, // HISTCNT_ZPzZZ_D
|
|
67252440U, // HISTCNT_ZPzZZ_S
|
|
10329U, // HISTSEG_ZZZ
|
|
0U, // HLT
|
|
0U, // HVC
|
|
2U, // INCB_XPiI
|
|
2U, // INCD_XPiI
|
|
2U, // INCD_ZPiI
|
|
2U, // INCH_XPiI
|
|
0U, // INCH_ZPiI
|
|
1U, // INCP_XP_B
|
|
0U, // INCP_XP_D
|
|
0U, // INCP_XP_H
|
|
1U, // INCP_XP_S
|
|
0U, // INCP_ZP_D
|
|
0U, // INCP_ZP_H
|
|
0U, // INCP_ZP_S
|
|
2U, // INCW_XPiI
|
|
2U, // INCW_ZPiI
|
|
571U, // INDEX_II_B
|
|
3160U, // INDEX_II_D
|
|
3U, // INDEX_II_H
|
|
3160U, // INDEX_II_S
|
|
227U, // INDEX_IR_B
|
|
3160U, // INDEX_IR_D
|
|
1U, // INDEX_IR_H
|
|
3160U, // INDEX_IR_S
|
|
51288U, // INDEX_RI_B
|
|
3160U, // INDEX_RI_D
|
|
576U, // INDEX_RI_H
|
|
3160U, // INDEX_RI_S
|
|
3160U, // INDEX_RR_B
|
|
3160U, // INDEX_RR_D
|
|
224U, // INDEX_RR_H
|
|
3160U, // INDEX_RR_S
|
|
48712U, // INSERT_MXIPZ_H_B
|
|
52808U, // INSERT_MXIPZ_H_D
|
|
53832U, // INSERT_MXIPZ_H_H
|
|
54856U, // INSERT_MXIPZ_H_Q
|
|
55880U, // INSERT_MXIPZ_H_S
|
|
48712U, // INSERT_MXIPZ_V_B
|
|
52808U, // INSERT_MXIPZ_V_D
|
|
53832U, // INSERT_MXIPZ_V_H
|
|
54856U, // INSERT_MXIPZ_V_Q
|
|
55880U, // INSERT_MXIPZ_V_S
|
|
1U, // INSR_ZR_B
|
|
1U, // INSR_ZR_D
|
|
0U, // INSR_ZR_H
|
|
1U, // INSR_ZR_S
|
|
3U, // INSR_ZV_B
|
|
3U, // INSR_ZV_D
|
|
0U, // INSR_ZV_H
|
|
3U, // INSR_ZV_S
|
|
2U, // INSvi16gpr
|
|
39315U, // INSvi16lane
|
|
2U, // INSvi32gpr
|
|
39323U, // INSvi32lane
|
|
2U, // INSvi64gpr
|
|
39331U, // INSvi64lane
|
|
2U, // INSvi8gpr
|
|
39339U, // INSvi8lane
|
|
3160U, // IRG
|
|
0U, // ISB
|
|
10328U, // LASTA_RPZ_B
|
|
6232U, // LASTA_RPZ_D
|
|
5208U, // LASTA_RPZ_H
|
|
12376U, // LASTA_RPZ_S
|
|
10328U, // LASTA_VPZ_B
|
|
6232U, // LASTA_VPZ_D
|
|
5208U, // LASTA_VPZ_H
|
|
12376U, // LASTA_VPZ_S
|
|
10328U, // LASTB_RPZ_B
|
|
6232U, // LASTB_RPZ_D
|
|
5208U, // LASTB_RPZ_H
|
|
12376U, // LASTB_RPZ_S
|
|
10328U, // LASTB_VPZ_B
|
|
6232U, // LASTB_VPZ_D
|
|
5208U, // LASTB_VPZ_H
|
|
12376U, // LASTB_VPZ_S
|
|
8793315U, // LD1B
|
|
8793315U, // LD1B_2Z
|
|
393096419U, // LD1B_2Z_IMM
|
|
56915U, // LD1B_2Z_STRIDED
|
|
57939U, // LD1B_2Z_STRIDED_IMM
|
|
8793315U, // LD1B_4Z
|
|
393882851U, // LD1B_4Z_IMM
|
|
8793315U, // LD1B_4Z_STRIDED
|
|
393882851U, // LD1B_4Z_STRIDED_IMM
|
|
8793315U, // LD1B_D
|
|
387984611U, // LD1B_D_IMM
|
|
8793315U, // LD1B_H
|
|
387984611U, // LD1B_H_IMM
|
|
387984611U, // LD1B_IMM
|
|
8793315U, // LD1B_S
|
|
387984611U, // LD1B_S_IMM
|
|
8924387U, // LD1D
|
|
8924387U, // LD1D_2Z
|
|
393096419U, // LD1D_2Z_IMM
|
|
8924387U, // LD1D_2Z_STRIDED
|
|
393096419U, // LD1D_2Z_STRIDED_IMM
|
|
8924387U, // LD1D_4Z
|
|
393882851U, // LD1D_4Z_IMM
|
|
8924387U, // LD1D_4Z_STRIDED
|
|
393882851U, // LD1D_4Z_STRIDED_IMM
|
|
387984611U, // LD1D_IMM
|
|
8924387U, // LD1D_Q
|
|
387984611U, // LD1D_Q_IMM
|
|
0U, // LD1Fourv16b
|
|
0U, // LD1Fourv16b_POST
|
|
0U, // LD1Fourv1d
|
|
0U, // LD1Fourv1d_POST
|
|
0U, // LD1Fourv2d
|
|
0U, // LD1Fourv2d_POST
|
|
0U, // LD1Fourv2s
|
|
0U, // LD1Fourv2s_POST
|
|
0U, // LD1Fourv4h
|
|
0U, // LD1Fourv4h_POST
|
|
0U, // LD1Fourv4s
|
|
0U, // LD1Fourv4s_POST
|
|
0U, // LD1Fourv8b
|
|
0U, // LD1Fourv8b_POST
|
|
0U, // LD1Fourv8h
|
|
0U, // LD1Fourv8h_POST
|
|
9055459U, // LD1H
|
|
9055459U, // LD1H_2Z
|
|
393096419U, // LD1H_2Z_IMM
|
|
58963U, // LD1H_2Z_STRIDED
|
|
57939U, // LD1H_2Z_STRIDED_IMM
|
|
9055459U, // LD1H_4Z
|
|
393882851U, // LD1H_4Z_IMM
|
|
9055459U, // LD1H_4Z_STRIDED
|
|
393882851U, // LD1H_4Z_STRIDED_IMM
|
|
9055459U, // LD1H_D
|
|
387984611U, // LD1H_D_IMM
|
|
387984611U, // LD1H_IMM
|
|
9055459U, // LD1H_S
|
|
387984611U, // LD1H_S_IMM
|
|
0U, // LD1Onev16b
|
|
0U, // LD1Onev16b_POST
|
|
0U, // LD1Onev1d
|
|
0U, // LD1Onev1d_POST
|
|
0U, // LD1Onev2d
|
|
0U, // LD1Onev2d_POST
|
|
0U, // LD1Onev2s
|
|
0U, // LD1Onev2s_POST
|
|
0U, // LD1Onev4h
|
|
0U, // LD1Onev4h_POST
|
|
0U, // LD1Onev4s
|
|
0U, // LD1Onev4s_POST
|
|
0U, // LD1Onev8b
|
|
0U, // LD1Onev8b_POST
|
|
0U, // LD1Onev8h
|
|
0U, // LD1Onev8h_POST
|
|
371207395U, // LD1RB_D_IMM
|
|
371207395U, // LD1RB_H_IMM
|
|
371207395U, // LD1RB_IMM
|
|
371207395U, // LD1RB_S_IMM
|
|
6696163U, // LD1RD_IMM
|
|
376319203U, // LD1RH_D_IMM
|
|
376319203U, // LD1RH_IMM
|
|
376319203U, // LD1RH_S_IMM
|
|
8793315U, // LD1RO_B
|
|
9186531U, // LD1RO_B_IMM
|
|
8924387U, // LD1RO_D
|
|
9186531U, // LD1RO_D_IMM
|
|
9055459U, // LD1RO_H
|
|
9186531U, // LD1RO_H_IMM
|
|
9317603U, // LD1RO_W
|
|
9186531U, // LD1RO_W_IMM
|
|
8793315U, // LD1RQ_B
|
|
9448675U, // LD1RQ_B_IMM
|
|
8924387U, // LD1RQ_D
|
|
9448675U, // LD1RQ_D_IMM
|
|
9055459U, // LD1RQ_H
|
|
9448675U, // LD1RQ_H_IMM
|
|
9317603U, // LD1RQ_W
|
|
9448675U, // LD1RQ_W_IMM
|
|
371207395U, // LD1RSB_D_IMM
|
|
371207395U, // LD1RSB_H_IMM
|
|
371207395U, // LD1RSB_S_IMM
|
|
376319203U, // LD1RSH_D_IMM
|
|
376319203U, // LD1RSH_S_IMM
|
|
377105635U, // LD1RSW_IMM
|
|
377105635U, // LD1RW_D_IMM
|
|
377105635U, // LD1RW_IMM
|
|
0U, // LD1Rv16b
|
|
0U, // LD1Rv16b_POST
|
|
0U, // LD1Rv1d
|
|
0U, // LD1Rv1d_POST
|
|
0U, // LD1Rv2d
|
|
0U, // LD1Rv2d_POST
|
|
0U, // LD1Rv2s
|
|
0U, // LD1Rv2s_POST
|
|
0U, // LD1Rv4h
|
|
0U, // LD1Rv4h_POST
|
|
0U, // LD1Rv4s
|
|
0U, // LD1Rv4s_POST
|
|
0U, // LD1Rv8b
|
|
0U, // LD1Rv8b_POST
|
|
0U, // LD1Rv8h
|
|
0U, // LD1Rv8h_POST
|
|
8793315U, // LD1SB_D
|
|
387984611U, // LD1SB_D_IMM
|
|
8793315U, // LD1SB_H
|
|
387984611U, // LD1SB_H_IMM
|
|
8793315U, // LD1SB_S
|
|
387984611U, // LD1SB_S_IMM
|
|
9055459U, // LD1SH_D
|
|
387984611U, // LD1SH_D_IMM
|
|
9055459U, // LD1SH_S
|
|
387984611U, // LD1SH_S_IMM
|
|
9317603U, // LD1SW_D
|
|
387984611U, // LD1SW_D_IMM
|
|
0U, // LD1Threev16b
|
|
0U, // LD1Threev16b_POST
|
|
0U, // LD1Threev1d
|
|
0U, // LD1Threev1d_POST
|
|
0U, // LD1Threev2d
|
|
0U, // LD1Threev2d_POST
|
|
0U, // LD1Threev2s
|
|
0U, // LD1Threev2s_POST
|
|
0U, // LD1Threev4h
|
|
0U, // LD1Threev4h_POST
|
|
0U, // LD1Threev4s
|
|
0U, // LD1Threev4s_POST
|
|
0U, // LD1Threev8b
|
|
0U, // LD1Threev8b_POST
|
|
0U, // LD1Threev8h
|
|
0U, // LD1Threev8h_POST
|
|
0U, // LD1Twov16b
|
|
0U, // LD1Twov16b_POST
|
|
0U, // LD1Twov1d
|
|
0U, // LD1Twov1d_POST
|
|
0U, // LD1Twov2d
|
|
0U, // LD1Twov2d_POST
|
|
0U, // LD1Twov2s
|
|
0U, // LD1Twov2s_POST
|
|
0U, // LD1Twov4h
|
|
0U, // LD1Twov4h_POST
|
|
0U, // LD1Twov4s
|
|
0U, // LD1Twov4s_POST
|
|
0U, // LD1Twov8b
|
|
0U, // LD1Twov8b_POST
|
|
0U, // LD1Twov8h
|
|
0U, // LD1Twov8h_POST
|
|
9317603U, // LD1W
|
|
9317603U, // LD1W_2Z
|
|
393096419U, // LD1W_2Z_IMM
|
|
9317603U, // LD1W_2Z_STRIDED
|
|
393096419U, // LD1W_2Z_STRIDED_IMM
|
|
9317603U, // LD1W_4Z
|
|
393882851U, // LD1W_4Z_IMM
|
|
9317603U, // LD1W_4Z_STRIDED
|
|
393882851U, // LD1W_4Z_STRIDED_IMM
|
|
9317603U, // LD1W_D
|
|
387984611U, // LD1W_D_IMM
|
|
387984611U, // LD1W_IMM
|
|
9317603U, // LD1W_Q
|
|
387984611U, // LD1W_Q_IMM
|
|
9628248U, // LD1_MXIPXX_H_B
|
|
9759320U, // LD1_MXIPXX_H_D
|
|
9890392U, // LD1_MXIPXX_H_H
|
|
10021464U, // LD1_MXIPXX_H_Q
|
|
10152536U, // LD1_MXIPXX_H_S
|
|
9628248U, // LD1_MXIPXX_V_B
|
|
9759320U, // LD1_MXIPXX_V_D
|
|
9890392U, // LD1_MXIPXX_V_H
|
|
10021464U, // LD1_MXIPXX_V_Q
|
|
10152536U, // LD1_MXIPXX_V_S
|
|
0U, // LD1i16
|
|
0U, // LD1i16_POST
|
|
0U, // LD1i32
|
|
0U, // LD1i32_POST
|
|
0U, // LD1i64
|
|
0U, // LD1i64_POST
|
|
0U, // LD1i8
|
|
0U, // LD1i8_POST
|
|
8793315U, // LD2B
|
|
393096419U, // LD2B_IMM
|
|
8924387U, // LD2D
|
|
393096419U, // LD2D_IMM
|
|
9055459U, // LD2H
|
|
393096419U, // LD2H_IMM
|
|
10235107U, // LD2Q
|
|
393096419U, // LD2Q_IMM
|
|
0U, // LD2Rv16b
|
|
0U, // LD2Rv16b_POST
|
|
0U, // LD2Rv1d
|
|
0U, // LD2Rv1d_POST
|
|
0U, // LD2Rv2d
|
|
0U, // LD2Rv2d_POST
|
|
0U, // LD2Rv2s
|
|
0U, // LD2Rv2s_POST
|
|
0U, // LD2Rv4h
|
|
0U, // LD2Rv4h_POST
|
|
0U, // LD2Rv4s
|
|
0U, // LD2Rv4s_POST
|
|
0U, // LD2Rv8b
|
|
0U, // LD2Rv8b_POST
|
|
0U, // LD2Rv8h
|
|
0U, // LD2Rv8h_POST
|
|
0U, // LD2Twov16b
|
|
0U, // LD2Twov16b_POST
|
|
0U, // LD2Twov2d
|
|
0U, // LD2Twov2d_POST
|
|
0U, // LD2Twov2s
|
|
0U, // LD2Twov2s_POST
|
|
0U, // LD2Twov4h
|
|
0U, // LD2Twov4h_POST
|
|
0U, // LD2Twov4s
|
|
0U, // LD2Twov4s_POST
|
|
0U, // LD2Twov8b
|
|
0U, // LD2Twov8b_POST
|
|
0U, // LD2Twov8h
|
|
0U, // LD2Twov8h_POST
|
|
9317603U, // LD2W
|
|
393096419U, // LD2W_IMM
|
|
0U, // LD2i16
|
|
0U, // LD2i16_POST
|
|
0U, // LD2i32
|
|
0U, // LD2i32_POST
|
|
0U, // LD2i64
|
|
0U, // LD2i64_POST
|
|
0U, // LD2i8
|
|
0U, // LD2i8_POST
|
|
8793315U, // LD3B
|
|
10366179U, // LD3B_IMM
|
|
8924387U, // LD3D
|
|
10366179U, // LD3D_IMM
|
|
9055459U, // LD3H
|
|
10366179U, // LD3H_IMM
|
|
10235107U, // LD3Q
|
|
10366179U, // LD3Q_IMM
|
|
0U, // LD3Rv16b
|
|
0U, // LD3Rv16b_POST
|
|
0U, // LD3Rv1d
|
|
0U, // LD3Rv1d_POST
|
|
0U, // LD3Rv2d
|
|
0U, // LD3Rv2d_POST
|
|
0U, // LD3Rv2s
|
|
0U, // LD3Rv2s_POST
|
|
0U, // LD3Rv4h
|
|
0U, // LD3Rv4h_POST
|
|
0U, // LD3Rv4s
|
|
0U, // LD3Rv4s_POST
|
|
0U, // LD3Rv8b
|
|
0U, // LD3Rv8b_POST
|
|
0U, // LD3Rv8h
|
|
0U, // LD3Rv8h_POST
|
|
0U, // LD3Threev16b
|
|
0U, // LD3Threev16b_POST
|
|
0U, // LD3Threev2d
|
|
0U, // LD3Threev2d_POST
|
|
0U, // LD3Threev2s
|
|
0U, // LD3Threev2s_POST
|
|
0U, // LD3Threev4h
|
|
0U, // LD3Threev4h_POST
|
|
0U, // LD3Threev4s
|
|
0U, // LD3Threev4s_POST
|
|
0U, // LD3Threev8b
|
|
0U, // LD3Threev8b_POST
|
|
0U, // LD3Threev8h
|
|
0U, // LD3Threev8h_POST
|
|
9317603U, // LD3W
|
|
10366179U, // LD3W_IMM
|
|
0U, // LD3i16
|
|
0U, // LD3i16_POST
|
|
0U, // LD3i32
|
|
0U, // LD3i32_POST
|
|
0U, // LD3i64
|
|
0U, // LD3i64_POST
|
|
0U, // LD3i8
|
|
0U, // LD3i8_POST
|
|
8793315U, // LD4B
|
|
393882851U, // LD4B_IMM
|
|
8924387U, // LD4D
|
|
393882851U, // LD4D_IMM
|
|
0U, // LD4Fourv16b
|
|
0U, // LD4Fourv16b_POST
|
|
0U, // LD4Fourv2d
|
|
0U, // LD4Fourv2d_POST
|
|
0U, // LD4Fourv2s
|
|
0U, // LD4Fourv2s_POST
|
|
0U, // LD4Fourv4h
|
|
0U, // LD4Fourv4h_POST
|
|
0U, // LD4Fourv4s
|
|
0U, // LD4Fourv4s_POST
|
|
0U, // LD4Fourv8b
|
|
0U, // LD4Fourv8b_POST
|
|
0U, // LD4Fourv8h
|
|
0U, // LD4Fourv8h_POST
|
|
9055459U, // LD4H
|
|
393882851U, // LD4H_IMM
|
|
10235107U, // LD4Q
|
|
393882851U, // LD4Q_IMM
|
|
0U, // LD4Rv16b
|
|
0U, // LD4Rv16b_POST
|
|
0U, // LD4Rv1d
|
|
0U, // LD4Rv1d_POST
|
|
0U, // LD4Rv2d
|
|
0U, // LD4Rv2d_POST
|
|
0U, // LD4Rv2s
|
|
0U, // LD4Rv2s_POST
|
|
0U, // LD4Rv4h
|
|
0U, // LD4Rv4h_POST
|
|
0U, // LD4Rv4s
|
|
0U, // LD4Rv4s_POST
|
|
0U, // LD4Rv8b
|
|
0U, // LD4Rv8b_POST
|
|
0U, // LD4Rv8h
|
|
0U, // LD4Rv8h_POST
|
|
9317603U, // LD4W
|
|
393882851U, // LD4W_IMM
|
|
0U, // LD4i16
|
|
0U, // LD4i16_POST
|
|
0U, // LD4i32
|
|
0U, // LD4i32_POST
|
|
0U, // LD4i64
|
|
0U, // LD4i64_POST
|
|
0U, // LD4i8
|
|
0U, // LD4i8_POST
|
|
0U, // LD64B
|
|
3U, // LDADDAB
|
|
3U, // LDADDAH
|
|
3U, // LDADDALB
|
|
3U, // LDADDALH
|
|
3U, // LDADDALW
|
|
3U, // LDADDALX
|
|
3U, // LDADDAW
|
|
3U, // LDADDAX
|
|
3U, // LDADDB
|
|
3U, // LDADDH
|
|
3U, // LDADDLB
|
|
3U, // LDADDLH
|
|
3U, // LDADDLW
|
|
3U, // LDADDLX
|
|
3U, // LDADDW
|
|
3U, // LDADDX
|
|
0U, // LDAP1
|
|
608U, // LDAPRB
|
|
608U, // LDAPRH
|
|
608U, // LDAPRW
|
|
617U, // LDAPRWpost
|
|
608U, // LDAPRX
|
|
625U, // LDAPRXpost
|
|
3411032U, // LDAPURBi
|
|
3411032U, // LDAPURHi
|
|
3411032U, // LDAPURSBWi
|
|
3411032U, // LDAPURSBXi
|
|
3411032U, // LDAPURSHWi
|
|
3411032U, // LDAPURSHXi
|
|
3411032U, // LDAPURSWi
|
|
3411032U, // LDAPURXi
|
|
3411032U, // LDAPURbi
|
|
3411032U, // LDAPURdi
|
|
3411032U, // LDAPURhi
|
|
3411032U, // LDAPURi
|
|
3411032U, // LDAPURqi
|
|
3411032U, // LDAPURsi
|
|
608U, // LDARB
|
|
608U, // LDARH
|
|
608U, // LDARW
|
|
608U, // LDARX
|
|
3411216U, // LDAXPW
|
|
3411216U, // LDAXPX
|
|
608U, // LDAXRB
|
|
608U, // LDAXRH
|
|
608U, // LDAXRW
|
|
608U, // LDAXRX
|
|
3U, // LDCLRAB
|
|
3U, // LDCLRAH
|
|
3U, // LDCLRALB
|
|
3U, // LDCLRALH
|
|
3U, // LDCLRALW
|
|
3U, // LDCLRALX
|
|
3U, // LDCLRAW
|
|
3U, // LDCLRAX
|
|
3U, // LDCLRB
|
|
3U, // LDCLRH
|
|
3U, // LDCLRLB
|
|
3U, // LDCLRLH
|
|
3U, // LDCLRLW
|
|
3U, // LDCLRLX
|
|
60690U, // LDCLRP
|
|
60690U, // LDCLRPA
|
|
60690U, // LDCLRPAL
|
|
60690U, // LDCLRPL
|
|
3U, // LDCLRW
|
|
3U, // LDCLRX
|
|
3U, // LDEORAB
|
|
3U, // LDEORAH
|
|
3U, // LDEORALB
|
|
3U, // LDEORALH
|
|
3U, // LDEORALW
|
|
3U, // LDEORALX
|
|
3U, // LDEORAW
|
|
3U, // LDEORAX
|
|
3U, // LDEORB
|
|
3U, // LDEORH
|
|
3U, // LDEORLB
|
|
3U, // LDEORLH
|
|
3U, // LDEORLW
|
|
3U, // LDEORLX
|
|
3U, // LDEORW
|
|
3U, // LDEORX
|
|
8793315U, // LDFF1B_D_REAL
|
|
8793315U, // LDFF1B_H_REAL
|
|
8793315U, // LDFF1B_REAL
|
|
8793315U, // LDFF1B_S_REAL
|
|
8924387U, // LDFF1D_REAL
|
|
9055459U, // LDFF1H_D_REAL
|
|
9055459U, // LDFF1H_REAL
|
|
9055459U, // LDFF1H_S_REAL
|
|
8793315U, // LDFF1SB_D_REAL
|
|
8793315U, // LDFF1SB_H_REAL
|
|
8793315U, // LDFF1SB_S_REAL
|
|
9055459U, // LDFF1SH_D_REAL
|
|
9055459U, // LDFF1SH_S_REAL
|
|
9317603U, // LDFF1SW_D_REAL
|
|
9317603U, // LDFF1W_D_REAL
|
|
9317603U, // LDFF1W_REAL
|
|
3469401U, // LDG
|
|
608U, // LDGM
|
|
3411216U, // LDIAPPW
|
|
10526993U, // LDIAPPWpost
|
|
3411216U, // LDIAPPX
|
|
10658065U, // LDIAPPXpost
|
|
608U, // LDLARB
|
|
608U, // LDLARH
|
|
608U, // LDLARW
|
|
608U, // LDLARX
|
|
387984611U, // LDNF1B_D_IMM_REAL
|
|
387984611U, // LDNF1B_H_IMM_REAL
|
|
387984611U, // LDNF1B_IMM_REAL
|
|
387984611U, // LDNF1B_S_IMM_REAL
|
|
387984611U, // LDNF1D_IMM_REAL
|
|
387984611U, // LDNF1H_D_IMM_REAL
|
|
387984611U, // LDNF1H_IMM_REAL
|
|
387984611U, // LDNF1H_S_IMM_REAL
|
|
387984611U, // LDNF1SB_D_IMM_REAL
|
|
387984611U, // LDNF1SB_H_IMM_REAL
|
|
387984611U, // LDNF1SB_S_IMM_REAL
|
|
387984611U, // LDNF1SH_D_IMM_REAL
|
|
387984611U, // LDNF1SH_S_IMM_REAL
|
|
387984611U, // LDNF1SW_D_IMM_REAL
|
|
387984611U, // LDNF1W_D_IMM_REAL
|
|
387984611U, // LDNF1W_IMM_REAL
|
|
402787600U, // LDNPDi
|
|
419564816U, // LDNPQi
|
|
436342032U, // LDNPSi
|
|
436342032U, // LDNPWi
|
|
402787600U, // LDNPXi
|
|
8793315U, // LDNT1B_2Z
|
|
393096419U, // LDNT1B_2Z_IMM
|
|
56915U, // LDNT1B_2Z_STRIDED
|
|
57939U, // LDNT1B_2Z_STRIDED_IMM
|
|
8793315U, // LDNT1B_4Z
|
|
393882851U, // LDNT1B_4Z_IMM
|
|
8793315U, // LDNT1B_4Z_STRIDED
|
|
393882851U, // LDNT1B_4Z_STRIDED_IMM
|
|
387984611U, // LDNT1B_ZRI
|
|
8793315U, // LDNT1B_ZRR
|
|
371207355U, // LDNT1B_ZZR_D_REAL
|
|
371207267U, // LDNT1B_ZZR_S_REAL
|
|
8924387U, // LDNT1D_2Z
|
|
393096419U, // LDNT1D_2Z_IMM
|
|
8924387U, // LDNT1D_2Z_STRIDED
|
|
393096419U, // LDNT1D_2Z_STRIDED_IMM
|
|
8924387U, // LDNT1D_4Z
|
|
393882851U, // LDNT1D_4Z_IMM
|
|
8924387U, // LDNT1D_4Z_STRIDED
|
|
393882851U, // LDNT1D_4Z_STRIDED_IMM
|
|
387984611U, // LDNT1D_ZRI
|
|
8924387U, // LDNT1D_ZRR
|
|
371207355U, // LDNT1D_ZZR_D_REAL
|
|
9055459U, // LDNT1H_2Z
|
|
393096419U, // LDNT1H_2Z_IMM
|
|
58963U, // LDNT1H_2Z_STRIDED
|
|
57939U, // LDNT1H_2Z_STRIDED_IMM
|
|
9055459U, // LDNT1H_4Z
|
|
393882851U, // LDNT1H_4Z_IMM
|
|
9055459U, // LDNT1H_4Z_STRIDED
|
|
393882851U, // LDNT1H_4Z_STRIDED_IMM
|
|
387984611U, // LDNT1H_ZRI
|
|
9055459U, // LDNT1H_ZRR
|
|
371207355U, // LDNT1H_ZZR_D_REAL
|
|
371207267U, // LDNT1H_ZZR_S_REAL
|
|
371207355U, // LDNT1SB_ZZR_D_REAL
|
|
371207267U, // LDNT1SB_ZZR_S_REAL
|
|
371207355U, // LDNT1SH_ZZR_D_REAL
|
|
371207267U, // LDNT1SH_ZZR_S_REAL
|
|
371207355U, // LDNT1SW_ZZR_D_REAL
|
|
9317603U, // LDNT1W_2Z
|
|
393096419U, // LDNT1W_2Z_IMM
|
|
9317603U, // LDNT1W_2Z_STRIDED
|
|
393096419U, // LDNT1W_2Z_STRIDED_IMM
|
|
9317603U, // LDNT1W_4Z
|
|
393882851U, // LDNT1W_4Z_IMM
|
|
9317603U, // LDNT1W_4Z_STRIDED
|
|
393882851U, // LDNT1W_4Z_STRIDED_IMM
|
|
387984611U, // LDNT1W_ZRI
|
|
9317603U, // LDNT1W_ZRR
|
|
371207355U, // LDNT1W_ZZR_D_REAL
|
|
371207267U, // LDNT1W_ZZR_S_REAL
|
|
402787600U, // LDPDi
|
|
463773969U, // LDPDpost
|
|
453157137U, // LDPDpre
|
|
419564816U, // LDPQi
|
|
480551185U, // LDPQpost
|
|
469934353U, // LDPQpre
|
|
436342032U, // LDPSWi
|
|
497328401U, // LDPSWpost
|
|
486711569U, // LDPSWpre
|
|
436342032U, // LDPSi
|
|
497328401U, // LDPSpost
|
|
486711569U, // LDPSpre
|
|
436342032U, // LDPWi
|
|
497328401U, // LDPWpost
|
|
486711569U, // LDPWpre
|
|
402787600U, // LDPXi
|
|
463773969U, // LDPXpost
|
|
453157137U, // LDPXpre
|
|
62552U, // LDRAAindexed
|
|
63577U, // LDRAAwriteback
|
|
62552U, // LDRABindexed
|
|
63577U, // LDRABwriteback
|
|
41593U, // LDRBBpost
|
|
10920025U, // LDRBBpre
|
|
503450712U, // LDRBBroW
|
|
520227928U, // LDRBBroX
|
|
64600U, // LDRBBui
|
|
41593U, // LDRBpost
|
|
10920025U, // LDRBpre
|
|
503450712U, // LDRBroW
|
|
520227928U, // LDRBroX
|
|
64600U, // LDRBui
|
|
1U, // LDRDl
|
|
41593U, // LDRDpost
|
|
10920025U, // LDRDpre
|
|
537005144U, // LDRDroW
|
|
553782360U, // LDRDroX
|
|
65624U, // LDRDui
|
|
41593U, // LDRHHpost
|
|
10920025U, // LDRHHpre
|
|
570559576U, // LDRHHroW
|
|
587336792U, // LDRHHroX
|
|
66648U, // LDRHHui
|
|
41593U, // LDRHpost
|
|
10920025U, // LDRHpre
|
|
570559576U, // LDRHroW
|
|
587336792U, // LDRHroX
|
|
66648U, // LDRHui
|
|
1U, // LDRQl
|
|
41593U, // LDRQpost
|
|
10920025U, // LDRQpre
|
|
604114008U, // LDRQroW
|
|
620891224U, // LDRQroX
|
|
67672U, // LDRQui
|
|
41593U, // LDRSBWpost
|
|
10920025U, // LDRSBWpre
|
|
503450712U, // LDRSBWroW
|
|
520227928U, // LDRSBWroX
|
|
64600U, // LDRSBWui
|
|
41593U, // LDRSBXpost
|
|
10920025U, // LDRSBXpre
|
|
503450712U, // LDRSBXroW
|
|
520227928U, // LDRSBXroX
|
|
64600U, // LDRSBXui
|
|
41593U, // LDRSHWpost
|
|
10920025U, // LDRSHWpre
|
|
570559576U, // LDRSHWroW
|
|
587336792U, // LDRSHWroX
|
|
66648U, // LDRSHWui
|
|
41593U, // LDRSHXpost
|
|
10920025U, // LDRSHXpre
|
|
570559576U, // LDRSHXroW
|
|
587336792U, // LDRSHXroX
|
|
66648U, // LDRSHXui
|
|
1U, // LDRSWl
|
|
41593U, // LDRSWpost
|
|
10920025U, // LDRSWpre
|
|
637668440U, // LDRSWroW
|
|
654445656U, // LDRSWroX
|
|
68696U, // LDRSWui
|
|
1U, // LDRSl
|
|
41593U, // LDRSpost
|
|
10920025U, // LDRSpre
|
|
637668440U, // LDRSroW
|
|
654445656U, // LDRSroX
|
|
68696U, // LDRSui
|
|
1U, // LDRWl
|
|
41593U, // LDRWpost
|
|
10920025U, // LDRWpre
|
|
637668440U, // LDRWroW
|
|
654445656U, // LDRWroX
|
|
68696U, // LDRWui
|
|
1U, // LDRXl
|
|
41593U, // LDRXpost
|
|
10920025U, // LDRXpre
|
|
537005144U, // LDRXroW
|
|
553782360U, // LDRXroX
|
|
65624U, // LDRXui
|
|
11013208U, // LDR_PXI
|
|
608U, // LDR_TX
|
|
0U, // LDR_ZA
|
|
11013208U, // LDR_ZXI
|
|
3U, // LDSETAB
|
|
3U, // LDSETAH
|
|
3U, // LDSETALB
|
|
3U, // LDSETALH
|
|
3U, // LDSETALW
|
|
3U, // LDSETALX
|
|
3U, // LDSETAW
|
|
3U, // LDSETAX
|
|
3U, // LDSETB
|
|
3U, // LDSETH
|
|
3U, // LDSETLB
|
|
3U, // LDSETLH
|
|
3U, // LDSETLW
|
|
3U, // LDSETLX
|
|
60690U, // LDSETP
|
|
60690U, // LDSETPA
|
|
60690U, // LDSETPAL
|
|
60690U, // LDSETPL
|
|
3U, // LDSETW
|
|
3U, // LDSETX
|
|
3U, // LDSMAXAB
|
|
3U, // LDSMAXAH
|
|
3U, // LDSMAXALB
|
|
3U, // LDSMAXALH
|
|
3U, // LDSMAXALW
|
|
3U, // LDSMAXALX
|
|
3U, // LDSMAXAW
|
|
3U, // LDSMAXAX
|
|
3U, // LDSMAXB
|
|
3U, // LDSMAXH
|
|
3U, // LDSMAXLB
|
|
3U, // LDSMAXLH
|
|
3U, // LDSMAXLW
|
|
3U, // LDSMAXLX
|
|
3U, // LDSMAXW
|
|
3U, // LDSMAXX
|
|
3U, // LDSMINAB
|
|
3U, // LDSMINAH
|
|
3U, // LDSMINALB
|
|
3U, // LDSMINALH
|
|
3U, // LDSMINALW
|
|
3U, // LDSMINALX
|
|
3U, // LDSMINAW
|
|
3U, // LDSMINAX
|
|
3U, // LDSMINB
|
|
3U, // LDSMINH
|
|
3U, // LDSMINLB
|
|
3U, // LDSMINLH
|
|
3U, // LDSMINLW
|
|
3U, // LDSMINLX
|
|
3U, // LDSMINW
|
|
3U, // LDSMINX
|
|
3411032U, // LDTRBi
|
|
3411032U, // LDTRHi
|
|
3411032U, // LDTRSBWi
|
|
3411032U, // LDTRSBXi
|
|
3411032U, // LDTRSHWi
|
|
3411032U, // LDTRSHXi
|
|
3411032U, // LDTRSWi
|
|
3411032U, // LDTRWi
|
|
3411032U, // LDTRXi
|
|
3U, // LDUMAXAB
|
|
3U, // LDUMAXAH
|
|
3U, // LDUMAXALB
|
|
3U, // LDUMAXALH
|
|
3U, // LDUMAXALW
|
|
3U, // LDUMAXALX
|
|
3U, // LDUMAXAW
|
|
3U, // LDUMAXAX
|
|
3U, // LDUMAXB
|
|
3U, // LDUMAXH
|
|
3U, // LDUMAXLB
|
|
3U, // LDUMAXLH
|
|
3U, // LDUMAXLW
|
|
3U, // LDUMAXLX
|
|
3U, // LDUMAXW
|
|
3U, // LDUMAXX
|
|
3U, // LDUMINAB
|
|
3U, // LDUMINAH
|
|
3U, // LDUMINALB
|
|
3U, // LDUMINALH
|
|
3U, // LDUMINALW
|
|
3U, // LDUMINALX
|
|
3U, // LDUMINAW
|
|
3U, // LDUMINAX
|
|
3U, // LDUMINB
|
|
3U, // LDUMINH
|
|
3U, // LDUMINLB
|
|
3U, // LDUMINLH
|
|
3U, // LDUMINLW
|
|
3U, // LDUMINLX
|
|
3U, // LDUMINW
|
|
3U, // LDUMINX
|
|
3411032U, // LDURBBi
|
|
3411032U, // LDURBi
|
|
3411032U, // LDURDi
|
|
3411032U, // LDURHHi
|
|
3411032U, // LDURHi
|
|
3411032U, // LDURQi
|
|
3411032U, // LDURSBWi
|
|
3411032U, // LDURSBXi
|
|
3411032U, // LDURSHWi
|
|
3411032U, // LDURSHXi
|
|
3411032U, // LDURSWi
|
|
3411032U, // LDURSi
|
|
3411032U, // LDURWi
|
|
3411032U, // LDURXi
|
|
0U, // LDX
|
|
3411216U, // LDXPW
|
|
3411216U, // LDXPX
|
|
608U, // LDXRB
|
|
608U, // LDXRH
|
|
608U, // LDXRW
|
|
608U, // LDXRX
|
|
0U, // LDY
|
|
0U, // LDZ
|
|
0U, // LDZI
|
|
16918656U, // LSLR_ZPmZ_B
|
|
33691776U, // LSLR_ZPmZ_D
|
|
51129480U, // LSLR_ZPmZ_H
|
|
67252352U, // LSLR_ZPmZ_S
|
|
3160U, // LSLVWr
|
|
3160U, // LSLVXr
|
|
33695872U, // LSL_WIDE_ZPmZ_B
|
|
2239624U, // LSL_WIDE_ZPmZ_H
|
|
33697920U, // LSL_WIDE_ZPmZ_S
|
|
6233U, // LSL_WIDE_ZZZ_B
|
|
184U, // LSL_WIDE_ZZZ_H
|
|
6233U, // LSL_WIDE_ZZZ_S
|
|
141440U, // LSL_ZPmI_B
|
|
137344U, // LSL_ZPmI_D
|
|
52440200U, // LSL_ZPmI_H
|
|
143488U, // LSL_ZPmI_S
|
|
16918656U, // LSL_ZPmZ_B
|
|
33691776U, // LSL_ZPmZ_D
|
|
51129480U, // LSL_ZPmZ_H
|
|
67252352U, // LSL_ZPmZ_S
|
|
3161U, // LSL_ZZI_B
|
|
3160U, // LSL_ZZI_D
|
|
224U, // LSL_ZZI_H
|
|
3161U, // LSL_ZZI_S
|
|
16918656U, // LSRR_ZPmZ_B
|
|
33691776U, // LSRR_ZPmZ_D
|
|
51129480U, // LSRR_ZPmZ_H
|
|
67252352U, // LSRR_ZPmZ_S
|
|
3160U, // LSRVWr
|
|
3160U, // LSRVXr
|
|
33695872U, // LSR_WIDE_ZPmZ_B
|
|
2239624U, // LSR_WIDE_ZPmZ_H
|
|
33697920U, // LSR_WIDE_ZPmZ_S
|
|
6233U, // LSR_WIDE_ZZZ_B
|
|
184U, // LSR_WIDE_ZZZ_H
|
|
6233U, // LSR_WIDE_ZZZ_S
|
|
141440U, // LSR_ZPmI_B
|
|
137344U, // LSR_ZPmI_D
|
|
52440200U, // LSR_ZPmI_H
|
|
143488U, // LSR_ZPmI_S
|
|
16918656U, // LSR_ZPmZ_B
|
|
33691776U, // LSR_ZPmZ_D
|
|
51129480U, // LSR_ZPmZ_H
|
|
67252352U, // LSR_ZPmZ_S
|
|
3161U, // LSR_ZZI_B
|
|
3160U, // LSR_ZZI_D
|
|
224U, // LSR_ZZI_H
|
|
3161U, // LSR_ZZI_S
|
|
643U, // LUT2v16f8
|
|
3U, // LUT2v8f16
|
|
643U, // LUT4v16f8
|
|
3U, // LUT4v8f16
|
|
648U, // LUTI2_2ZTZI_B
|
|
648U, // LUTI2_2ZTZI_H
|
|
648U, // LUTI2_2ZTZI_S
|
|
648U, // LUTI2_4ZTZI_B
|
|
648U, // LUTI2_4ZTZI_H
|
|
648U, // LUTI2_4ZTZI_S
|
|
69720U, // LUTI2_S_2ZTZI_B
|
|
69720U, // LUTI2_S_2ZTZI_H
|
|
648U, // LUTI2_S_4ZTZI_B
|
|
648U, // LUTI2_S_4ZTZI_H
|
|
69720U, // LUTI2_ZTZI_B
|
|
648U, // LUTI2_ZTZI_H
|
|
69720U, // LUTI2_ZTZI_S
|
|
650U, // LUTI2_ZZZI_B
|
|
648U, // LUTI2_ZZZI_H
|
|
648U, // LUTI4_2ZTZI_B
|
|
648U, // LUTI4_2ZTZI_H
|
|
648U, // LUTI4_2ZTZI_S
|
|
648U, // LUTI4_4ZTZI_H
|
|
648U, // LUTI4_4ZTZI_S
|
|
656U, // LUTI4_4ZZT2Z
|
|
69720U, // LUTI4_S_2ZTZI_B
|
|
69720U, // LUTI4_S_2ZTZI_H
|
|
648U, // LUTI4_S_4ZTZI_H
|
|
656U, // LUTI4_S_4ZZT2Z
|
|
648U, // LUTI4_Z2ZZI_H
|
|
69720U, // LUTI4_ZTZI_B
|
|
648U, // LUTI4_ZTZI_H
|
|
69720U, // LUTI4_ZTZI_S
|
|
650U, // LUTI4_ZZZI_B
|
|
648U, // LUTI4_ZZZI_H
|
|
0U, // MAC16
|
|
134232U, // MADDPT
|
|
134232U, // MADDWrrr
|
|
134232U, // MADDXrrr
|
|
1112U, // MAD_CPA
|
|
70784U, // MAD_ZPmZZ_B
|
|
285344896U, // MAD_ZPmZZ_D
|
|
53488880U, // MAD_ZPmZZ_H
|
|
302123136U, // MAD_ZPmZZ_S
|
|
16918744U, // MATCH_PPzZZ_B
|
|
51129481U, // MATCH_PPzZZ_H
|
|
0U, // MATFP
|
|
0U, // MATINT
|
|
1112U, // MLA_CPA
|
|
70784U, // MLA_ZPmZZ_B
|
|
285344896U, // MLA_ZPmZZ_D
|
|
53488880U, // MLA_ZPmZZ_H
|
|
302123136U, // MLA_ZPmZZ_S
|
|
53216344U, // MLA_ZZZI_D
|
|
39152U, // MLA_ZZZI_H
|
|
53217368U, // MLA_ZZZI_S
|
|
926864U, // MLAv16i8
|
|
1057944U, // MLAv2i32
|
|
122299544U, // MLAv2i32_indexed
|
|
1189024U, // MLAv4i16
|
|
120464544U, // MLAv4i16_indexed
|
|
402544U, // MLAv4i32
|
|
122299504U, // MLAv4i32_indexed
|
|
533624U, // MLAv8i16
|
|
120464504U, // MLAv8i16_indexed
|
|
1320104U, // MLAv8i8
|
|
70784U, // MLS_ZPmZZ_B
|
|
285344896U, // MLS_ZPmZZ_D
|
|
53488880U, // MLS_ZPmZZ_H
|
|
302123136U, // MLS_ZPmZZ_S
|
|
53216344U, // MLS_ZZZI_D
|
|
39152U, // MLS_ZZZI_H
|
|
53217368U, // MLS_ZZZI_S
|
|
926864U, // MLSv16i8
|
|
1057944U, // MLSv2i32
|
|
122299544U, // MLSv2i32_indexed
|
|
1189024U, // MLSv4i16
|
|
120464544U, // MLSv4i16_indexed
|
|
402544U, // MLSv4i32
|
|
122299504U, // MLSv4i32_indexed
|
|
533624U, // MLSv8i16
|
|
120464504U, // MLSv8i16_indexed
|
|
1320104U, // MLSv8i8
|
|
0U, // MOPSSETGE
|
|
0U, // MOPSSETGEN
|
|
0U, // MOPSSETGET
|
|
0U, // MOPSSETGETN
|
|
3U, // MOVAZ_2ZMI_H_B
|
|
3U, // MOVAZ_2ZMI_H_D
|
|
3U, // MOVAZ_2ZMI_H_H
|
|
3U, // MOVAZ_2ZMI_H_S
|
|
3U, // MOVAZ_2ZMI_V_B
|
|
3U, // MOVAZ_2ZMI_V_D
|
|
3U, // MOVAZ_2ZMI_V_H
|
|
3U, // MOVAZ_2ZMI_V_S
|
|
3U, // MOVAZ_4ZMI_H_B
|
|
3U, // MOVAZ_4ZMI_H_D
|
|
3U, // MOVAZ_4ZMI_H_H
|
|
3U, // MOVAZ_4ZMI_H_S
|
|
3U, // MOVAZ_4ZMI_V_B
|
|
3U, // MOVAZ_4ZMI_V_D
|
|
3U, // MOVAZ_4ZMI_V_H
|
|
3U, // MOVAZ_4ZMI_V_S
|
|
3U, // MOVAZ_VG2_2ZM
|
|
3U, // MOVAZ_VG4_4ZM
|
|
4U, // MOVAZ_ZMI_H_B
|
|
4U, // MOVAZ_ZMI_H_D
|
|
71770U, // MOVAZ_ZMI_H_H
|
|
71770U, // MOVAZ_ZMI_H_Q
|
|
4U, // MOVAZ_ZMI_H_S
|
|
4U, // MOVAZ_ZMI_V_B
|
|
4U, // MOVAZ_ZMI_V_D
|
|
71770U, // MOVAZ_ZMI_V_H
|
|
71770U, // MOVAZ_ZMI_V_Q
|
|
4U, // MOVAZ_ZMI_V_S
|
|
72793U, // MOVA_2ZMXI_H_B
|
|
72793U, // MOVA_2ZMXI_H_D
|
|
72793U, // MOVA_2ZMXI_H_H
|
|
72793U, // MOVA_2ZMXI_H_S
|
|
72793U, // MOVA_2ZMXI_V_B
|
|
72793U, // MOVA_2ZMXI_V_D
|
|
72793U, // MOVA_2ZMXI_V_H
|
|
72793U, // MOVA_2ZMXI_V_S
|
|
73817U, // MOVA_4ZMXI_H_B
|
|
73817U, // MOVA_4ZMXI_H_D
|
|
73817U, // MOVA_4ZMXI_H_H
|
|
73817U, // MOVA_4ZMXI_H_S
|
|
73817U, // MOVA_4ZMXI_V_B
|
|
73817U, // MOVA_4ZMXI_V_D
|
|
73817U, // MOVA_4ZMXI_V_H
|
|
73817U, // MOVA_4ZMXI_V_S
|
|
75416U, // MOVA_MXI2Z_H_B
|
|
76440U, // MOVA_MXI2Z_H_D
|
|
77464U, // MOVA_MXI2Z_H_H
|
|
78488U, // MOVA_MXI2Z_H_S
|
|
75416U, // MOVA_MXI2Z_V_B
|
|
76440U, // MOVA_MXI2Z_V_D
|
|
77464U, // MOVA_MXI2Z_V_H
|
|
78488U, // MOVA_MXI2Z_V_S
|
|
75424U, // MOVA_MXI4Z_H_B
|
|
76448U, // MOVA_MXI4Z_H_D
|
|
77472U, // MOVA_MXI4Z_H_H
|
|
78496U, // MOVA_MXI4Z_H_S
|
|
75424U, // MOVA_MXI4Z_V_B
|
|
76448U, // MOVA_MXI4Z_V_D
|
|
77472U, // MOVA_MXI4Z_V_H
|
|
78496U, // MOVA_MXI4Z_V_S
|
|
3U, // MOVA_VG2_2ZMXI
|
|
192U, // MOVA_VG2_MXI2Z
|
|
3U, // MOVA_VG4_4ZMXI
|
|
192U, // MOVA_VG4_MXI4Z
|
|
4U, // MOVID
|
|
4U, // MOVIv16b_ns
|
|
4U, // MOVIv2d_ns
|
|
684U, // MOVIv2i32
|
|
684U, // MOVIv2s_msl
|
|
684U, // MOVIv4i16
|
|
684U, // MOVIv4i32
|
|
684U, // MOVIv4s_msl
|
|
4U, // MOVIv8b_ns
|
|
684U, // MOVIv8i16
|
|
1U, // MOVKWi
|
|
1U, // MOVKXi
|
|
684U, // MOVNWi
|
|
684U, // MOVNXi
|
|
8U, // MOVPRFX_ZPmZ_B
|
|
16U, // MOVPRFX_ZPmZ_D
|
|
0U, // MOVPRFX_ZPmZ_H
|
|
24U, // MOVPRFX_ZPmZ_S
|
|
10456U, // MOVPRFX_ZPzZ_B
|
|
6360U, // MOVPRFX_ZPzZ_D
|
|
137U, // MOVPRFX_ZPzZ_H
|
|
12504U, // MOVPRFX_ZPzZ_S
|
|
0U, // MOVPRFX_ZZ
|
|
4U, // MOVT
|
|
4U, // MOVT_TIX
|
|
688U, // MOVT_XTI
|
|
684U, // MOVZWi
|
|
684U, // MOVZXi
|
|
0U, // MRRS
|
|
4U, // MRS
|
|
70784U, // MSB_ZPmZZ_B
|
|
285344896U, // MSB_ZPmZZ_D
|
|
53488880U, // MSB_ZPmZZ_H
|
|
302123136U, // MSB_ZPmZZ_S
|
|
0U, // MSR
|
|
0U, // MSRR
|
|
0U, // MSRpstateImm1
|
|
0U, // MSRpstateImm4
|
|
0U, // MSRpstatesvcrImm1
|
|
134232U, // MSUBPT
|
|
134232U, // MSUBWrrr
|
|
134232U, // MSUBXrrr
|
|
0U, // MUL53HI
|
|
0U, // MUL53LO
|
|
3161U, // MUL_ZI_B
|
|
3160U, // MUL_ZI_D
|
|
224U, // MUL_ZI_H
|
|
3161U, // MUL_ZI_S
|
|
16918656U, // MUL_ZPmZ_B
|
|
33691776U, // MUL_ZPmZ_D
|
|
51129480U, // MUL_ZPmZ_H
|
|
67252352U, // MUL_ZPmZ_S
|
|
5904472U, // MUL_ZZZI_D
|
|
40072U, // MUL_ZZZI_H
|
|
5910617U, // MUL_ZZZI_S
|
|
10329U, // MUL_ZZZ_B
|
|
6232U, // MUL_ZZZ_D
|
|
136U, // MUL_ZZZ_H
|
|
12377U, // MUL_ZZZ_S
|
|
925840U, // MULv16i8
|
|
1056920U, // MULv2i32
|
|
340402328U, // MULv2i32_indexed
|
|
1188000U, // MULv4i16
|
|
338567328U, // MULv4i16_indexed
|
|
401520U, // MULv4i32
|
|
340402288U, // MULv4i32_indexed
|
|
532600U, // MULv8i16
|
|
338567288U, // MULv8i16_indexed
|
|
1319080U, // MULv8i8
|
|
684U, // MVNIv2i32
|
|
684U, // MVNIv2s_msl
|
|
684U, // MVNIv4i16
|
|
684U, // MVNIv4i32
|
|
684U, // MVNIv4s_msl
|
|
684U, // MVNIv8i16
|
|
16918744U, // NANDS_PPzPP
|
|
16918744U, // NAND_PPzPP
|
|
33691736U, // NBSL_ZZZZ
|
|
8U, // NEG_ZPmZ_B
|
|
16U, // NEG_ZPmZ_D
|
|
0U, // NEG_ZPmZ_H
|
|
24U, // NEG_ZPmZ_S
|
|
32U, // NEGv16i8
|
|
0U, // NEGv1i64
|
|
40U, // NEGv2i32
|
|
48U, // NEGv2i64
|
|
56U, // NEGv4i16
|
|
64U, // NEGv4i32
|
|
72U, // NEGv8i16
|
|
80U, // NEGv8i8
|
|
16918744U, // NMATCH_PPzZZ_B
|
|
51129481U, // NMATCH_PPzZZ_H
|
|
16918744U, // NORS_PPzPP
|
|
16918744U, // NOR_PPzPP
|
|
8U, // NOT_ZPmZ_B
|
|
16U, // NOT_ZPmZ_D
|
|
0U, // NOT_ZPmZ_H
|
|
24U, // NOT_ZPmZ_S
|
|
32U, // NOTv16i8
|
|
80U, // NOTv8i8
|
|
16918744U, // ORNS_PPzPP
|
|
14424U, // ORNWrs
|
|
14424U, // ORNXrs
|
|
16918744U, // ORN_PPzPP
|
|
925840U, // ORNv16i8
|
|
1319080U, // ORNv8i8
|
|
10328U, // ORQV_VPZ_B
|
|
6232U, // ORQV_VPZ_D
|
|
5208U, // ORQV_VPZ_H
|
|
12376U, // ORQV_VPZ_S
|
|
16918744U, // ORRS_PPzPP
|
|
35928U, // ORRWri
|
|
14424U, // ORRWrs
|
|
36952U, // ORRXri
|
|
14424U, // ORRXrs
|
|
16918744U, // ORR_PPzPP
|
|
36952U, // ORR_ZI
|
|
16918656U, // ORR_ZPmZ_B
|
|
33691776U, // ORR_ZPmZ_D
|
|
51129480U, // ORR_ZPmZ_H
|
|
67252352U, // ORR_ZPmZ_S
|
|
6232U, // ORR_ZZZ
|
|
925840U, // ORRv16i8
|
|
1U, // ORRv2i32
|
|
1U, // ORRv4i16
|
|
1U, // ORRv4i32
|
|
1U, // ORRv8i16
|
|
1319080U, // ORRv8i8
|
|
0U, // ORV_VPZ_B
|
|
0U, // ORV_VPZ_D
|
|
0U, // ORV_VPZ_H
|
|
0U, // ORV_VPZ_S
|
|
1U, // PACDA
|
|
1U, // PACDB
|
|
0U, // PACDZA
|
|
0U, // PACDZB
|
|
3160U, // PACGA
|
|
1U, // PACIA
|
|
0U, // PACIA1716
|
|
0U, // PACIA171615
|
|
0U, // PACIASP
|
|
0U, // PACIASPPC
|
|
0U, // PACIAZ
|
|
1U, // PACIB
|
|
0U, // PACIB1716
|
|
0U, // PACIB171615
|
|
0U, // PACIBSP
|
|
0U, // PACIBSPPC
|
|
0U, // PACIBZ
|
|
0U, // PACIZA
|
|
0U, // PACIZB
|
|
0U, // PACM
|
|
0U, // PACNBIASPPC
|
|
0U, // PACNBIBSPPC
|
|
2U, // PEXT_2PCI_B
|
|
2U, // PEXT_2PCI_D
|
|
2U, // PEXT_2PCI_H
|
|
2U, // PEXT_2PCI_S
|
|
395U, // PEXT_PCI_B
|
|
395U, // PEXT_PCI_D
|
|
2U, // PEXT_PCI_H
|
|
395U, // PEXT_PCI_S
|
|
0U, // PFALSE
|
|
10328U, // PFIRST_B
|
|
392U, // PMOV_PZI_B
|
|
392U, // PMOV_PZI_D
|
|
2U, // PMOV_PZI_H
|
|
392U, // PMOV_PZI_S
|
|
4U, // PMOV_ZIP_B
|
|
2U, // PMOV_ZIP_D
|
|
0U, // PMOV_ZIP_H
|
|
1U, // PMOV_ZIP_S
|
|
12377U, // PMULLB_ZZZ_D
|
|
176U, // PMULLB_ZZZ_H
|
|
0U, // PMULLB_ZZZ_Q
|
|
12377U, // PMULLT_ZZZ_D
|
|
176U, // PMULLT_ZZZ_H
|
|
0U, // PMULLT_ZZZ_Q
|
|
925840U, // PMULLv16i8
|
|
4U, // PMULLv1i64
|
|
4U, // PMULLv2i64
|
|
1319080U, // PMULLv8i8
|
|
10329U, // PMUL_ZZZ_B
|
|
925840U, // PMULv16i8
|
|
1319080U, // PMULv8i8
|
|
10328U, // PNEXT_B
|
|
6232U, // PNEXT_D
|
|
136U, // PNEXT_H
|
|
12376U, // PNEXT_S
|
|
79224U, // PRFB_D_PZI
|
|
696U, // PRFB_D_SCALED
|
|
704U, // PRFB_D_SXTW_SCALED
|
|
712U, // PRFB_D_UXTW_SCALED
|
|
80248U, // PRFB_PRI
|
|
720U, // PRFB_PRR
|
|
79224U, // PRFB_S_PZI
|
|
728U, // PRFB_S_SXTW_SCALED
|
|
736U, // PRFB_S_UXTW_SCALED
|
|
744U, // PRFD_D_PZI
|
|
752U, // PRFD_D_SCALED
|
|
760U, // PRFD_D_SXTW_SCALED
|
|
768U, // PRFD_D_UXTW_SCALED
|
|
80248U, // PRFD_PRI
|
|
776U, // PRFD_PRR
|
|
744U, // PRFD_S_PZI
|
|
784U, // PRFD_S_SXTW_SCALED
|
|
792U, // PRFD_S_UXTW_SCALED
|
|
800U, // PRFH_D_PZI
|
|
808U, // PRFH_D_SCALED
|
|
816U, // PRFH_D_SXTW_SCALED
|
|
824U, // PRFH_D_UXTW_SCALED
|
|
80248U, // PRFH_PRI
|
|
832U, // PRFH_PRR
|
|
800U, // PRFH_S_PZI
|
|
840U, // PRFH_S_SXTW_SCALED
|
|
848U, // PRFH_S_UXTW_SCALED
|
|
1U, // PRFMl
|
|
537005144U, // PRFMroW
|
|
553782360U, // PRFMroX
|
|
65624U, // PRFMui
|
|
3411032U, // PRFUMi
|
|
856U, // PRFW_D_PZI
|
|
864U, // PRFW_D_SCALED
|
|
872U, // PRFW_D_SXTW_SCALED
|
|
880U, // PRFW_D_UXTW_SCALED
|
|
80248U, // PRFW_PRI
|
|
888U, // PRFW_PRR
|
|
856U, // PRFW_S_PZI
|
|
896U, // PRFW_S_SXTW_SCALED
|
|
904U, // PRFW_S_UXTW_SCALED
|
|
11151448U, // PSEL_PPPRI_B
|
|
11147352U, // PSEL_PPPRI_D
|
|
11146328U, // PSEL_PPPRI_H
|
|
11153496U, // PSEL_PPPRI_S
|
|
1U, // PTEST_PP
|
|
1U, // PTRUES_B
|
|
1U, // PTRUES_D
|
|
0U, // PTRUES_H
|
|
1U, // PTRUES_S
|
|
1U, // PTRUE_B
|
|
0U, // PTRUE_C_B
|
|
0U, // PTRUE_C_D
|
|
0U, // PTRUE_C_H
|
|
0U, // PTRUE_C_S
|
|
1U, // PTRUE_D
|
|
0U, // PTRUE_H
|
|
1U, // PTRUE_S
|
|
0U, // PUNPKHI_PP
|
|
0U, // PUNPKLO_PP
|
|
5208U, // RADDHNB_ZZZ_B
|
|
96U, // RADDHNB_ZZZ_H
|
|
6232U, // RADDHNB_ZZZ_S
|
|
7256U, // RADDHNT_ZZZ_B
|
|
24U, // RADDHNT_ZZZ_H
|
|
1112U, // RADDHNT_ZZZ_S
|
|
270440U, // RADDHNv2i64_v2i32
|
|
271464U, // RADDHNv2i64_v4i32
|
|
401520U, // RADDHNv4i32_v4i16
|
|
402544U, // RADDHNv4i32_v8i16
|
|
533624U, // RADDHNv8i16_v16i8
|
|
532600U, // RADDHNv8i16_v8i8
|
|
270440U, // RAX1
|
|
6232U, // RAX1_ZZZ_D
|
|
0U, // RBITWr
|
|
0U, // RBITXr
|
|
8U, // RBIT_ZPmZ_B
|
|
16U, // RBIT_ZPmZ_D
|
|
0U, // RBIT_ZPmZ_H
|
|
24U, // RBIT_ZPmZ_S
|
|
32U, // RBITv16i8
|
|
80U, // RBITv8i8
|
|
3449105U, // RCWCAS
|
|
3449105U, // RCWCASA
|
|
3449105U, // RCWCASAL
|
|
3449105U, // RCWCASL
|
|
0U, // RCWCASP
|
|
0U, // RCWCASPA
|
|
0U, // RCWCASPAL
|
|
0U, // RCWCASPL
|
|
3U, // RCWCLR
|
|
3U, // RCWCLRA
|
|
3U, // RCWCLRAL
|
|
3U, // RCWCLRL
|
|
60690U, // RCWCLRP
|
|
60690U, // RCWCLRPA
|
|
60690U, // RCWCLRPAL
|
|
60690U, // RCWCLRPL
|
|
3U, // RCWCLRS
|
|
3U, // RCWCLRSA
|
|
3U, // RCWCLRSAL
|
|
3U, // RCWCLRSL
|
|
60690U, // RCWCLRSP
|
|
60690U, // RCWCLRSPA
|
|
60690U, // RCWCLRSPAL
|
|
60690U, // RCWCLRSPL
|
|
3449105U, // RCWSCAS
|
|
3449105U, // RCWSCASA
|
|
3449105U, // RCWSCASAL
|
|
3449105U, // RCWSCASL
|
|
0U, // RCWSCASP
|
|
0U, // RCWSCASPA
|
|
0U, // RCWSCASPAL
|
|
0U, // RCWSCASPL
|
|
3U, // RCWSET
|
|
3U, // RCWSETA
|
|
3U, // RCWSETAL
|
|
3U, // RCWSETL
|
|
60690U, // RCWSETP
|
|
60690U, // RCWSETPA
|
|
60690U, // RCWSETPAL
|
|
60690U, // RCWSETPL
|
|
3U, // RCWSETS
|
|
3U, // RCWSETSA
|
|
3U, // RCWSETSAL
|
|
3U, // RCWSETSL
|
|
60690U, // RCWSETSP
|
|
60690U, // RCWSETSPA
|
|
60690U, // RCWSETSPAL
|
|
60690U, // RCWSETSPL
|
|
3U, // RCWSWP
|
|
3U, // RCWSWPA
|
|
3U, // RCWSWPAL
|
|
3U, // RCWSWPL
|
|
60690U, // RCWSWPP
|
|
60690U, // RCWSWPPA
|
|
60690U, // RCWSWPPAL
|
|
60690U, // RCWSWPPL
|
|
3U, // RCWSWPS
|
|
3U, // RCWSWPSA
|
|
3U, // RCWSWPSAL
|
|
3U, // RCWSWPSL
|
|
60690U, // RCWSWPSP
|
|
60690U, // RCWSWPSPA
|
|
60690U, // RCWSWPSPAL
|
|
60690U, // RCWSWPSPL
|
|
912U, // RDFFRS_PPz
|
|
912U, // RDFFR_PPz_REAL
|
|
0U, // RDFFR_P_REAL
|
|
0U, // RDSVLI_XI
|
|
0U, // RDVLI_XI
|
|
0U, // RET
|
|
0U, // RETAA
|
|
0U, // RETAASPPCi
|
|
0U, // RETAASPPCr
|
|
0U, // RETAB
|
|
0U, // RETABSPPCi
|
|
0U, // RETABSPPCr
|
|
0U, // REV16Wr
|
|
0U, // REV16Xr
|
|
32U, // REV16v16i8
|
|
80U, // REV16v8i8
|
|
0U, // REV32Xr
|
|
32U, // REV32v16i8
|
|
56U, // REV32v4i16
|
|
72U, // REV32v8i16
|
|
80U, // REV32v8i8
|
|
32U, // REV64v16i8
|
|
40U, // REV64v2i32
|
|
56U, // REV64v4i16
|
|
64U, // REV64v4i32
|
|
72U, // REV64v8i16
|
|
80U, // REV64v8i8
|
|
16U, // REVB_ZPmZ_D
|
|
0U, // REVB_ZPmZ_H
|
|
24U, // REVB_ZPmZ_S
|
|
4U, // REVD_ZPmZ
|
|
16U, // REVH_ZPmZ_D
|
|
24U, // REVH_ZPmZ_S
|
|
16U, // REVW_ZPmZ_D
|
|
0U, // REVWr
|
|
0U, // REVXr
|
|
1U, // REV_PP_B
|
|
0U, // REV_PP_D
|
|
0U, // REV_PP_H
|
|
1U, // REV_PP_S
|
|
1U, // REV_ZZ_B
|
|
0U, // REV_ZZ_D
|
|
0U, // REV_ZZ_H
|
|
1U, // REV_ZZ_S
|
|
3160U, // RMIF
|
|
3160U, // RORVWr
|
|
3160U, // RORVXr
|
|
0U, // RPRFM
|
|
3160U, // RSHRNB_ZZI_B
|
|
224U, // RSHRNB_ZZI_H
|
|
3160U, // RSHRNB_ZZI_S
|
|
41048U, // RSHRNT_ZZI_B
|
|
376U, // RSHRNT_ZZI_H
|
|
41048U, // RSHRNT_ZZI_S
|
|
41080U, // RSHRNv16i8_shift
|
|
3176U, // RSHRNv2i32_shift
|
|
3184U, // RSHRNv4i16_shift
|
|
41064U, // RSHRNv4i32_shift
|
|
41072U, // RSHRNv8i16_shift
|
|
3192U, // RSHRNv8i8_shift
|
|
5208U, // RSUBHNB_ZZZ_B
|
|
96U, // RSUBHNB_ZZZ_H
|
|
6232U, // RSUBHNB_ZZZ_S
|
|
7256U, // RSUBHNT_ZZZ_B
|
|
24U, // RSUBHNT_ZZZ_H
|
|
1112U, // RSUBHNT_ZZZ_S
|
|
270440U, // RSUBHNv2i64_v2i32
|
|
271464U, // RSUBHNv2i64_v4i32
|
|
401520U, // RSUBHNv4i32_v4i16
|
|
402544U, // RSUBHNv4i32_v8i16
|
|
533624U, // RSUBHNv8i16_v16i8
|
|
532600U, // RSUBHNv8i16_v8i8
|
|
2136U, // SABALB_ZZZ_D
|
|
8U, // SABALB_ZZZ_H
|
|
7256U, // SABALB_ZZZ_S
|
|
2136U, // SABALT_ZZZ_D
|
|
8U, // SABALT_ZZZ_H
|
|
7256U, // SABALT_ZZZ_S
|
|
926864U, // SABALv16i8_v8i16
|
|
1057944U, // SABALv2i32_v2i64
|
|
1189024U, // SABALv4i16_v4i32
|
|
402544U, // SABALv4i32_v2i64
|
|
533624U, // SABALv8i16_v4i32
|
|
1320104U, // SABALv8i8_v8i16
|
|
9U, // SABA_ZZZ_B
|
|
1112U, // SABA_ZZZ_D
|
|
240U, // SABA_ZZZ_H
|
|
2136U, // SABA_ZZZ_S
|
|
926864U, // SABAv16i8
|
|
1057944U, // SABAv2i32
|
|
1189024U, // SABAv4i16
|
|
402544U, // SABAv4i32
|
|
533624U, // SABAv8i16
|
|
1320104U, // SABAv8i8
|
|
12377U, // SABDLB_ZZZ_D
|
|
176U, // SABDLB_ZZZ_H
|
|
5208U, // SABDLB_ZZZ_S
|
|
12377U, // SABDLT_ZZZ_D
|
|
176U, // SABDLT_ZZZ_H
|
|
5208U, // SABDLT_ZZZ_S
|
|
925840U, // SABDLv16i8_v8i16
|
|
1056920U, // SABDLv2i32_v2i64
|
|
1188000U, // SABDLv4i16_v4i32
|
|
401520U, // SABDLv4i32_v2i64
|
|
532600U, // SABDLv8i16_v4i32
|
|
1319080U, // SABDLv8i8_v8i16
|
|
16918656U, // SABD_ZPmZ_B
|
|
33691776U, // SABD_ZPmZ_D
|
|
51129480U, // SABD_ZPmZ_H
|
|
67252352U, // SABD_ZPmZ_S
|
|
925840U, // SABDv16i8
|
|
1056920U, // SABDv2i32
|
|
1188000U, // SABDv4i16
|
|
401520U, // SABDv4i32
|
|
532600U, // SABDv8i16
|
|
1319080U, // SABDv8i8
|
|
2176U, // SADALP_ZPmZ_D
|
|
8U, // SADALP_ZPmZ_H
|
|
7296U, // SADALP_ZPmZ_S
|
|
32U, // SADALPv16i8_v8i16
|
|
40U, // SADALPv2i32_v1i64
|
|
56U, // SADALPv4i16_v2i32
|
|
64U, // SADALPv4i32_v2i64
|
|
72U, // SADALPv8i16_v4i32
|
|
80U, // SADALPv8i8_v4i16
|
|
12377U, // SADDLBT_ZZZ_D
|
|
176U, // SADDLBT_ZZZ_H
|
|
5208U, // SADDLBT_ZZZ_S
|
|
12377U, // SADDLB_ZZZ_D
|
|
176U, // SADDLB_ZZZ_H
|
|
5208U, // SADDLB_ZZZ_S
|
|
32U, // SADDLPv16i8_v8i16
|
|
40U, // SADDLPv2i32_v1i64
|
|
56U, // SADDLPv4i16_v2i32
|
|
64U, // SADDLPv4i32_v2i64
|
|
72U, // SADDLPv8i16_v4i32
|
|
80U, // SADDLPv8i8_v4i16
|
|
12377U, // SADDLT_ZZZ_D
|
|
176U, // SADDLT_ZZZ_H
|
|
5208U, // SADDLT_ZZZ_S
|
|
32U, // SADDLVv16i8v
|
|
56U, // SADDLVv4i16v
|
|
64U, // SADDLVv4i32v
|
|
72U, // SADDLVv8i16v
|
|
80U, // SADDLVv8i8v
|
|
925840U, // SADDLv16i8_v8i16
|
|
1056920U, // SADDLv2i32_v2i64
|
|
1188000U, // SADDLv4i16_v4i32
|
|
401520U, // SADDLv4i32_v2i64
|
|
532600U, // SADDLv8i16_v4i32
|
|
1319080U, // SADDLv8i8_v8i16
|
|
0U, // SADDV_VPZ_B
|
|
0U, // SADDV_VPZ_H
|
|
0U, // SADDV_VPZ_S
|
|
12376U, // SADDWB_ZZZ_D
|
|
176U, // SADDWB_ZZZ_H
|
|
5209U, // SADDWB_ZZZ_S
|
|
12376U, // SADDWT_ZZZ_D
|
|
176U, // SADDWT_ZZZ_H
|
|
5209U, // SADDWT_ZZZ_S
|
|
925816U, // SADDWv16i8_v8i16
|
|
1056872U, // SADDWv2i32_v2i64
|
|
1187952U, // SADDWv4i16_v4i32
|
|
401512U, // SADDWv4i32_v2i64
|
|
532592U, // SADDWv8i16_v4i32
|
|
1319032U, // SADDWv8i8_v8i16
|
|
0U, // SB
|
|
1112U, // SBCLB_ZZZ_D
|
|
2136U, // SBCLB_ZZZ_S
|
|
1112U, // SBCLT_ZZZ_D
|
|
2136U, // SBCLT_ZZZ_S
|
|
3160U, // SBCSWr
|
|
3160U, // SBCSXr
|
|
3160U, // SBCWr
|
|
3160U, // SBCXr
|
|
134232U, // SBFMWri
|
|
134232U, // SBFMXri
|
|
8U, // SCLAMP_VG2_2Z2Z_B
|
|
16U, // SCLAMP_VG2_2Z2Z_D
|
|
240U, // SCLAMP_VG2_2Z2Z_H
|
|
24U, // SCLAMP_VG2_2Z2Z_S
|
|
8U, // SCLAMP_VG4_4Z4Z_B
|
|
16U, // SCLAMP_VG4_4Z4Z_D
|
|
240U, // SCLAMP_VG4_4Z4Z_H
|
|
24U, // SCLAMP_VG4_4Z4Z_S
|
|
9U, // SCLAMP_ZZZ_B
|
|
1112U, // SCLAMP_ZZZ_D
|
|
240U, // SCLAMP_ZZZ_H
|
|
2136U, // SCLAMP_ZZZ_S
|
|
3160U, // SCVTFSWDri
|
|
3160U, // SCVTFSWHri
|
|
3160U, // SCVTFSWSri
|
|
3160U, // SCVTFSXDri
|
|
3160U, // SCVTFSXHri
|
|
3160U, // SCVTFSXSri
|
|
0U, // SCVTFUWDri
|
|
0U, // SCVTFUWHri
|
|
0U, // SCVTFUWSri
|
|
0U, // SCVTFUXDri
|
|
0U, // SCVTFUXHri
|
|
0U, // SCVTFUXSri
|
|
0U, // SCVTF_2Z2Z_StoS
|
|
0U, // SCVTF_4Z4Z_StoS
|
|
16U, // SCVTF_ZPmZ_DtoD
|
|
2U, // SCVTF_ZPmZ_DtoH
|
|
16U, // SCVTF_ZPmZ_DtoS
|
|
0U, // SCVTF_ZPmZ_HtoH
|
|
24U, // SCVTF_ZPmZ_StoD
|
|
1U, // SCVTF_ZPmZ_StoH
|
|
24U, // SCVTF_ZPmZ_StoS
|
|
3160U, // SCVTFd
|
|
3160U, // SCVTFh
|
|
3160U, // SCVTFs
|
|
0U, // SCVTFv1i16
|
|
0U, // SCVTFv1i32
|
|
0U, // SCVTFv1i64
|
|
40U, // SCVTFv2f32
|
|
48U, // SCVTFv2f64
|
|
3224U, // SCVTFv2i32_shift
|
|
3176U, // SCVTFv2i64_shift
|
|
56U, // SCVTFv4f16
|
|
64U, // SCVTFv4f32
|
|
3232U, // SCVTFv4i16_shift
|
|
3184U, // SCVTFv4i32_shift
|
|
72U, // SCVTFv8f16
|
|
3192U, // SCVTFv8i16_shift
|
|
33691776U, // SDIVR_ZPmZ_D
|
|
67252352U, // SDIVR_ZPmZ_S
|
|
3160U, // SDIVWr
|
|
3160U, // SDIVXr
|
|
33691776U, // SDIV_ZPmZ_D
|
|
67252352U, // SDIV_ZPmZ_S
|
|
47640U, // SDOT_VG2_M2Z2Z_BtoS
|
|
2632936U, // SDOT_VG2_M2Z2Z_HtoD
|
|
2632936U, // SDOT_VG2_M2Z2Z_HtoS
|
|
5029400U, // SDOT_VG2_M2ZZI_BToS
|
|
103427304U, // SDOT_VG2_M2ZZI_HToS
|
|
103427304U, // SDOT_VG2_M2ZZI_HtoD
|
|
48664U, // SDOT_VG2_M2ZZ_BtoS
|
|
53095656U, // SDOT_VG2_M2ZZ_HtoD
|
|
53095656U, // SDOT_VG2_M2ZZ_HtoS
|
|
47640U, // SDOT_VG4_M4Z4Z_BtoS
|
|
2632936U, // SDOT_VG4_M4Z4Z_HtoD
|
|
2632936U, // SDOT_VG4_M4Z4Z_HtoS
|
|
5029400U, // SDOT_VG4_M4ZZI_BToS
|
|
103427304U, // SDOT_VG4_M4ZZI_HToS
|
|
103427304U, // SDOT_VG4_M4ZZI_HtoD
|
|
48664U, // SDOT_VG4_M4ZZ_BtoS
|
|
53095656U, // SDOT_VG4_M4ZZ_HtoD
|
|
53095656U, // SDOT_VG4_M4ZZ_HtoS
|
|
53222488U, // SDOT_ZZZI_D
|
|
53222488U, // SDOT_ZZZI_HtoS
|
|
38921U, // SDOT_ZZZI_S
|
|
7256U, // SDOT_ZZZ_D
|
|
7256U, // SDOT_ZZZ_HtoS
|
|
9U, // SDOT_ZZZ_S
|
|
5121168U, // SDOTlanev16i8
|
|
5121192U, // SDOTlanev8i8
|
|
926864U, // SDOTv16i8
|
|
1320104U, // SDOTv8i8
|
|
0U, // SDSB
|
|
16918616U, // SEL_PPPP
|
|
11284376U, // SEL_VG2_2ZC2Z2Z_B
|
|
11414992U, // SEL_VG2_2ZC2Z2Z_D
|
|
11545848U, // SEL_VG2_2ZC2Z2Z_H
|
|
11677144U, // SEL_VG2_2ZC2Z2Z_S
|
|
11284376U, // SEL_VG4_4ZC4Z4Z_B
|
|
11414992U, // SEL_VG4_4ZC4Z4Z_D
|
|
11545848U, // SEL_VG4_4ZC4Z4Z_H
|
|
11677144U, // SEL_VG4_4ZC4Z4Z_S
|
|
16918616U, // SEL_ZPZZ_B
|
|
33691736U, // SEL_ZPZZ_D
|
|
51129480U, // SEL_ZPZZ_H
|
|
67252312U, // SEL_ZPZZ_S
|
|
0U, // SET
|
|
0U, // SETE
|
|
0U, // SETEN
|
|
0U, // SETET
|
|
0U, // SETETN
|
|
0U, // SETF16
|
|
0U, // SETF8
|
|
0U, // SETFFR
|
|
0U, // SETGM
|
|
0U, // SETGMN
|
|
0U, // SETGMT
|
|
0U, // SETGMTN
|
|
0U, // SETGP
|
|
0U, // SETGPN
|
|
0U, // SETGPT
|
|
0U, // SETGPTN
|
|
0U, // SETM
|
|
0U, // SETMN
|
|
0U, // SETMT
|
|
0U, // SETMTN
|
|
0U, // SETP
|
|
0U, // SETPN
|
|
0U, // SETPT
|
|
0U, // SETPTN
|
|
402521U, // SHA1Crrr
|
|
0U, // SHA1Hrr
|
|
402521U, // SHA1Mrrr
|
|
402521U, // SHA1Prrr
|
|
402544U, // SHA1SU0rrr
|
|
64U, // SHA1SU1rr
|
|
402521U, // SHA256H2rrr
|
|
402521U, // SHA256Hrrr
|
|
64U, // SHA256SU0rr
|
|
402544U, // SHA256SU1rrr
|
|
271449U, // SHA512H
|
|
271449U, // SHA512H2
|
|
48U, // SHA512SU0
|
|
271464U, // SHA512SU1
|
|
16918656U, // SHADD_ZPmZ_B
|
|
33691776U, // SHADD_ZPmZ_D
|
|
51129480U, // SHADD_ZPmZ_H
|
|
67252352U, // SHADD_ZPmZ_S
|
|
925840U, // SHADDv16i8
|
|
1056920U, // SHADDv2i32
|
|
1188000U, // SHADDv4i16
|
|
401520U, // SHADDv4i32
|
|
532600U, // SHADDv8i16
|
|
1319080U, // SHADDv8i8
|
|
928U, // SHLLv16i8
|
|
936U, // SHLLv2i32
|
|
944U, // SHLLv4i16
|
|
952U, // SHLLv4i32
|
|
960U, // SHLLv8i16
|
|
968U, // SHLLv8i8
|
|
3160U, // SHLd
|
|
3216U, // SHLv16i8_shift
|
|
3224U, // SHLv2i32_shift
|
|
3176U, // SHLv2i64_shift
|
|
3232U, // SHLv4i16_shift
|
|
3184U, // SHLv4i32_shift
|
|
3192U, // SHLv8i16_shift
|
|
3240U, // SHLv8i8_shift
|
|
3160U, // SHRNB_ZZI_B
|
|
224U, // SHRNB_ZZI_H
|
|
3160U, // SHRNB_ZZI_S
|
|
41048U, // SHRNT_ZZI_B
|
|
376U, // SHRNT_ZZI_H
|
|
41048U, // SHRNT_ZZI_S
|
|
41080U, // SHRNv16i8_shift
|
|
3176U, // SHRNv2i32_shift
|
|
3184U, // SHRNv4i16_shift
|
|
41064U, // SHRNv4i32_shift
|
|
41072U, // SHRNv8i16_shift
|
|
3192U, // SHRNv8i8_shift
|
|
16918656U, // SHSUBR_ZPmZ_B
|
|
33691776U, // SHSUBR_ZPmZ_D
|
|
51129480U, // SHSUBR_ZPmZ_H
|
|
67252352U, // SHSUBR_ZPmZ_S
|
|
16918656U, // SHSUB_ZPmZ_B
|
|
33691776U, // SHSUB_ZPmZ_D
|
|
51129480U, // SHSUB_ZPmZ_H
|
|
67252352U, // SHSUB_ZPmZ_S
|
|
925840U, // SHSUBv16i8
|
|
1056920U, // SHSUBv2i32
|
|
1188000U, // SHSUBv4i16
|
|
401520U, // SHSUBv4i32
|
|
532600U, // SHSUBv8i16
|
|
1319080U, // SHSUBv8i8
|
|
377U, // SLI_ZZI_B
|
|
41048U, // SLI_ZZI_D
|
|
376U, // SLI_ZZI_H
|
|
41048U, // SLI_ZZI_S
|
|
41049U, // SLId
|
|
41104U, // SLIv16i8_shift
|
|
41112U, // SLIv2i32_shift
|
|
41064U, // SLIv2i64_shift
|
|
41120U, // SLIv4i16_shift
|
|
41072U, // SLIv4i32_shift
|
|
41080U, // SLIv8i16_shift
|
|
41128U, // SLIv8i8_shift
|
|
402544U, // SM3PARTW1
|
|
402544U, // SM3PARTW2
|
|
88350832U, // SM3SS1
|
|
122299504U, // SM3TT1A
|
|
122299504U, // SM3TT1B
|
|
122299504U, // SM3TT2A
|
|
122299504U, // SM3TT2B
|
|
64U, // SM4E
|
|
12377U, // SM4EKEY_ZZZ_S
|
|
401520U, // SM4ENCKEY
|
|
12377U, // SM4E_ZZZ_S
|
|
134232U, // SMADDLrrr
|
|
16918656U, // SMAXP_ZPmZ_B
|
|
33691776U, // SMAXP_ZPmZ_D
|
|
51129480U, // SMAXP_ZPmZ_H
|
|
67252352U, // SMAXP_ZPmZ_S
|
|
925840U, // SMAXPv16i8
|
|
1056920U, // SMAXPv2i32
|
|
1188000U, // SMAXPv4i16
|
|
401520U, // SMAXPv4i32
|
|
532600U, // SMAXPv8i16
|
|
1319080U, // SMAXPv8i8
|
|
10328U, // SMAXQV_VPZ_B
|
|
6232U, // SMAXQV_VPZ_D
|
|
5208U, // SMAXQV_VPZ_H
|
|
12376U, // SMAXQV_VPZ_S
|
|
0U, // SMAXV_VPZ_B
|
|
0U, // SMAXV_VPZ_D
|
|
0U, // SMAXV_VPZ_H
|
|
0U, // SMAXV_VPZ_S
|
|
32U, // SMAXVv16i8v
|
|
56U, // SMAXVv4i16v
|
|
64U, // SMAXVv4i32v
|
|
72U, // SMAXVv8i16v
|
|
80U, // SMAXVv8i8v
|
|
3160U, // SMAXWri
|
|
3160U, // SMAXWrr
|
|
3160U, // SMAXXri
|
|
3160U, // SMAXXrr
|
|
920U, // SMAX_VG2_2Z2Z_B
|
|
464U, // SMAX_VG2_2Z2Z_D
|
|
248U, // SMAX_VG2_2Z2Z_H
|
|
472U, // SMAX_VG2_2Z2Z_S
|
|
176U, // SMAX_VG2_2ZZ_B
|
|
184U, // SMAX_VG2_2ZZ_D
|
|
136U, // SMAX_VG2_2ZZ_H
|
|
96U, // SMAX_VG2_2ZZ_S
|
|
920U, // SMAX_VG4_4Z4Z_B
|
|
464U, // SMAX_VG4_4Z4Z_D
|
|
248U, // SMAX_VG4_4Z4Z_H
|
|
472U, // SMAX_VG4_4Z4Z_S
|
|
176U, // SMAX_VG4_4ZZ_B
|
|
184U, // SMAX_VG4_4ZZ_D
|
|
136U, // SMAX_VG4_4ZZ_H
|
|
96U, // SMAX_VG4_4ZZ_S
|
|
3161U, // SMAX_ZI_B
|
|
3160U, // SMAX_ZI_D
|
|
224U, // SMAX_ZI_H
|
|
3161U, // SMAX_ZI_S
|
|
16918656U, // SMAX_ZPmZ_B
|
|
33691776U, // SMAX_ZPmZ_D
|
|
51129480U, // SMAX_ZPmZ_H
|
|
67252352U, // SMAX_ZPmZ_S
|
|
925840U, // SMAXv16i8
|
|
1056920U, // SMAXv2i32
|
|
1188000U, // SMAXv4i16
|
|
401520U, // SMAXv4i32
|
|
532600U, // SMAXv8i16
|
|
1319080U, // SMAXv8i8
|
|
0U, // SMC
|
|
16918656U, // SMINP_ZPmZ_B
|
|
33691776U, // SMINP_ZPmZ_D
|
|
51129480U, // SMINP_ZPmZ_H
|
|
67252352U, // SMINP_ZPmZ_S
|
|
925840U, // SMINPv16i8
|
|
1056920U, // SMINPv2i32
|
|
1188000U, // SMINPv4i16
|
|
401520U, // SMINPv4i32
|
|
532600U, // SMINPv8i16
|
|
1319080U, // SMINPv8i8
|
|
10328U, // SMINQV_VPZ_B
|
|
6232U, // SMINQV_VPZ_D
|
|
5208U, // SMINQV_VPZ_H
|
|
12376U, // SMINQV_VPZ_S
|
|
0U, // SMINV_VPZ_B
|
|
0U, // SMINV_VPZ_D
|
|
0U, // SMINV_VPZ_H
|
|
0U, // SMINV_VPZ_S
|
|
32U, // SMINVv16i8v
|
|
56U, // SMINVv4i16v
|
|
64U, // SMINVv4i32v
|
|
72U, // SMINVv8i16v
|
|
80U, // SMINVv8i8v
|
|
3160U, // SMINWri
|
|
3160U, // SMINWrr
|
|
3160U, // SMINXri
|
|
3160U, // SMINXrr
|
|
920U, // SMIN_VG2_2Z2Z_B
|
|
464U, // SMIN_VG2_2Z2Z_D
|
|
248U, // SMIN_VG2_2Z2Z_H
|
|
472U, // SMIN_VG2_2Z2Z_S
|
|
176U, // SMIN_VG2_2ZZ_B
|
|
184U, // SMIN_VG2_2ZZ_D
|
|
136U, // SMIN_VG2_2ZZ_H
|
|
96U, // SMIN_VG2_2ZZ_S
|
|
920U, // SMIN_VG4_4Z4Z_B
|
|
464U, // SMIN_VG4_4Z4Z_D
|
|
248U, // SMIN_VG4_4Z4Z_H
|
|
472U, // SMIN_VG4_4Z4Z_S
|
|
176U, // SMIN_VG4_4ZZ_B
|
|
184U, // SMIN_VG4_4ZZ_D
|
|
136U, // SMIN_VG4_4ZZ_H
|
|
96U, // SMIN_VG4_4ZZ_S
|
|
3161U, // SMIN_ZI_B
|
|
3160U, // SMIN_ZI_D
|
|
224U, // SMIN_ZI_H
|
|
3161U, // SMIN_ZI_S
|
|
16918656U, // SMIN_ZPmZ_B
|
|
33691776U, // SMIN_ZPmZ_D
|
|
51129480U, // SMIN_ZPmZ_H
|
|
67252352U, // SMIN_ZPmZ_S
|
|
925840U, // SMINv16i8
|
|
1056920U, // SMINv2i32
|
|
1188000U, // SMINv4i16
|
|
401520U, // SMINv4i32
|
|
532600U, // SMINv8i16
|
|
1319080U, // SMINv8i8
|
|
53217368U, // SMLALB_ZZZI_D
|
|
53222488U, // SMLALB_ZZZI_S
|
|
2136U, // SMLALB_ZZZ_D
|
|
8U, // SMLALB_ZZZ_H
|
|
7256U, // SMLALB_ZZZ_S
|
|
38441U, // SMLALL_MZZI_BtoS
|
|
38145U, // SMLALL_MZZI_HtoD
|
|
553U, // SMLALL_MZZ_BtoS
|
|
257U, // SMLALL_MZZ_HtoD
|
|
47640U, // SMLALL_VG2_M2Z2Z_BtoS
|
|
2632936U, // SMLALL_VG2_M2Z2Z_HtoD
|
|
5029400U, // SMLALL_VG2_M2ZZI_BtoS
|
|
103427304U, // SMLALL_VG2_M2ZZI_HtoD
|
|
48666U, // SMLALL_VG2_M2ZZ_BtoS
|
|
53095658U, // SMLALL_VG2_M2ZZ_HtoD
|
|
47640U, // SMLALL_VG4_M4Z4Z_BtoS
|
|
2632936U, // SMLALL_VG4_M4Z4Z_HtoD
|
|
5029400U, // SMLALL_VG4_M4ZZI_BtoS
|
|
103427304U, // SMLALL_VG4_M4ZZI_HtoD
|
|
48667U, // SMLALL_VG4_M4ZZ_BtoS
|
|
53095659U, // SMLALL_VG4_M4ZZ_HtoD
|
|
53217368U, // SMLALT_ZZZI_D
|
|
53222488U, // SMLALT_ZZZI_S
|
|
2136U, // SMLALT_ZZZ_D
|
|
8U, // SMLALT_ZZZ_H
|
|
7256U, // SMLALT_ZZZ_S
|
|
38145U, // SMLAL_MZZI_HtoS
|
|
257U, // SMLAL_MZZ_HtoS
|
|
2632936U, // SMLAL_VG2_M2Z2Z_HtoS
|
|
103427304U, // SMLAL_VG2_M2ZZI_S
|
|
53095656U, // SMLAL_VG2_M2ZZ_HtoS
|
|
2632936U, // SMLAL_VG4_M4Z4Z_HtoS
|
|
103427304U, // SMLAL_VG4_M4ZZI_HtoS
|
|
53095656U, // SMLAL_VG4_M4ZZ_HtoS
|
|
926864U, // SMLALv16i8_v8i16
|
|
122299544U, // SMLALv2i32_indexed
|
|
1057944U, // SMLALv2i32_v2i64
|
|
120464544U, // SMLALv4i16_indexed
|
|
1189024U, // SMLALv4i16_v4i32
|
|
122299504U, // SMLALv4i32_indexed
|
|
402544U, // SMLALv4i32_v2i64
|
|
120464504U, // SMLALv8i16_indexed
|
|
533624U, // SMLALv8i16_v4i32
|
|
1320104U, // SMLALv8i8_v8i16
|
|
53217368U, // SMLSLB_ZZZI_D
|
|
53222488U, // SMLSLB_ZZZI_S
|
|
2136U, // SMLSLB_ZZZ_D
|
|
8U, // SMLSLB_ZZZ_H
|
|
7256U, // SMLSLB_ZZZ_S
|
|
38441U, // SMLSLL_MZZI_BtoS
|
|
38145U, // SMLSLL_MZZI_HtoD
|
|
553U, // SMLSLL_MZZ_BtoS
|
|
257U, // SMLSLL_MZZ_HtoD
|
|
47640U, // SMLSLL_VG2_M2Z2Z_BtoS
|
|
2632936U, // SMLSLL_VG2_M2Z2Z_HtoD
|
|
5029400U, // SMLSLL_VG2_M2ZZI_BtoS
|
|
103427304U, // SMLSLL_VG2_M2ZZI_HtoD
|
|
48666U, // SMLSLL_VG2_M2ZZ_BtoS
|
|
53095658U, // SMLSLL_VG2_M2ZZ_HtoD
|
|
47640U, // SMLSLL_VG4_M4Z4Z_BtoS
|
|
2632936U, // SMLSLL_VG4_M4Z4Z_HtoD
|
|
5029400U, // SMLSLL_VG4_M4ZZI_BtoS
|
|
103427304U, // SMLSLL_VG4_M4ZZI_HtoD
|
|
48667U, // SMLSLL_VG4_M4ZZ_BtoS
|
|
53095659U, // SMLSLL_VG4_M4ZZ_HtoD
|
|
53217368U, // SMLSLT_ZZZI_D
|
|
53222488U, // SMLSLT_ZZZI_S
|
|
2136U, // SMLSLT_ZZZ_D
|
|
8U, // SMLSLT_ZZZ_H
|
|
7256U, // SMLSLT_ZZZ_S
|
|
38145U, // SMLSL_MZZI_HtoS
|
|
257U, // SMLSL_MZZ_HtoS
|
|
2632936U, // SMLSL_VG2_M2Z2Z_HtoS
|
|
103427304U, // SMLSL_VG2_M2ZZI_S
|
|
53095656U, // SMLSL_VG2_M2ZZ_HtoS
|
|
2632936U, // SMLSL_VG4_M4Z4Z_HtoS
|
|
103427304U, // SMLSL_VG4_M4ZZI_HtoS
|
|
53095656U, // SMLSL_VG4_M4ZZ_HtoS
|
|
926864U, // SMLSLv16i8_v8i16
|
|
122299544U, // SMLSLv2i32_indexed
|
|
1057944U, // SMLSLv2i32_v2i64
|
|
120464544U, // SMLSLv4i16_indexed
|
|
1189024U, // SMLSLv4i16_v4i32
|
|
122299504U, // SMLSLv4i32_indexed
|
|
402544U, // SMLSLv4i32_v2i64
|
|
120464504U, // SMLSLv8i16_indexed
|
|
533624U, // SMLSLv8i16_v4i32
|
|
1320104U, // SMLSLv8i8_v8i16
|
|
926864U, // SMMLA
|
|
9U, // SMMLA_ZZZ
|
|
0U, // SMOPA_MPPZZ_D
|
|
0U, // SMOPA_MPPZZ_HtoS
|
|
0U, // SMOPA_MPPZZ_S
|
|
0U, // SMOPS_MPPZZ_D
|
|
0U, // SMOPS_MPPZZ_HtoS
|
|
0U, // SMOPS_MPPZZ_S
|
|
45456U, // SMOVvi16to32
|
|
45456U, // SMOVvi16to32_idx0
|
|
45456U, // SMOVvi16to64
|
|
45456U, // SMOVvi16to64_idx0
|
|
45464U, // SMOVvi32to64
|
|
45464U, // SMOVvi32to64_idx0
|
|
45480U, // SMOVvi8to32
|
|
45480U, // SMOVvi8to32_idx0
|
|
45480U, // SMOVvi8to64
|
|
45480U, // SMOVvi8to64_idx0
|
|
134232U, // SMSUBLrrr
|
|
16918656U, // SMULH_ZPmZ_B
|
|
33691776U, // SMULH_ZPmZ_D
|
|
51129480U, // SMULH_ZPmZ_H
|
|
67252352U, // SMULH_ZPmZ_S
|
|
10329U, // SMULH_ZZZ_B
|
|
6232U, // SMULH_ZZZ_D
|
|
136U, // SMULH_ZZZ_H
|
|
12377U, // SMULH_ZZZ_S
|
|
3160U, // SMULHrr
|
|
5910617U, // SMULLB_ZZZI_D
|
|
5903448U, // SMULLB_ZZZI_S
|
|
12377U, // SMULLB_ZZZ_D
|
|
176U, // SMULLB_ZZZ_H
|
|
5208U, // SMULLB_ZZZ_S
|
|
5910617U, // SMULLT_ZZZI_D
|
|
5903448U, // SMULLT_ZZZI_S
|
|
12377U, // SMULLT_ZZZ_D
|
|
176U, // SMULLT_ZZZ_H
|
|
5208U, // SMULLT_ZZZ_S
|
|
925840U, // SMULLv16i8_v8i16
|
|
340402328U, // SMULLv2i32_indexed
|
|
1056920U, // SMULLv2i32_v2i64
|
|
338567328U, // SMULLv4i16_indexed
|
|
1188000U, // SMULLv4i16_v4i32
|
|
340402288U, // SMULLv4i32_indexed
|
|
401520U, // SMULLv4i32_v2i64
|
|
338567288U, // SMULLv8i16_indexed
|
|
532600U, // SMULLv8i16_v4i32
|
|
1319080U, // SMULLv8i8_v8i16
|
|
80984U, // SPLICE_ZPZZ_B
|
|
82008U, // SPLICE_ZPZZ_D
|
|
248U, // SPLICE_ZPZZ_H
|
|
83032U, // SPLICE_ZPZZ_S
|
|
16918616U, // SPLICE_ZPZ_B
|
|
33691736U, // SPLICE_ZPZ_D
|
|
51129480U, // SPLICE_ZPZ_H
|
|
67252312U, // SPLICE_ZPZ_S
|
|
8U, // SQABS_ZPmZ_B
|
|
16U, // SQABS_ZPmZ_D
|
|
0U, // SQABS_ZPmZ_H
|
|
24U, // SQABS_ZPmZ_S
|
|
32U, // SQABSv16i8
|
|
0U, // SQABSv1i16
|
|
0U, // SQABSv1i32
|
|
0U, // SQABSv1i64
|
|
0U, // SQABSv1i8
|
|
40U, // SQABSv2i32
|
|
48U, // SQABSv2i64
|
|
56U, // SQABSv4i16
|
|
64U, // SQABSv4i32
|
|
72U, // SQABSv8i16
|
|
80U, // SQABSv8i8
|
|
16473U, // SQADD_ZI_B
|
|
17496U, // SQADD_ZI_D
|
|
208U, // SQADD_ZI_H
|
|
18521U, // SQADD_ZI_S
|
|
16918656U, // SQADD_ZPmZ_B
|
|
33691776U, // SQADD_ZPmZ_D
|
|
51129480U, // SQADD_ZPmZ_H
|
|
67252352U, // SQADD_ZPmZ_S
|
|
10329U, // SQADD_ZZZ_B
|
|
6232U, // SQADD_ZZZ_D
|
|
136U, // SQADD_ZZZ_H
|
|
12377U, // SQADD_ZZZ_S
|
|
925840U, // SQADDv16i8
|
|
3160U, // SQADDv1i16
|
|
3160U, // SQADDv1i32
|
|
3160U, // SQADDv1i64
|
|
3160U, // SQADDv1i8
|
|
1056920U, // SQADDv2i32
|
|
270440U, // SQADDv2i64
|
|
1188000U, // SQADDv4i16
|
|
401520U, // SQADDv4i32
|
|
532600U, // SQADDv8i16
|
|
1319080U, // SQADDv8i8
|
|
151136345U, // SQCADD_ZZI_B
|
|
151132248U, // SQCADD_ZZI_D
|
|
3288200U, // SQCADD_ZZI_H
|
|
151138393U, // SQCADD_ZZI_S
|
|
0U, // SQCVTN_Z2Z_StoH
|
|
0U, // SQCVTN_Z4Z_DtoH
|
|
2U, // SQCVTN_Z4Z_StoB
|
|
0U, // SQCVTUN_Z2Z_StoH
|
|
0U, // SQCVTUN_Z4Z_DtoH
|
|
2U, // SQCVTUN_Z4Z_StoB
|
|
0U, // SQCVTU_Z2Z_StoH
|
|
0U, // SQCVTU_Z4Z_DtoH
|
|
2U, // SQCVTU_Z4Z_StoB
|
|
0U, // SQCVT_Z2Z_StoH
|
|
0U, // SQCVT_Z4Z_DtoH
|
|
2U, // SQCVT_Z4Z_StoB
|
|
2U, // SQDECB_XPiI
|
|
4U, // SQDECB_XPiWdI
|
|
2U, // SQDECD_XPiI
|
|
4U, // SQDECD_XPiWdI
|
|
2U, // SQDECD_ZPiI
|
|
2U, // SQDECH_XPiI
|
|
4U, // SQDECH_XPiWdI
|
|
0U, // SQDECH_ZPiI
|
|
84057U, // SQDECP_XPWd_B
|
|
84056U, // SQDECP_XPWd_D
|
|
84056U, // SQDECP_XPWd_H
|
|
84057U, // SQDECP_XPWd_S
|
|
1U, // SQDECP_XP_B
|
|
0U, // SQDECP_XP_D
|
|
0U, // SQDECP_XP_H
|
|
1U, // SQDECP_XP_S
|
|
0U, // SQDECP_ZP_D
|
|
0U, // SQDECP_ZP_H
|
|
0U, // SQDECP_ZP_S
|
|
2U, // SQDECW_XPiI
|
|
4U, // SQDECW_XPiWdI
|
|
2U, // SQDECW_ZPiI
|
|
2136U, // SQDMLALBT_ZZZ_D
|
|
8U, // SQDMLALBT_ZZZ_H
|
|
7256U, // SQDMLALBT_ZZZ_S
|
|
53217368U, // SQDMLALB_ZZZI_D
|
|
53222488U, // SQDMLALB_ZZZI_S
|
|
2136U, // SQDMLALB_ZZZ_D
|
|
8U, // SQDMLALB_ZZZ_H
|
|
7256U, // SQDMLALB_ZZZ_S
|
|
53217368U, // SQDMLALT_ZZZI_D
|
|
53222488U, // SQDMLALT_ZZZI_S
|
|
2136U, // SQDMLALT_ZZZ_D
|
|
8U, // SQDMLALT_ZZZ_H
|
|
7256U, // SQDMLALT_ZZZ_S
|
|
41049U, // SQDMLALi16
|
|
41049U, // SQDMLALi32
|
|
120464473U, // SQDMLALv1i32_indexed
|
|
122299481U, // SQDMLALv1i64_indexed
|
|
122299544U, // SQDMLALv2i32_indexed
|
|
1057944U, // SQDMLALv2i32_v2i64
|
|
120464544U, // SQDMLALv4i16_indexed
|
|
1189024U, // SQDMLALv4i16_v4i32
|
|
122299504U, // SQDMLALv4i32_indexed
|
|
402544U, // SQDMLALv4i32_v2i64
|
|
120464504U, // SQDMLALv8i16_indexed
|
|
533624U, // SQDMLALv8i16_v4i32
|
|
2136U, // SQDMLSLBT_ZZZ_D
|
|
8U, // SQDMLSLBT_ZZZ_H
|
|
7256U, // SQDMLSLBT_ZZZ_S
|
|
53217368U, // SQDMLSLB_ZZZI_D
|
|
53222488U, // SQDMLSLB_ZZZI_S
|
|
2136U, // SQDMLSLB_ZZZ_D
|
|
8U, // SQDMLSLB_ZZZ_H
|
|
7256U, // SQDMLSLB_ZZZ_S
|
|
53217368U, // SQDMLSLT_ZZZI_D
|
|
53222488U, // SQDMLSLT_ZZZI_S
|
|
2136U, // SQDMLSLT_ZZZ_D
|
|
8U, // SQDMLSLT_ZZZ_H
|
|
7256U, // SQDMLSLT_ZZZ_S
|
|
41049U, // SQDMLSLi16
|
|
41049U, // SQDMLSLi32
|
|
120464473U, // SQDMLSLv1i32_indexed
|
|
122299481U, // SQDMLSLv1i64_indexed
|
|
122299544U, // SQDMLSLv2i32_indexed
|
|
1057944U, // SQDMLSLv2i32_v2i64
|
|
120464544U, // SQDMLSLv4i16_indexed
|
|
1189024U, // SQDMLSLv4i16_v4i32
|
|
122299504U, // SQDMLSLv4i32_indexed
|
|
402544U, // SQDMLSLv4i32_v2i64
|
|
120464504U, // SQDMLSLv8i16_indexed
|
|
533624U, // SQDMLSLv8i16_v4i32
|
|
920U, // SQDMULH_VG2_2Z2Z_B
|
|
464U, // SQDMULH_VG2_2Z2Z_D
|
|
248U, // SQDMULH_VG2_2Z2Z_H
|
|
472U, // SQDMULH_VG2_2Z2Z_S
|
|
176U, // SQDMULH_VG2_2ZZ_B
|
|
184U, // SQDMULH_VG2_2ZZ_D
|
|
136U, // SQDMULH_VG2_2ZZ_H
|
|
96U, // SQDMULH_VG2_2ZZ_S
|
|
920U, // SQDMULH_VG4_4Z4Z_B
|
|
464U, // SQDMULH_VG4_4Z4Z_D
|
|
248U, // SQDMULH_VG4_4Z4Z_H
|
|
472U, // SQDMULH_VG4_4Z4Z_S
|
|
176U, // SQDMULH_VG4_4ZZ_B
|
|
184U, // SQDMULH_VG4_4ZZ_D
|
|
136U, // SQDMULH_VG4_4ZZ_H
|
|
96U, // SQDMULH_VG4_4ZZ_S
|
|
5904472U, // SQDMULH_ZZZI_D
|
|
40072U, // SQDMULH_ZZZI_H
|
|
5910617U, // SQDMULH_ZZZI_S
|
|
10329U, // SQDMULH_ZZZ_B
|
|
6232U, // SQDMULH_ZZZ_D
|
|
136U, // SQDMULH_ZZZ_H
|
|
12377U, // SQDMULH_ZZZ_S
|
|
3160U, // SQDMULHv1i16
|
|
338567256U, // SQDMULHv1i16_indexed
|
|
3160U, // SQDMULHv1i32
|
|
340402264U, // SQDMULHv1i32_indexed
|
|
1056920U, // SQDMULHv2i32
|
|
340402328U, // SQDMULHv2i32_indexed
|
|
1188000U, // SQDMULHv4i16
|
|
338567328U, // SQDMULHv4i16_indexed
|
|
401520U, // SQDMULHv4i32
|
|
340402288U, // SQDMULHv4i32_indexed
|
|
532600U, // SQDMULHv8i16
|
|
338567288U, // SQDMULHv8i16_indexed
|
|
5910617U, // SQDMULLB_ZZZI_D
|
|
5903448U, // SQDMULLB_ZZZI_S
|
|
12377U, // SQDMULLB_ZZZ_D
|
|
176U, // SQDMULLB_ZZZ_H
|
|
5208U, // SQDMULLB_ZZZ_S
|
|
5910617U, // SQDMULLT_ZZZI_D
|
|
5903448U, // SQDMULLT_ZZZI_S
|
|
12377U, // SQDMULLT_ZZZ_D
|
|
176U, // SQDMULLT_ZZZ_H
|
|
5208U, // SQDMULLT_ZZZ_S
|
|
3160U, // SQDMULLi16
|
|
3160U, // SQDMULLi32
|
|
338567256U, // SQDMULLv1i32_indexed
|
|
340402264U, // SQDMULLv1i64_indexed
|
|
340402328U, // SQDMULLv2i32_indexed
|
|
1056920U, // SQDMULLv2i32_v2i64
|
|
338567328U, // SQDMULLv4i16_indexed
|
|
1188000U, // SQDMULLv4i16_v4i32
|
|
340402288U, // SQDMULLv4i32_indexed
|
|
401520U, // SQDMULLv4i32_v2i64
|
|
338567288U, // SQDMULLv8i16_indexed
|
|
532600U, // SQDMULLv8i16_v4i32
|
|
2U, // SQINCB_XPiI
|
|
4U, // SQINCB_XPiWdI
|
|
2U, // SQINCD_XPiI
|
|
4U, // SQINCD_XPiWdI
|
|
2U, // SQINCD_ZPiI
|
|
2U, // SQINCH_XPiI
|
|
4U, // SQINCH_XPiWdI
|
|
0U, // SQINCH_ZPiI
|
|
84057U, // SQINCP_XPWd_B
|
|
84056U, // SQINCP_XPWd_D
|
|
84056U, // SQINCP_XPWd_H
|
|
84057U, // SQINCP_XPWd_S
|
|
1U, // SQINCP_XP_B
|
|
0U, // SQINCP_XP_D
|
|
0U, // SQINCP_XP_H
|
|
1U, // SQINCP_XP_S
|
|
0U, // SQINCP_ZP_D
|
|
0U, // SQINCP_ZP_H
|
|
0U, // SQINCP_ZP_S
|
|
2U, // SQINCW_XPiI
|
|
4U, // SQINCW_XPiWdI
|
|
2U, // SQINCW_ZPiI
|
|
8U, // SQNEG_ZPmZ_B
|
|
16U, // SQNEG_ZPmZ_D
|
|
0U, // SQNEG_ZPmZ_H
|
|
24U, // SQNEG_ZPmZ_S
|
|
32U, // SQNEGv16i8
|
|
0U, // SQNEGv1i16
|
|
0U, // SQNEGv1i32
|
|
0U, // SQNEGv1i64
|
|
0U, // SQNEGv1i8
|
|
40U, // SQNEGv2i32
|
|
48U, // SQNEGv2i64
|
|
56U, // SQNEGv4i16
|
|
64U, // SQNEGv4i32
|
|
72U, // SQNEGv8i16
|
|
80U, // SQNEGv8i8
|
|
201496816U, // SQRDCMLAH_ZZZI_H
|
|
187435096U, // SQRDCMLAH_ZZZI_S
|
|
3550217U, // SQRDCMLAH_ZZZ_B
|
|
218235992U, // SQRDCMLAH_ZZZ_D
|
|
3550448U, // SQRDCMLAH_ZZZ_H
|
|
218237016U, // SQRDCMLAH_ZZZ_S
|
|
53216344U, // SQRDMLAH_ZZZI_D
|
|
39152U, // SQRDMLAH_ZZZI_H
|
|
53217368U, // SQRDMLAH_ZZZI_S
|
|
9U, // SQRDMLAH_ZZZ_B
|
|
1112U, // SQRDMLAH_ZZZ_D
|
|
240U, // SQRDMLAH_ZZZ_H
|
|
2136U, // SQRDMLAH_ZZZ_S
|
|
41049U, // SQRDMLAHv1i16
|
|
120464473U, // SQRDMLAHv1i16_indexed
|
|
41049U, // SQRDMLAHv1i32
|
|
122299481U, // SQRDMLAHv1i32_indexed
|
|
1057944U, // SQRDMLAHv2i32
|
|
122299544U, // SQRDMLAHv2i32_indexed
|
|
1189024U, // SQRDMLAHv4i16
|
|
120464544U, // SQRDMLAHv4i16_indexed
|
|
402544U, // SQRDMLAHv4i32
|
|
122299504U, // SQRDMLAHv4i32_indexed
|
|
533624U, // SQRDMLAHv8i16
|
|
120464504U, // SQRDMLAHv8i16_indexed
|
|
53216344U, // SQRDMLSH_ZZZI_D
|
|
39152U, // SQRDMLSH_ZZZI_H
|
|
53217368U, // SQRDMLSH_ZZZI_S
|
|
9U, // SQRDMLSH_ZZZ_B
|
|
1112U, // SQRDMLSH_ZZZ_D
|
|
240U, // SQRDMLSH_ZZZ_H
|
|
2136U, // SQRDMLSH_ZZZ_S
|
|
41049U, // SQRDMLSHv1i16
|
|
120464473U, // SQRDMLSHv1i16_indexed
|
|
41049U, // SQRDMLSHv1i32
|
|
122299481U, // SQRDMLSHv1i32_indexed
|
|
1057944U, // SQRDMLSHv2i32
|
|
122299544U, // SQRDMLSHv2i32_indexed
|
|
1189024U, // SQRDMLSHv4i16
|
|
120464544U, // SQRDMLSHv4i16_indexed
|
|
402544U, // SQRDMLSHv4i32
|
|
122299504U, // SQRDMLSHv4i32_indexed
|
|
533624U, // SQRDMLSHv8i16
|
|
120464504U, // SQRDMLSHv8i16_indexed
|
|
5904472U, // SQRDMULH_ZZZI_D
|
|
40072U, // SQRDMULH_ZZZI_H
|
|
5910617U, // SQRDMULH_ZZZI_S
|
|
10329U, // SQRDMULH_ZZZ_B
|
|
6232U, // SQRDMULH_ZZZ_D
|
|
136U, // SQRDMULH_ZZZ_H
|
|
12377U, // SQRDMULH_ZZZ_S
|
|
3160U, // SQRDMULHv1i16
|
|
338567256U, // SQRDMULHv1i16_indexed
|
|
3160U, // SQRDMULHv1i32
|
|
340402264U, // SQRDMULHv1i32_indexed
|
|
1056920U, // SQRDMULHv2i32
|
|
340402328U, // SQRDMULHv2i32_indexed
|
|
1188000U, // SQRDMULHv4i16
|
|
338567328U, // SQRDMULHv4i16_indexed
|
|
401520U, // SQRDMULHv4i32
|
|
340402288U, // SQRDMULHv4i32_indexed
|
|
532600U, // SQRDMULHv8i16
|
|
338567288U, // SQRDMULHv8i16_indexed
|
|
16918656U, // SQRSHLR_ZPmZ_B
|
|
33691776U, // SQRSHLR_ZPmZ_D
|
|
51129480U, // SQRSHLR_ZPmZ_H
|
|
67252352U, // SQRSHLR_ZPmZ_S
|
|
16918656U, // SQRSHL_ZPmZ_B
|
|
33691776U, // SQRSHL_ZPmZ_D
|
|
51129480U, // SQRSHL_ZPmZ_H
|
|
67252352U, // SQRSHL_ZPmZ_S
|
|
925840U, // SQRSHLv16i8
|
|
3160U, // SQRSHLv1i16
|
|
3160U, // SQRSHLv1i32
|
|
3160U, // SQRSHLv1i64
|
|
3160U, // SQRSHLv1i8
|
|
1056920U, // SQRSHLv2i32
|
|
270440U, // SQRSHLv2i64
|
|
1188000U, // SQRSHLv4i16
|
|
401520U, // SQRSHLv4i32
|
|
532600U, // SQRSHLv8i16
|
|
1319080U, // SQRSHLv8i8
|
|
3160U, // SQRSHRNB_ZZI_B
|
|
224U, // SQRSHRNB_ZZI_H
|
|
3160U, // SQRSHRNB_ZZI_S
|
|
41048U, // SQRSHRNT_ZZI_B
|
|
376U, // SQRSHRNT_ZZI_H
|
|
41048U, // SQRSHRNT_ZZI_S
|
|
3162U, // SQRSHRN_VG4_Z4ZI_B
|
|
224U, // SQRSHRN_VG4_Z4ZI_H
|
|
224U, // SQRSHRN_Z2ZI_StoH
|
|
3160U, // SQRSHRNb
|
|
3160U, // SQRSHRNh
|
|
3160U, // SQRSHRNs
|
|
41080U, // SQRSHRNv16i8_shift
|
|
3176U, // SQRSHRNv2i32_shift
|
|
3184U, // SQRSHRNv4i16_shift
|
|
41064U, // SQRSHRNv4i32_shift
|
|
41072U, // SQRSHRNv8i16_shift
|
|
3192U, // SQRSHRNv8i8_shift
|
|
3160U, // SQRSHRUNB_ZZI_B
|
|
224U, // SQRSHRUNB_ZZI_H
|
|
3160U, // SQRSHRUNB_ZZI_S
|
|
41048U, // SQRSHRUNT_ZZI_B
|
|
376U, // SQRSHRUNT_ZZI_H
|
|
41048U, // SQRSHRUNT_ZZI_S
|
|
3162U, // SQRSHRUN_VG4_Z4ZI_B
|
|
224U, // SQRSHRUN_VG4_Z4ZI_H
|
|
224U, // SQRSHRUN_Z2ZI_StoH
|
|
3160U, // SQRSHRUNb
|
|
3160U, // SQRSHRUNh
|
|
3160U, // SQRSHRUNs
|
|
41080U, // SQRSHRUNv16i8_shift
|
|
3176U, // SQRSHRUNv2i32_shift
|
|
3184U, // SQRSHRUNv4i16_shift
|
|
41064U, // SQRSHRUNv4i32_shift
|
|
41072U, // SQRSHRUNv8i16_shift
|
|
3192U, // SQRSHRUNv8i8_shift
|
|
224U, // SQRSHRU_VG2_Z2ZI_H
|
|
3162U, // SQRSHRU_VG4_Z4ZI_B
|
|
224U, // SQRSHRU_VG4_Z4ZI_H
|
|
224U, // SQRSHR_VG2_Z2ZI_H
|
|
3162U, // SQRSHR_VG4_Z4ZI_B
|
|
224U, // SQRSHR_VG4_Z4ZI_H
|
|
16918656U, // SQSHLR_ZPmZ_B
|
|
33691776U, // SQSHLR_ZPmZ_D
|
|
51129480U, // SQSHLR_ZPmZ_H
|
|
67252352U, // SQSHLR_ZPmZ_S
|
|
141440U, // SQSHLU_ZPmI_B
|
|
137344U, // SQSHLU_ZPmI_D
|
|
52440200U, // SQSHLU_ZPmI_H
|
|
143488U, // SQSHLU_ZPmI_S
|
|
3160U, // SQSHLUb
|
|
3160U, // SQSHLUd
|
|
3160U, // SQSHLUh
|
|
3160U, // SQSHLUs
|
|
3216U, // SQSHLUv16i8_shift
|
|
3224U, // SQSHLUv2i32_shift
|
|
3176U, // SQSHLUv2i64_shift
|
|
3232U, // SQSHLUv4i16_shift
|
|
3184U, // SQSHLUv4i32_shift
|
|
3192U, // SQSHLUv8i16_shift
|
|
3240U, // SQSHLUv8i8_shift
|
|
141440U, // SQSHL_ZPmI_B
|
|
137344U, // SQSHL_ZPmI_D
|
|
52440200U, // SQSHL_ZPmI_H
|
|
143488U, // SQSHL_ZPmI_S
|
|
16918656U, // SQSHL_ZPmZ_B
|
|
33691776U, // SQSHL_ZPmZ_D
|
|
51129480U, // SQSHL_ZPmZ_H
|
|
67252352U, // SQSHL_ZPmZ_S
|
|
3160U, // SQSHLb
|
|
3160U, // SQSHLd
|
|
3160U, // SQSHLh
|
|
3160U, // SQSHLs
|
|
925840U, // SQSHLv16i8
|
|
3216U, // SQSHLv16i8_shift
|
|
3160U, // SQSHLv1i16
|
|
3160U, // SQSHLv1i32
|
|
3160U, // SQSHLv1i64
|
|
3160U, // SQSHLv1i8
|
|
1056920U, // SQSHLv2i32
|
|
3224U, // SQSHLv2i32_shift
|
|
270440U, // SQSHLv2i64
|
|
3176U, // SQSHLv2i64_shift
|
|
1188000U, // SQSHLv4i16
|
|
3232U, // SQSHLv4i16_shift
|
|
401520U, // SQSHLv4i32
|
|
3184U, // SQSHLv4i32_shift
|
|
532600U, // SQSHLv8i16
|
|
3192U, // SQSHLv8i16_shift
|
|
1319080U, // SQSHLv8i8
|
|
3240U, // SQSHLv8i8_shift
|
|
3160U, // SQSHRNB_ZZI_B
|
|
224U, // SQSHRNB_ZZI_H
|
|
3160U, // SQSHRNB_ZZI_S
|
|
41048U, // SQSHRNT_ZZI_B
|
|
376U, // SQSHRNT_ZZI_H
|
|
41048U, // SQSHRNT_ZZI_S
|
|
3160U, // SQSHRNb
|
|
3160U, // SQSHRNh
|
|
3160U, // SQSHRNs
|
|
41080U, // SQSHRNv16i8_shift
|
|
3176U, // SQSHRNv2i32_shift
|
|
3184U, // SQSHRNv4i16_shift
|
|
41064U, // SQSHRNv4i32_shift
|
|
41072U, // SQSHRNv8i16_shift
|
|
3192U, // SQSHRNv8i8_shift
|
|
3160U, // SQSHRUNB_ZZI_B
|
|
224U, // SQSHRUNB_ZZI_H
|
|
3160U, // SQSHRUNB_ZZI_S
|
|
41048U, // SQSHRUNT_ZZI_B
|
|
376U, // SQSHRUNT_ZZI_H
|
|
41048U, // SQSHRUNT_ZZI_S
|
|
3160U, // SQSHRUNb
|
|
3160U, // SQSHRUNh
|
|
3160U, // SQSHRUNs
|
|
41080U, // SQSHRUNv16i8_shift
|
|
3176U, // SQSHRUNv2i32_shift
|
|
3184U, // SQSHRUNv4i16_shift
|
|
41064U, // SQSHRUNv4i32_shift
|
|
41072U, // SQSHRUNv8i16_shift
|
|
3192U, // SQSHRUNv8i8_shift
|
|
16918656U, // SQSUBR_ZPmZ_B
|
|
33691776U, // SQSUBR_ZPmZ_D
|
|
51129480U, // SQSUBR_ZPmZ_H
|
|
67252352U, // SQSUBR_ZPmZ_S
|
|
16473U, // SQSUB_ZI_B
|
|
17496U, // SQSUB_ZI_D
|
|
208U, // SQSUB_ZI_H
|
|
18521U, // SQSUB_ZI_S
|
|
16918656U, // SQSUB_ZPmZ_B
|
|
33691776U, // SQSUB_ZPmZ_D
|
|
51129480U, // SQSUB_ZPmZ_H
|
|
67252352U, // SQSUB_ZPmZ_S
|
|
10329U, // SQSUB_ZZZ_B
|
|
6232U, // SQSUB_ZZZ_D
|
|
136U, // SQSUB_ZZZ_H
|
|
12377U, // SQSUB_ZZZ_S
|
|
925840U, // SQSUBv16i8
|
|
3160U, // SQSUBv1i16
|
|
3160U, // SQSUBv1i32
|
|
3160U, // SQSUBv1i64
|
|
3160U, // SQSUBv1i8
|
|
1056920U, // SQSUBv2i32
|
|
270440U, // SQSUBv2i64
|
|
1188000U, // SQSUBv4i16
|
|
401520U, // SQSUBv4i32
|
|
532600U, // SQSUBv8i16
|
|
1319080U, // SQSUBv8i8
|
|
0U, // SQXTNB_ZZ_B
|
|
0U, // SQXTNB_ZZ_H
|
|
0U, // SQXTNB_ZZ_S
|
|
0U, // SQXTNT_ZZ_B
|
|
0U, // SQXTNT_ZZ_H
|
|
0U, // SQXTNT_ZZ_S
|
|
72U, // SQXTNv16i8
|
|
0U, // SQXTNv1i16
|
|
0U, // SQXTNv1i32
|
|
0U, // SQXTNv1i8
|
|
48U, // SQXTNv2i32
|
|
64U, // SQXTNv4i16
|
|
48U, // SQXTNv4i32
|
|
64U, // SQXTNv8i16
|
|
72U, // SQXTNv8i8
|
|
0U, // SQXTUNB_ZZ_B
|
|
0U, // SQXTUNB_ZZ_H
|
|
0U, // SQXTUNB_ZZ_S
|
|
0U, // SQXTUNT_ZZ_B
|
|
0U, // SQXTUNT_ZZ_H
|
|
0U, // SQXTUNT_ZZ_S
|
|
72U, // SQXTUNv16i8
|
|
0U, // SQXTUNv1i16
|
|
0U, // SQXTUNv1i32
|
|
0U, // SQXTUNv1i8
|
|
48U, // SQXTUNv2i32
|
|
64U, // SQXTUNv4i16
|
|
48U, // SQXTUNv4i32
|
|
64U, // SQXTUNv8i16
|
|
72U, // SQXTUNv8i8
|
|
16918656U, // SRHADD_ZPmZ_B
|
|
33691776U, // SRHADD_ZPmZ_D
|
|
51129480U, // SRHADD_ZPmZ_H
|
|
67252352U, // SRHADD_ZPmZ_S
|
|
925840U, // SRHADDv16i8
|
|
1056920U, // SRHADDv2i32
|
|
1188000U, // SRHADDv4i16
|
|
401520U, // SRHADDv4i32
|
|
532600U, // SRHADDv8i16
|
|
1319080U, // SRHADDv8i8
|
|
377U, // SRI_ZZI_B
|
|
41048U, // SRI_ZZI_D
|
|
376U, // SRI_ZZI_H
|
|
41048U, // SRI_ZZI_S
|
|
41049U, // SRId
|
|
41104U, // SRIv16i8_shift
|
|
41112U, // SRIv2i32_shift
|
|
41064U, // SRIv2i64_shift
|
|
41120U, // SRIv4i16_shift
|
|
41072U, // SRIv4i32_shift
|
|
41080U, // SRIv8i16_shift
|
|
41128U, // SRIv8i8_shift
|
|
16918656U, // SRSHLR_ZPmZ_B
|
|
33691776U, // SRSHLR_ZPmZ_D
|
|
51129480U, // SRSHLR_ZPmZ_H
|
|
67252352U, // SRSHLR_ZPmZ_S
|
|
920U, // SRSHL_VG2_2Z2Z_B
|
|
464U, // SRSHL_VG2_2Z2Z_D
|
|
248U, // SRSHL_VG2_2Z2Z_H
|
|
472U, // SRSHL_VG2_2Z2Z_S
|
|
176U, // SRSHL_VG2_2ZZ_B
|
|
184U, // SRSHL_VG2_2ZZ_D
|
|
136U, // SRSHL_VG2_2ZZ_H
|
|
96U, // SRSHL_VG2_2ZZ_S
|
|
920U, // SRSHL_VG4_4Z4Z_B
|
|
464U, // SRSHL_VG4_4Z4Z_D
|
|
248U, // SRSHL_VG4_4Z4Z_H
|
|
472U, // SRSHL_VG4_4Z4Z_S
|
|
176U, // SRSHL_VG4_4ZZ_B
|
|
184U, // SRSHL_VG4_4ZZ_D
|
|
136U, // SRSHL_VG4_4ZZ_H
|
|
96U, // SRSHL_VG4_4ZZ_S
|
|
16918656U, // SRSHL_ZPmZ_B
|
|
33691776U, // SRSHL_ZPmZ_D
|
|
51129480U, // SRSHL_ZPmZ_H
|
|
67252352U, // SRSHL_ZPmZ_S
|
|
925840U, // SRSHLv16i8
|
|
3160U, // SRSHLv1i64
|
|
1056920U, // SRSHLv2i32
|
|
270440U, // SRSHLv2i64
|
|
1188000U, // SRSHLv4i16
|
|
401520U, // SRSHLv4i32
|
|
532600U, // SRSHLv8i16
|
|
1319080U, // SRSHLv8i8
|
|
141440U, // SRSHR_ZPmI_B
|
|
137344U, // SRSHR_ZPmI_D
|
|
52440200U, // SRSHR_ZPmI_H
|
|
143488U, // SRSHR_ZPmI_S
|
|
3160U, // SRSHRd
|
|
3216U, // SRSHRv16i8_shift
|
|
3224U, // SRSHRv2i32_shift
|
|
3176U, // SRSHRv2i64_shift
|
|
3232U, // SRSHRv4i16_shift
|
|
3184U, // SRSHRv4i32_shift
|
|
3192U, // SRSHRv8i16_shift
|
|
3240U, // SRSHRv8i8_shift
|
|
377U, // SRSRA_ZZI_B
|
|
41048U, // SRSRA_ZZI_D
|
|
376U, // SRSRA_ZZI_H
|
|
41048U, // SRSRA_ZZI_S
|
|
41049U, // SRSRAd
|
|
41104U, // SRSRAv16i8_shift
|
|
41112U, // SRSRAv2i32_shift
|
|
41064U, // SRSRAv2i64_shift
|
|
41120U, // SRSRAv4i16_shift
|
|
41072U, // SRSRAv4i32_shift
|
|
41080U, // SRSRAv8i16_shift
|
|
41128U, // SRSRAv8i8_shift
|
|
3161U, // SSHLLB_ZZI_D
|
|
224U, // SSHLLB_ZZI_H
|
|
3160U, // SSHLLB_ZZI_S
|
|
3161U, // SSHLLT_ZZI_D
|
|
224U, // SSHLLT_ZZI_H
|
|
3160U, // SSHLLT_ZZI_S
|
|
3216U, // SSHLLv16i8_shift
|
|
3224U, // SSHLLv2i32_shift
|
|
3232U, // SSHLLv4i16_shift
|
|
3184U, // SSHLLv4i32_shift
|
|
3192U, // SSHLLv8i16_shift
|
|
3240U, // SSHLLv8i8_shift
|
|
925840U, // SSHLv16i8
|
|
3160U, // SSHLv1i64
|
|
1056920U, // SSHLv2i32
|
|
270440U, // SSHLv2i64
|
|
1188000U, // SSHLv4i16
|
|
401520U, // SSHLv4i32
|
|
532600U, // SSHLv8i16
|
|
1319080U, // SSHLv8i8
|
|
3160U, // SSHRd
|
|
3216U, // SSHRv16i8_shift
|
|
3224U, // SSHRv2i32_shift
|
|
3176U, // SSHRv2i64_shift
|
|
3232U, // SSHRv4i16_shift
|
|
3184U, // SSHRv4i32_shift
|
|
3192U, // SSHRv8i16_shift
|
|
3240U, // SSHRv8i8_shift
|
|
377U, // SSRA_ZZI_B
|
|
41048U, // SSRA_ZZI_D
|
|
376U, // SSRA_ZZI_H
|
|
41048U, // SSRA_ZZI_S
|
|
41049U, // SSRAd
|
|
41104U, // SSRAv16i8_shift
|
|
41112U, // SSRAv2i32_shift
|
|
41064U, // SSRAv2i64_shift
|
|
41120U, // SSRAv4i16_shift
|
|
41072U, // SSRAv4i32_shift
|
|
41080U, // SSRAv8i16_shift
|
|
41128U, // SSRAv8i8_shift
|
|
6040804U, // SST1B_D
|
|
371207356U, // SST1B_D_IMM
|
|
6171876U, // SST1B_D_SXTW
|
|
6302948U, // SST1B_D_UXTW
|
|
371207268U, // SST1B_S_IMM
|
|
6434020U, // SST1B_S_SXTW
|
|
6565092U, // SST1B_S_UXTW
|
|
6040804U, // SST1D
|
|
6696124U, // SST1D_IMM
|
|
6827236U, // SST1D_SCALED
|
|
6171876U, // SST1D_SXTW
|
|
6958308U, // SST1D_SXTW_SCALED
|
|
6302948U, // SST1D_UXTW
|
|
7089380U, // SST1D_UXTW_SCALED
|
|
6040804U, // SST1H_D
|
|
376319164U, // SST1H_D_IMM
|
|
7351524U, // SST1H_D_SCALED
|
|
6171876U, // SST1H_D_SXTW
|
|
7482596U, // SST1H_D_SXTW_SCALED
|
|
6302948U, // SST1H_D_UXTW
|
|
7613668U, // SST1H_D_UXTW_SCALED
|
|
376319076U, // SST1H_S_IMM
|
|
6434020U, // SST1H_S_SXTW
|
|
7744740U, // SST1H_S_SXTW_SCALED
|
|
6565092U, // SST1H_S_UXTW
|
|
7875812U, // SST1H_S_UXTW_SCALED
|
|
371207356U, // SST1Q
|
|
6040804U, // SST1W_D
|
|
377105596U, // SST1W_D_IMM
|
|
8137956U, // SST1W_D_SCALED
|
|
6171876U, // SST1W_D_SXTW
|
|
8269028U, // SST1W_D_SXTW_SCALED
|
|
6302948U, // SST1W_D_UXTW
|
|
8400100U, // SST1W_D_UXTW_SCALED
|
|
377105508U, // SST1W_IMM
|
|
6434020U, // SST1W_SXTW
|
|
8531172U, // SST1W_SXTW_SCALED
|
|
6565092U, // SST1W_UXTW
|
|
8662244U, // SST1W_UXTW_SCALED
|
|
12377U, // SSUBLBT_ZZZ_D
|
|
176U, // SSUBLBT_ZZZ_H
|
|
5208U, // SSUBLBT_ZZZ_S
|
|
12377U, // SSUBLB_ZZZ_D
|
|
176U, // SSUBLB_ZZZ_H
|
|
5208U, // SSUBLB_ZZZ_S
|
|
12377U, // SSUBLTB_ZZZ_D
|
|
176U, // SSUBLTB_ZZZ_H
|
|
5208U, // SSUBLTB_ZZZ_S
|
|
12377U, // SSUBLT_ZZZ_D
|
|
176U, // SSUBLT_ZZZ_H
|
|
5208U, // SSUBLT_ZZZ_S
|
|
925840U, // SSUBLv16i8_v8i16
|
|
1056920U, // SSUBLv2i32_v2i64
|
|
1188000U, // SSUBLv4i16_v4i32
|
|
401520U, // SSUBLv4i32_v2i64
|
|
532600U, // SSUBLv8i16_v4i32
|
|
1319080U, // SSUBLv8i8_v8i16
|
|
12376U, // SSUBWB_ZZZ_D
|
|
176U, // SSUBWB_ZZZ_H
|
|
5209U, // SSUBWB_ZZZ_S
|
|
12376U, // SSUBWT_ZZZ_D
|
|
176U, // SSUBWT_ZZZ_H
|
|
5209U, // SSUBWT_ZZZ_S
|
|
925816U, // SSUBWv16i8_v8i16
|
|
1056872U, // SSUBWv2i32_v2i64
|
|
1187952U, // SSUBWv4i16_v4i32
|
|
401512U, // SSUBWv4i32_v2i64
|
|
532592U, // SSUBWv8i16_v4i32
|
|
1319032U, // SSUBWv8i8_v8i16
|
|
8793316U, // ST1B
|
|
8793316U, // ST1B_2Z
|
|
393096420U, // ST1B_2Z_IMM
|
|
671223059U, // ST1B_2Z_STRIDED
|
|
688000275U, // ST1B_2Z_STRIDED_IMM
|
|
8793316U, // ST1B_4Z
|
|
393882852U, // ST1B_4Z_IMM
|
|
8793316U, // ST1B_4Z_STRIDED
|
|
393882852U, // ST1B_4Z_STRIDED_IMM
|
|
8793316U, // ST1B_D
|
|
387984612U, // ST1B_D_IMM
|
|
8793316U, // ST1B_H
|
|
387984612U, // ST1B_H_IMM
|
|
387984612U, // ST1B_IMM
|
|
8793316U, // ST1B_S
|
|
387984612U, // ST1B_S_IMM
|
|
8924388U, // ST1D
|
|
8924388U, // ST1D_2Z
|
|
393096420U, // ST1D_2Z_IMM
|
|
8924388U, // ST1D_2Z_STRIDED
|
|
393096420U, // ST1D_2Z_STRIDED_IMM
|
|
8924388U, // ST1D_4Z
|
|
393882852U, // ST1D_4Z_IMM
|
|
8924388U, // ST1D_4Z_STRIDED
|
|
393882852U, // ST1D_4Z_STRIDED_IMM
|
|
387984612U, // ST1D_IMM
|
|
8924388U, // ST1D_Q
|
|
387984612U, // ST1D_Q_IMM
|
|
0U, // ST1Fourv16b
|
|
0U, // ST1Fourv16b_POST
|
|
0U, // ST1Fourv1d
|
|
0U, // ST1Fourv1d_POST
|
|
0U, // ST1Fourv2d
|
|
0U, // ST1Fourv2d_POST
|
|
0U, // ST1Fourv2s
|
|
0U, // ST1Fourv2s_POST
|
|
0U, // ST1Fourv4h
|
|
0U, // ST1Fourv4h_POST
|
|
0U, // ST1Fourv4s
|
|
0U, // ST1Fourv4s_POST
|
|
0U, // ST1Fourv8b
|
|
0U, // ST1Fourv8b_POST
|
|
0U, // ST1Fourv8h
|
|
0U, // ST1Fourv8h_POST
|
|
9055460U, // ST1H
|
|
9055460U, // ST1H_2Z
|
|
393096420U, // ST1H_2Z_IMM
|
|
704777491U, // ST1H_2Z_STRIDED
|
|
688000275U, // ST1H_2Z_STRIDED_IMM
|
|
9055460U, // ST1H_4Z
|
|
393882852U, // ST1H_4Z_IMM
|
|
9055460U, // ST1H_4Z_STRIDED
|
|
393882852U, // ST1H_4Z_STRIDED_IMM
|
|
9055460U, // ST1H_D
|
|
387984612U, // ST1H_D_IMM
|
|
387984612U, // ST1H_IMM
|
|
9055460U, // ST1H_S
|
|
387984612U, // ST1H_S_IMM
|
|
0U, // ST1Onev16b
|
|
0U, // ST1Onev16b_POST
|
|
0U, // ST1Onev1d
|
|
0U, // ST1Onev1d_POST
|
|
0U, // ST1Onev2d
|
|
0U, // ST1Onev2d_POST
|
|
0U, // ST1Onev2s
|
|
0U, // ST1Onev2s_POST
|
|
0U, // ST1Onev4h
|
|
0U, // ST1Onev4h_POST
|
|
0U, // ST1Onev4s
|
|
0U, // ST1Onev4s_POST
|
|
0U, // ST1Onev8b
|
|
0U, // ST1Onev8b_POST
|
|
0U, // ST1Onev8h
|
|
0U, // ST1Onev8h_POST
|
|
0U, // ST1Threev16b
|
|
0U, // ST1Threev16b_POST
|
|
0U, // ST1Threev1d
|
|
0U, // ST1Threev1d_POST
|
|
0U, // ST1Threev2d
|
|
0U, // ST1Threev2d_POST
|
|
0U, // ST1Threev2s
|
|
0U, // ST1Threev2s_POST
|
|
0U, // ST1Threev4h
|
|
0U, // ST1Threev4h_POST
|
|
0U, // ST1Threev4s
|
|
0U, // ST1Threev4s_POST
|
|
0U, // ST1Threev8b
|
|
0U, // ST1Threev8b_POST
|
|
0U, // ST1Threev8h
|
|
0U, // ST1Threev8h_POST
|
|
0U, // ST1Twov16b
|
|
0U, // ST1Twov16b_POST
|
|
0U, // ST1Twov1d
|
|
0U, // ST1Twov1d_POST
|
|
0U, // ST1Twov2d
|
|
0U, // ST1Twov2d_POST
|
|
0U, // ST1Twov2s
|
|
0U, // ST1Twov2s_POST
|
|
0U, // ST1Twov4h
|
|
0U, // ST1Twov4h_POST
|
|
0U, // ST1Twov4s
|
|
0U, // ST1Twov4s_POST
|
|
0U, // ST1Twov8b
|
|
0U, // ST1Twov8b_POST
|
|
0U, // ST1Twov8h
|
|
0U, // ST1Twov8h_POST
|
|
9317604U, // ST1W
|
|
9317604U, // ST1W_2Z
|
|
393096420U, // ST1W_2Z_IMM
|
|
9317604U, // ST1W_2Z_STRIDED
|
|
393096420U, // ST1W_2Z_STRIDED_IMM
|
|
9317604U, // ST1W_4Z
|
|
393882852U, // ST1W_4Z_IMM
|
|
9317604U, // ST1W_4Z_STRIDED
|
|
393882852U, // ST1W_4Z_STRIDED_IMM
|
|
9317604U, // ST1W_D
|
|
387984612U, // ST1W_D_IMM
|
|
387984612U, // ST1W_IMM
|
|
9317604U, // ST1W_Q
|
|
387984612U, // ST1W_Q_IMM
|
|
9653848U, // ST1_MXIPXX_H_B
|
|
9784920U, // ST1_MXIPXX_H_D
|
|
9915992U, // ST1_MXIPXX_H_H
|
|
10047064U, // ST1_MXIPXX_H_Q
|
|
10178136U, // ST1_MXIPXX_H_S
|
|
9653848U, // ST1_MXIPXX_V_B
|
|
9784920U, // ST1_MXIPXX_V_D
|
|
9915992U, // ST1_MXIPXX_V_H
|
|
10047064U, // ST1_MXIPXX_V_Q
|
|
10178136U, // ST1_MXIPXX_V_S
|
|
0U, // ST1i16
|
|
4U, // ST1i16_POST
|
|
0U, // ST1i32
|
|
4U, // ST1i32_POST
|
|
0U, // ST1i64
|
|
4U, // ST1i64_POST
|
|
0U, // ST1i8
|
|
5U, // ST1i8_POST
|
|
8793316U, // ST2B
|
|
393096420U, // ST2B_IMM
|
|
8924388U, // ST2D
|
|
393096420U, // ST2D_IMM
|
|
62073U, // ST2GPostIndex
|
|
10940505U, // ST2GPreIndex
|
|
3412056U, // ST2Gi
|
|
9055460U, // ST2H
|
|
393096420U, // ST2H_IMM
|
|
10235108U, // ST2Q
|
|
393096420U, // ST2Q_IMM
|
|
0U, // ST2Twov16b
|
|
0U, // ST2Twov16b_POST
|
|
0U, // ST2Twov2d
|
|
0U, // ST2Twov2d_POST
|
|
0U, // ST2Twov2s
|
|
0U, // ST2Twov2s_POST
|
|
0U, // ST2Twov4h
|
|
0U, // ST2Twov4h_POST
|
|
0U, // ST2Twov4s
|
|
0U, // ST2Twov4s_POST
|
|
0U, // ST2Twov8b
|
|
0U, // ST2Twov8b_POST
|
|
0U, // ST2Twov8h
|
|
0U, // ST2Twov8h_POST
|
|
9317604U, // ST2W
|
|
393096420U, // ST2W_IMM
|
|
0U, // ST2i16
|
|
4U, // ST2i16_POST
|
|
0U, // ST2i32
|
|
4U, // ST2i32_POST
|
|
0U, // ST2i64
|
|
5U, // ST2i64_POST
|
|
0U, // ST2i8
|
|
4U, // ST2i8_POST
|
|
8793316U, // ST3B
|
|
10366180U, // ST3B_IMM
|
|
8924388U, // ST3D
|
|
10366180U, // ST3D_IMM
|
|
9055460U, // ST3H
|
|
10366180U, // ST3H_IMM
|
|
10235108U, // ST3Q
|
|
10366180U, // ST3Q_IMM
|
|
0U, // ST3Threev16b
|
|
0U, // ST3Threev16b_POST
|
|
0U, // ST3Threev2d
|
|
0U, // ST3Threev2d_POST
|
|
0U, // ST3Threev2s
|
|
0U, // ST3Threev2s_POST
|
|
0U, // ST3Threev4h
|
|
0U, // ST3Threev4h_POST
|
|
0U, // ST3Threev4s
|
|
0U, // ST3Threev4s_POST
|
|
0U, // ST3Threev8b
|
|
0U, // ST3Threev8b_POST
|
|
0U, // ST3Threev8h
|
|
0U, // ST3Threev8h_POST
|
|
9317604U, // ST3W
|
|
10366180U, // ST3W_IMM
|
|
0U, // ST3i16
|
|
5U, // ST3i16_POST
|
|
0U, // ST3i32
|
|
5U, // ST3i32_POST
|
|
0U, // ST3i64
|
|
5U, // ST3i64_POST
|
|
0U, // ST3i8
|
|
5U, // ST3i8_POST
|
|
8793316U, // ST4B
|
|
393882852U, // ST4B_IMM
|
|
8924388U, // ST4D
|
|
393882852U, // ST4D_IMM
|
|
0U, // ST4Fourv16b
|
|
0U, // ST4Fourv16b_POST
|
|
0U, // ST4Fourv2d
|
|
0U, // ST4Fourv2d_POST
|
|
0U, // ST4Fourv2s
|
|
0U, // ST4Fourv2s_POST
|
|
0U, // ST4Fourv4h
|
|
0U, // ST4Fourv4h_POST
|
|
0U, // ST4Fourv4s
|
|
0U, // ST4Fourv4s_POST
|
|
0U, // ST4Fourv8b
|
|
0U, // ST4Fourv8b_POST
|
|
0U, // ST4Fourv8h
|
|
0U, // ST4Fourv8h_POST
|
|
9055460U, // ST4H
|
|
393882852U, // ST4H_IMM
|
|
10235108U, // ST4Q
|
|
393882852U, // ST4Q_IMM
|
|
9317604U, // ST4W
|
|
393882852U, // ST4W_IMM
|
|
0U, // ST4i16
|
|
4U, // ST4i16_POST
|
|
0U, // ST4i32
|
|
5U, // ST4i32_POST
|
|
0U, // ST4i64
|
|
5U, // ST4i64_POST
|
|
0U, // ST4i8
|
|
4U, // ST4i8_POST
|
|
0U, // ST64B
|
|
5U, // ST64BV
|
|
5U, // ST64BV0
|
|
608U, // STGM
|
|
419564816U, // STGPi
|
|
62073U, // STGPostIndex
|
|
480551185U, // STGPpost
|
|
469934353U, // STGPpre
|
|
10940505U, // STGPreIndex
|
|
3412056U, // STGi
|
|
3411216U, // STILPW
|
|
11837713U, // STILPWpre
|
|
3411216U, // STILPX
|
|
11968785U, // STILPXpre
|
|
0U, // STL1
|
|
608U, // STLLRB
|
|
608U, // STLLRH
|
|
608U, // STLLRW
|
|
608U, // STLLRX
|
|
608U, // STLRB
|
|
608U, // STLRH
|
|
608U, // STLRW
|
|
977U, // STLRWpre
|
|
608U, // STLRX
|
|
985U, // STLRXpre
|
|
3411032U, // STLURBi
|
|
3411032U, // STLURHi
|
|
3411032U, // STLURWi
|
|
3411032U, // STLURXi
|
|
3411032U, // STLURbi
|
|
3411032U, // STLURdi
|
|
3411032U, // STLURhi
|
|
3411032U, // STLURqi
|
|
3411032U, // STLURsi
|
|
12061784U, // STLXPW
|
|
12061784U, // STLXPX
|
|
3411216U, // STLXRB
|
|
3411216U, // STLXRH
|
|
3411216U, // STLXRW
|
|
3411216U, // STLXRX
|
|
402787600U, // STNPDi
|
|
419564816U, // STNPQi
|
|
436342032U, // STNPSi
|
|
436342032U, // STNPWi
|
|
402787600U, // STNPXi
|
|
8793316U, // STNT1B_2Z
|
|
393096420U, // STNT1B_2Z_IMM
|
|
671223059U, // STNT1B_2Z_STRIDED
|
|
688000275U, // STNT1B_2Z_STRIDED_IMM
|
|
8793316U, // STNT1B_4Z
|
|
393882852U, // STNT1B_4Z_IMM
|
|
8793316U, // STNT1B_4Z_STRIDED
|
|
393882852U, // STNT1B_4Z_STRIDED_IMM
|
|
387984612U, // STNT1B_ZRI
|
|
8793316U, // STNT1B_ZRR
|
|
371207356U, // STNT1B_ZZR_D_REAL
|
|
371207268U, // STNT1B_ZZR_S_REAL
|
|
8924388U, // STNT1D_2Z
|
|
393096420U, // STNT1D_2Z_IMM
|
|
8924388U, // STNT1D_2Z_STRIDED
|
|
393096420U, // STNT1D_2Z_STRIDED_IMM
|
|
8924388U, // STNT1D_4Z
|
|
393882852U, // STNT1D_4Z_IMM
|
|
8924388U, // STNT1D_4Z_STRIDED
|
|
393882852U, // STNT1D_4Z_STRIDED_IMM
|
|
387984612U, // STNT1D_ZRI
|
|
8924388U, // STNT1D_ZRR
|
|
371207356U, // STNT1D_ZZR_D_REAL
|
|
9055460U, // STNT1H_2Z
|
|
393096420U, // STNT1H_2Z_IMM
|
|
704777491U, // STNT1H_2Z_STRIDED
|
|
688000275U, // STNT1H_2Z_STRIDED_IMM
|
|
9055460U, // STNT1H_4Z
|
|
393882852U, // STNT1H_4Z_IMM
|
|
9055460U, // STNT1H_4Z_STRIDED
|
|
393882852U, // STNT1H_4Z_STRIDED_IMM
|
|
387984612U, // STNT1H_ZRI
|
|
9055460U, // STNT1H_ZRR
|
|
371207356U, // STNT1H_ZZR_D_REAL
|
|
371207268U, // STNT1H_ZZR_S_REAL
|
|
9317604U, // STNT1W_2Z
|
|
393096420U, // STNT1W_2Z_IMM
|
|
9317604U, // STNT1W_2Z_STRIDED
|
|
393096420U, // STNT1W_2Z_STRIDED_IMM
|
|
9317604U, // STNT1W_4Z
|
|
393882852U, // STNT1W_4Z_IMM
|
|
9317604U, // STNT1W_4Z_STRIDED
|
|
393882852U, // STNT1W_4Z_STRIDED_IMM
|
|
387984612U, // STNT1W_ZRI
|
|
9317604U, // STNT1W_ZRR
|
|
371207356U, // STNT1W_ZZR_D_REAL
|
|
371207268U, // STNT1W_ZZR_S_REAL
|
|
402787600U, // STPDi
|
|
463773969U, // STPDpost
|
|
453157137U, // STPDpre
|
|
419564816U, // STPQi
|
|
480551185U, // STPQpost
|
|
469934353U, // STPQpre
|
|
436342032U, // STPSi
|
|
497328401U, // STPSpost
|
|
486711569U, // STPSpre
|
|
436342032U, // STPWi
|
|
497328401U, // STPWpost
|
|
486711569U, // STPWpre
|
|
402787600U, // STPXi
|
|
463773969U, // STPXpost
|
|
453157137U, // STPXpre
|
|
41593U, // STRBBpost
|
|
10920025U, // STRBBpre
|
|
503450712U, // STRBBroW
|
|
520227928U, // STRBBroX
|
|
64600U, // STRBBui
|
|
41593U, // STRBpost
|
|
10920025U, // STRBpre
|
|
503450712U, // STRBroW
|
|
520227928U, // STRBroX
|
|
64600U, // STRBui
|
|
41593U, // STRDpost
|
|
10920025U, // STRDpre
|
|
537005144U, // STRDroW
|
|
553782360U, // STRDroX
|
|
65624U, // STRDui
|
|
41593U, // STRHHpost
|
|
10920025U, // STRHHpre
|
|
570559576U, // STRHHroW
|
|
587336792U, // STRHHroX
|
|
66648U, // STRHHui
|
|
41593U, // STRHpost
|
|
10920025U, // STRHpre
|
|
570559576U, // STRHroW
|
|
587336792U, // STRHroX
|
|
66648U, // STRHui
|
|
41593U, // STRQpost
|
|
10920025U, // STRQpre
|
|
604114008U, // STRQroW
|
|
620891224U, // STRQroX
|
|
67672U, // STRQui
|
|
41593U, // STRSpost
|
|
10920025U, // STRSpre
|
|
637668440U, // STRSroW
|
|
654445656U, // STRSroX
|
|
68696U, // STRSui
|
|
41593U, // STRWpost
|
|
10920025U, // STRWpre
|
|
637668440U, // STRWroW
|
|
654445656U, // STRWroX
|
|
68696U, // STRWui
|
|
41593U, // STRXpost
|
|
10920025U, // STRXpre
|
|
537005144U, // STRXroW
|
|
553782360U, // STRXroX
|
|
65624U, // STRXui
|
|
11013208U, // STR_PXI
|
|
608U, // STR_TX
|
|
0U, // STR_ZA
|
|
11013208U, // STR_ZXI
|
|
3411032U, // STTRBi
|
|
3411032U, // STTRHi
|
|
3411032U, // STTRWi
|
|
3411032U, // STTRXi
|
|
3411032U, // STURBBi
|
|
3411032U, // STURBi
|
|
3411032U, // STURDi
|
|
3411032U, // STURHHi
|
|
3411032U, // STURHi
|
|
3411032U, // STURQi
|
|
3411032U, // STURSi
|
|
3411032U, // STURWi
|
|
3411032U, // STURXi
|
|
0U, // STX
|
|
12061784U, // STXPW
|
|
12061784U, // STXPX
|
|
3411216U, // STXRB
|
|
3411216U, // STXRH
|
|
3411216U, // STXRW
|
|
3411216U, // STXRX
|
|
0U, // STY
|
|
0U, // STZ
|
|
62073U, // STZ2GPostIndex
|
|
10940505U, // STZ2GPreIndex
|
|
3412056U, // STZ2Gi
|
|
608U, // STZGM
|
|
62073U, // STZGPostIndex
|
|
10940505U, // STZGPreIndex
|
|
3412056U, // STZGi
|
|
0U, // STZI
|
|
135256U, // SUBG
|
|
5208U, // SUBHNB_ZZZ_B
|
|
96U, // SUBHNB_ZZZ_H
|
|
6232U, // SUBHNB_ZZZ_S
|
|
7256U, // SUBHNT_ZZZ_B
|
|
24U, // SUBHNT_ZZZ_H
|
|
1112U, // SUBHNT_ZZZ_S
|
|
270440U, // SUBHNv2i64_v2i32
|
|
271464U, // SUBHNv2i64_v4i32
|
|
401520U, // SUBHNv4i32_v4i16
|
|
402544U, // SUBHNv4i32_v8i16
|
|
533624U, // SUBHNv8i16_v16i8
|
|
532600U, // SUBHNv8i16_v8i8
|
|
3160U, // SUBP
|
|
3160U, // SUBPS
|
|
658520U, // SUBPT_shift
|
|
16473U, // SUBR_ZI_B
|
|
17496U, // SUBR_ZI_D
|
|
208U, // SUBR_ZI_H
|
|
18521U, // SUBR_ZI_S
|
|
16918656U, // SUBR_ZPmZ_B
|
|
33691776U, // SUBR_ZPmZ_D
|
|
51129480U, // SUBR_ZPmZ_H
|
|
67252352U, // SUBR_ZPmZ_S
|
|
13400U, // SUBSWri
|
|
14424U, // SUBSWrs
|
|
15448U, // SUBSWrx
|
|
13400U, // SUBSXri
|
|
14424U, // SUBSXrs
|
|
15448U, // SUBSXrx
|
|
1444952U, // SUBSXrx64
|
|
13400U, // SUBWri
|
|
14424U, // SUBWrs
|
|
15448U, // SUBWrx
|
|
13400U, // SUBXri
|
|
14424U, // SUBXrs
|
|
15448U, // SUBXrx
|
|
1444952U, // SUBXrx64
|
|
1584320U, // SUB_VG2_M2Z2Z_D
|
|
1715400U, // SUB_VG2_M2Z2Z_S
|
|
52178112U, // SUB_VG2_M2ZZ_D
|
|
52309192U, // SUB_VG2_M2ZZ_S
|
|
192U, // SUB_VG2_M2Z_D
|
|
200U, // SUB_VG2_M2Z_S
|
|
1584320U, // SUB_VG4_M4Z4Z_D
|
|
1715400U, // SUB_VG4_M4Z4Z_S
|
|
52178112U, // SUB_VG4_M4ZZ_D
|
|
52309192U, // SUB_VG4_M4ZZ_S
|
|
192U, // SUB_VG4_M4Z_D
|
|
200U, // SUB_VG4_M4Z_S
|
|
16473U, // SUB_ZI_B
|
|
17496U, // SUB_ZI_D
|
|
208U, // SUB_ZI_H
|
|
18521U, // SUB_ZI_S
|
|
16918656U, // SUB_ZPmZ_B
|
|
33691776U, // SUB_ZPmZ_CPA
|
|
33691776U, // SUB_ZPmZ_D
|
|
51129480U, // SUB_ZPmZ_H
|
|
67252352U, // SUB_ZPmZ_S
|
|
10329U, // SUB_ZZZ_B
|
|
6232U, // SUB_ZZZ_CPA
|
|
6232U, // SUB_ZZZ_D
|
|
136U, // SUB_ZZZ_H
|
|
12377U, // SUB_ZZZ_S
|
|
925840U, // SUBv16i8
|
|
3160U, // SUBv1i64
|
|
1056920U, // SUBv2i32
|
|
270440U, // SUBv2i64
|
|
1188000U, // SUBv4i16
|
|
401520U, // SUBv4i32
|
|
532600U, // SUBv8i16
|
|
1319080U, // SUBv8i8
|
|
5029400U, // SUDOT_VG2_M2ZZI_BToS
|
|
48664U, // SUDOT_VG2_M2ZZ_BToS
|
|
5029400U, // SUDOT_VG4_M4ZZI_BToS
|
|
48664U, // SUDOT_VG4_M4ZZ_BToS
|
|
38921U, // SUDOT_ZZZI
|
|
5121168U, // SUDOTlanev16i8
|
|
5121192U, // SUDOTlanev8i8
|
|
38441U, // SUMLALL_MZZI_BtoS
|
|
5029400U, // SUMLALL_VG2_M2ZZI_BtoS
|
|
48666U, // SUMLALL_VG2_M2ZZ_BtoS
|
|
5029400U, // SUMLALL_VG4_M4ZZI_BtoS
|
|
48667U, // SUMLALL_VG4_M4ZZ_BtoS
|
|
0U, // SUMOPA_MPPZZ_D
|
|
0U, // SUMOPA_MPPZZ_S
|
|
0U, // SUMOPS_MPPZZ_D
|
|
0U, // SUMOPS_MPPZZ_S
|
|
1U, // SUNPKHI_ZZ_D
|
|
0U, // SUNPKHI_ZZ_H
|
|
0U, // SUNPKHI_ZZ_S
|
|
1U, // SUNPKLO_ZZ_D
|
|
0U, // SUNPKLO_ZZ_H
|
|
0U, // SUNPKLO_ZZ_S
|
|
0U, // SUNPK_VG2_2ZZ_D
|
|
0U, // SUNPK_VG2_2ZZ_H
|
|
0U, // SUNPK_VG2_2ZZ_S
|
|
0U, // SUNPK_VG4_4Z2Z_D
|
|
0U, // SUNPK_VG4_4Z2Z_H
|
|
0U, // SUNPK_VG4_4Z2Z_S
|
|
16918656U, // SUQADD_ZPmZ_B
|
|
33691776U, // SUQADD_ZPmZ_D
|
|
51129480U, // SUQADD_ZPmZ_H
|
|
67252352U, // SUQADD_ZPmZ_S
|
|
32U, // SUQADDv16i8
|
|
1U, // SUQADDv1i16
|
|
1U, // SUQADDv1i32
|
|
1U, // SUQADDv1i64
|
|
1U, // SUQADDv1i8
|
|
40U, // SUQADDv2i32
|
|
48U, // SUQADDv2i64
|
|
56U, // SUQADDv4i16
|
|
64U, // SUQADDv4i32
|
|
72U, // SUQADDv8i16
|
|
80U, // SUQADDv8i8
|
|
5029400U, // SUVDOT_VG4_M4ZZI_BToS
|
|
0U, // SVC
|
|
103427304U, // SVDOT_VG2_M2ZZI_HtoS
|
|
5029400U, // SVDOT_VG4_M4ZZI_BtoS
|
|
103427304U, // SVDOT_VG4_M4ZZI_HtoD
|
|
3U, // SWPAB
|
|
3U, // SWPAH
|
|
3U, // SWPALB
|
|
3U, // SWPALH
|
|
3U, // SWPALW
|
|
3U, // SWPALX
|
|
3U, // SWPAW
|
|
3U, // SWPAX
|
|
3U, // SWPB
|
|
3U, // SWPH
|
|
3U, // SWPLB
|
|
3U, // SWPLH
|
|
3U, // SWPLW
|
|
3U, // SWPLX
|
|
60690U, // SWPP
|
|
60690U, // SWPPA
|
|
60690U, // SWPPAL
|
|
60690U, // SWPPL
|
|
3U, // SWPW
|
|
3U, // SWPX
|
|
16U, // SXTB_ZPmZ_D
|
|
0U, // SXTB_ZPmZ_H
|
|
24U, // SXTB_ZPmZ_S
|
|
16U, // SXTH_ZPmZ_D
|
|
24U, // SXTH_ZPmZ_S
|
|
16U, // SXTW_ZPmZ_D
|
|
86104U, // SYSLxt
|
|
997U, // SYSPxt
|
|
1005U, // SYSPxt_XZR
|
|
1013U, // SYSxt
|
|
178U, // TBLQ_ZZZ_B
|
|
5U, // TBLQ_ZZZ_D
|
|
136U, // TBLQ_ZZZ_H
|
|
12378U, // TBLQ_ZZZ_S
|
|
178U, // TBL_ZZZZ_B
|
|
5U, // TBL_ZZZZ_D
|
|
136U, // TBL_ZZZZ_H
|
|
12378U, // TBL_ZZZZ_S
|
|
178U, // TBL_ZZZ_B
|
|
5U, // TBL_ZZZ_D
|
|
136U, // TBL_ZZZ_H
|
|
12378U, // TBL_ZZZ_S
|
|
35U, // TBLv16i8Four
|
|
35U, // TBLv16i8One
|
|
35U, // TBLv16i8Three
|
|
35U, // TBLv16i8Two
|
|
83U, // TBLv8i8Four
|
|
83U, // TBLv8i8One
|
|
83U, // TBLv8i8Three
|
|
83U, // TBLv8i8Two
|
|
87128U, // TBNZW
|
|
87128U, // TBNZX
|
|
9U, // TBXQ_ZZZ_B
|
|
1112U, // TBXQ_ZZZ_D
|
|
240U, // TBXQ_ZZZ_H
|
|
2136U, // TBXQ_ZZZ_S
|
|
9U, // TBX_ZZZ_B
|
|
1112U, // TBX_ZZZ_D
|
|
240U, // TBX_ZZZ_H
|
|
2136U, // TBX_ZZZ_S
|
|
37U, // TBXv16i8Four
|
|
37U, // TBXv16i8One
|
|
37U, // TBXv16i8Three
|
|
37U, // TBXv16i8Two
|
|
85U, // TBXv8i8Four
|
|
85U, // TBXv8i8One
|
|
85U, // TBXv8i8Three
|
|
85U, // TBXv8i8Two
|
|
87128U, // TBZW
|
|
87128U, // TBZX
|
|
0U, // TCANCEL
|
|
0U, // TCOMMIT
|
|
0U, // TRCIT
|
|
10329U, // TRN1_PPP_B
|
|
6232U, // TRN1_PPP_D
|
|
136U, // TRN1_PPP_H
|
|
12377U, // TRN1_PPP_S
|
|
10329U, // TRN1_ZZZ_B
|
|
6232U, // TRN1_ZZZ_D
|
|
136U, // TRN1_ZZZ_H
|
|
1016U, // TRN1_ZZZ_Q
|
|
12377U, // TRN1_ZZZ_S
|
|
925840U, // TRN1v16i8
|
|
1056920U, // TRN1v2i32
|
|
270440U, // TRN1v2i64
|
|
1188000U, // TRN1v4i16
|
|
401520U, // TRN1v4i32
|
|
532600U, // TRN1v8i16
|
|
1319080U, // TRN1v8i8
|
|
10329U, // TRN2_PPP_B
|
|
6232U, // TRN2_PPP_D
|
|
136U, // TRN2_PPP_H
|
|
12377U, // TRN2_PPP_S
|
|
10329U, // TRN2_ZZZ_B
|
|
6232U, // TRN2_ZZZ_D
|
|
136U, // TRN2_ZZZ_H
|
|
1016U, // TRN2_ZZZ_Q
|
|
12377U, // TRN2_ZZZ_S
|
|
925840U, // TRN2v16i8
|
|
1056920U, // TRN2v2i32
|
|
270440U, // TRN2v2i64
|
|
1188000U, // TRN2v4i16
|
|
401520U, // TRN2v4i32
|
|
532600U, // TRN2v8i16
|
|
1319080U, // TRN2v8i8
|
|
0U, // TSB
|
|
0U, // TSTART
|
|
0U, // TTEST
|
|
2136U, // UABALB_ZZZ_D
|
|
8U, // UABALB_ZZZ_H
|
|
7256U, // UABALB_ZZZ_S
|
|
2136U, // UABALT_ZZZ_D
|
|
8U, // UABALT_ZZZ_H
|
|
7256U, // UABALT_ZZZ_S
|
|
926864U, // UABALv16i8_v8i16
|
|
1057944U, // UABALv2i32_v2i64
|
|
1189024U, // UABALv4i16_v4i32
|
|
402544U, // UABALv4i32_v2i64
|
|
533624U, // UABALv8i16_v4i32
|
|
1320104U, // UABALv8i8_v8i16
|
|
9U, // UABA_ZZZ_B
|
|
1112U, // UABA_ZZZ_D
|
|
240U, // UABA_ZZZ_H
|
|
2136U, // UABA_ZZZ_S
|
|
926864U, // UABAv16i8
|
|
1057944U, // UABAv2i32
|
|
1189024U, // UABAv4i16
|
|
402544U, // UABAv4i32
|
|
533624U, // UABAv8i16
|
|
1320104U, // UABAv8i8
|
|
12377U, // UABDLB_ZZZ_D
|
|
176U, // UABDLB_ZZZ_H
|
|
5208U, // UABDLB_ZZZ_S
|
|
12377U, // UABDLT_ZZZ_D
|
|
176U, // UABDLT_ZZZ_H
|
|
5208U, // UABDLT_ZZZ_S
|
|
925840U, // UABDLv16i8_v8i16
|
|
1056920U, // UABDLv2i32_v2i64
|
|
1188000U, // UABDLv4i16_v4i32
|
|
401520U, // UABDLv4i32_v2i64
|
|
532600U, // UABDLv8i16_v4i32
|
|
1319080U, // UABDLv8i8_v8i16
|
|
16918656U, // UABD_ZPmZ_B
|
|
33691776U, // UABD_ZPmZ_D
|
|
51129480U, // UABD_ZPmZ_H
|
|
67252352U, // UABD_ZPmZ_S
|
|
925840U, // UABDv16i8
|
|
1056920U, // UABDv2i32
|
|
1188000U, // UABDv4i16
|
|
401520U, // UABDv4i32
|
|
532600U, // UABDv8i16
|
|
1319080U, // UABDv8i8
|
|
2176U, // UADALP_ZPmZ_D
|
|
8U, // UADALP_ZPmZ_H
|
|
7296U, // UADALP_ZPmZ_S
|
|
32U, // UADALPv16i8_v8i16
|
|
40U, // UADALPv2i32_v1i64
|
|
56U, // UADALPv4i16_v2i32
|
|
64U, // UADALPv4i32_v2i64
|
|
72U, // UADALPv8i16_v4i32
|
|
80U, // UADALPv8i8_v4i16
|
|
12377U, // UADDLB_ZZZ_D
|
|
176U, // UADDLB_ZZZ_H
|
|
5208U, // UADDLB_ZZZ_S
|
|
32U, // UADDLPv16i8_v8i16
|
|
40U, // UADDLPv2i32_v1i64
|
|
56U, // UADDLPv4i16_v2i32
|
|
64U, // UADDLPv4i32_v2i64
|
|
72U, // UADDLPv8i16_v4i32
|
|
80U, // UADDLPv8i8_v4i16
|
|
12377U, // UADDLT_ZZZ_D
|
|
176U, // UADDLT_ZZZ_H
|
|
5208U, // UADDLT_ZZZ_S
|
|
32U, // UADDLVv16i8v
|
|
56U, // UADDLVv4i16v
|
|
64U, // UADDLVv4i32v
|
|
72U, // UADDLVv8i16v
|
|
80U, // UADDLVv8i8v
|
|
925840U, // UADDLv16i8_v8i16
|
|
1056920U, // UADDLv2i32_v2i64
|
|
1188000U, // UADDLv4i16_v4i32
|
|
401520U, // UADDLv4i32_v2i64
|
|
532600U, // UADDLv8i16_v4i32
|
|
1319080U, // UADDLv8i8_v8i16
|
|
0U, // UADDV_VPZ_B
|
|
0U, // UADDV_VPZ_D
|
|
0U, // UADDV_VPZ_H
|
|
0U, // UADDV_VPZ_S
|
|
12376U, // UADDWB_ZZZ_D
|
|
176U, // UADDWB_ZZZ_H
|
|
5209U, // UADDWB_ZZZ_S
|
|
12376U, // UADDWT_ZZZ_D
|
|
176U, // UADDWT_ZZZ_H
|
|
5209U, // UADDWT_ZZZ_S
|
|
925816U, // UADDWv16i8_v8i16
|
|
1056872U, // UADDWv2i32_v2i64
|
|
1187952U, // UADDWv4i16_v4i32
|
|
401512U, // UADDWv4i32_v2i64
|
|
532592U, // UADDWv8i16_v4i32
|
|
1319032U, // UADDWv8i8_v8i16
|
|
134232U, // UBFMWri
|
|
134232U, // UBFMXri
|
|
8U, // UCLAMP_VG2_2Z2Z_B
|
|
16U, // UCLAMP_VG2_2Z2Z_D
|
|
240U, // UCLAMP_VG2_2Z2Z_H
|
|
24U, // UCLAMP_VG2_2Z2Z_S
|
|
8U, // UCLAMP_VG4_4Z4Z_B
|
|
16U, // UCLAMP_VG4_4Z4Z_D
|
|
240U, // UCLAMP_VG4_4Z4Z_H
|
|
24U, // UCLAMP_VG4_4Z4Z_S
|
|
9U, // UCLAMP_ZZZ_B
|
|
1112U, // UCLAMP_ZZZ_D
|
|
240U, // UCLAMP_ZZZ_H
|
|
2136U, // UCLAMP_ZZZ_S
|
|
3160U, // UCVTFSWDri
|
|
3160U, // UCVTFSWHri
|
|
3160U, // UCVTFSWSri
|
|
3160U, // UCVTFSXDri
|
|
3160U, // UCVTFSXHri
|
|
3160U, // UCVTFSXSri
|
|
0U, // UCVTFUWDri
|
|
0U, // UCVTFUWHri
|
|
0U, // UCVTFUWSri
|
|
0U, // UCVTFUXDri
|
|
0U, // UCVTFUXHri
|
|
0U, // UCVTFUXSri
|
|
0U, // UCVTF_2Z2Z_StoS
|
|
0U, // UCVTF_4Z4Z_StoS
|
|
16U, // UCVTF_ZPmZ_DtoD
|
|
2U, // UCVTF_ZPmZ_DtoH
|
|
16U, // UCVTF_ZPmZ_DtoS
|
|
0U, // UCVTF_ZPmZ_HtoH
|
|
24U, // UCVTF_ZPmZ_StoD
|
|
1U, // UCVTF_ZPmZ_StoH
|
|
24U, // UCVTF_ZPmZ_StoS
|
|
3160U, // UCVTFd
|
|
3160U, // UCVTFh
|
|
3160U, // UCVTFs
|
|
0U, // UCVTFv1i16
|
|
0U, // UCVTFv1i32
|
|
0U, // UCVTFv1i64
|
|
40U, // UCVTFv2f32
|
|
48U, // UCVTFv2f64
|
|
3224U, // UCVTFv2i32_shift
|
|
3176U, // UCVTFv2i64_shift
|
|
56U, // UCVTFv4f16
|
|
64U, // UCVTFv4f32
|
|
3232U, // UCVTFv4i16_shift
|
|
3184U, // UCVTFv4i32_shift
|
|
72U, // UCVTFv8f16
|
|
3192U, // UCVTFv8i16_shift
|
|
0U, // UDF
|
|
33691776U, // UDIVR_ZPmZ_D
|
|
67252352U, // UDIVR_ZPmZ_S
|
|
3160U, // UDIVWr
|
|
3160U, // UDIVXr
|
|
33691776U, // UDIV_ZPmZ_D
|
|
67252352U, // UDIV_ZPmZ_S
|
|
47640U, // UDOT_VG2_M2Z2Z_BtoS
|
|
2632936U, // UDOT_VG2_M2Z2Z_HtoD
|
|
2632936U, // UDOT_VG2_M2Z2Z_HtoS
|
|
5029400U, // UDOT_VG2_M2ZZI_BToS
|
|
103427304U, // UDOT_VG2_M2ZZI_HToS
|
|
103427304U, // UDOT_VG2_M2ZZI_HtoD
|
|
48664U, // UDOT_VG2_M2ZZ_BtoS
|
|
53095656U, // UDOT_VG2_M2ZZ_HtoD
|
|
53095656U, // UDOT_VG2_M2ZZ_HtoS
|
|
47640U, // UDOT_VG4_M4Z4Z_BtoS
|
|
2632936U, // UDOT_VG4_M4Z4Z_HtoD
|
|
2632936U, // UDOT_VG4_M4Z4Z_HtoS
|
|
5029400U, // UDOT_VG4_M4ZZI_BtoS
|
|
103427304U, // UDOT_VG4_M4ZZI_HToS
|
|
103427304U, // UDOT_VG4_M4ZZI_HtoD
|
|
48664U, // UDOT_VG4_M4ZZ_BtoS
|
|
53095656U, // UDOT_VG4_M4ZZ_HtoD
|
|
53095656U, // UDOT_VG4_M4ZZ_HtoS
|
|
53222488U, // UDOT_ZZZI_D
|
|
53222488U, // UDOT_ZZZI_HtoS
|
|
38921U, // UDOT_ZZZI_S
|
|
7256U, // UDOT_ZZZ_D
|
|
7256U, // UDOT_ZZZ_HtoS
|
|
9U, // UDOT_ZZZ_S
|
|
5121168U, // UDOTlanev16i8
|
|
5121192U, // UDOTlanev8i8
|
|
926864U, // UDOTv16i8
|
|
1320104U, // UDOTv8i8
|
|
16918656U, // UHADD_ZPmZ_B
|
|
33691776U, // UHADD_ZPmZ_D
|
|
51129480U, // UHADD_ZPmZ_H
|
|
67252352U, // UHADD_ZPmZ_S
|
|
925840U, // UHADDv16i8
|
|
1056920U, // UHADDv2i32
|
|
1188000U, // UHADDv4i16
|
|
401520U, // UHADDv4i32
|
|
532600U, // UHADDv8i16
|
|
1319080U, // UHADDv8i8
|
|
16918656U, // UHSUBR_ZPmZ_B
|
|
33691776U, // UHSUBR_ZPmZ_D
|
|
51129480U, // UHSUBR_ZPmZ_H
|
|
67252352U, // UHSUBR_ZPmZ_S
|
|
16918656U, // UHSUB_ZPmZ_B
|
|
33691776U, // UHSUB_ZPmZ_D
|
|
51129480U, // UHSUB_ZPmZ_H
|
|
67252352U, // UHSUB_ZPmZ_S
|
|
925840U, // UHSUBv16i8
|
|
1056920U, // UHSUBv2i32
|
|
1188000U, // UHSUBv4i16
|
|
401520U, // UHSUBv4i32
|
|
532600U, // UHSUBv8i16
|
|
1319080U, // UHSUBv8i8
|
|
134232U, // UMADDLrrr
|
|
16918656U, // UMAXP_ZPmZ_B
|
|
33691776U, // UMAXP_ZPmZ_D
|
|
51129480U, // UMAXP_ZPmZ_H
|
|
67252352U, // UMAXP_ZPmZ_S
|
|
925840U, // UMAXPv16i8
|
|
1056920U, // UMAXPv2i32
|
|
1188000U, // UMAXPv4i16
|
|
401520U, // UMAXPv4i32
|
|
532600U, // UMAXPv8i16
|
|
1319080U, // UMAXPv8i8
|
|
10328U, // UMAXQV_VPZ_B
|
|
6232U, // UMAXQV_VPZ_D
|
|
5208U, // UMAXQV_VPZ_H
|
|
12376U, // UMAXQV_VPZ_S
|
|
0U, // UMAXV_VPZ_B
|
|
0U, // UMAXV_VPZ_D
|
|
0U, // UMAXV_VPZ_H
|
|
0U, // UMAXV_VPZ_S
|
|
32U, // UMAXVv16i8v
|
|
56U, // UMAXVv4i16v
|
|
64U, // UMAXVv4i32v
|
|
72U, // UMAXVv8i16v
|
|
80U, // UMAXVv8i8v
|
|
3160U, // UMAXWri
|
|
3160U, // UMAXWrr
|
|
3160U, // UMAXXri
|
|
3160U, // UMAXXrr
|
|
920U, // UMAX_VG2_2Z2Z_B
|
|
464U, // UMAX_VG2_2Z2Z_D
|
|
248U, // UMAX_VG2_2Z2Z_H
|
|
472U, // UMAX_VG2_2Z2Z_S
|
|
176U, // UMAX_VG2_2ZZ_B
|
|
184U, // UMAX_VG2_2ZZ_D
|
|
136U, // UMAX_VG2_2ZZ_H
|
|
96U, // UMAX_VG2_2ZZ_S
|
|
920U, // UMAX_VG4_4Z4Z_B
|
|
464U, // UMAX_VG4_4Z4Z_D
|
|
248U, // UMAX_VG4_4Z4Z_H
|
|
472U, // UMAX_VG4_4Z4Z_S
|
|
176U, // UMAX_VG4_4ZZ_B
|
|
184U, // UMAX_VG4_4ZZ_D
|
|
136U, // UMAX_VG4_4ZZ_H
|
|
96U, // UMAX_VG4_4ZZ_S
|
|
88153U, // UMAX_ZI_B
|
|
88152U, // UMAX_ZI_D
|
|
448U, // UMAX_ZI_H
|
|
88153U, // UMAX_ZI_S
|
|
16918656U, // UMAX_ZPmZ_B
|
|
33691776U, // UMAX_ZPmZ_D
|
|
51129480U, // UMAX_ZPmZ_H
|
|
67252352U, // UMAX_ZPmZ_S
|
|
925840U, // UMAXv16i8
|
|
1056920U, // UMAXv2i32
|
|
1188000U, // UMAXv4i16
|
|
401520U, // UMAXv4i32
|
|
532600U, // UMAXv8i16
|
|
1319080U, // UMAXv8i8
|
|
16918656U, // UMINP_ZPmZ_B
|
|
33691776U, // UMINP_ZPmZ_D
|
|
51129480U, // UMINP_ZPmZ_H
|
|
67252352U, // UMINP_ZPmZ_S
|
|
925840U, // UMINPv16i8
|
|
1056920U, // UMINPv2i32
|
|
1188000U, // UMINPv4i16
|
|
401520U, // UMINPv4i32
|
|
532600U, // UMINPv8i16
|
|
1319080U, // UMINPv8i8
|
|
10328U, // UMINQV_VPZ_B
|
|
6232U, // UMINQV_VPZ_D
|
|
5208U, // UMINQV_VPZ_H
|
|
12376U, // UMINQV_VPZ_S
|
|
0U, // UMINV_VPZ_B
|
|
0U, // UMINV_VPZ_D
|
|
0U, // UMINV_VPZ_H
|
|
0U, // UMINV_VPZ_S
|
|
32U, // UMINVv16i8v
|
|
56U, // UMINVv4i16v
|
|
64U, // UMINVv4i32v
|
|
72U, // UMINVv8i16v
|
|
80U, // UMINVv8i8v
|
|
3160U, // UMINWri
|
|
3160U, // UMINWrr
|
|
3160U, // UMINXri
|
|
3160U, // UMINXrr
|
|
920U, // UMIN_VG2_2Z2Z_B
|
|
464U, // UMIN_VG2_2Z2Z_D
|
|
248U, // UMIN_VG2_2Z2Z_H
|
|
472U, // UMIN_VG2_2Z2Z_S
|
|
176U, // UMIN_VG2_2ZZ_B
|
|
184U, // UMIN_VG2_2ZZ_D
|
|
136U, // UMIN_VG2_2ZZ_H
|
|
96U, // UMIN_VG2_2ZZ_S
|
|
920U, // UMIN_VG4_4Z4Z_B
|
|
464U, // UMIN_VG4_4Z4Z_D
|
|
248U, // UMIN_VG4_4Z4Z_H
|
|
472U, // UMIN_VG4_4Z4Z_S
|
|
176U, // UMIN_VG4_4ZZ_B
|
|
184U, // UMIN_VG4_4ZZ_D
|
|
136U, // UMIN_VG4_4ZZ_H
|
|
96U, // UMIN_VG4_4ZZ_S
|
|
88153U, // UMIN_ZI_B
|
|
88152U, // UMIN_ZI_D
|
|
448U, // UMIN_ZI_H
|
|
88153U, // UMIN_ZI_S
|
|
16918656U, // UMIN_ZPmZ_B
|
|
33691776U, // UMIN_ZPmZ_D
|
|
51129480U, // UMIN_ZPmZ_H
|
|
67252352U, // UMIN_ZPmZ_S
|
|
925840U, // UMINv16i8
|
|
1056920U, // UMINv2i32
|
|
1188000U, // UMINv4i16
|
|
401520U, // UMINv4i32
|
|
532600U, // UMINv8i16
|
|
1319080U, // UMINv8i8
|
|
53217368U, // UMLALB_ZZZI_D
|
|
53222488U, // UMLALB_ZZZI_S
|
|
2136U, // UMLALB_ZZZ_D
|
|
8U, // UMLALB_ZZZ_H
|
|
7256U, // UMLALB_ZZZ_S
|
|
38441U, // UMLALL_MZZI_BtoS
|
|
38145U, // UMLALL_MZZI_HtoD
|
|
553U, // UMLALL_MZZ_BtoS
|
|
257U, // UMLALL_MZZ_HtoD
|
|
47640U, // UMLALL_VG2_M2Z2Z_BtoS
|
|
2632936U, // UMLALL_VG2_M2Z2Z_HtoD
|
|
5029400U, // UMLALL_VG2_M2ZZI_BtoS
|
|
103427304U, // UMLALL_VG2_M2ZZI_HtoD
|
|
48666U, // UMLALL_VG2_M2ZZ_BtoS
|
|
53095658U, // UMLALL_VG2_M2ZZ_HtoD
|
|
47640U, // UMLALL_VG4_M4Z4Z_BtoS
|
|
2632936U, // UMLALL_VG4_M4Z4Z_HtoD
|
|
5029400U, // UMLALL_VG4_M4ZZI_BtoS
|
|
103427304U, // UMLALL_VG4_M4ZZI_HtoD
|
|
48667U, // UMLALL_VG4_M4ZZ_BtoS
|
|
53095659U, // UMLALL_VG4_M4ZZ_HtoD
|
|
53217368U, // UMLALT_ZZZI_D
|
|
53222488U, // UMLALT_ZZZI_S
|
|
2136U, // UMLALT_ZZZ_D
|
|
8U, // UMLALT_ZZZ_H
|
|
7256U, // UMLALT_ZZZ_S
|
|
38145U, // UMLAL_MZZI_HtoS
|
|
257U, // UMLAL_MZZ_HtoS
|
|
2632936U, // UMLAL_VG2_M2Z2Z_HtoS
|
|
103427304U, // UMLAL_VG2_M2ZZI_S
|
|
53095656U, // UMLAL_VG2_M2ZZ_HtoS
|
|
2632936U, // UMLAL_VG4_M4Z4Z_HtoS
|
|
103427304U, // UMLAL_VG4_M4ZZI_HtoS
|
|
53095656U, // UMLAL_VG4_M4ZZ_HtoS
|
|
926864U, // UMLALv16i8_v8i16
|
|
122299544U, // UMLALv2i32_indexed
|
|
1057944U, // UMLALv2i32_v2i64
|
|
120464544U, // UMLALv4i16_indexed
|
|
1189024U, // UMLALv4i16_v4i32
|
|
122299504U, // UMLALv4i32_indexed
|
|
402544U, // UMLALv4i32_v2i64
|
|
120464504U, // UMLALv8i16_indexed
|
|
533624U, // UMLALv8i16_v4i32
|
|
1320104U, // UMLALv8i8_v8i16
|
|
53217368U, // UMLSLB_ZZZI_D
|
|
53222488U, // UMLSLB_ZZZI_S
|
|
2136U, // UMLSLB_ZZZ_D
|
|
8U, // UMLSLB_ZZZ_H
|
|
7256U, // UMLSLB_ZZZ_S
|
|
38441U, // UMLSLL_MZZI_BtoS
|
|
38145U, // UMLSLL_MZZI_HtoD
|
|
553U, // UMLSLL_MZZ_BtoS
|
|
257U, // UMLSLL_MZZ_HtoD
|
|
47640U, // UMLSLL_VG2_M2Z2Z_BtoS
|
|
2632936U, // UMLSLL_VG2_M2Z2Z_HtoD
|
|
5029400U, // UMLSLL_VG2_M2ZZI_BtoS
|
|
103427304U, // UMLSLL_VG2_M2ZZI_HtoD
|
|
48666U, // UMLSLL_VG2_M2ZZ_BtoS
|
|
53095658U, // UMLSLL_VG2_M2ZZ_HtoD
|
|
47640U, // UMLSLL_VG4_M4Z4Z_BtoS
|
|
2632936U, // UMLSLL_VG4_M4Z4Z_HtoD
|
|
5029400U, // UMLSLL_VG4_M4ZZI_BtoS
|
|
103427304U, // UMLSLL_VG4_M4ZZI_HtoD
|
|
48667U, // UMLSLL_VG4_M4ZZ_BtoS
|
|
53095659U, // UMLSLL_VG4_M4ZZ_HtoD
|
|
53217368U, // UMLSLT_ZZZI_D
|
|
53222488U, // UMLSLT_ZZZI_S
|
|
2136U, // UMLSLT_ZZZ_D
|
|
8U, // UMLSLT_ZZZ_H
|
|
7256U, // UMLSLT_ZZZ_S
|
|
38145U, // UMLSL_MZZI_HtoS
|
|
257U, // UMLSL_MZZ_HtoS
|
|
2632936U, // UMLSL_VG2_M2Z2Z_HtoS
|
|
103427304U, // UMLSL_VG2_M2ZZI_S
|
|
53095656U, // UMLSL_VG2_M2ZZ_HtoS
|
|
2632936U, // UMLSL_VG4_M4Z4Z_HtoS
|
|
103427304U, // UMLSL_VG4_M4ZZI_HtoS
|
|
53095656U, // UMLSL_VG4_M4ZZ_HtoS
|
|
926864U, // UMLSLv16i8_v8i16
|
|
122299544U, // UMLSLv2i32_indexed
|
|
1057944U, // UMLSLv2i32_v2i64
|
|
120464544U, // UMLSLv4i16_indexed
|
|
1189024U, // UMLSLv4i16_v4i32
|
|
122299504U, // UMLSLv4i32_indexed
|
|
402544U, // UMLSLv4i32_v2i64
|
|
120464504U, // UMLSLv8i16_indexed
|
|
533624U, // UMLSLv8i16_v4i32
|
|
1320104U, // UMLSLv8i8_v8i16
|
|
926864U, // UMMLA
|
|
9U, // UMMLA_ZZZ
|
|
0U, // UMOPA_MPPZZ_D
|
|
0U, // UMOPA_MPPZZ_HtoS
|
|
0U, // UMOPA_MPPZZ_S
|
|
0U, // UMOPS_MPPZZ_D
|
|
0U, // UMOPS_MPPZZ_HtoS
|
|
0U, // UMOPS_MPPZZ_S
|
|
45456U, // UMOVvi16
|
|
45456U, // UMOVvi16_idx0
|
|
45464U, // UMOVvi32
|
|
45464U, // UMOVvi32_idx0
|
|
45472U, // UMOVvi64
|
|
45472U, // UMOVvi64_idx0
|
|
45480U, // UMOVvi8
|
|
45480U, // UMOVvi8_idx0
|
|
134232U, // UMSUBLrrr
|
|
16918656U, // UMULH_ZPmZ_B
|
|
33691776U, // UMULH_ZPmZ_D
|
|
51129480U, // UMULH_ZPmZ_H
|
|
67252352U, // UMULH_ZPmZ_S
|
|
10329U, // UMULH_ZZZ_B
|
|
6232U, // UMULH_ZZZ_D
|
|
136U, // UMULH_ZZZ_H
|
|
12377U, // UMULH_ZZZ_S
|
|
3160U, // UMULHrr
|
|
5910617U, // UMULLB_ZZZI_D
|
|
5903448U, // UMULLB_ZZZI_S
|
|
12377U, // UMULLB_ZZZ_D
|
|
176U, // UMULLB_ZZZ_H
|
|
5208U, // UMULLB_ZZZ_S
|
|
5910617U, // UMULLT_ZZZI_D
|
|
5903448U, // UMULLT_ZZZI_S
|
|
12377U, // UMULLT_ZZZ_D
|
|
176U, // UMULLT_ZZZ_H
|
|
5208U, // UMULLT_ZZZ_S
|
|
925840U, // UMULLv16i8_v8i16
|
|
340402328U, // UMULLv2i32_indexed
|
|
1056920U, // UMULLv2i32_v2i64
|
|
338567328U, // UMULLv4i16_indexed
|
|
1188000U, // UMULLv4i16_v4i32
|
|
340402288U, // UMULLv4i32_indexed
|
|
401520U, // UMULLv4i32_v2i64
|
|
338567288U, // UMULLv8i16_indexed
|
|
532600U, // UMULLv8i16_v4i32
|
|
1319080U, // UMULLv8i8_v8i16
|
|
16473U, // UQADD_ZI_B
|
|
17496U, // UQADD_ZI_D
|
|
208U, // UQADD_ZI_H
|
|
18521U, // UQADD_ZI_S
|
|
16918656U, // UQADD_ZPmZ_B
|
|
33691776U, // UQADD_ZPmZ_D
|
|
51129480U, // UQADD_ZPmZ_H
|
|
67252352U, // UQADD_ZPmZ_S
|
|
10329U, // UQADD_ZZZ_B
|
|
6232U, // UQADD_ZZZ_D
|
|
136U, // UQADD_ZZZ_H
|
|
12377U, // UQADD_ZZZ_S
|
|
925840U, // UQADDv16i8
|
|
3160U, // UQADDv1i16
|
|
3160U, // UQADDv1i32
|
|
3160U, // UQADDv1i64
|
|
3160U, // UQADDv1i8
|
|
1056920U, // UQADDv2i32
|
|
270440U, // UQADDv2i64
|
|
1188000U, // UQADDv4i16
|
|
401520U, // UQADDv4i32
|
|
532600U, // UQADDv8i16
|
|
1319080U, // UQADDv8i8
|
|
0U, // UQCVTN_Z2Z_StoH
|
|
0U, // UQCVTN_Z4Z_DtoH
|
|
2U, // UQCVTN_Z4Z_StoB
|
|
0U, // UQCVT_Z2Z_StoH
|
|
0U, // UQCVT_Z4Z_DtoH
|
|
2U, // UQCVT_Z4Z_StoB
|
|
2U, // UQDECB_WPiI
|
|
2U, // UQDECB_XPiI
|
|
2U, // UQDECD_WPiI
|
|
2U, // UQDECD_XPiI
|
|
2U, // UQDECD_ZPiI
|
|
2U, // UQDECH_WPiI
|
|
2U, // UQDECH_XPiI
|
|
0U, // UQDECH_ZPiI
|
|
1U, // UQDECP_WP_B
|
|
0U, // UQDECP_WP_D
|
|
0U, // UQDECP_WP_H
|
|
1U, // UQDECP_WP_S
|
|
1U, // UQDECP_XP_B
|
|
0U, // UQDECP_XP_D
|
|
0U, // UQDECP_XP_H
|
|
1U, // UQDECP_XP_S
|
|
0U, // UQDECP_ZP_D
|
|
0U, // UQDECP_ZP_H
|
|
0U, // UQDECP_ZP_S
|
|
2U, // UQDECW_WPiI
|
|
2U, // UQDECW_XPiI
|
|
2U, // UQDECW_ZPiI
|
|
2U, // UQINCB_WPiI
|
|
2U, // UQINCB_XPiI
|
|
2U, // UQINCD_WPiI
|
|
2U, // UQINCD_XPiI
|
|
2U, // UQINCD_ZPiI
|
|
2U, // UQINCH_WPiI
|
|
2U, // UQINCH_XPiI
|
|
0U, // UQINCH_ZPiI
|
|
1U, // UQINCP_WP_B
|
|
0U, // UQINCP_WP_D
|
|
0U, // UQINCP_WP_H
|
|
1U, // UQINCP_WP_S
|
|
1U, // UQINCP_XP_B
|
|
0U, // UQINCP_XP_D
|
|
0U, // UQINCP_XP_H
|
|
1U, // UQINCP_XP_S
|
|
0U, // UQINCP_ZP_D
|
|
0U, // UQINCP_ZP_H
|
|
0U, // UQINCP_ZP_S
|
|
2U, // UQINCW_WPiI
|
|
2U, // UQINCW_XPiI
|
|
2U, // UQINCW_ZPiI
|
|
16918656U, // UQRSHLR_ZPmZ_B
|
|
33691776U, // UQRSHLR_ZPmZ_D
|
|
51129480U, // UQRSHLR_ZPmZ_H
|
|
67252352U, // UQRSHLR_ZPmZ_S
|
|
16918656U, // UQRSHL_ZPmZ_B
|
|
33691776U, // UQRSHL_ZPmZ_D
|
|
51129480U, // UQRSHL_ZPmZ_H
|
|
67252352U, // UQRSHL_ZPmZ_S
|
|
925840U, // UQRSHLv16i8
|
|
3160U, // UQRSHLv1i16
|
|
3160U, // UQRSHLv1i32
|
|
3160U, // UQRSHLv1i64
|
|
3160U, // UQRSHLv1i8
|
|
1056920U, // UQRSHLv2i32
|
|
270440U, // UQRSHLv2i64
|
|
1188000U, // UQRSHLv4i16
|
|
401520U, // UQRSHLv4i32
|
|
532600U, // UQRSHLv8i16
|
|
1319080U, // UQRSHLv8i8
|
|
3160U, // UQRSHRNB_ZZI_B
|
|
224U, // UQRSHRNB_ZZI_H
|
|
3160U, // UQRSHRNB_ZZI_S
|
|
41048U, // UQRSHRNT_ZZI_B
|
|
376U, // UQRSHRNT_ZZI_H
|
|
41048U, // UQRSHRNT_ZZI_S
|
|
3162U, // UQRSHRN_VG4_Z4ZI_B
|
|
224U, // UQRSHRN_VG4_Z4ZI_H
|
|
224U, // UQRSHRN_Z2ZI_StoH
|
|
3160U, // UQRSHRNb
|
|
3160U, // UQRSHRNh
|
|
3160U, // UQRSHRNs
|
|
41080U, // UQRSHRNv16i8_shift
|
|
3176U, // UQRSHRNv2i32_shift
|
|
3184U, // UQRSHRNv4i16_shift
|
|
41064U, // UQRSHRNv4i32_shift
|
|
41072U, // UQRSHRNv8i16_shift
|
|
3192U, // UQRSHRNv8i8_shift
|
|
224U, // UQRSHR_VG2_Z2ZI_H
|
|
3162U, // UQRSHR_VG4_Z4ZI_B
|
|
224U, // UQRSHR_VG4_Z4ZI_H
|
|
16918656U, // UQSHLR_ZPmZ_B
|
|
33691776U, // UQSHLR_ZPmZ_D
|
|
51129480U, // UQSHLR_ZPmZ_H
|
|
67252352U, // UQSHLR_ZPmZ_S
|
|
141440U, // UQSHL_ZPmI_B
|
|
137344U, // UQSHL_ZPmI_D
|
|
52440200U, // UQSHL_ZPmI_H
|
|
143488U, // UQSHL_ZPmI_S
|
|
16918656U, // UQSHL_ZPmZ_B
|
|
33691776U, // UQSHL_ZPmZ_D
|
|
51129480U, // UQSHL_ZPmZ_H
|
|
67252352U, // UQSHL_ZPmZ_S
|
|
3160U, // UQSHLb
|
|
3160U, // UQSHLd
|
|
3160U, // UQSHLh
|
|
3160U, // UQSHLs
|
|
925840U, // UQSHLv16i8
|
|
3216U, // UQSHLv16i8_shift
|
|
3160U, // UQSHLv1i16
|
|
3160U, // UQSHLv1i32
|
|
3160U, // UQSHLv1i64
|
|
3160U, // UQSHLv1i8
|
|
1056920U, // UQSHLv2i32
|
|
3224U, // UQSHLv2i32_shift
|
|
270440U, // UQSHLv2i64
|
|
3176U, // UQSHLv2i64_shift
|
|
1188000U, // UQSHLv4i16
|
|
3232U, // UQSHLv4i16_shift
|
|
401520U, // UQSHLv4i32
|
|
3184U, // UQSHLv4i32_shift
|
|
532600U, // UQSHLv8i16
|
|
3192U, // UQSHLv8i16_shift
|
|
1319080U, // UQSHLv8i8
|
|
3240U, // UQSHLv8i8_shift
|
|
3160U, // UQSHRNB_ZZI_B
|
|
224U, // UQSHRNB_ZZI_H
|
|
3160U, // UQSHRNB_ZZI_S
|
|
41048U, // UQSHRNT_ZZI_B
|
|
376U, // UQSHRNT_ZZI_H
|
|
41048U, // UQSHRNT_ZZI_S
|
|
3160U, // UQSHRNb
|
|
3160U, // UQSHRNh
|
|
3160U, // UQSHRNs
|
|
41080U, // UQSHRNv16i8_shift
|
|
3176U, // UQSHRNv2i32_shift
|
|
3184U, // UQSHRNv4i16_shift
|
|
41064U, // UQSHRNv4i32_shift
|
|
41072U, // UQSHRNv8i16_shift
|
|
3192U, // UQSHRNv8i8_shift
|
|
16918656U, // UQSUBR_ZPmZ_B
|
|
33691776U, // UQSUBR_ZPmZ_D
|
|
51129480U, // UQSUBR_ZPmZ_H
|
|
67252352U, // UQSUBR_ZPmZ_S
|
|
16473U, // UQSUB_ZI_B
|
|
17496U, // UQSUB_ZI_D
|
|
208U, // UQSUB_ZI_H
|
|
18521U, // UQSUB_ZI_S
|
|
16918656U, // UQSUB_ZPmZ_B
|
|
33691776U, // UQSUB_ZPmZ_D
|
|
51129480U, // UQSUB_ZPmZ_H
|
|
67252352U, // UQSUB_ZPmZ_S
|
|
10329U, // UQSUB_ZZZ_B
|
|
6232U, // UQSUB_ZZZ_D
|
|
136U, // UQSUB_ZZZ_H
|
|
12377U, // UQSUB_ZZZ_S
|
|
925840U, // UQSUBv16i8
|
|
3160U, // UQSUBv1i16
|
|
3160U, // UQSUBv1i32
|
|
3160U, // UQSUBv1i64
|
|
3160U, // UQSUBv1i8
|
|
1056920U, // UQSUBv2i32
|
|
270440U, // UQSUBv2i64
|
|
1188000U, // UQSUBv4i16
|
|
401520U, // UQSUBv4i32
|
|
532600U, // UQSUBv8i16
|
|
1319080U, // UQSUBv8i8
|
|
0U, // UQXTNB_ZZ_B
|
|
0U, // UQXTNB_ZZ_H
|
|
0U, // UQXTNB_ZZ_S
|
|
0U, // UQXTNT_ZZ_B
|
|
0U, // UQXTNT_ZZ_H
|
|
0U, // UQXTNT_ZZ_S
|
|
72U, // UQXTNv16i8
|
|
0U, // UQXTNv1i16
|
|
0U, // UQXTNv1i32
|
|
0U, // UQXTNv1i8
|
|
48U, // UQXTNv2i32
|
|
64U, // UQXTNv4i16
|
|
48U, // UQXTNv4i32
|
|
64U, // UQXTNv8i16
|
|
72U, // UQXTNv8i8
|
|
24U, // URECPE_ZPmZ_S
|
|
40U, // URECPEv2i32
|
|
64U, // URECPEv4i32
|
|
16918656U, // URHADD_ZPmZ_B
|
|
33691776U, // URHADD_ZPmZ_D
|
|
51129480U, // URHADD_ZPmZ_H
|
|
67252352U, // URHADD_ZPmZ_S
|
|
925840U, // URHADDv16i8
|
|
1056920U, // URHADDv2i32
|
|
1188000U, // URHADDv4i16
|
|
401520U, // URHADDv4i32
|
|
532600U, // URHADDv8i16
|
|
1319080U, // URHADDv8i8
|
|
16918656U, // URSHLR_ZPmZ_B
|
|
33691776U, // URSHLR_ZPmZ_D
|
|
51129480U, // URSHLR_ZPmZ_H
|
|
67252352U, // URSHLR_ZPmZ_S
|
|
920U, // URSHL_VG2_2Z2Z_B
|
|
464U, // URSHL_VG2_2Z2Z_D
|
|
248U, // URSHL_VG2_2Z2Z_H
|
|
472U, // URSHL_VG2_2Z2Z_S
|
|
176U, // URSHL_VG2_2ZZ_B
|
|
184U, // URSHL_VG2_2ZZ_D
|
|
136U, // URSHL_VG2_2ZZ_H
|
|
96U, // URSHL_VG2_2ZZ_S
|
|
920U, // URSHL_VG4_4Z4Z_B
|
|
464U, // URSHL_VG4_4Z4Z_D
|
|
248U, // URSHL_VG4_4Z4Z_H
|
|
472U, // URSHL_VG4_4Z4Z_S
|
|
176U, // URSHL_VG4_4ZZ_B
|
|
184U, // URSHL_VG4_4ZZ_D
|
|
136U, // URSHL_VG4_4ZZ_H
|
|
96U, // URSHL_VG4_4ZZ_S
|
|
16918656U, // URSHL_ZPmZ_B
|
|
33691776U, // URSHL_ZPmZ_D
|
|
51129480U, // URSHL_ZPmZ_H
|
|
67252352U, // URSHL_ZPmZ_S
|
|
925840U, // URSHLv16i8
|
|
3160U, // URSHLv1i64
|
|
1056920U, // URSHLv2i32
|
|
270440U, // URSHLv2i64
|
|
1188000U, // URSHLv4i16
|
|
401520U, // URSHLv4i32
|
|
532600U, // URSHLv8i16
|
|
1319080U, // URSHLv8i8
|
|
141440U, // URSHR_ZPmI_B
|
|
137344U, // URSHR_ZPmI_D
|
|
52440200U, // URSHR_ZPmI_H
|
|
143488U, // URSHR_ZPmI_S
|
|
3160U, // URSHRd
|
|
3216U, // URSHRv16i8_shift
|
|
3224U, // URSHRv2i32_shift
|
|
3176U, // URSHRv2i64_shift
|
|
3232U, // URSHRv4i16_shift
|
|
3184U, // URSHRv4i32_shift
|
|
3192U, // URSHRv8i16_shift
|
|
3240U, // URSHRv8i8_shift
|
|
24U, // URSQRTE_ZPmZ_S
|
|
40U, // URSQRTEv2i32
|
|
64U, // URSQRTEv4i32
|
|
377U, // URSRA_ZZI_B
|
|
41048U, // URSRA_ZZI_D
|
|
376U, // URSRA_ZZI_H
|
|
41048U, // URSRA_ZZI_S
|
|
41049U, // URSRAd
|
|
41104U, // URSRAv16i8_shift
|
|
41112U, // URSRAv2i32_shift
|
|
41064U, // URSRAv2i64_shift
|
|
41120U, // URSRAv4i16_shift
|
|
41072U, // URSRAv4i32_shift
|
|
41080U, // URSRAv8i16_shift
|
|
41128U, // URSRAv8i8_shift
|
|
47640U, // USDOT_VG2_M2Z2Z_BToS
|
|
5029400U, // USDOT_VG2_M2ZZI_BToS
|
|
48664U, // USDOT_VG2_M2ZZ_BToS
|
|
47640U, // USDOT_VG4_M4Z4Z_BToS
|
|
5029400U, // USDOT_VG4_M4ZZI_BToS
|
|
48664U, // USDOT_VG4_M4ZZ_BToS
|
|
9U, // USDOT_ZZZ
|
|
38921U, // USDOT_ZZZI
|
|
5121168U, // USDOTlanev16i8
|
|
5121192U, // USDOTlanev8i8
|
|
926864U, // USDOTv16i8
|
|
1320104U, // USDOTv8i8
|
|
3161U, // USHLLB_ZZI_D
|
|
224U, // USHLLB_ZZI_H
|
|
3160U, // USHLLB_ZZI_S
|
|
3161U, // USHLLT_ZZI_D
|
|
224U, // USHLLT_ZZI_H
|
|
3160U, // USHLLT_ZZI_S
|
|
3216U, // USHLLv16i8_shift
|
|
3224U, // USHLLv2i32_shift
|
|
3232U, // USHLLv4i16_shift
|
|
3184U, // USHLLv4i32_shift
|
|
3192U, // USHLLv8i16_shift
|
|
3240U, // USHLLv8i8_shift
|
|
925840U, // USHLv16i8
|
|
3160U, // USHLv1i64
|
|
1056920U, // USHLv2i32
|
|
270440U, // USHLv2i64
|
|
1188000U, // USHLv4i16
|
|
401520U, // USHLv4i32
|
|
532600U, // USHLv8i16
|
|
1319080U, // USHLv8i8
|
|
3160U, // USHRd
|
|
3216U, // USHRv16i8_shift
|
|
3224U, // USHRv2i32_shift
|
|
3176U, // USHRv2i64_shift
|
|
3232U, // USHRv4i16_shift
|
|
3184U, // USHRv4i32_shift
|
|
3192U, // USHRv8i16_shift
|
|
3240U, // USHRv8i8_shift
|
|
38441U, // USMLALL_MZZI_BtoS
|
|
553U, // USMLALL_MZZ_BtoS
|
|
47640U, // USMLALL_VG2_M2Z2Z_BtoS
|
|
5029400U, // USMLALL_VG2_M2ZZI_BtoS
|
|
48666U, // USMLALL_VG2_M2ZZ_BtoS
|
|
47640U, // USMLALL_VG4_M4Z4Z_BtoS
|
|
5029400U, // USMLALL_VG4_M4ZZI_BtoS
|
|
48667U, // USMLALL_VG4_M4ZZ_BtoS
|
|
926864U, // USMMLA
|
|
9U, // USMMLA_ZZZ
|
|
0U, // USMOPA_MPPZZ_D
|
|
0U, // USMOPA_MPPZZ_S
|
|
0U, // USMOPS_MPPZZ_D
|
|
0U, // USMOPS_MPPZZ_S
|
|
16918656U, // USQADD_ZPmZ_B
|
|
33691776U, // USQADD_ZPmZ_D
|
|
51129480U, // USQADD_ZPmZ_H
|
|
67252352U, // USQADD_ZPmZ_S
|
|
32U, // USQADDv16i8
|
|
1U, // USQADDv1i16
|
|
1U, // USQADDv1i32
|
|
1U, // USQADDv1i64
|
|
1U, // USQADDv1i8
|
|
40U, // USQADDv2i32
|
|
48U, // USQADDv2i64
|
|
56U, // USQADDv4i16
|
|
64U, // USQADDv4i32
|
|
72U, // USQADDv8i16
|
|
80U, // USQADDv8i8
|
|
377U, // USRA_ZZI_B
|
|
41048U, // USRA_ZZI_D
|
|
376U, // USRA_ZZI_H
|
|
41048U, // USRA_ZZI_S
|
|
41049U, // USRAd
|
|
41104U, // USRAv16i8_shift
|
|
41112U, // USRAv2i32_shift
|
|
41064U, // USRAv2i64_shift
|
|
41120U, // USRAv4i16_shift
|
|
41072U, // USRAv4i32_shift
|
|
41080U, // USRAv8i16_shift
|
|
41128U, // USRAv8i8_shift
|
|
12377U, // USUBLB_ZZZ_D
|
|
176U, // USUBLB_ZZZ_H
|
|
5208U, // USUBLB_ZZZ_S
|
|
12377U, // USUBLT_ZZZ_D
|
|
176U, // USUBLT_ZZZ_H
|
|
5208U, // USUBLT_ZZZ_S
|
|
925840U, // USUBLv16i8_v8i16
|
|
1056920U, // USUBLv2i32_v2i64
|
|
1188000U, // USUBLv4i16_v4i32
|
|
401520U, // USUBLv4i32_v2i64
|
|
532600U, // USUBLv8i16_v4i32
|
|
1319080U, // USUBLv8i8_v8i16
|
|
12376U, // USUBWB_ZZZ_D
|
|
176U, // USUBWB_ZZZ_H
|
|
5209U, // USUBWB_ZZZ_S
|
|
12376U, // USUBWT_ZZZ_D
|
|
176U, // USUBWT_ZZZ_H
|
|
5209U, // USUBWT_ZZZ_S
|
|
925816U, // USUBWv16i8_v8i16
|
|
1056872U, // USUBWv2i32_v2i64
|
|
1187952U, // USUBWv4i16_v4i32
|
|
401512U, // USUBWv4i32_v2i64
|
|
532592U, // USUBWv8i16_v4i32
|
|
1319032U, // USUBWv8i8_v8i16
|
|
5029400U, // USVDOT_VG4_M4ZZI_BToS
|
|
1U, // UUNPKHI_ZZ_D
|
|
0U, // UUNPKHI_ZZ_H
|
|
0U, // UUNPKHI_ZZ_S
|
|
1U, // UUNPKLO_ZZ_D
|
|
0U, // UUNPKLO_ZZ_H
|
|
0U, // UUNPKLO_ZZ_S
|
|
0U, // UUNPK_VG2_2ZZ_D
|
|
0U, // UUNPK_VG2_2ZZ_H
|
|
0U, // UUNPK_VG2_2ZZ_S
|
|
0U, // UUNPK_VG4_4Z2Z_D
|
|
0U, // UUNPK_VG4_4Z2Z_H
|
|
0U, // UUNPK_VG4_4Z2Z_S
|
|
103427304U, // UVDOT_VG2_M2ZZI_HtoS
|
|
5029400U, // UVDOT_VG4_M4ZZI_BtoS
|
|
103427304U, // UVDOT_VG4_M4ZZI_HtoD
|
|
16U, // UXTB_ZPmZ_D
|
|
0U, // UXTB_ZPmZ_H
|
|
24U, // UXTB_ZPmZ_S
|
|
16U, // UXTH_ZPmZ_D
|
|
24U, // UXTH_ZPmZ_S
|
|
16U, // UXTW_ZPmZ_D
|
|
10329U, // UZP1_PPP_B
|
|
6232U, // UZP1_PPP_D
|
|
136U, // UZP1_PPP_H
|
|
12377U, // UZP1_PPP_S
|
|
10329U, // UZP1_ZZZ_B
|
|
6232U, // UZP1_ZZZ_D
|
|
136U, // UZP1_ZZZ_H
|
|
1016U, // UZP1_ZZZ_Q
|
|
12377U, // UZP1_ZZZ_S
|
|
925840U, // UZP1v16i8
|
|
1056920U, // UZP1v2i32
|
|
270440U, // UZP1v2i64
|
|
1188000U, // UZP1v4i16
|
|
401520U, // UZP1v4i32
|
|
532600U, // UZP1v8i16
|
|
1319080U, // UZP1v8i8
|
|
10329U, // UZP2_PPP_B
|
|
6232U, // UZP2_PPP_D
|
|
136U, // UZP2_PPP_H
|
|
12377U, // UZP2_PPP_S
|
|
10329U, // UZP2_ZZZ_B
|
|
6232U, // UZP2_ZZZ_D
|
|
136U, // UZP2_ZZZ_H
|
|
1016U, // UZP2_ZZZ_Q
|
|
12377U, // UZP2_ZZZ_S
|
|
925840U, // UZP2v16i8
|
|
1056920U, // UZP2v2i32
|
|
270440U, // UZP2v2i64
|
|
1188000U, // UZP2v4i16
|
|
401520U, // UZP2v4i32
|
|
532600U, // UZP2v8i16
|
|
1319080U, // UZP2v8i8
|
|
10329U, // UZPQ1_ZZZ_B
|
|
6232U, // UZPQ1_ZZZ_D
|
|
136U, // UZPQ1_ZZZ_H
|
|
12377U, // UZPQ1_ZZZ_S
|
|
10329U, // UZPQ2_ZZZ_B
|
|
6232U, // UZPQ2_ZZZ_D
|
|
136U, // UZPQ2_ZZZ_H
|
|
12377U, // UZPQ2_ZZZ_S
|
|
176U, // UZP_VG2_2ZZZ_B
|
|
0U, // UZP_VG2_2ZZZ_D
|
|
136U, // UZP_VG2_2ZZZ_H
|
|
1016U, // UZP_VG2_2ZZZ_Q
|
|
96U, // UZP_VG2_2ZZZ_S
|
|
0U, // UZP_VG4_4Z4Z_B
|
|
0U, // UZP_VG4_4Z4Z_D
|
|
0U, // UZP_VG4_4Z4Z_H
|
|
0U, // UZP_VG4_4Z4Z_Q
|
|
0U, // UZP_VG4_4Z4Z_S
|
|
0U, // VECFP
|
|
0U, // VECINT
|
|
0U, // WFET
|
|
0U, // WFIT
|
|
224U, // WHILEGE_2PXX_B
|
|
224U, // WHILEGE_2PXX_D
|
|
224U, // WHILEGE_2PXX_H
|
|
224U, // WHILEGE_2PXX_S
|
|
721554520U, // WHILEGE_CXX_B
|
|
721554520U, // WHILEGE_CXX_D
|
|
721554520U, // WHILEGE_CXX_H
|
|
721554520U, // WHILEGE_CXX_S
|
|
3160U, // WHILEGE_PWW_B
|
|
3160U, // WHILEGE_PWW_D
|
|
224U, // WHILEGE_PWW_H
|
|
3160U, // WHILEGE_PWW_S
|
|
3160U, // WHILEGE_PXX_B
|
|
3160U, // WHILEGE_PXX_D
|
|
224U, // WHILEGE_PXX_H
|
|
3160U, // WHILEGE_PXX_S
|
|
224U, // WHILEGT_2PXX_B
|
|
224U, // WHILEGT_2PXX_D
|
|
224U, // WHILEGT_2PXX_H
|
|
224U, // WHILEGT_2PXX_S
|
|
721554520U, // WHILEGT_CXX_B
|
|
721554520U, // WHILEGT_CXX_D
|
|
721554520U, // WHILEGT_CXX_H
|
|
721554520U, // WHILEGT_CXX_S
|
|
3160U, // WHILEGT_PWW_B
|
|
3160U, // WHILEGT_PWW_D
|
|
224U, // WHILEGT_PWW_H
|
|
3160U, // WHILEGT_PWW_S
|
|
3160U, // WHILEGT_PXX_B
|
|
3160U, // WHILEGT_PXX_D
|
|
224U, // WHILEGT_PXX_H
|
|
3160U, // WHILEGT_PXX_S
|
|
224U, // WHILEHI_2PXX_B
|
|
224U, // WHILEHI_2PXX_D
|
|
224U, // WHILEHI_2PXX_H
|
|
224U, // WHILEHI_2PXX_S
|
|
721554520U, // WHILEHI_CXX_B
|
|
721554520U, // WHILEHI_CXX_D
|
|
721554520U, // WHILEHI_CXX_H
|
|
721554520U, // WHILEHI_CXX_S
|
|
3160U, // WHILEHI_PWW_B
|
|
3160U, // WHILEHI_PWW_D
|
|
224U, // WHILEHI_PWW_H
|
|
3160U, // WHILEHI_PWW_S
|
|
3160U, // WHILEHI_PXX_B
|
|
3160U, // WHILEHI_PXX_D
|
|
224U, // WHILEHI_PXX_H
|
|
3160U, // WHILEHI_PXX_S
|
|
224U, // WHILEHS_2PXX_B
|
|
224U, // WHILEHS_2PXX_D
|
|
224U, // WHILEHS_2PXX_H
|
|
224U, // WHILEHS_2PXX_S
|
|
721554520U, // WHILEHS_CXX_B
|
|
721554520U, // WHILEHS_CXX_D
|
|
721554520U, // WHILEHS_CXX_H
|
|
721554520U, // WHILEHS_CXX_S
|
|
3160U, // WHILEHS_PWW_B
|
|
3160U, // WHILEHS_PWW_D
|
|
224U, // WHILEHS_PWW_H
|
|
3160U, // WHILEHS_PWW_S
|
|
3160U, // WHILEHS_PXX_B
|
|
3160U, // WHILEHS_PXX_D
|
|
224U, // WHILEHS_PXX_H
|
|
3160U, // WHILEHS_PXX_S
|
|
224U, // WHILELE_2PXX_B
|
|
224U, // WHILELE_2PXX_D
|
|
224U, // WHILELE_2PXX_H
|
|
224U, // WHILELE_2PXX_S
|
|
721554520U, // WHILELE_CXX_B
|
|
721554520U, // WHILELE_CXX_D
|
|
721554520U, // WHILELE_CXX_H
|
|
721554520U, // WHILELE_CXX_S
|
|
3160U, // WHILELE_PWW_B
|
|
3160U, // WHILELE_PWW_D
|
|
224U, // WHILELE_PWW_H
|
|
3160U, // WHILELE_PWW_S
|
|
3160U, // WHILELE_PXX_B
|
|
3160U, // WHILELE_PXX_D
|
|
224U, // WHILELE_PXX_H
|
|
3160U, // WHILELE_PXX_S
|
|
224U, // WHILELO_2PXX_B
|
|
224U, // WHILELO_2PXX_D
|
|
224U, // WHILELO_2PXX_H
|
|
224U, // WHILELO_2PXX_S
|
|
721554520U, // WHILELO_CXX_B
|
|
721554520U, // WHILELO_CXX_D
|
|
721554520U, // WHILELO_CXX_H
|
|
721554520U, // WHILELO_CXX_S
|
|
3160U, // WHILELO_PWW_B
|
|
3160U, // WHILELO_PWW_D
|
|
224U, // WHILELO_PWW_H
|
|
3160U, // WHILELO_PWW_S
|
|
3160U, // WHILELO_PXX_B
|
|
3160U, // WHILELO_PXX_D
|
|
224U, // WHILELO_PXX_H
|
|
3160U, // WHILELO_PXX_S
|
|
224U, // WHILELS_2PXX_B
|
|
224U, // WHILELS_2PXX_D
|
|
224U, // WHILELS_2PXX_H
|
|
224U, // WHILELS_2PXX_S
|
|
721554520U, // WHILELS_CXX_B
|
|
721554520U, // WHILELS_CXX_D
|
|
721554520U, // WHILELS_CXX_H
|
|
721554520U, // WHILELS_CXX_S
|
|
3160U, // WHILELS_PWW_B
|
|
3160U, // WHILELS_PWW_D
|
|
224U, // WHILELS_PWW_H
|
|
3160U, // WHILELS_PWW_S
|
|
3160U, // WHILELS_PXX_B
|
|
3160U, // WHILELS_PXX_D
|
|
224U, // WHILELS_PXX_H
|
|
3160U, // WHILELS_PXX_S
|
|
224U, // WHILELT_2PXX_B
|
|
224U, // WHILELT_2PXX_D
|
|
224U, // WHILELT_2PXX_H
|
|
224U, // WHILELT_2PXX_S
|
|
721554520U, // WHILELT_CXX_B
|
|
721554520U, // WHILELT_CXX_D
|
|
721554520U, // WHILELT_CXX_H
|
|
721554520U, // WHILELT_CXX_S
|
|
3160U, // WHILELT_PWW_B
|
|
3160U, // WHILELT_PWW_D
|
|
224U, // WHILELT_PWW_H
|
|
3160U, // WHILELT_PWW_S
|
|
3160U, // WHILELT_PXX_B
|
|
3160U, // WHILELT_PXX_D
|
|
224U, // WHILELT_PXX_H
|
|
3160U, // WHILELT_PXX_S
|
|
3160U, // WHILERW_PXX_B
|
|
3160U, // WHILERW_PXX_D
|
|
224U, // WHILERW_PXX_H
|
|
3160U, // WHILERW_PXX_S
|
|
3160U, // WHILEWR_PXX_B
|
|
3160U, // WHILEWR_PXX_D
|
|
224U, // WHILEWR_PXX_H
|
|
3160U, // WHILEWR_PXX_S
|
|
1U, // WKDMC
|
|
1U, // WKDMD
|
|
0U, // WRFFR
|
|
0U, // XAFLAG
|
|
4202600U, // XAR
|
|
141401U, // XAR_ZZZI_B
|
|
137304U, // XAR_ZZZI_D
|
|
52440200U, // XAR_ZZZI_H
|
|
143449U, // XAR_ZZZI_S
|
|
0U, // XPACD
|
|
0U, // XPACI
|
|
0U, // XPACLRI
|
|
72U, // XTNv16i8
|
|
48U, // XTNv2i32
|
|
64U, // XTNv4i16
|
|
48U, // XTNv4i32
|
|
64U, // XTNv8i16
|
|
72U, // XTNv8i8
|
|
0U, // ZERO_M
|
|
5U, // ZERO_MXI_2Z
|
|
5U, // ZERO_MXI_4Z
|
|
3U, // ZERO_MXI_VG2_2Z
|
|
3U, // ZERO_MXI_VG2_4Z
|
|
3U, // ZERO_MXI_VG2_Z
|
|
3U, // ZERO_MXI_VG4_2Z
|
|
3U, // ZERO_MXI_VG4_4Z
|
|
3U, // ZERO_MXI_VG4_Z
|
|
0U, // ZERO_T
|
|
10329U, // ZIP1_PPP_B
|
|
6232U, // ZIP1_PPP_D
|
|
136U, // ZIP1_PPP_H
|
|
12377U, // ZIP1_PPP_S
|
|
10329U, // ZIP1_ZZZ_B
|
|
6232U, // ZIP1_ZZZ_D
|
|
136U, // ZIP1_ZZZ_H
|
|
1016U, // ZIP1_ZZZ_Q
|
|
12377U, // ZIP1_ZZZ_S
|
|
925840U, // ZIP1v16i8
|
|
1056920U, // ZIP1v2i32
|
|
270440U, // ZIP1v2i64
|
|
1188000U, // ZIP1v4i16
|
|
401520U, // ZIP1v4i32
|
|
532600U, // ZIP1v8i16
|
|
1319080U, // ZIP1v8i8
|
|
10329U, // ZIP2_PPP_B
|
|
6232U, // ZIP2_PPP_D
|
|
136U, // ZIP2_PPP_H
|
|
12377U, // ZIP2_PPP_S
|
|
10329U, // ZIP2_ZZZ_B
|
|
6232U, // ZIP2_ZZZ_D
|
|
136U, // ZIP2_ZZZ_H
|
|
1016U, // ZIP2_ZZZ_Q
|
|
12377U, // ZIP2_ZZZ_S
|
|
925840U, // ZIP2v16i8
|
|
1056920U, // ZIP2v2i32
|
|
270440U, // ZIP2v2i64
|
|
1188000U, // ZIP2v4i16
|
|
401520U, // ZIP2v4i32
|
|
532600U, // ZIP2v8i16
|
|
1319080U, // ZIP2v8i8
|
|
10329U, // ZIPQ1_ZZZ_B
|
|
6232U, // ZIPQ1_ZZZ_D
|
|
136U, // ZIPQ1_ZZZ_H
|
|
12377U, // ZIPQ1_ZZZ_S
|
|
10329U, // ZIPQ2_ZZZ_B
|
|
6232U, // ZIPQ2_ZZZ_D
|
|
136U, // ZIPQ2_ZZZ_H
|
|
12377U, // ZIPQ2_ZZZ_S
|
|
176U, // ZIP_VG2_2ZZZ_B
|
|
0U, // ZIP_VG2_2ZZZ_D
|
|
136U, // ZIP_VG2_2ZZZ_H
|
|
1016U, // ZIP_VG2_2ZZZ_Q
|
|
96U, // ZIP_VG2_2ZZZ_S
|
|
0U, // ZIP_VG4_4Z4Z_B
|
|
0U, // ZIP_VG4_4Z4Z_D
|
|
0U, // ZIP_VG4_4Z4Z_H
|
|
0U, // ZIP_VG4_4Z4Z_Q
|
|
0U, // ZIP_VG4_4Z4Z_S
|
|
};
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint64_t Bits = 0;
|
|
Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0;
|
|
Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32;
|
|
MnemonicBitsInfo MBI = {
|
|
#ifndef CAPSTONE_DIET
|
|
AsmStrs+(Bits & 16383)-1,
|
|
#else
|
|
NULL,
|
|
#endif // CAPSTONE_DIET
|
|
Bits
|
|
};
|
|
return MBI;
|
|
}
|
|
|
|
/// printInstruction - This method is automatically generated by tablegen
|
|
/// from the instruction set description.
|
|
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
|
|
SStream_concat0(O, "");
|
|
MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
|
|
|
|
SStream_concat0(O, MnemonicInfo.first);
|
|
|
|
uint64_t Bits = MnemonicInfo.second;
|
|
CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
|
|
|
|
// Fragment 0 encoded into 7 bits for 79 unique commands.
|
|
switch ((Bits >> 14) & 127) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// TLSDESCCALL, ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADD...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm...
|
|
printSVERegOp_b(MI, 0, O);
|
|
break;
|
|
case 3:
|
|
// ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_...
|
|
printSVERegOp_d(MI, 0, O);
|
|
break;
|
|
case 4:
|
|
// ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm...
|
|
printSVERegOp_h(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 5:
|
|
// ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP...
|
|
printSVERegOp_s(MI, 0, O);
|
|
break;
|
|
case 6:
|
|
// ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
|
|
printVRegOperand(MI, 0, O);
|
|
break;
|
|
case 7:
|
|
// ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOPA_MPPZZ, ...
|
|
printMatrixTile(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_0(MI, 2, O);
|
|
SStream_concat0(O, "/m, ");
|
|
printSVERegOp_0(MI, 3, O);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 8:
|
|
// ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
|
|
printVRegOperand(MI, 1, O);
|
|
break;
|
|
case 9:
|
|
// ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, LD1B, LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1...
|
|
printTypedVectorList_0_b(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 10:
|
|
// ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D...
|
|
printTypedVectorList_0_d(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 11:
|
|
// ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BF1CVTL_2ZZ_BtoH_NAME, BF1CVT_2ZZ_BtoH_N...
|
|
printTypedVectorList_0_h(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S...
|
|
printTypedVectorList_0_s(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 13:
|
|
// ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V...
|
|
printMatrix_64(MI, 0, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 14:
|
|
// ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V...
|
|
printMatrix_32(MI, 0, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 15:
|
|
// ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ...
|
|
printZPRasFPR_8(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_0(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_b(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV...
|
|
printZPRasFPR_64(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_0(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 17:
|
|
// ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV...
|
|
printZPRasFPR_16(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_0(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 18:
|
|
// ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV...
|
|
printZPRasFPR_32(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_0(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 19:
|
|
// AT_AS1ELX, AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB,...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 20:
|
|
// AUTIASPPCi, AUTIBSPPCi, B, BL, RETAASPPCi, RETABSPPCi
|
|
printAlignedLabel(MI, Address, 0, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// BCcc, Bcc
|
|
printCondCode(MI, 0, O);
|
|
SStream_concat0(O, "\t");
|
|
printAlignedLabel(MI, Address, 1, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFMLA_VG2_M2Z2Z, BFMLA_VG2_M2ZZ, BFM...
|
|
printMatrix_16(MI, 0, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 23:
|
|
// BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL
|
|
printImmHex(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// CASPALW, CASPAW, CASPLW, CASPW
|
|
printGPRSeqPairsClassOperand_32(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printGPRSeqPairsClassOperand_32(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 25:
|
|
// CASPALX, CASPAX, CASPLX, CASPX, RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL...
|
|
printGPRSeqPairsClassOperand_64(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printGPRSeqPairsClassOperand_64(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 26:
|
|
// CPYE, CPYEN, CPYERN, CPYERT, CPYERTN, CPYERTRN, CPYERTWN, CPYET, CPYET...
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "]!, [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "]!, ");
|
|
printOperand(MI, 5, O);
|
|
SStream_concat1(O, '!');
|
|
return;
|
|
break;
|
|
case 27:
|
|
// DMB, DSB, ISB, TSB
|
|
printBarrierOption(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// DSBnXS
|
|
printBarriernXSOption(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, MOVAZ_ZMI_H_Q, MOVAZ_...
|
|
printSVERegOp_q(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 30:
|
|
// GLD1Q, LD1D_Q, LD1D_Q_IMM, LD1W_Q, LD1W_Q_IMM, LD2Q, LD2Q_IMM, LD3Q, L...
|
|
printTypedVectorList_0_q(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 31:
|
|
// HINT
|
|
printImm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q...
|
|
printMatrixTileVector_0(MI, 0, O);
|
|
SStream_concat1(O, '[');
|
|
break;
|
|
case 33:
|
|
// INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q...
|
|
printMatrixTileVector_1(MI, 0, O);
|
|
SStream_concat1(O, '[');
|
|
break;
|
|
case 34:
|
|
// LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED, LDNT1B_2Z_STR...
|
|
printTypedVectorList_0_b(MI, 0, O);
|
|
break;
|
|
case 35:
|
|
// LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,...
|
|
printTypedVectorList_16_b(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 36:
|
|
// LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L...
|
|
printTypedVectorList_16_b(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 37:
|
|
// LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv...
|
|
printTypedVectorList_1_d(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 38:
|
|
// LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw...
|
|
printTypedVectorList_1_d(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 39:
|
|
// LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw...
|
|
printTypedVectorList_2_d(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 40:
|
|
// LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw...
|
|
printTypedVectorList_2_d(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 41:
|
|
// LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw...
|
|
printTypedVectorList_2_s(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 42:
|
|
// LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw...
|
|
printTypedVectorList_2_s(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 43:
|
|
// LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw...
|
|
printTypedVectorList_4_h(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 44:
|
|
// LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw...
|
|
printTypedVectorList_4_h(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 45:
|
|
// LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw...
|
|
printTypedVectorList_4_s(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 46:
|
|
// LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw...
|
|
printTypedVectorList_4_s(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 47:
|
|
// LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw...
|
|
printTypedVectorList_8_b(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 48:
|
|
// LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw...
|
|
printTypedVectorList_8_b(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 49:
|
|
// LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw...
|
|
printTypedVectorList_8_h(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 50:
|
|
// LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw...
|
|
printTypedVectorList_8_h(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 51:
|
|
// LD1H_2Z_STRIDED, LD1H_2Z_STRIDED_IMM, LDNT1H_2Z_STRIDED, LDNT1H_2Z_STR...
|
|
printTypedVectorList_0_h(MI, 0, O);
|
|
break;
|
|
case 52:
|
|
// LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,...
|
|
printTypedVectorList_0_h(MI, 1, O);
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 53:
|
|
// LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST
|
|
printTypedVectorList_0_h(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 54:
|
|
// LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,...
|
|
printTypedVectorList_0_s(MI, 1, O);
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 55:
|
|
// LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST
|
|
printTypedVectorList_0_s(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 56:
|
|
// LD1i64, LD2i64, LD3i64, LD4i64, LDAP1, ST1i64_POST, ST2i64_POST, ST3i6...
|
|
printTypedVectorList_0_d(MI, 1, O);
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 57:
|
|
// LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST
|
|
printTypedVectorList_0_d(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 58:
|
|
// LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_...
|
|
printTypedVectorList_0_b(MI, 1, O);
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 59:
|
|
// LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST
|
|
printTypedVectorList_0_b(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 60:
|
|
// LD64B, ST64B
|
|
printGPR64x8(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 61:
|
|
// LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 62:
|
|
// LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV...
|
|
printSVERegOp_0(MI, 0, O);
|
|
break;
|
|
case 63:
|
|
// LDR_ZA, STR_ZA
|
|
printMatrix_0(MI, 0, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 2, O);
|
|
SStream_concat0(O, "], [");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 64:
|
|
// MRRS
|
|
printGPRSeqPairsClassOperand_64(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printMRSSystemRegister(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 65:
|
|
// MSR, MSRR
|
|
printMSRSystemRegister(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 66:
|
|
// MSRpstateImm1, MSRpstateImm4
|
|
printSystemPStateField(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// MSRpstatesvcrImm1
|
|
printSVCROp(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 68:
|
|
// PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF...
|
|
printPrefetchOp_1(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_0(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
break;
|
|
case 69:
|
|
// PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi
|
|
printPrefetchOp_0(MI, 0, O);
|
|
break;
|
|
case 70:
|
|
// PTRUE_C_B, WHILEGE_CXX_B, WHILEGT_CXX_B, WHILEHI_CXX_B, WHILEHS_CXX_B,...
|
|
printPredicateAsCounter_8(MI, 0, O);
|
|
break;
|
|
case 71:
|
|
// PTRUE_C_D, WHILEGE_CXX_D, WHILEGT_CXX_D, WHILEHI_CXX_D, WHILEHS_CXX_D,...
|
|
printPredicateAsCounter_64(MI, 0, O);
|
|
break;
|
|
case 72:
|
|
// PTRUE_C_H, WHILEGE_CXX_H, WHILEGT_CXX_H, WHILEHI_CXX_H, WHILEHS_CXX_H,...
|
|
printPredicateAsCounter_16(MI, 0, O);
|
|
break;
|
|
case 73:
|
|
// PTRUE_C_S, WHILEGE_CXX_S, WHILEGT_CXX_S, WHILEHI_CXX_S, WHILEHS_CXX_S,...
|
|
printPredicateAsCounter_32(MI, 0, O);
|
|
break;
|
|
case 74:
|
|
// RPRFM
|
|
printRPRFMOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 75:
|
|
// SDSB
|
|
printAppleSysBarrierOption(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 76:
|
|
// ST1i32, ST2i32, ST3i32, ST4i32
|
|
printTypedVectorList_0_s(MI, 0, O);
|
|
printVectorIndex_1(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 77:
|
|
// ST1i64, ST2i64, ST3i64, ST4i64, STL1
|
|
printTypedVectorList_0_d(MI, 0, O);
|
|
printVectorIndex_1(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 78:
|
|
// ZERO_M
|
|
printMatrixTileList(MI, 0, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 7 bits for 87 unique commands.
|
|
switch ((Bits >> 21) & 127) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// TLSDESCCALL, AT_AS1ELX, AUTDZA, AUTDZB, AUTIASPPCr, AUTIBSPPCr, AUTIZA...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ABSWr, ABSXr, ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCLB_ZZZ_...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm...
|
|
printSVERegOp_0(MI, 2, O);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 3:
|
|
// ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDQV_VPZ_B, ADDv16i8, AESDrr, ...
|
|
SStream_concat0(O, ".16b, ");
|
|
break;
|
|
case 4:
|
|
// ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BF16DOTlanev4bf16, BF...
|
|
SStream_concat0(O, ".2s, ");
|
|
break;
|
|
case 5:
|
|
// ABSv2i64, ADDPv2i64, ADDQV_VPZ_D, ADDv2i64, ANDQV_VPZ_D, CMEQv2i64, CM...
|
|
SStream_concat0(O, ".2d, ");
|
|
break;
|
|
case 6:
|
|
// ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BFCVTN, BICv4i16, CLS...
|
|
SStream_concat0(O, ".4h, ");
|
|
break;
|
|
case 7:
|
|
// ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDQV_VPZ_S, ADDv4i32, ANDQV_VP...
|
|
SStream_concat0(O, ".4s, ");
|
|
break;
|
|
case 8:
|
|
// ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDQV_VPZ_H, ADDv8i16, ANDQV_VP...
|
|
SStream_concat0(O, ".8h, ");
|
|
break;
|
|
case 9:
|
|
// ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8...
|
|
SStream_concat0(O, ".8b, ");
|
|
break;
|
|
case 10:
|
|
// ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D
|
|
printSVERegOp_d(MI, 4, O);
|
|
break;
|
|
case 11:
|
|
// ADDHA_MPPZ_S, ADDVA_MPPZ_S, BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_...
|
|
printSVERegOp_s(MI, 4, O);
|
|
break;
|
|
case 12:
|
|
// ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,...
|
|
printSVERegOp_s(MI, 1, O);
|
|
break;
|
|
case 13:
|
|
// ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FCLAMP_VG2_2Z2Z_S, ...
|
|
printSVERegOp_s(MI, 2, O);
|
|
break;
|
|
case 14:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
|
|
printSVERegOp_0(MI, 1, O);
|
|
break;
|
|
case 15:
|
|
// ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, SMAX_VG2_2Z2Z_B, SMAX_VG2_2ZZ_B, SMAX_VG...
|
|
printTypedVectorList_0_b(MI, 1, O);
|
|
break;
|
|
case 16:
|
|
// ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D...
|
|
printTypedVectorList_0_d(MI, 1, O);
|
|
break;
|
|
case 17:
|
|
// ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG2_2ZZ_H, B...
|
|
printTypedVectorList_0_h(MI, 1, O);
|
|
break;
|
|
case 18:
|
|
// ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVTN_Z2Z_StoH, BFCVT_Z2Z_StoH, FAMAX_2...
|
|
printTypedVectorList_0_s(MI, 1, O);
|
|
break;
|
|
case 19:
|
|
// ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_...
|
|
printMatrixIndex_1(MI, 3, O);
|
|
break;
|
|
case 20:
|
|
// ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H...
|
|
printSVERegOp_h(MI, 1, O);
|
|
break;
|
|
case 21:
|
|
// ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD...
|
|
SStream_concat0(O, ", [");
|
|
break;
|
|
case 22:
|
|
// ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4...
|
|
printSVERegOp_d(MI, 2, O);
|
|
break;
|
|
case 23:
|
|
// ANDV_VPZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA...
|
|
printSVERegOp_h(MI, 2, O);
|
|
break;
|
|
case 24:
|
|
// BF1CVTLT_ZZ_BtoH, BF1CVTL_2ZZ_BtoH_NAME, BF1CVT_2ZZ_BtoH_NAME, BF1CVT_...
|
|
printSVERegOp_b(MI, 1, O);
|
|
break;
|
|
case 25:
|
|
// BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFMLAL_VG2_M...
|
|
printImmRangeScale_2_1(MI, 3, O);
|
|
break;
|
|
case 26:
|
|
// BFMOPA_MPPZZ, BFMOPA_MPPZZ_H, BFMOPS_MPPZZ, BFMOPS_MPPZZ_H, FMOPAL_MPP...
|
|
printSVERegOp_h(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_h(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP...
|
|
printSVEPattern(MI, 2, O);
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// DUP_ZI_H
|
|
printImm8OptLsl_int16_t(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 30:
|
|
// DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZ...
|
|
printSVERegOp_q(MI, 1, O);
|
|
break;
|
|
case 31:
|
|
// FADDA_VPZ_D
|
|
printZPRasFPR_64(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_d(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// FADDA_VPZ_H, INSR_ZV_H
|
|
printZPRasFPR_16(MI, 2, O);
|
|
break;
|
|
case 33:
|
|
// FADDA_VPZ_S
|
|
printZPRasFPR_32(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_s(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri
|
|
SStream_concat0(O, ", #0.0");
|
|
return;
|
|
break;
|
|
case 35:
|
|
// FDOT_ZZZI_BtoH, FDOT_ZZZ_BtoH, FMLALB_ZZZ, FMLALB_ZZZI, FMLALT_ZZZ, FM...
|
|
printSVERegOp_b(MI, 2, O);
|
|
break;
|
|
case 36:
|
|
// FDUP_ZI_H
|
|
printFPImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLALL_VG2_M2Z2Z_BtoS, FMLALL_VG2_M...
|
|
printImmRangeScale_4_3(MI, 3, O);
|
|
break;
|
|
case 38:
|
|
// FMOPA_MPPZZ_BtoH, FMOPA_MPPZZ_BtoS, SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMO...
|
|
printSVERegOp_b(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_b(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// FMOVXDHighr, INSvi64gpr, INSvi64lane
|
|
SStream_concat0(O, ".d");
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 40:
|
|
// INDEX_II_H, INDEX_IR_H
|
|
printSImm_16(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 41:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 42:
|
|
// INSvi16gpr, INSvi16lane
|
|
SStream_concat0(O, ".h");
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 43:
|
|
// INSvi32gpr, INSvi32lane
|
|
SStream_concat0(O, ".s");
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 44:
|
|
// INSvi8gpr, INSvi8lane
|
|
SStream_concat0(O, ".b");
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 45:
|
|
// LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1B_4Z_IMM, LD1B_4Z_STRIDED, LD1B_4Z_S...
|
|
printPredicateAsCounter_0(MI, 1, O);
|
|
break;
|
|
case 46:
|
|
// LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L...
|
|
printPostIncOperand_64(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD...
|
|
printPostIncOperand_32(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw...
|
|
printPostIncOperand_16(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1...
|
|
printPostIncOperand_8(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// LD1Rv16b_POST, LD1Rv8b_POST
|
|
printPostIncOperand_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 51:
|
|
// LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,...
|
|
printPostIncOperand_4(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST
|
|
printPostIncOperand_2(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS...
|
|
printPostIncOperand_48(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST...
|
|
printPostIncOperand_24(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ...
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 56:
|
|
// LD1i16_POST, LD2i8_POST
|
|
printPostIncOperand_2(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// LD1i32_POST, LD2i16_POST, LD4i8_POST
|
|
printPostIncOperand_4(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 58:
|
|
// LD1i64_POST, LD2i32_POST, LD4i16_POST
|
|
printPostIncOperand_8(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 59:
|
|
// LD1i8_POST
|
|
printPostIncOperand_1(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// LD2i64_POST, LD4i32_POST
|
|
printPostIncOperand_16(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 61:
|
|
// LD3Rv16b_POST, LD3Rv8b_POST
|
|
printPostIncOperand_3(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 62:
|
|
// LD3Rv2s_POST, LD3Rv4s_POST
|
|
printPostIncOperand_12(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 63:
|
|
// LD3Rv4h_POST, LD3Rv8h_POST
|
|
printPostIncOperand_6(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 64:
|
|
// LD3i16_POST
|
|
printPostIncOperand_6(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 65:
|
|
// LD3i32_POST
|
|
printPostIncOperand_12(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 66:
|
|
// LD3i64_POST
|
|
printPostIncOperand_24(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// LD3i8_POST
|
|
printPostIncOperand_3(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 68:
|
|
// LD4i64_POST
|
|
printPostIncOperand_32(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 69:
|
|
// MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE...
|
|
SStream_concat0(O, "]!, ");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "!, ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_...
|
|
printMatrixTileVector_0(MI, 2, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 71:
|
|
// MOVAZ_2ZMI_V_B, MOVAZ_2ZMI_V_D, MOVAZ_2ZMI_V_H, MOVAZ_2ZMI_V_S, MOVAZ_...
|
|
printMatrixTileVector_1(MI, 2, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 72:
|
|
// MOVAZ_VG2_2ZM, MOVAZ_VG4_4ZM
|
|
printMatrix_64(MI, 2, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 4, O);
|
|
break;
|
|
case 73:
|
|
// MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZM...
|
|
printMatrixTileVector_0(MI, 1, O);
|
|
SStream_concat1(O, '[');
|
|
break;
|
|
case 74:
|
|
// MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q, MOVA_2ZMXI_V_B, MOVA_2ZMXI_V_D, MOVA_2ZM...
|
|
printMatrixTileVector_1(MI, 1, O);
|
|
SStream_concat1(O, '[');
|
|
break;
|
|
case 75:
|
|
// MOVA_VG2_2ZMXI, MOVA_VG4_4ZMXI
|
|
printMatrix_64(MI, 1, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 3, O);
|
|
break;
|
|
case 76:
|
|
// MOVT, MOVT_TIX
|
|
SStream_concat1(O, '[');
|
|
break;
|
|
case 77:
|
|
// MSRR
|
|
printGPRSeqPairsClassOperand_64(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 78:
|
|
// PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV_ZIP_S
|
|
printVectorIndex_1(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 79:
|
|
// PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, UZP_VG2_2ZZZ_D, ZIP_VG2_2ZZZ_D
|
|
printSVERegOp_d(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_d(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// PMULLv1i64, PMULLv2i64
|
|
SStream_concat0(O, ".1q, ");
|
|
printVRegOperand(MI, 1, O);
|
|
break;
|
|
case 81:
|
|
// PTRUES_H, PTRUE_H
|
|
printSVEPattern(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v...
|
|
SStream_concat0(O, ".1d, ");
|
|
break;
|
|
case 83:
|
|
// ST1i16, ST1i8, ST2i16, ST2i8, ST3i16, ST3i8, ST4i16, ST4i8
|
|
printVectorIndex_1(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 84:
|
|
// ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32...
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 85:
|
|
// UZP_VG4_4Z4Z_Q, ZIP_VG4_4Z4Z_Q
|
|
printTypedVectorList_0_q(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// ZERO_T
|
|
SStream_concat0(O, " }");
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 7 bits for 92 unique commands.
|
|
switch ((Bits >> 28) & 127) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI,...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 1:
|
|
// ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ...
|
|
printSVERegOp_0(MI, 2, O);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ...
|
|
printSVERegOp_h(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
|
|
printVRegOperand(MI, 1, O);
|
|
break;
|
|
case 4:
|
|
// ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z...
|
|
printSVERegOp_d(MI, 2, O);
|
|
break;
|
|
case 5:
|
|
// ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ...
|
|
printSVERegOp_s(MI, 2, O);
|
|
break;
|
|
case 6:
|
|
// ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, ANDV_VPZ_D, AN...
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH...
|
|
printSVERegOp_h(MI, 1, O);
|
|
break;
|
|
case 8:
|
|
// ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_VG2_2ZZ_B, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 9:
|
|
// ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_CPA, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_L...
|
|
printSVERegOp_d(MI, 1, O);
|
|
break;
|
|
case 10:
|
|
// ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT...
|
|
printSVERegOp_h(MI, 2, O);
|
|
break;
|
|
case 11:
|
|
// ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
|
|
printVRegOperand(MI, 2, O);
|
|
break;
|
|
case 12:
|
|
// ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADDQV_VPZ_B, ADDQV_VPZ_D, ADDQV...
|
|
printSVERegOp_0(MI, 1, O);
|
|
break;
|
|
case 13:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 14:
|
|
// ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_...
|
|
SStream_concat0(O, ", vgx2], ");
|
|
break;
|
|
case 15:
|
|
// ADD_VG4_M4Z4Z_D, ADD_VG4_M4Z4Z_S, ADD_VG4_M4ZZ_D, ADD_VG4_M4ZZ_S, ADD_...
|
|
SStream_concat0(O, ", vgx4], ");
|
|
break;
|
|
case 16:
|
|
// ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ...
|
|
printSVERegOp_b(MI, 1, O);
|
|
break;
|
|
case 17:
|
|
// ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2...
|
|
printSVERegOp_s(MI, 1, O);
|
|
break;
|
|
case 18:
|
|
// ADR, ADRP
|
|
printAdrAdrpLabel(MI, Address, 1, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 20:
|
|
// BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, PMOV_ZIP_S...
|
|
printSVERegOp_s(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// BFCVTN_Z2Z_HtoB, BFCVT_Z2Z_HtoB, FCVTN_Z2Z_HtoB, FCVT_Z2Z_HtoB
|
|
printTypedVectorList_0_h(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ...
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 23:
|
|
// BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv...
|
|
printImm(MI, 2, O);
|
|
printShifter(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P...
|
|
printAlignedLabel(MI, Address, 1, O);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, FDOT_ZZ...
|
|
printSVERegOp_b(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 26:
|
|
// CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE...
|
|
SStream_concat0(O, "/z, ");
|
|
break;
|
|
case 27:
|
|
// CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES...
|
|
printSVEPattern(MI, 1, O);
|
|
break;
|
|
case 28:
|
|
// CNTP_XCI_B
|
|
printPredicateAsCounter_8(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVEVecLenSpecifier(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// CNTP_XCI_D
|
|
printPredicateAsCounter_64(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVEVecLenSpecifier(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// CNTP_XCI_H
|
|
printPredicateAsCounter_16(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVEVecLenSpecifier(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// CNTP_XCI_S
|
|
printPredicateAsCounter_32(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVEVecLenSpecifier(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// CPY_ZPmI_H
|
|
printImm8OptLsl_int16_t(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr,...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 34:
|
|
// DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB...
|
|
printSVEPattern(MI, 2, O);
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// DUPM_ZI
|
|
printLogicalImm_int64_t(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// DUPQ_ZZI_H, DUP_ZZI_H, DUP_ZZI_Q, PEXT_2PCI_B, PEXT_2PCI_D, PEXT_2PCI_...
|
|
printVectorIndex_1(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// DUP_ZI_B
|
|
printImm8OptLsl_int8_t(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// DUP_ZI_D
|
|
printImm8OptLsl_int64_t(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// DUP_ZI_S
|
|
printImm8OptLsl_int32_t(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q
|
|
printMatrixTileVector_0(MI, 3, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 41:
|
|
// EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q
|
|
printMatrixTileVector_1(MI, 3, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 42:
|
|
// EXT_ZZI_B, LUTI2_ZZZI_B, LUTI4_ZZZI_B, TBLQ_ZZZ_B, TBL_ZZZZ_B, TBL_ZZZ...
|
|
printTypedVectorList_0_b(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 43:
|
|
// FCPY_ZPmI_H
|
|
printFPImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// FCVTNB_Z2Z_StoB, FCVTNT_Z2Z_StoB, FCVTN_Z4Z_StoB_NAME, FCVT_Z4Z_StoB_N...
|
|
printTypedVectorList_0_s(MI, 1, O);
|
|
break;
|
|
case 45:
|
|
// FCVT_ZPmZ_DtoH, PMOV_ZIP_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH
|
|
printSVERegOp_d(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 46:
|
|
// FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_...
|
|
printFPImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// FMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_HtoD, SMLS...
|
|
SStream_concat0(O, ", vgx2], ");
|
|
break;
|
|
case 48:
|
|
// FMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_HtoD, SMLS...
|
|
SStream_concat0(O, ", vgx4], ");
|
|
break;
|
|
case 49:
|
|
// GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
|
|
SStream_concat0(O, "/z, [");
|
|
break;
|
|
case 50:
|
|
// INDEX_II_B, INDEX_IR_B
|
|
printSImm_8(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 51:
|
|
// INDEX_II_H
|
|
printSImm_16(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// INSR_ZV_B
|
|
printZPRasFPR_8(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// INSR_ZV_D
|
|
printZPRasFPR_64(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// INSR_ZV_S
|
|
printZPRasFPR_32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 56:
|
|
// LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED...
|
|
printPredicateAsCounter_0(MI, 1, O);
|
|
break;
|
|
case 57:
|
|
// LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA...
|
|
printOperand(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 58:
|
|
// LUT2v16f8, LUT4v16f8, TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16...
|
|
printTypedVectorList_16_b(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printVRegOperand(MI, 2, O);
|
|
break;
|
|
case 59:
|
|
// LUT2v8f16, LUT4v8f16
|
|
printTypedVectorList_8_h(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printVRegOperand(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_...
|
|
printImmRangeScale_2_1(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 61:
|
|
// MOVAZ_4ZMI_H_B, MOVAZ_4ZMI_H_D, MOVAZ_4ZMI_H_H, MOVAZ_4ZMI_H_S, MOVAZ_...
|
|
printImmRangeScale_4_3(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 62:
|
|
// MOVAZ_VG2_2ZM, MOVA_VG2_2ZMXI, ZERO_MXI_VG2_2Z, ZERO_MXI_VG2_4Z, ZERO_...
|
|
SStream_concat0(O, ", vgx2]");
|
|
return;
|
|
break;
|
|
case 63:
|
|
// MOVAZ_VG4_4ZM, MOVA_VG4_4ZMXI, ZERO_MXI_VG4_2Z, ZERO_MXI_VG4_4Z, ZERO_...
|
|
SStream_concat0(O, ", vgx4]");
|
|
return;
|
|
break;
|
|
case 64:
|
|
// MOVAZ_ZMI_H_B, MOVAZ_ZMI_H_D, MOVAZ_ZMI_H_S
|
|
printMatrixTileVector_0(MI, 1, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 65:
|
|
// MOVAZ_ZMI_V_B, MOVAZ_ZMI_V_D, MOVAZ_ZMI_V_S
|
|
printMatrixTileVector_1(MI, 1, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 66:
|
|
// MOVID, MOVIv2d_ns
|
|
printSIMDType10Operand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl...
|
|
printImm(MI, 1, O);
|
|
break;
|
|
case 68:
|
|
// MOVT
|
|
printMatrixIndex_1(MI, 1, O);
|
|
SStream_concat0(O, ", mul vl], ");
|
|
printSVERegOp_0(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 69:
|
|
// MOVT_TIX
|
|
printMatrixIndex_8(MI, 1, O);
|
|
SStream_concat0(O, "], ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// MRS
|
|
printMRSSystemRegister(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 71:
|
|
// PMOV_ZIP_B
|
|
printSVERegOp_b(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 72:
|
|
// PMULLv1i64
|
|
SStream_concat0(O, ".1d, ");
|
|
printVRegOperand(MI, 2, O);
|
|
SStream_concat0(O, ".1d");
|
|
return;
|
|
break;
|
|
case 73:
|
|
// PMULLv2i64
|
|
SStream_concat0(O, ".2d, ");
|
|
printVRegOperand(MI, 2, O);
|
|
SStream_concat0(O, ".2d");
|
|
return;
|
|
break;
|
|
case 74:
|
|
// REVD_ZPmZ
|
|
printSVERegOp_q(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 75:
|
|
// SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi...
|
|
printGPR64as32(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVEPattern(MI, 2, O);
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 76:
|
|
// SST1B_D, SST1B_D_IMM, SST1B_D_SXTW, SST1B_D_UXTW, SST1B_S_IMM, SST1B_S...
|
|
SStream_concat0(O, ", [");
|
|
break;
|
|
case 77:
|
|
// ST1i16_POST, ST2i8_POST
|
|
printPostIncOperand_2(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 78:
|
|
// ST1i32_POST, ST2i16_POST, ST4i8_POST
|
|
printPostIncOperand_4(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 79:
|
|
// ST1i64_POST, ST2i32_POST, ST4i16_POST
|
|
printPostIncOperand_8(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// ST1i8_POST
|
|
printPostIncOperand_1(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// ST2i64_POST, ST4i32_POST
|
|
printPostIncOperand_16(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// ST3i16_POST
|
|
printPostIncOperand_6(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// ST3i32_POST
|
|
printPostIncOperand_12(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 84:
|
|
// ST3i64_POST
|
|
printPostIncOperand_24(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 85:
|
|
// ST3i8_POST
|
|
printPostIncOperand_3(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// ST4i64_POST
|
|
printPostIncOperand_32(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 87:
|
|
// ST64BV, ST64BV0
|
|
printGPR64x8(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 88:
|
|
// SYSPxt, SYSPxt_XZR, SYSxt
|
|
printSysCROperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSysCROperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 89:
|
|
// TBLQ_ZZZ_D, TBL_ZZZZ_D, TBL_ZZZ_D
|
|
printTypedVectorList_0_d(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_d(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 90:
|
|
// TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB...
|
|
printTypedVectorList_16_b(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 91:
|
|
// ZERO_MXI_2Z, ZERO_MXI_4Z
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 7 bits for 128 unique commands.
|
|
switch ((Bits >> 35) & 127) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSWr, ABSXr, ABSv1i64, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,...
|
|
printSVERegOp_b(MI, 3, O);
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ...
|
|
printSVERegOp_d(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm...
|
|
printSVERegOp_s(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, BF1CVTL2v8f16...
|
|
SStream_concat0(O, ".16b");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV...
|
|
SStream_concat0(O, ".2s");
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64...
|
|
SStream_concat0(O, ".2d");
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT...
|
|
SStream_concat0(O, ".4h");
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ABSv4i32, ADDVv4i32v, BFCVTN, BFCVTN2, CLSv4i32, CLZv4i32, FABSv4f32, ...
|
|
SStream_concat0(O, ".4s");
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT...
|
|
SStream_concat0(O, ".8h");
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ABSv8i8, ADDVv8i8v, BF1CVTLv8f16, BF2CVTLv8f16, CLSv8i8, CLZv8i8, CNTv...
|
|
SStream_concat0(O, ".8b");
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// ADDHNB_ZZZ_H, ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FMAXNM_VG2_2ZZ_S, FMAXNM_V...
|
|
printSVERegOp_s(MI, 2, O);
|
|
break;
|
|
case 13:
|
|
// ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
|
|
SStream_concat0(O, ".2d, ");
|
|
break;
|
|
case 14:
|
|
// ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
|
|
SStream_concat0(O, ".4s, ");
|
|
break;
|
|
case 15:
|
|
// ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BF16DOTlanev8b...
|
|
SStream_concat0(O, ".8h, ");
|
|
break;
|
|
case 16:
|
|
// ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_CPA, ADD_Z...
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 17:
|
|
// ADDP_ZPmZ_H, ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_...
|
|
printSVERegOp_h(MI, 2, O);
|
|
break;
|
|
case 18:
|
|
// ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL...
|
|
SStream_concat0(O, ".16b, ");
|
|
break;
|
|
case 19:
|
|
// ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
|
|
SStream_concat0(O, ".2s, ");
|
|
break;
|
|
case 20:
|
|
// ADDPv4i16, ADDv4i16, BF16DOTlanev4bf16, BFDOTv4bf16, CMEQv4i16, CMGEv4...
|
|
SStream_concat0(O, ".4h, ");
|
|
break;
|
|
case 21:
|
|
// ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
|
|
SStream_concat0(O, ".8b, ");
|
|
break;
|
|
case 22:
|
|
// ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H...
|
|
printSVERegOp_b(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, ASR_WIDE_ZZZ_H, FMAXNM_VG2_2ZZ_D, FMAXNM...
|
|
printSVERegOp_d(MI, 2, O);
|
|
break;
|
|
case 24:
|
|
// ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V...
|
|
printTypedVectorList_0_d(MI, 4, O);
|
|
break;
|
|
case 25:
|
|
// ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V...
|
|
printTypedVectorList_0_s(MI, 4, O);
|
|
break;
|
|
case 26:
|
|
// ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS...
|
|
printImm8OptLsl_uint16_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B...
|
|
SStream_concat0(O, "/z, ");
|
|
break;
|
|
case 28:
|
|
// ASR_ZZI_H, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, GLD1B_S...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 29:
|
|
// BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG2_M2ZZ...
|
|
printTypedVectorList_0_h(MI, 4, O);
|
|
break;
|
|
case 30:
|
|
// BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA_ZPmZZ, BFML...
|
|
printSVERegOp_h(MI, 3, O);
|
|
break;
|
|
case 31:
|
|
// BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG4_4Z2Z_H, BFMAX_VG2_2Z2Z_H, BFMAX_VG4_4Z...
|
|
printTypedVectorList_0_h(MI, 2, O);
|
|
break;
|
|
case 32:
|
|
// BFMLAL_MZZI_HtoS, BFMLAL_MZZ_HtoS, BFMLSL_MZZI_HtoS, BFMLSL_MZZ_HtoS, ...
|
|
printSVERegOp_h(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_h(MI, 5, O);
|
|
break;
|
|
case 33:
|
|
// BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S
|
|
printSVERegOp_s(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
|
|
SStream_concat0(O, ", [");
|
|
break;
|
|
case 35:
|
|
// CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz
|
|
SStream_concat0(O, ".16b, #0");
|
|
return;
|
|
break;
|
|
case 36:
|
|
// CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz
|
|
SStream_concat0(O, ", #0");
|
|
return;
|
|
break;
|
|
case 37:
|
|
// CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz
|
|
SStream_concat0(O, ".2s, #0");
|
|
return;
|
|
break;
|
|
case 38:
|
|
// CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz
|
|
SStream_concat0(O, ".2d, #0");
|
|
return;
|
|
break;
|
|
case 39:
|
|
// CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz
|
|
SStream_concat0(O, ".4h, #0");
|
|
return;
|
|
break;
|
|
case 40:
|
|
// CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz
|
|
SStream_concat0(O, ".4s, #0");
|
|
return;
|
|
break;
|
|
case 41:
|
|
// CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz
|
|
SStream_concat0(O, ".8h, #0");
|
|
return;
|
|
break;
|
|
case 42:
|
|
// CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz
|
|
SStream_concat0(O, ".8b, #0");
|
|
return;
|
|
break;
|
|
case 43:
|
|
// CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// CPY_ZPmI_B
|
|
printImm8OptLsl_int8_t(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// CPY_ZPmI_D
|
|
printImm8OptLsl_int64_t(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 46:
|
|
// CPY_ZPmI_S
|
|
printImm8OptLsl_int32_t(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 48:
|
|
// CPY_ZPzI_H
|
|
printImm8OptLsl_int16_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// DUPQ_ZZI_B, DUPQ_ZZI_D, DUPQ_ZZI_S, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, P...
|
|
printVectorIndex_1(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// DUPi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1...
|
|
SStream_concat0(O, ".h");
|
|
break;
|
|
case 51:
|
|
// DUPi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, SMOVvi3...
|
|
SStream_concat0(O, ".s");
|
|
break;
|
|
case 52:
|
|
// DUPi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64, UMOVvi64_idx...
|
|
SStream_concat0(O, ".d");
|
|
break;
|
|
case 53:
|
|
// DUPi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to32...
|
|
SStream_concat0(O, ".b");
|
|
break;
|
|
case 54:
|
|
// EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S
|
|
printMatrixTileVector_0(MI, 3, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 55:
|
|
// EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S
|
|
printMatrixTileVector_1(MI, 3, O);
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 56:
|
|
// EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H
|
|
printImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p
|
|
SStream_concat0(O, ".2h");
|
|
return;
|
|
break;
|
|
case 58:
|
|
// FAMAX_2Z2Z_D, FAMAX_4Z4Z_D, FAMIN_2Z2Z_D, FAMIN_4Z4Z_D, FMAXNM_VG2_2Z2...
|
|
printTypedVectorList_0_d(MI, 2, O);
|
|
break;
|
|
case 59:
|
|
// FAMAX_2Z2Z_S, FAMAX_4Z4Z_S, FAMIN_2Z2Z_S, FAMIN_4Z4Z_S, FMAXNM_VG2_2Z2...
|
|
printTypedVectorList_0_s(MI, 2, O);
|
|
break;
|
|
case 60:
|
|
// FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ...
|
|
SStream_concat0(O, ", #0.0");
|
|
return;
|
|
break;
|
|
case 61:
|
|
// FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz
|
|
SStream_concat0(O, ".2s, #0.0");
|
|
return;
|
|
break;
|
|
case 62:
|
|
// FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz
|
|
SStream_concat0(O, ".2d, #0.0");
|
|
return;
|
|
break;
|
|
case 63:
|
|
// FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz
|
|
SStream_concat0(O, ".4h, #0.0");
|
|
return;
|
|
break;
|
|
case 64:
|
|
// FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz
|
|
SStream_concat0(O, ".4s, #0.0");
|
|
return;
|
|
break;
|
|
case 65:
|
|
// FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz
|
|
SStream_concat0(O, ".8h, #0.0");
|
|
return;
|
|
break;
|
|
case 66:
|
|
// FCPY_ZPmI_D, FCPY_ZPmI_S
|
|
printFPImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG2_M2ZZI_BtoH, FDOT_VG...
|
|
printTypedVectorList_0_b(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 68:
|
|
// FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4...
|
|
SStream_concat0(O, ".2h, ");
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 69:
|
|
// FMLALL_MZZI_BtoS, FMLALL_MZZ_BtoS, FMLAL_MZZI_BtoH, FMLAL_VG2_MZZ_BtoH...
|
|
printSVERegOp_b(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_b(MI, 5, O);
|
|
break;
|
|
case 70:
|
|
// FMOPA_MPPZZ_D, FMOPS_MPPZZ_D
|
|
printSVERegOp_d(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 71:
|
|
// INDEX_II_B
|
|
printSImm_8(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 72:
|
|
// INDEX_RI_H
|
|
printSImm_16(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 73:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q...
|
|
printMatrixIndex_1(MI, 3, O);
|
|
SStream_concat0(O, "], ");
|
|
printSVERegOp_0(MI, 4, O);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 74:
|
|
// LD1B_2Z_STRIDED, LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED, LD1H_2Z_STRIDED...
|
|
SStream_concat0(O, "/z, [");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 75:
|
|
// LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX...
|
|
printMatrixIndex_1(MI, 2, O);
|
|
SStream_concat0(O, "]}, ");
|
|
printSVERegOp_0(MI, 3, O);
|
|
break;
|
|
case 76:
|
|
// LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD...
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 77:
|
|
// LDAPRWpost
|
|
SStream_concat0(O, "], #4");
|
|
return;
|
|
break;
|
|
case 78:
|
|
// LDAPRXpost
|
|
SStream_concat0(O, "], #8");
|
|
return;
|
|
break;
|
|
case 79:
|
|
// LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo...
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 80:
|
|
// LUT2v16f8, LUT4v16f8
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// LUTI2_2ZTZI_B, LUTI2_2ZTZI_H, LUTI2_2ZTZI_S, LUTI2_4ZTZI_B, LUTI2_4ZTZ...
|
|
printSVERegOp_0(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// LUTI4_4ZZT2Z, LUTI4_S_4ZZT2Z
|
|
printTypedVectorList_0_0(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// MOVA_MXI2Z_H_B, MOVA_MXI2Z_H_D, MOVA_MXI2Z_H_H, MOVA_MXI2Z_H_S, MOVA_M...
|
|
printImmRangeScale_2_1(MI, 3, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 84:
|
|
// MOVA_MXI4Z_H_B, MOVA_MXI4Z_H_D, MOVA_MXI4Z_H_H, MOVA_MXI4Z_H_S, MOVA_M...
|
|
printImmRangeScale_4_3(MI, 3, O);
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 85:
|
|
// MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ...
|
|
printShifter(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// MOVT_XTI
|
|
SStream_concat1(O, '[');
|
|
printMatrixIndex_8(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 87:
|
|
// PRFB_D_SCALED
|
|
printRegWithShiftExtend_0_8_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 88:
|
|
// PRFB_D_SXTW_SCALED
|
|
printRegWithShiftExtend_1_8_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 89:
|
|
// PRFB_D_UXTW_SCALED
|
|
printRegWithShiftExtend_0_8_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 90:
|
|
// PRFB_PRR
|
|
printRegWithShiftExtend_0_8_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 91:
|
|
// PRFB_S_SXTW_SCALED
|
|
printRegWithShiftExtend_1_8_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 92:
|
|
// PRFB_S_UXTW_SCALED
|
|
printRegWithShiftExtend_0_8_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 93:
|
|
// PRFD_D_PZI, PRFD_S_PZI
|
|
printImmScale_8(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 94:
|
|
// PRFD_D_SCALED
|
|
printRegWithShiftExtend_0_64_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 95:
|
|
// PRFD_D_SXTW_SCALED
|
|
printRegWithShiftExtend_1_64_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 96:
|
|
// PRFD_D_UXTW_SCALED
|
|
printRegWithShiftExtend_0_64_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 97:
|
|
// PRFD_PRR
|
|
printRegWithShiftExtend_0_64_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 98:
|
|
// PRFD_S_SXTW_SCALED
|
|
printRegWithShiftExtend_1_64_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 99:
|
|
// PRFD_S_UXTW_SCALED
|
|
printRegWithShiftExtend_0_64_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 100:
|
|
// PRFH_D_PZI, PRFH_S_PZI
|
|
printImmScale_2(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 101:
|
|
// PRFH_D_SCALED
|
|
printRegWithShiftExtend_0_16_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 102:
|
|
// PRFH_D_SXTW_SCALED
|
|
printRegWithShiftExtend_1_16_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 103:
|
|
// PRFH_D_UXTW_SCALED
|
|
printRegWithShiftExtend_0_16_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 104:
|
|
// PRFH_PRR
|
|
printRegWithShiftExtend_0_16_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 105:
|
|
// PRFH_S_SXTW_SCALED
|
|
printRegWithShiftExtend_1_16_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 106:
|
|
// PRFH_S_UXTW_SCALED
|
|
printRegWithShiftExtend_0_16_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 107:
|
|
// PRFW_D_PZI, PRFW_S_PZI
|
|
printImmScale_4(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 108:
|
|
// PRFW_D_SCALED
|
|
printRegWithShiftExtend_0_32_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 109:
|
|
// PRFW_D_SXTW_SCALED
|
|
printRegWithShiftExtend_1_32_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 110:
|
|
// PRFW_D_UXTW_SCALED
|
|
printRegWithShiftExtend_0_32_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 111:
|
|
// PRFW_PRR
|
|
printRegWithShiftExtend_0_32_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 112:
|
|
// PRFW_S_SXTW_SCALED
|
|
printRegWithShiftExtend_1_32_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 113:
|
|
// PRFW_S_UXTW_SCALED
|
|
printRegWithShiftExtend_0_32_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 114:
|
|
// RDFFRS_PPz, RDFFR_PPz_REAL
|
|
SStream_concat0(O, "/z");
|
|
return;
|
|
break;
|
|
case 115:
|
|
// SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B, SMAX_VG2_2Z2Z_B, SMAX_VG4_4Z4Z_B...
|
|
printTypedVectorList_0_b(MI, 2, O);
|
|
break;
|
|
case 116:
|
|
// SHLLv16i8
|
|
SStream_concat0(O, ".16b, #8");
|
|
return;
|
|
break;
|
|
case 117:
|
|
// SHLLv2i32
|
|
SStream_concat0(O, ".2s, #32");
|
|
return;
|
|
break;
|
|
case 118:
|
|
// SHLLv4i16
|
|
SStream_concat0(O, ".4h, #16");
|
|
return;
|
|
break;
|
|
case 119:
|
|
// SHLLv4i32
|
|
SStream_concat0(O, ".4s, #32");
|
|
return;
|
|
break;
|
|
case 120:
|
|
// SHLLv8i16
|
|
SStream_concat0(O, ".8h, #16");
|
|
return;
|
|
break;
|
|
case 121:
|
|
// SHLLv8i8
|
|
SStream_concat0(O, ".8b, #8");
|
|
return;
|
|
break;
|
|
case 122:
|
|
// STLRWpre
|
|
SStream_concat0(O, ", #-4]!");
|
|
return;
|
|
break;
|
|
case 123:
|
|
// STLRXpre
|
|
SStream_concat0(O, ", #-8]!");
|
|
return;
|
|
break;
|
|
case 124:
|
|
// SYSPxt
|
|
printGPRSeqPairsClassOperand_64(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 125:
|
|
// SYSPxt_XZR
|
|
printSyspXzrPair(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 126:
|
|
// SYSxt
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 127:
|
|
// TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZZ_Q, ZIP1_Z...
|
|
printSVERegOp_q(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 7 bits for 87 unique commands.
|
|
switch ((Bits >> 42) & 127) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABS_ZPmZ_B, ADDHNB_ZZZ_H, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_H, ADD_VG2_2ZZ_S,...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB...
|
|
printSVERegOp_d(MI, 3, O);
|
|
break;
|
|
case 2:
|
|
// ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_...
|
|
printSVERegOp_s(MI, 3, O);
|
|
break;
|
|
case 3:
|
|
// ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPT_shift, ADDSPL_XXI, ADDS...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 4:
|
|
// ADDG, ST2Gi, STGi, STZ2Gi, STZGi, SUBG
|
|
printImmScale_16(MI, 2, O);
|
|
break;
|
|
case 5:
|
|
// ADDHNB_ZZZ_B, ADDQV_VPZ_H, ANDQV_VPZ_H, CNTP_XPP_H, EORQV_VPZ_H, FADDQ...
|
|
printSVERegOp_h(MI, 2, O);
|
|
break;
|
|
case 6:
|
|
// ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADDQV_VPZ_D, ADD_ZPmZ_CPA, ADD_ZPmZ_D, ADD_...
|
|
printSVERegOp_d(MI, 2, O);
|
|
break;
|
|
case 7:
|
|
// ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT...
|
|
printSVERegOp_h(MI, 3, O);
|
|
break;
|
|
case 8:
|
|
// ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2...
|
|
printVRegOperand(MI, 2, O);
|
|
break;
|
|
case 9:
|
|
// ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1...
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 10:
|
|
// ADDP_ZPmZ_B, ADDQV_VPZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_...
|
|
printSVERegOp_b(MI, 2, O);
|
|
break;
|
|
case 11:
|
|
// ADDP_ZPmZ_H, ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// ADDP_ZPmZ_S, ADDQV_VPZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, ANDQV_VPZ_S, AND_ZPmZ...
|
|
printSVERegOp_s(MI, 2, O);
|
|
break;
|
|
case 13:
|
|
// ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri
|
|
printAddSubImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI...
|
|
printShiftedRegister(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx
|
|
printExtendedRegister(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS...
|
|
printImm8OptLsl_uint8_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS...
|
|
printImm8OptLsl_uint64_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS...
|
|
printImm8OptLsl_uint32_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// ADR_LSL_ZZZ_D_0
|
|
printRegWithShiftExtend_0_8_x_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 20:
|
|
// ADR_LSL_ZZZ_D_1
|
|
printRegWithShiftExtend_0_16_x_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 21:
|
|
// ADR_LSL_ZZZ_D_2
|
|
printRegWithShiftExtend_0_32_x_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 22:
|
|
// ADR_LSL_ZZZ_D_3
|
|
printRegWithShiftExtend_0_64_x_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ADR_LSL_ZZZ_S_0
|
|
printRegWithShiftExtend_0_8_x_s(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 24:
|
|
// ADR_LSL_ZZZ_S_1
|
|
printRegWithShiftExtend_0_16_x_s(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ADR_LSL_ZZZ_S_2
|
|
printRegWithShiftExtend_0_32_x_s(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 26:
|
|
// ADR_LSL_ZZZ_S_3
|
|
printRegWithShiftExtend_0_64_x_s(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ADR_SXTW_ZZZ_D_0
|
|
printRegWithShiftExtend_1_8_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 28:
|
|
// ADR_SXTW_ZZZ_D_1
|
|
printRegWithShiftExtend_1_16_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 29:
|
|
// ADR_SXTW_ZZZ_D_2
|
|
printRegWithShiftExtend_1_32_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 30:
|
|
// ADR_SXTW_ZZZ_D_3
|
|
printRegWithShiftExtend_1_64_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 31:
|
|
// ADR_UXTW_ZZZ_D_0
|
|
printRegWithShiftExtend_0_8_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 32:
|
|
// ADR_UXTW_ZZZ_D_1
|
|
printRegWithShiftExtend_0_16_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 33:
|
|
// ADR_UXTW_ZZZ_D_2
|
|
printRegWithShiftExtend_0_32_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 34:
|
|
// ADR_UXTW_ZZZ_D_3
|
|
printRegWithShiftExtend_0_64_w_d(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 35:
|
|
// ANDSWri, ANDWri, EORWri, ORRWri
|
|
printLogicalImm_int32_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI
|
|
printLogicalImm_int64_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// BFMLAL_MZZI_HtoS, BFMLSL_MZZI_HtoS, FMLALL_MZZI_BtoS, FMLAL_MZZI_BtoH,...
|
|
printVectorIndex_1(MI, 6, O);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// BFMLA_ZZZI, BFMLS_ZZZI, CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FDOT_Z...
|
|
printVectorIndex_1(MI, 4, O);
|
|
break;
|
|
case 39:
|
|
// BFMUL_ZZZI, FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 41:
|
|
// CPY_ZPzI_B
|
|
printImm8OptLsl_int8_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// CPY_ZPzI_D
|
|
printImm8OptLsl_int64_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// CPY_ZPzI_S
|
|
printImm8OptLsl_int32_t(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// DUPi16, DUPi32, DUPi64, DUPi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan...
|
|
printVectorIndex_1(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ...
|
|
SStream_concat0(O, ", #0.0");
|
|
return;
|
|
break;
|
|
case 46:
|
|
// FDOT_VG2_M2Z2Z_BtoH, FDOT_VG2_M2Z2Z_BtoS, FDOT_VG4_M4Z4Z_BtoH, FDOT_VG...
|
|
printTypedVectorList_0_b(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG2_M2ZZ_BtoH, FDOT_VG2...
|
|
printSVERegOp_b(MI, 5, O);
|
|
break;
|
|
case 48:
|
|
// FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16
|
|
SStream_concat0(O, ".h");
|
|
printVectorIndex_1(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16
|
|
SStream_concat0(O, ".2h");
|
|
return;
|
|
break;
|
|
case 50:
|
|
// INDEX_RI_B
|
|
printSImm_8(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 51:
|
|
// INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D
|
|
printSVERegOp_d(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// INSERT_MXIPZ_H_H, INSERT_MXIPZ_V_H
|
|
printSVERegOp_h(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q
|
|
printSVERegOp_q(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S
|
|
printSVERegOp_s(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// LD1B_2Z_STRIDED, LDNT1B_2Z_STRIDED
|
|
printRegWithShiftExtend_0_8_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 56:
|
|
// LD1B_2Z_STRIDED_IMM, LD1H_2Z_STRIDED_IMM, LDNT1B_2Z_STRIDED_IMM, LDNT1...
|
|
printImmScale_2(MI, 3, O);
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 57:
|
|
// LD1H_2Z_STRIDED, LDNT1H_2Z_STRIDED
|
|
printRegWithShiftExtend_0_16_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 58:
|
|
// LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX...
|
|
SStream_concat0(O, "/z, [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 59:
|
|
// LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL...
|
|
printOperand(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 60:
|
|
// LDG, ST2GPostIndex, ST2GPreIndex, STGPostIndex, STGPreIndex, STZ2GPost...
|
|
printImmScale_16(MI, 3, O);
|
|
break;
|
|
case 61:
|
|
// LDRAAindexed, LDRABindexed
|
|
printImmScale_8(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 62:
|
|
// LDRAAwriteback, LDRABwriteback
|
|
printImmScale_8(MI, 3, O);
|
|
SStream_concat0(O, "]!");
|
|
return;
|
|
break;
|
|
case 63:
|
|
// LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui
|
|
printUImm12Offset_1(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 64:
|
|
// LDRDui, LDRXui, PRFMui, STRDui, STRXui
|
|
printUImm12Offset_8(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 65:
|
|
// LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui
|
|
printUImm12Offset_2(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 66:
|
|
// LDRQui, STRQui
|
|
printUImm12Offset_16(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 67:
|
|
// LDRSWui, LDRSui, LDRWui, STRSui, STRWui
|
|
printUImm12Offset_4(MI, 2, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 68:
|
|
// LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI_B, LUTI2_ZTZI_S, LUTI4_S_...
|
|
printSVERegOp_0(MI, 2, O);
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 69:
|
|
// MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B
|
|
printSVERegOp_b(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp_b(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q
|
|
printMatrixIndex_1(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 71:
|
|
// MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZMXI_H_H, MOVA_2ZMXI_H_S, MOVA_2...
|
|
printImmRangeScale_2_1(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 72:
|
|
// MOVA_4ZMXI_H_B, MOVA_4ZMXI_H_D, MOVA_4ZMXI_H_H, MOVA_4ZMXI_H_S, MOVA_4...
|
|
printImmRangeScale_4_3(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 73:
|
|
// MOVA_MXI2Z_H_B, MOVA_MXI2Z_V_B, MOVA_MXI4Z_H_B, MOVA_MXI4Z_V_B
|
|
printTypedVectorList_0_b(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 74:
|
|
// MOVA_MXI2Z_H_D, MOVA_MXI2Z_V_D, MOVA_MXI4Z_H_D, MOVA_MXI4Z_V_D
|
|
printTypedVectorList_0_d(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 75:
|
|
// MOVA_MXI2Z_H_H, MOVA_MXI2Z_V_H, MOVA_MXI4Z_H_H, MOVA_MXI4Z_V_H
|
|
printTypedVectorList_0_h(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 76:
|
|
// MOVA_MXI2Z_H_S, MOVA_MXI2Z_V_S, MOVA_MXI4Z_H_S, MOVA_MXI4Z_V_S
|
|
printTypedVectorList_0_s(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 77:
|
|
// PRFB_D_PZI, PRFB_S_PZI
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 78:
|
|
// PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 79:
|
|
// SPLICE_ZPZZ_B
|
|
printTypedVectorList_0_b(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// SPLICE_ZPZZ_D
|
|
printTypedVectorList_0_d(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// SPLICE_ZPZZ_S
|
|
printTypedVectorList_0_s(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW...
|
|
printGPR64as32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX...
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 84:
|
|
// SYSLxt
|
|
printSysCROperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printSysCROperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 85:
|
|
// TBNZW, TBNZX, TBZW, TBZX
|
|
printAlignedLabel(MI, Address, 2, O);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S
|
|
printImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 7 bits for 93 unique commands.
|
|
switch ((Bits >> 49) & 127) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_CPA,...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
|
|
SStream_concat0(O, ".2d");
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
|
|
SStream_concat0(O, ".4s");
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BFDOTv8bf16, B...
|
|
SStream_concat0(O, ".8h");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ADDPT_shift, SUBPT_shift
|
|
printShifter(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFADD_ZP...
|
|
printSVERegOp_h(MI, 3, O);
|
|
break;
|
|
case 7:
|
|
// ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,...
|
|
SStream_concat0(O, ".16b");
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
|
|
SStream_concat0(O, ".2s");
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ADDPv4i16, ADDv4i16, BFDOTv4bf16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMH...
|
|
SStream_concat0(O, ".4h");
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
|
|
SStream_concat0(O, ".8b");
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64
|
|
printArithExtend(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ADD_VG2_M2Z2Z_D, ADD_VG4_M4Z4Z_D, FMLA_VG2_M2Z2Z_D, FMLA_VG4_M4Z4Z_D, ...
|
|
printTypedVectorList_0_d(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ADD_VG2_M2Z2Z_S, ADD_VG4_M4Z4Z_S, FMLA_VG2_M2Z2Z_S, FMLA_VG4_M4Z4Z_S, ...
|
|
printTypedVectorList_0_s(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ADD_VG2_M2ZZ_D, ADD_VG4_M4ZZ_D, FMLA_VG2_M2ZZI_D, FMLA_VG2_M2ZZ_D, FML...
|
|
printSVERegOp_d(MI, 5, O);
|
|
break;
|
|
case 15:
|
|
// ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_S, FMLA_VG2_M2ZZI_S, FMLA_VG2_M2ZZ_S, FML...
|
|
printSVERegOp_s(MI, 5, O);
|
|
break;
|
|
case 16:
|
|
// ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 17:
|
|
// ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP...
|
|
printSVERegOp_d(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// BCAX, EOR3, EXTv16i8
|
|
SStream_concat0(O, ".16b, ");
|
|
break;
|
|
case 19:
|
|
// BF16DOTlanev4bf16, BF16DOTlanev8bf16
|
|
SStream_concat0(O, ".2h");
|
|
printVectorIndex_1(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG4_M4Z4Z_HtoS, BFMLAL_VG2_M2Z2Z_HtoS, BFM...
|
|
printTypedVectorList_0_h(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFDOT...
|
|
printSVERegOp_h(MI, 5, O);
|
|
break;
|
|
case 22:
|
|
// BFDOT_ZZI, BFMLALB_ZZZI, BFMLALT_ZZZI, BFMLSLB_ZZZI_S, BFMLSLT_ZZZI_S,...
|
|
printVectorIndex_1(MI, 4, O);
|
|
break;
|
|
case 23:
|
|
// BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2...
|
|
SStream_concat0(O, ".h");
|
|
break;
|
|
case 24:
|
|
// BFMLA_ZPmZZ, BFMLS_ZPmZZ, FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, F...
|
|
printSVERegOp_h(MI, 4, O);
|
|
break;
|
|
case 25:
|
|
// CADD_ZZI_H, SQCADD_ZZI_H
|
|
printComplexRotationOp_180_90(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 27:
|
|
// CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H
|
|
printComplexRotationOp_90_0(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H
|
|
printImm(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// EXTv8i8
|
|
SStream_concat0(O, ".8b, ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H
|
|
printExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// FCADDv2f32, FCMLAv2f32
|
|
SStream_concat0(O, ".2s, ");
|
|
break;
|
|
case 32:
|
|
// FCADDv2f64, FCMLAv2f64, XAR
|
|
SStream_concat0(O, ".2d, ");
|
|
break;
|
|
case 33:
|
|
// FCADDv4f16, FCMLAv4f16
|
|
SStream_concat0(O, ".4h, ");
|
|
break;
|
|
case 34:
|
|
// FCADDv4f32, FCMLAv4f32, SM3SS1
|
|
SStream_concat0(O, ".4s, ");
|
|
break;
|
|
case 35:
|
|
// FCADDv8f16, FCMLAv8f16
|
|
SStream_concat0(O, ".8h, ");
|
|
break;
|
|
case 36:
|
|
// FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ...
|
|
SStream_concat0(O, ", #0.0");
|
|
return;
|
|
break;
|
|
case 37:
|
|
// FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in...
|
|
SStream_concat0(O, ".s");
|
|
break;
|
|
case 38:
|
|
// FDOT_VG2_M2ZZI_BtoH, FDOT_VG2_M2ZZI_BtoS, FDOT_VG4_M4ZZI_BtoH, FDOT_VG...
|
|
printVectorIndex_1(MI, 6, O);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// FDOTlanev16f8, FDOTlanev8f8, SDOTlanev16i8, SDOTlanev8i8, SUDOTlanev16...
|
|
SStream_concat0(O, ".4b");
|
|
printVectorIndex_1(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// FDOTlanev4f16, FDOTlanev8f16
|
|
SStream_concat0(O, ".2b");
|
|
printVectorIndex_1(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 41:
|
|
// FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H
|
|
printExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// FMLALBlanev8f16, FMLALLBBlanev4f32, FMLALLBTlanev4f32, FMLALLTBlanev4f...
|
|
SStream_concat0(O, ".b");
|
|
printVectorIndex_1(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind...
|
|
SStream_concat0(O, ".d");
|
|
break;
|
|
case 44:
|
|
// FMUL_ZPmI_H
|
|
printExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// FMUL_ZZZI_D, FMUL_ZZZI_S, MUL_ZZZI_D, MUL_ZZZI_S, SMULLB_ZZZI_D, SMULL...
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 46:
|
|
// GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ...
|
|
printRegWithShiftExtend_0_8_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 47:
|
|
// GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R...
|
|
printRegWithShiftExtend_1_8_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 48:
|
|
// GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R...
|
|
printRegWithShiftExtend_0_8_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 49:
|
|
// GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT...
|
|
printRegWithShiftExtend_1_8_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 50:
|
|
// GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT...
|
|
printRegWithShiftExtend_0_8_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 51:
|
|
// GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, SST1D_IMM
|
|
printImmScale_8(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 52:
|
|
// GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED
|
|
printRegWithShiftExtend_0_64_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 53:
|
|
// GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED
|
|
printRegWithShiftExtend_1_64_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 54:
|
|
// GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED
|
|
printRegWithShiftExtend_0_64_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 55:
|
|
// GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE...
|
|
printImmScale_2(MI, 3, O);
|
|
break;
|
|
case 56:
|
|
// GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF...
|
|
printRegWithShiftExtend_0_16_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 57:
|
|
// GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC...
|
|
printRegWithShiftExtend_1_16_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 58:
|
|
// GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC...
|
|
printRegWithShiftExtend_0_16_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 59:
|
|
// GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC...
|
|
printRegWithShiftExtend_1_16_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 60:
|
|
// GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC...
|
|
printRegWithShiftExtend_0_16_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 61:
|
|
// GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE...
|
|
printImmScale_4(MI, 3, O);
|
|
break;
|
|
case 62:
|
|
// GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD...
|
|
printRegWithShiftExtend_0_32_x_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 63:
|
|
// GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S...
|
|
printRegWithShiftExtend_1_32_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 64:
|
|
// GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S...
|
|
printRegWithShiftExtend_0_32_w_d(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 65:
|
|
// GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED
|
|
printRegWithShiftExtend_1_32_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 66:
|
|
// GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED
|
|
printRegWithShiftExtend_0_32_w_s(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 67:
|
|
// LD1B, LD1B_2Z, LD1B_4Z, LD1B_4Z_STRIDED, LD1B_D, LD1B_H, LD1B_S, LD1RO...
|
|
printRegWithShiftExtend_0_8_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 68:
|
|
// LD1D, LD1D_2Z, LD1D_2Z_STRIDED, LD1D_4Z, LD1D_4Z_STRIDED, LD1D_Q, LD1R...
|
|
printRegWithShiftExtend_0_64_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 69:
|
|
// LD1H, LD1H_2Z, LD1H_4Z, LD1H_4Z_STRIDED, LD1H_D, LD1H_S, LD1RO_H, LD1R...
|
|
printRegWithShiftExtend_0_16_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 70:
|
|
// LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM
|
|
printImmScale_32(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 71:
|
|
// LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_2Z, LD1W_2Z_STRIDED, LD1W_4Z, LD...
|
|
printRegWithShiftExtend_0_32_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 72:
|
|
// LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM
|
|
printImmScale_16(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 73:
|
|
// LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B
|
|
printRegWithShiftExtend_0_8_x_0(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 74:
|
|
// LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D
|
|
printRegWithShiftExtend_0_64_x_0(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 75:
|
|
// LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H
|
|
printRegWithShiftExtend_0_16_x_0(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 76:
|
|
// LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q
|
|
printRegWithShiftExtend_0_128_x_0(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 77:
|
|
// LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S
|
|
printRegWithShiftExtend_0_32_x_0(MI, 5, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 78:
|
|
// LD2Q, LD3Q, LD4Q, ST2Q, ST3Q, ST4Q
|
|
printRegWithShiftExtend_0_128_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 79:
|
|
// LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3Q_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ...
|
|
printImmScale_3(MI, 3, O);
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 80:
|
|
// LDIAPPWpost
|
|
SStream_concat0(O, "], #8");
|
|
return;
|
|
break;
|
|
case 81:
|
|
// LDIAPPXpost
|
|
SStream_concat0(O, "], #16");
|
|
return;
|
|
break;
|
|
case 82:
|
|
// LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,...
|
|
SStream_concat0(O, "], ");
|
|
break;
|
|
case 83:
|
|
// LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR...
|
|
SStream_concat0(O, "]!");
|
|
return;
|
|
break;
|
|
case 84:
|
|
// LDR_PXI, LDR_ZXI, STR_PXI, STR_ZXI
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 85:
|
|
// PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S
|
|
SStream_concat1(O, '[');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex_1(MI, 4, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 86:
|
|
// SEL_VG2_2ZC2Z2Z_B, SEL_VG4_4ZC4Z4Z_B
|
|
printTypedVectorList_0_b(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 87:
|
|
// SEL_VG2_2ZC2Z2Z_D, SEL_VG4_4ZC4Z4Z_D
|
|
printTypedVectorList_0_d(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 88:
|
|
// SEL_VG2_2ZC2Z2Z_H, SEL_VG4_4ZC4Z4Z_H
|
|
printTypedVectorList_0_h(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 89:
|
|
// SEL_VG2_2ZC2Z2Z_S, SEL_VG4_4ZC4Z4Z_S
|
|
printTypedVectorList_0_s(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 90:
|
|
// STILPWpre
|
|
SStream_concat0(O, ", #-8]!");
|
|
return;
|
|
break;
|
|
case 91:
|
|
// STILPXpre
|
|
SStream_concat0(O, ", #-16]!");
|
|
return;
|
|
break;
|
|
case 92:
|
|
// STLXPW, STLXPX, STXPW, STXPX
|
|
SStream_concat0(O, ", [");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 6 encoded into 6 bits for 44 unique commands.
|
|
switch ((Bits >> 56) & 63) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A...
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_...
|
|
printSVERegOp_b(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDP_ZPmZ_D, ADD_ZPmZ_CPA, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WI...
|
|
printSVERegOp_d(MI, 3, O);
|
|
break;
|
|
case 3:
|
|
// ADDP_ZPmZ_H, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_D, ADD_VG4_M...
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ...
|
|
printSVERegOp_s(MI, 3, O);
|
|
break;
|
|
case 5:
|
|
// BCAX, EOR3, SM3SS1
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 6:
|
|
// BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFMLAL_VG2_M2ZZI_HtoS, BFM...
|
|
printVectorIndex_1(MI, 6, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv...
|
|
printVectorIndex_1(MI, 4, O);
|
|
break;
|
|
case 8:
|
|
// BFMWri, BFMXri
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16...
|
|
printComplexRotationOp_180_90(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr...
|
|
printCondCode(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H
|
|
printComplexRotationOp_90_0(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16...
|
|
printComplexRotationOp_90_0(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H
|
|
printSVERegOp_h(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ...
|
|
printImm(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU...
|
|
printExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,...
|
|
printSVERegOp_d(MI, 4, O);
|
|
break;
|
|
case 18:
|
|
// FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,...
|
|
printSVERegOp_s(MI, 4, O);
|
|
break;
|
|
case 19:
|
|
// FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,...
|
|
printExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32...
|
|
printVectorIndex_1(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// FMUL_ZPmI_D, FMUL_ZPmI_S
|
|
printExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL...
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 23:
|
|
// LD1B_2Z_IMM, LD1B_4Z_IMM, LD1B_4Z_STRIDED_IMM, LD1B_D_IMM, LD1B_H_IMM,...
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 24:
|
|
// LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi
|
|
printImmScale_8(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 25:
|
|
// LDNPQi, LDPQi, STGPi, STNPQi, STPQi
|
|
printImmScale_16(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 26:
|
|
// LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi
|
|
printImmScale_4(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 27:
|
|
// LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP...
|
|
printImmScale_8(MI, 4, O);
|
|
break;
|
|
case 28:
|
|
// LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre
|
|
printImmScale_16(MI, 4, O);
|
|
break;
|
|
case 29:
|
|
// LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S...
|
|
printImmScale_4(MI, 4, O);
|
|
break;
|
|
case 30:
|
|
// LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW
|
|
printMemExtend_w_8(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 31:
|
|
// LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX
|
|
printMemExtend_x_8(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 32:
|
|
// LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW
|
|
printMemExtend_w_64(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 33:
|
|
// LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX
|
|
printMemExtend_x_64(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 34:
|
|
// LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW
|
|
printMemExtend_w_16(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 35:
|
|
// LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX
|
|
printMemExtend_x_16(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 36:
|
|
// LDRQroW, STRQroW
|
|
printMemExtend_w_128(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 37:
|
|
// LDRQroX, STRQroX
|
|
printMemExtend_x_128(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 38:
|
|
// LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW
|
|
printMemExtend_w_32(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 39:
|
|
// LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX
|
|
printMemExtend_x_32(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 40:
|
|
// ST1B_2Z_STRIDED, STNT1B_2Z_STRIDED
|
|
printRegWithShiftExtend_0_8_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 41:
|
|
// ST1B_2Z_STRIDED_IMM, ST1H_2Z_STRIDED_IMM, STNT1B_2Z_STRIDED_IMM, STNT1...
|
|
printImmScale_2(MI, 3, O);
|
|
SStream_concat0(O, ", mul vl]");
|
|
return;
|
|
break;
|
|
case 42:
|
|
// ST1H_2Z_STRIDED, STNT1H_2Z_STRIDED
|
|
printRegWithShiftExtend_0_16_x_0(MI, 3, O);
|
|
SStream_concat1(O, ']');
|
|
return;
|
|
break;
|
|
case 43:
|
|
// WHILEGE_CXX_B, WHILEGE_CXX_D, WHILEGE_CXX_H, WHILEGE_CXX_S, WHILEGT_CX...
|
|
printSVEVecLenSpecifier(MI, 3, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default: CS_ASSERT_RET(0 && "Unexpected opcode.");
|
|
case AArch64_ADDP_ZPmZ_D:
|
|
case AArch64_ADDP_ZPmZ_S:
|
|
case AArch64_ADD_ZPmZ_CPA:
|
|
case AArch64_ADD_ZPmZ_D:
|
|
case AArch64_ADD_ZPmZ_S:
|
|
case AArch64_AND_ZPmZ_D:
|
|
case AArch64_AND_ZPmZ_S:
|
|
case AArch64_ASRR_ZPmZ_D:
|
|
case AArch64_ASRR_ZPmZ_S:
|
|
case AArch64_ASR_WIDE_ZPmZ_B:
|
|
case AArch64_ASR_WIDE_ZPmZ_S:
|
|
case AArch64_ASR_ZPmZ_D:
|
|
case AArch64_ASR_ZPmZ_S:
|
|
case AArch64_BCAX_ZZZZ:
|
|
case AArch64_BFMLALBIdx:
|
|
case AArch64_BFMLALTIdx:
|
|
case AArch64_BIC_ZPmZ_D:
|
|
case AArch64_BIC_ZPmZ_S:
|
|
case AArch64_BSL1N_ZZZZ:
|
|
case AArch64_BSL2N_ZZZZ:
|
|
case AArch64_BSL_ZZZZ:
|
|
case AArch64_CLASTA_RPZ_D:
|
|
case AArch64_CLASTA_RPZ_S:
|
|
case AArch64_CLASTA_VPZ_D:
|
|
case AArch64_CLASTA_VPZ_S:
|
|
case AArch64_CLASTA_ZPZ_D:
|
|
case AArch64_CLASTA_ZPZ_S:
|
|
case AArch64_CLASTB_RPZ_D:
|
|
case AArch64_CLASTB_RPZ_S:
|
|
case AArch64_CLASTB_VPZ_D:
|
|
case AArch64_CLASTB_VPZ_S:
|
|
case AArch64_CLASTB_ZPZ_D:
|
|
case AArch64_CLASTB_ZPZ_S:
|
|
case AArch64_CMPEQ_PPzZZ_D:
|
|
case AArch64_CMPEQ_PPzZZ_S:
|
|
case AArch64_CMPEQ_WIDE_PPzZZ_B:
|
|
case AArch64_CMPEQ_WIDE_PPzZZ_S:
|
|
case AArch64_CMPGE_PPzZZ_D:
|
|
case AArch64_CMPGE_PPzZZ_S:
|
|
case AArch64_CMPGE_WIDE_PPzZZ_B:
|
|
case AArch64_CMPGE_WIDE_PPzZZ_S:
|
|
case AArch64_CMPGT_PPzZZ_D:
|
|
case AArch64_CMPGT_PPzZZ_S:
|
|
case AArch64_CMPGT_WIDE_PPzZZ_B:
|
|
case AArch64_CMPGT_WIDE_PPzZZ_S:
|
|
case AArch64_CMPHI_PPzZZ_D:
|
|
case AArch64_CMPHI_PPzZZ_S:
|
|
case AArch64_CMPHI_WIDE_PPzZZ_B:
|
|
case AArch64_CMPHI_WIDE_PPzZZ_S:
|
|
case AArch64_CMPHS_PPzZZ_D:
|
|
case AArch64_CMPHS_PPzZZ_S:
|
|
case AArch64_CMPHS_WIDE_PPzZZ_B:
|
|
case AArch64_CMPHS_WIDE_PPzZZ_S:
|
|
case AArch64_CMPLE_WIDE_PPzZZ_B:
|
|
case AArch64_CMPLE_WIDE_PPzZZ_S:
|
|
case AArch64_CMPLO_WIDE_PPzZZ_B:
|
|
case AArch64_CMPLO_WIDE_PPzZZ_S:
|
|
case AArch64_CMPLS_WIDE_PPzZZ_B:
|
|
case AArch64_CMPLS_WIDE_PPzZZ_S:
|
|
case AArch64_CMPLT_WIDE_PPzZZ_B:
|
|
case AArch64_CMPLT_WIDE_PPzZZ_S:
|
|
case AArch64_CMPNE_PPzZZ_D:
|
|
case AArch64_CMPNE_PPzZZ_S:
|
|
case AArch64_CMPNE_WIDE_PPzZZ_B:
|
|
case AArch64_CMPNE_WIDE_PPzZZ_S:
|
|
case AArch64_EOR3_ZZZZ:
|
|
case AArch64_EOR_ZPmZ_D:
|
|
case AArch64_EOR_ZPmZ_S:
|
|
case AArch64_FABD_ZPmZ_D:
|
|
case AArch64_FABD_ZPmZ_S:
|
|
case AArch64_FACGE_PPzZZ_D:
|
|
case AArch64_FACGE_PPzZZ_S:
|
|
case AArch64_FACGT_PPzZZ_D:
|
|
case AArch64_FACGT_PPzZZ_S:
|
|
case AArch64_FADDP_ZPmZZ_D:
|
|
case AArch64_FADDP_ZPmZZ_S:
|
|
case AArch64_FADD_ZPmZ_D:
|
|
case AArch64_FADD_ZPmZ_S:
|
|
case AArch64_FAMAX_ZPmZ_D:
|
|
case AArch64_FAMAX_ZPmZ_S:
|
|
case AArch64_FAMIN_ZPmZ_D:
|
|
case AArch64_FAMIN_ZPmZ_S:
|
|
case AArch64_FCMEQ_PPzZZ_D:
|
|
case AArch64_FCMEQ_PPzZZ_S:
|
|
case AArch64_FCMGE_PPzZZ_D:
|
|
case AArch64_FCMGE_PPzZZ_S:
|
|
case AArch64_FCMGT_PPzZZ_D:
|
|
case AArch64_FCMGT_PPzZZ_S:
|
|
case AArch64_FCMNE_PPzZZ_D:
|
|
case AArch64_FCMNE_PPzZZ_S:
|
|
case AArch64_FCMUO_PPzZZ_D:
|
|
case AArch64_FCMUO_PPzZZ_S:
|
|
case AArch64_FDIVR_ZPmZ_D:
|
|
case AArch64_FDIVR_ZPmZ_S:
|
|
case AArch64_FDIV_ZPmZ_D:
|
|
case AArch64_FDIV_ZPmZ_S:
|
|
case AArch64_FMAD_ZPmZZ_D:
|
|
case AArch64_FMAD_ZPmZZ_S:
|
|
case AArch64_FMAXNMP_ZPmZZ_D:
|
|
case AArch64_FMAXNMP_ZPmZZ_S:
|
|
case AArch64_FMAXNM_ZPmZ_D:
|
|
case AArch64_FMAXNM_ZPmZ_S:
|
|
case AArch64_FMAXP_ZPmZZ_D:
|
|
case AArch64_FMAXP_ZPmZZ_S:
|
|
case AArch64_FMAX_ZPmZ_D:
|
|
case AArch64_FMAX_ZPmZ_S:
|
|
case AArch64_FMINNMP_ZPmZZ_D:
|
|
case AArch64_FMINNMP_ZPmZZ_S:
|
|
case AArch64_FMINNM_ZPmZ_D:
|
|
case AArch64_FMINNM_ZPmZ_S:
|
|
case AArch64_FMINP_ZPmZZ_D:
|
|
case AArch64_FMINP_ZPmZZ_S:
|
|
case AArch64_FMIN_ZPmZ_D:
|
|
case AArch64_FMIN_ZPmZ_S:
|
|
case AArch64_FMLAL2lanev8f16:
|
|
case AArch64_FMLALlanev8f16:
|
|
case AArch64_FMLA_ZPmZZ_D:
|
|
case AArch64_FMLA_ZPmZZ_S:
|
|
case AArch64_FMLAv1i16_indexed:
|
|
case AArch64_FMLAv1i32_indexed:
|
|
case AArch64_FMLAv1i64_indexed:
|
|
case AArch64_FMLAv2i32_indexed:
|
|
case AArch64_FMLAv2i64_indexed:
|
|
case AArch64_FMLAv4i16_indexed:
|
|
case AArch64_FMLAv4i32_indexed:
|
|
case AArch64_FMLAv8i16_indexed:
|
|
case AArch64_FMLSL2lanev8f16:
|
|
case AArch64_FMLSLlanev8f16:
|
|
case AArch64_FMLS_ZPmZZ_D:
|
|
case AArch64_FMLS_ZPmZZ_S:
|
|
case AArch64_FMLSv1i16_indexed:
|
|
case AArch64_FMLSv1i32_indexed:
|
|
case AArch64_FMLSv1i64_indexed:
|
|
case AArch64_FMLSv2i32_indexed:
|
|
case AArch64_FMLSv2i64_indexed:
|
|
case AArch64_FMLSv4i16_indexed:
|
|
case AArch64_FMLSv4i32_indexed:
|
|
case AArch64_FMLSv8i16_indexed:
|
|
case AArch64_FMSB_ZPmZZ_D:
|
|
case AArch64_FMSB_ZPmZZ_S:
|
|
case AArch64_FMULX_ZPmZ_D:
|
|
case AArch64_FMULX_ZPmZ_S:
|
|
case AArch64_FMUL_ZPmZ_D:
|
|
case AArch64_FMUL_ZPmZ_S:
|
|
case AArch64_FNMAD_ZPmZZ_D:
|
|
case AArch64_FNMAD_ZPmZZ_S:
|
|
case AArch64_FNMLA_ZPmZZ_D:
|
|
case AArch64_FNMLA_ZPmZZ_S:
|
|
case AArch64_FNMLS_ZPmZZ_D:
|
|
case AArch64_FNMLS_ZPmZZ_S:
|
|
case AArch64_FNMSB_ZPmZZ_D:
|
|
case AArch64_FNMSB_ZPmZZ_S:
|
|
case AArch64_FSCALE_ZPmZ_D:
|
|
case AArch64_FSCALE_ZPmZ_S:
|
|
case AArch64_FSUBR_ZPmZ_D:
|
|
case AArch64_FSUBR_ZPmZ_S:
|
|
case AArch64_FSUB_ZPmZ_D:
|
|
case AArch64_FSUB_ZPmZ_S:
|
|
case AArch64_HISTCNT_ZPzZZ_D:
|
|
case AArch64_HISTCNT_ZPzZZ_S:
|
|
case AArch64_LDPDpost:
|
|
case AArch64_LDPQpost:
|
|
case AArch64_LDPSWpost:
|
|
case AArch64_LDPSpost:
|
|
case AArch64_LDPWpost:
|
|
case AArch64_LDPXpost:
|
|
case AArch64_LSLR_ZPmZ_D:
|
|
case AArch64_LSLR_ZPmZ_S:
|
|
case AArch64_LSL_WIDE_ZPmZ_B:
|
|
case AArch64_LSL_WIDE_ZPmZ_S:
|
|
case AArch64_LSL_ZPmZ_D:
|
|
case AArch64_LSL_ZPmZ_S:
|
|
case AArch64_LSRR_ZPmZ_D:
|
|
case AArch64_LSRR_ZPmZ_S:
|
|
case AArch64_LSR_WIDE_ZPmZ_B:
|
|
case AArch64_LSR_WIDE_ZPmZ_S:
|
|
case AArch64_LSR_ZPmZ_D:
|
|
case AArch64_LSR_ZPmZ_S:
|
|
case AArch64_MAD_ZPmZZ_D:
|
|
case AArch64_MAD_ZPmZZ_S:
|
|
case AArch64_MLA_ZPmZZ_D:
|
|
case AArch64_MLA_ZPmZZ_S:
|
|
case AArch64_MLAv2i32_indexed:
|
|
case AArch64_MLAv4i16_indexed:
|
|
case AArch64_MLAv4i32_indexed:
|
|
case AArch64_MLAv8i16_indexed:
|
|
case AArch64_MLS_ZPmZZ_D:
|
|
case AArch64_MLS_ZPmZZ_S:
|
|
case AArch64_MLSv2i32_indexed:
|
|
case AArch64_MLSv4i16_indexed:
|
|
case AArch64_MLSv4i32_indexed:
|
|
case AArch64_MLSv8i16_indexed:
|
|
case AArch64_MSB_ZPmZZ_D:
|
|
case AArch64_MSB_ZPmZZ_S:
|
|
case AArch64_MUL_ZPmZ_D:
|
|
case AArch64_MUL_ZPmZ_S:
|
|
case AArch64_NBSL_ZZZZ:
|
|
case AArch64_ORR_ZPmZ_D:
|
|
case AArch64_ORR_ZPmZ_S:
|
|
case AArch64_SABD_ZPmZ_D:
|
|
case AArch64_SABD_ZPmZ_S:
|
|
case AArch64_SDIVR_ZPmZ_D:
|
|
case AArch64_SDIVR_ZPmZ_S:
|
|
case AArch64_SDIV_ZPmZ_D:
|
|
case AArch64_SDIV_ZPmZ_S:
|
|
case AArch64_SEL_ZPZZ_D:
|
|
case AArch64_SEL_ZPZZ_S:
|
|
case AArch64_SHADD_ZPmZ_D:
|
|
case AArch64_SHADD_ZPmZ_S:
|
|
case AArch64_SHSUBR_ZPmZ_D:
|
|
case AArch64_SHSUBR_ZPmZ_S:
|
|
case AArch64_SHSUB_ZPmZ_D:
|
|
case AArch64_SHSUB_ZPmZ_S:
|
|
case AArch64_SM3TT1A:
|
|
case AArch64_SM3TT1B:
|
|
case AArch64_SM3TT2A:
|
|
case AArch64_SM3TT2B:
|
|
case AArch64_SMAXP_ZPmZ_D:
|
|
case AArch64_SMAXP_ZPmZ_S:
|
|
case AArch64_SMAX_ZPmZ_D:
|
|
case AArch64_SMAX_ZPmZ_S:
|
|
case AArch64_SMINP_ZPmZ_D:
|
|
case AArch64_SMINP_ZPmZ_S:
|
|
case AArch64_SMIN_ZPmZ_D:
|
|
case AArch64_SMIN_ZPmZ_S:
|
|
case AArch64_SMLALv2i32_indexed:
|
|
case AArch64_SMLALv4i16_indexed:
|
|
case AArch64_SMLALv4i32_indexed:
|
|
case AArch64_SMLALv8i16_indexed:
|
|
case AArch64_SMLSLv2i32_indexed:
|
|
case AArch64_SMLSLv4i16_indexed:
|
|
case AArch64_SMLSLv4i32_indexed:
|
|
case AArch64_SMLSLv8i16_indexed:
|
|
case AArch64_SMULH_ZPmZ_D:
|
|
case AArch64_SMULH_ZPmZ_S:
|
|
case AArch64_SPLICE_ZPZ_D:
|
|
case AArch64_SPLICE_ZPZ_S:
|
|
case AArch64_SQADD_ZPmZ_D:
|
|
case AArch64_SQADD_ZPmZ_S:
|
|
case AArch64_SQDMLALv1i32_indexed:
|
|
case AArch64_SQDMLALv1i64_indexed:
|
|
case AArch64_SQDMLALv2i32_indexed:
|
|
case AArch64_SQDMLALv4i16_indexed:
|
|
case AArch64_SQDMLALv4i32_indexed:
|
|
case AArch64_SQDMLALv8i16_indexed:
|
|
case AArch64_SQDMLSLv1i32_indexed:
|
|
case AArch64_SQDMLSLv1i64_indexed:
|
|
case AArch64_SQDMLSLv2i32_indexed:
|
|
case AArch64_SQDMLSLv4i16_indexed:
|
|
case AArch64_SQDMLSLv4i32_indexed:
|
|
case AArch64_SQDMLSLv8i16_indexed:
|
|
case AArch64_SQRDMLAHv1i16_indexed:
|
|
case AArch64_SQRDMLAHv1i32_indexed:
|
|
case AArch64_SQRDMLAHv2i32_indexed:
|
|
case AArch64_SQRDMLAHv4i16_indexed:
|
|
case AArch64_SQRDMLAHv4i32_indexed:
|
|
case AArch64_SQRDMLAHv8i16_indexed:
|
|
case AArch64_SQRDMLSHv1i16_indexed:
|
|
case AArch64_SQRDMLSHv1i32_indexed:
|
|
case AArch64_SQRDMLSHv2i32_indexed:
|
|
case AArch64_SQRDMLSHv4i16_indexed:
|
|
case AArch64_SQRDMLSHv4i32_indexed:
|
|
case AArch64_SQRDMLSHv8i16_indexed:
|
|
case AArch64_SQRSHLR_ZPmZ_D:
|
|
case AArch64_SQRSHLR_ZPmZ_S:
|
|
case AArch64_SQRSHL_ZPmZ_D:
|
|
case AArch64_SQRSHL_ZPmZ_S:
|
|
case AArch64_SQSHLR_ZPmZ_D:
|
|
case AArch64_SQSHLR_ZPmZ_S:
|
|
case AArch64_SQSHL_ZPmZ_D:
|
|
case AArch64_SQSHL_ZPmZ_S:
|
|
case AArch64_SQSUBR_ZPmZ_D:
|
|
case AArch64_SQSUBR_ZPmZ_S:
|
|
case AArch64_SQSUB_ZPmZ_D:
|
|
case AArch64_SQSUB_ZPmZ_S:
|
|
case AArch64_SRHADD_ZPmZ_D:
|
|
case AArch64_SRHADD_ZPmZ_S:
|
|
case AArch64_SRSHLR_ZPmZ_D:
|
|
case AArch64_SRSHLR_ZPmZ_S:
|
|
case AArch64_SRSHL_ZPmZ_D:
|
|
case AArch64_SRSHL_ZPmZ_S:
|
|
case AArch64_STGPpost:
|
|
case AArch64_STPDpost:
|
|
case AArch64_STPQpost:
|
|
case AArch64_STPSpost:
|
|
case AArch64_STPWpost:
|
|
case AArch64_STPXpost:
|
|
case AArch64_SUBR_ZPmZ_D:
|
|
case AArch64_SUBR_ZPmZ_S:
|
|
case AArch64_SUB_ZPmZ_CPA:
|
|
case AArch64_SUB_ZPmZ_D:
|
|
case AArch64_SUB_ZPmZ_S:
|
|
case AArch64_SUQADD_ZPmZ_D:
|
|
case AArch64_SUQADD_ZPmZ_S:
|
|
case AArch64_UABD_ZPmZ_D:
|
|
case AArch64_UABD_ZPmZ_S:
|
|
case AArch64_UDIVR_ZPmZ_D:
|
|
case AArch64_UDIVR_ZPmZ_S:
|
|
case AArch64_UDIV_ZPmZ_D:
|
|
case AArch64_UDIV_ZPmZ_S:
|
|
case AArch64_UHADD_ZPmZ_D:
|
|
case AArch64_UHADD_ZPmZ_S:
|
|
case AArch64_UHSUBR_ZPmZ_D:
|
|
case AArch64_UHSUBR_ZPmZ_S:
|
|
case AArch64_UHSUB_ZPmZ_D:
|
|
case AArch64_UHSUB_ZPmZ_S:
|
|
case AArch64_UMAXP_ZPmZ_D:
|
|
case AArch64_UMAXP_ZPmZ_S:
|
|
case AArch64_UMAX_ZPmZ_D:
|
|
case AArch64_UMAX_ZPmZ_S:
|
|
case AArch64_UMINP_ZPmZ_D:
|
|
case AArch64_UMINP_ZPmZ_S:
|
|
case AArch64_UMIN_ZPmZ_D:
|
|
case AArch64_UMIN_ZPmZ_S:
|
|
case AArch64_UMLALv2i32_indexed:
|
|
case AArch64_UMLALv4i16_indexed:
|
|
case AArch64_UMLALv4i32_indexed:
|
|
case AArch64_UMLALv8i16_indexed:
|
|
case AArch64_UMLSLv2i32_indexed:
|
|
case AArch64_UMLSLv4i16_indexed:
|
|
case AArch64_UMLSLv4i32_indexed:
|
|
case AArch64_UMLSLv8i16_indexed:
|
|
case AArch64_UMULH_ZPmZ_D:
|
|
case AArch64_UMULH_ZPmZ_S:
|
|
case AArch64_UQADD_ZPmZ_D:
|
|
case AArch64_UQADD_ZPmZ_S:
|
|
case AArch64_UQRSHLR_ZPmZ_D:
|
|
case AArch64_UQRSHLR_ZPmZ_S:
|
|
case AArch64_UQRSHL_ZPmZ_D:
|
|
case AArch64_UQRSHL_ZPmZ_S:
|
|
case AArch64_UQSHLR_ZPmZ_D:
|
|
case AArch64_UQSHLR_ZPmZ_S:
|
|
case AArch64_UQSHL_ZPmZ_D:
|
|
case AArch64_UQSHL_ZPmZ_S:
|
|
case AArch64_UQSUBR_ZPmZ_D:
|
|
case AArch64_UQSUBR_ZPmZ_S:
|
|
case AArch64_UQSUB_ZPmZ_D:
|
|
case AArch64_UQSUB_ZPmZ_S:
|
|
case AArch64_URHADD_ZPmZ_D:
|
|
case AArch64_URHADD_ZPmZ_S:
|
|
case AArch64_URSHLR_ZPmZ_D:
|
|
case AArch64_URSHLR_ZPmZ_S:
|
|
case AArch64_URSHL_ZPmZ_D:
|
|
case AArch64_URSHL_ZPmZ_S:
|
|
case AArch64_USQADD_ZPmZ_D:
|
|
case AArch64_USQADD_ZPmZ_S:
|
|
return;
|
|
break;
|
|
case AArch64_BCAX:
|
|
case AArch64_CDOT_ZZZI_D:
|
|
case AArch64_CMLA_ZZZI_S:
|
|
case AArch64_EOR3:
|
|
case AArch64_FCADD_ZPmZ_H:
|
|
case AArch64_FCMLA_ZPmZZ_H:
|
|
case AArch64_FCMLA_ZZZI_S:
|
|
case AArch64_LDPDpre:
|
|
case AArch64_LDPQpre:
|
|
case AArch64_LDPSWpre:
|
|
case AArch64_LDPSpre:
|
|
case AArch64_LDPWpre:
|
|
case AArch64_LDPXpre:
|
|
case AArch64_SM3SS1:
|
|
case AArch64_SQRDCMLAH_ZZZI_S:
|
|
case AArch64_STGPpre:
|
|
case AArch64_STPDpre:
|
|
case AArch64_STPQpre:
|
|
case AArch64_STPSpre:
|
|
case AArch64_STPWpre:
|
|
case AArch64_STPXpre:
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default: CS_ASSERT_RET(0 && "Unexpected opcode.");
|
|
case AArch64_BCAX:
|
|
case AArch64_EOR3:
|
|
SStream_concat0(O, ".16b");
|
|
break;
|
|
case AArch64_CDOT_ZZZI_D:
|
|
case AArch64_CMLA_ZZZI_S:
|
|
case AArch64_FCMLA_ZPmZZ_H:
|
|
case AArch64_FCMLA_ZZZI_S:
|
|
case AArch64_SQRDCMLAH_ZZZI_S:
|
|
printComplexRotationOp_90_0(MI, 5, O);
|
|
break;
|
|
case AArch64_FCADD_ZPmZ_H:
|
|
printComplexRotationOp_180_90(MI, 4, O);
|
|
break;
|
|
case AArch64_LDPDpre:
|
|
case AArch64_LDPQpre:
|
|
case AArch64_LDPSWpre:
|
|
case AArch64_LDPSpre:
|
|
case AArch64_LDPWpre:
|
|
case AArch64_LDPXpre:
|
|
case AArch64_STGPpre:
|
|
case AArch64_STPDpre:
|
|
case AArch64_STPQpre:
|
|
case AArch64_STPSpre:
|
|
case AArch64_STPWpre:
|
|
case AArch64_STPXpre:
|
|
SStream_concat0(O, "]!");
|
|
break;
|
|
case AArch64_SM3SS1:
|
|
SStream_concat0(O, ".4s");
|
|
break;
|
|
}
|
|
return;
|
|
break;
|
|
case AArch64_FCADD_ZPmZ_D:
|
|
case AArch64_FCADD_ZPmZ_S:
|
|
case AArch64_FCMLA_ZPmZZ_D:
|
|
case AArch64_FCMLA_ZPmZZ_S:
|
|
case AArch64_FCMLAv4f16_indexed:
|
|
case AArch64_FCMLAv4f32_indexed:
|
|
case AArch64_FCMLAv8f16_indexed:
|
|
SStream_concat0(O, ", ");
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default: CS_ASSERT_RET(0 && "Unexpected opcode.");
|
|
case AArch64_FCADD_ZPmZ_D:
|
|
case AArch64_FCADD_ZPmZ_S:
|
|
printComplexRotationOp_180_90(MI, 4, O);
|
|
break;
|
|
case AArch64_FCMLA_ZPmZZ_D:
|
|
case AArch64_FCMLA_ZPmZZ_S:
|
|
case AArch64_FCMLAv4f16_indexed:
|
|
case AArch64_FCMLAv4f32_indexed:
|
|
case AArch64_FCMLAv8f16_indexed:
|
|
printComplexRotationOp_90_0(MI, 5, O);
|
|
break;
|
|
}
|
|
return;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
static const char *
|
|
getRegisterName(unsigned RegNo, unsigned AltIdx) {
|
|
#ifndef CAPSTONE_DIET
|
|
CS_ASSERT_RET_VAL(RegNo && RegNo < 703 && "Invalid register number!", NULL);
|
|
|
|
static const char AsmStrsNoRegAltName[] = {
|
|
/* 0 */ "D7_D8_D9_D10\0"
|
|
/* 13 */ "P9_P10\0"
|
|
/* 20 */ "Q7_Q8_Q9_Q10\0"
|
|
/* 33 */ "Z2_Z10\0"
|
|
/* 40 */ "Z7_Z8_Z9_Z10\0"
|
|
/* 53 */ "b10\0"
|
|
/* 57 */ "d10\0"
|
|
/* 61 */ "h10\0"
|
|
/* 65 */ "pn10\0"
|
|
/* 70 */ "p10\0"
|
|
/* 74 */ "q10\0"
|
|
/* 78 */ "s10\0"
|
|
/* 82 */ "w10\0"
|
|
/* 86 */ "x10\0"
|
|
/* 90 */ "z10\0"
|
|
/* 94 */ "D17_D18_D19_D20\0"
|
|
/* 110 */ "Q17_Q18_Q19_Q20\0"
|
|
/* 126 */ "Z17_Z18_Z19_Z20\0"
|
|
/* 142 */ "b20\0"
|
|
/* 146 */ "d20\0"
|
|
/* 150 */ "h20\0"
|
|
/* 154 */ "q20\0"
|
|
/* 158 */ "s20\0"
|
|
/* 162 */ "w20\0"
|
|
/* 166 */ "x20\0"
|
|
/* 170 */ "z20\0"
|
|
/* 174 */ "D27_D28_D29_D30\0"
|
|
/* 190 */ "Q27_Q28_Q29_Q30\0"
|
|
/* 206 */ "Z22_Z30\0"
|
|
/* 214 */ "Z18_Z22_Z26_Z30\0"
|
|
/* 230 */ "Z27_Z28_Z29_Z30\0"
|
|
/* 246 */ "b30\0"
|
|
/* 250 */ "d30\0"
|
|
/* 254 */ "h30\0"
|
|
/* 258 */ "q30\0"
|
|
/* 262 */ "s30\0"
|
|
/* 266 */ "w30\0"
|
|
/* 270 */ "x30\0"
|
|
/* 274 */ "z30\0"
|
|
/* 278 */ "D29_D30_D31_D0\0"
|
|
/* 293 */ "P15_P0\0"
|
|
/* 300 */ "Q29_Q30_Q31_Q0\0"
|
|
/* 315 */ "Z29_Z30_Z31_Z0\0"
|
|
/* 330 */ "b0\0"
|
|
/* 333 */ "d0\0"
|
|
/* 336 */ "h0\0"
|
|
/* 339 */ "pn0\0"
|
|
/* 343 */ "p0\0"
|
|
/* 346 */ "q0\0"
|
|
/* 349 */ "s0\0"
|
|
/* 352 */ "zt0\0"
|
|
/* 356 */ "w0\0"
|
|
/* 359 */ "x0\0"
|
|
/* 362 */ "z0\0"
|
|
/* 365 */ "D8_D9_D10_D11\0"
|
|
/* 379 */ "P10_P11\0"
|
|
/* 387 */ "Q8_Q9_Q10_Q11\0"
|
|
/* 401 */ "W10_W11\0"
|
|
/* 409 */ "X4_X5_X6_X7_X8_X9_X10_X11\0"
|
|
/* 435 */ "Z8_Z9_Z10_Z11\0"
|
|
/* 449 */ "Z3_Z11\0"
|
|
/* 456 */ "b11\0"
|
|
/* 460 */ "d11\0"
|
|
/* 464 */ "h11\0"
|
|
/* 468 */ "pn11\0"
|
|
/* 473 */ "p11\0"
|
|
/* 477 */ "q11\0"
|
|
/* 481 */ "s11\0"
|
|
/* 485 */ "w11\0"
|
|
/* 489 */ "x11\0"
|
|
/* 493 */ "z11\0"
|
|
/* 497 */ "D18_D19_D20_D21\0"
|
|
/* 513 */ "Q18_Q19_Q20_Q21\0"
|
|
/* 529 */ "W20_W21\0"
|
|
/* 537 */ "X14_X15_X16_X17_X18_X19_X20_X21\0"
|
|
/* 569 */ "Z18_Z19_Z20_Z21\0"
|
|
/* 585 */ "b21\0"
|
|
/* 589 */ "d21\0"
|
|
/* 593 */ "h21\0"
|
|
/* 597 */ "q21\0"
|
|
/* 601 */ "s21\0"
|
|
/* 605 */ "w21\0"
|
|
/* 609 */ "x21\0"
|
|
/* 613 */ "z21\0"
|
|
/* 617 */ "D28_D29_D30_D31\0"
|
|
/* 633 */ "Q28_Q29_Q30_Q31\0"
|
|
/* 649 */ "Z28_Z29_Z30_Z31\0"
|
|
/* 665 */ "Z23_Z31\0"
|
|
/* 673 */ "Z19_Z23_Z27_Z31\0"
|
|
/* 689 */ "b31\0"
|
|
/* 693 */ "d31\0"
|
|
/* 697 */ "h31\0"
|
|
/* 701 */ "q31\0"
|
|
/* 705 */ "s31\0"
|
|
/* 709 */ "z31\0"
|
|
/* 713 */ "D30_D31_D0_D1\0"
|
|
/* 727 */ "P0_P1\0"
|
|
/* 733 */ "Q30_Q31_Q0_Q1\0"
|
|
/* 747 */ "W0_W1\0"
|
|
/* 753 */ "X0_X1\0"
|
|
/* 759 */ "Z30_Z31_Z0_Z1\0"
|
|
/* 773 */ "b1\0"
|
|
/* 776 */ "d1\0"
|
|
/* 779 */ "h1\0"
|
|
/* 782 */ "pn1\0"
|
|
/* 786 */ "p1\0"
|
|
/* 789 */ "q1\0"
|
|
/* 792 */ "s1\0"
|
|
/* 795 */ "w1\0"
|
|
/* 798 */ "x1\0"
|
|
/* 801 */ "z1\0"
|
|
/* 804 */ "D9_D10_D11_D12\0"
|
|
/* 819 */ "P11_P12\0"
|
|
/* 827 */ "Q9_Q10_Q11_Q12\0"
|
|
/* 842 */ "Z9_Z10_Z11_Z12\0"
|
|
/* 857 */ "Z4_Z12\0"
|
|
/* 864 */ "Z0_Z4_Z8_Z12\0"
|
|
/* 877 */ "b12\0"
|
|
/* 881 */ "d12\0"
|
|
/* 885 */ "h12\0"
|
|
/* 889 */ "pn12\0"
|
|
/* 894 */ "p12\0"
|
|
/* 898 */ "q12\0"
|
|
/* 902 */ "s12\0"
|
|
/* 906 */ "w12\0"
|
|
/* 910 */ "x12\0"
|
|
/* 914 */ "z12\0"
|
|
/* 918 */ "D19_D20_D21_D22\0"
|
|
/* 934 */ "Q19_Q20_Q21_Q22\0"
|
|
/* 950 */ "Z19_Z20_Z21_Z22\0"
|
|
/* 966 */ "b22\0"
|
|
/* 970 */ "d22\0"
|
|
/* 974 */ "h22\0"
|
|
/* 978 */ "q22\0"
|
|
/* 982 */ "s22\0"
|
|
/* 986 */ "w22\0"
|
|
/* 990 */ "x22\0"
|
|
/* 994 */ "z22\0"
|
|
/* 998 */ "D31_D0_D1_D2\0"
|
|
/* 1011 */ "P1_P2\0"
|
|
/* 1017 */ "Q31_Q0_Q1_Q2\0"
|
|
/* 1030 */ "Z31_Z0_Z1_Z2\0"
|
|
/* 1043 */ "b2\0"
|
|
/* 1046 */ "d2\0"
|
|
/* 1049 */ "h2\0"
|
|
/* 1052 */ "pn2\0"
|
|
/* 1056 */ "p2\0"
|
|
/* 1059 */ "q2\0"
|
|
/* 1062 */ "s2\0"
|
|
/* 1065 */ "w2\0"
|
|
/* 1068 */ "x2\0"
|
|
/* 1071 */ "z2\0"
|
|
/* 1074 */ "D10_D11_D12_D13\0"
|
|
/* 1090 */ "P12_P13\0"
|
|
/* 1098 */ "Q10_Q11_Q12_Q13\0"
|
|
/* 1114 */ "W12_W13\0"
|
|
/* 1122 */ "X6_X7_X8_X9_X10_X11_X12_X13\0"
|
|
/* 1150 */ "Z10_Z11_Z12_Z13\0"
|
|
/* 1166 */ "Z5_Z13\0"
|
|
/* 1173 */ "Z1_Z5_Z9_Z13\0"
|
|
/* 1186 */ "b13\0"
|
|
/* 1190 */ "d13\0"
|
|
/* 1194 */ "h13\0"
|
|
/* 1198 */ "pn13\0"
|
|
/* 1203 */ "p13\0"
|
|
/* 1207 */ "q13\0"
|
|
/* 1211 */ "s13\0"
|
|
/* 1215 */ "w13\0"
|
|
/* 1219 */ "x13\0"
|
|
/* 1223 */ "z13\0"
|
|
/* 1227 */ "D20_D21_D22_D23\0"
|
|
/* 1243 */ "Q20_Q21_Q22_Q23\0"
|
|
/* 1259 */ "W22_W23\0"
|
|
/* 1267 */ "X16_X17_X18_X19_X20_X21_X22_X23\0"
|
|
/* 1299 */ "Z20_Z21_Z22_Z23\0"
|
|
/* 1315 */ "b23\0"
|
|
/* 1319 */ "d23\0"
|
|
/* 1323 */ "h23\0"
|
|
/* 1327 */ "q23\0"
|
|
/* 1331 */ "s23\0"
|
|
/* 1335 */ "w23\0"
|
|
/* 1339 */ "x23\0"
|
|
/* 1343 */ "z23\0"
|
|
/* 1347 */ "D0_D1_D2_D3\0"
|
|
/* 1359 */ "P2_P3\0"
|
|
/* 1365 */ "Q0_Q1_Q2_Q3\0"
|
|
/* 1377 */ "W2_W3\0"
|
|
/* 1383 */ "X2_X3\0"
|
|
/* 1389 */ "Z0_Z1_Z2_Z3\0"
|
|
/* 1401 */ "b3\0"
|
|
/* 1404 */ "d3\0"
|
|
/* 1407 */ "h3\0"
|
|
/* 1410 */ "pn3\0"
|
|
/* 1414 */ "p3\0"
|
|
/* 1417 */ "q3\0"
|
|
/* 1420 */ "s3\0"
|
|
/* 1423 */ "w3\0"
|
|
/* 1426 */ "x3\0"
|
|
/* 1429 */ "z3\0"
|
|
/* 1432 */ "D11_D12_D13_D14\0"
|
|
/* 1448 */ "P13_P14\0"
|
|
/* 1456 */ "Q11_Q12_Q13_Q14\0"
|
|
/* 1472 */ "Z2_Z6_Z10_Z14\0"
|
|
/* 1486 */ "Z11_Z12_Z13_Z14\0"
|
|
/* 1502 */ "Z6_Z14\0"
|
|
/* 1509 */ "b14\0"
|
|
/* 1513 */ "d14\0"
|
|
/* 1517 */ "h14\0"
|
|
/* 1521 */ "pn14\0"
|
|
/* 1526 */ "p14\0"
|
|
/* 1530 */ "q14\0"
|
|
/* 1534 */ "s14\0"
|
|
/* 1538 */ "w14\0"
|
|
/* 1542 */ "x14\0"
|
|
/* 1546 */ "z14\0"
|
|
/* 1550 */ "D21_D22_D23_D24\0"
|
|
/* 1566 */ "Q21_Q22_Q23_Q24\0"
|
|
/* 1582 */ "Z21_Z22_Z23_Z24\0"
|
|
/* 1598 */ "Z16_Z24\0"
|
|
/* 1606 */ "b24\0"
|
|
/* 1610 */ "d24\0"
|
|
/* 1614 */ "h24\0"
|
|
/* 1618 */ "q24\0"
|
|
/* 1622 */ "s24\0"
|
|
/* 1626 */ "w24\0"
|
|
/* 1630 */ "x24\0"
|
|
/* 1634 */ "z24\0"
|
|
/* 1638 */ "D1_D2_D3_D4\0"
|
|
/* 1650 */ "P3_P4\0"
|
|
/* 1656 */ "Q1_Q2_Q3_Q4\0"
|
|
/* 1668 */ "Z1_Z2_Z3_Z4\0"
|
|
/* 1680 */ "b4\0"
|
|
/* 1683 */ "d4\0"
|
|
/* 1686 */ "h4\0"
|
|
/* 1689 */ "pn4\0"
|
|
/* 1693 */ "p4\0"
|
|
/* 1696 */ "q4\0"
|
|
/* 1699 */ "s4\0"
|
|
/* 1702 */ "w4\0"
|
|
/* 1705 */ "x4\0"
|
|
/* 1708 */ "z4\0"
|
|
/* 1711 */ "D12_D13_D14_D15\0"
|
|
/* 1727 */ "P14_P15\0"
|
|
/* 1735 */ "Q12_Q13_Q14_Q15\0"
|
|
/* 1751 */ "W14_W15\0"
|
|
/* 1759 */ "X8_X9_X10_X11_X12_X13_X14_X15\0"
|
|
/* 1789 */ "Z3_Z7_Z11_Z15\0"
|
|
/* 1803 */ "Z12_Z13_Z14_Z15\0"
|
|
/* 1819 */ "Z7_Z15\0"
|
|
/* 1826 */ "b15\0"
|
|
/* 1830 */ "d15\0"
|
|
/* 1834 */ "h15\0"
|
|
/* 1838 */ "pn15\0"
|
|
/* 1843 */ "p15\0"
|
|
/* 1847 */ "q15\0"
|
|
/* 1851 */ "s15\0"
|
|
/* 1855 */ "w15\0"
|
|
/* 1859 */ "x15\0"
|
|
/* 1863 */ "z15\0"
|
|
/* 1867 */ "D22_D23_D24_D25\0"
|
|
/* 1883 */ "Q22_Q23_Q24_Q25\0"
|
|
/* 1899 */ "W24_W25\0"
|
|
/* 1907 */ "X18_X19_X20_X21_X22_X23_X24_X25\0"
|
|
/* 1939 */ "Z22_Z23_Z24_Z25\0"
|
|
/* 1955 */ "Z17_Z25\0"
|
|
/* 1963 */ "b25\0"
|
|
/* 1967 */ "d25\0"
|
|
/* 1971 */ "h25\0"
|
|
/* 1975 */ "q25\0"
|
|
/* 1979 */ "s25\0"
|
|
/* 1983 */ "w25\0"
|
|
/* 1987 */ "x25\0"
|
|
/* 1991 */ "z25\0"
|
|
/* 1995 */ "D2_D3_D4_D5\0"
|
|
/* 2007 */ "P4_P5\0"
|
|
/* 2013 */ "Q2_Q3_Q4_Q5\0"
|
|
/* 2025 */ "W4_W5\0"
|
|
/* 2031 */ "X4_X5\0"
|
|
/* 2037 */ "Z2_Z3_Z4_Z5\0"
|
|
/* 2049 */ "b5\0"
|
|
/* 2052 */ "d5\0"
|
|
/* 2055 */ "h5\0"
|
|
/* 2058 */ "pn5\0"
|
|
/* 2062 */ "p5\0"
|
|
/* 2065 */ "q5\0"
|
|
/* 2068 */ "s5\0"
|
|
/* 2071 */ "w5\0"
|
|
/* 2074 */ "x5\0"
|
|
/* 2077 */ "z5\0"
|
|
/* 2080 */ "D13_D14_D15_D16\0"
|
|
/* 2096 */ "Q13_Q14_Q15_Q16\0"
|
|
/* 2112 */ "Z13_Z14_Z15_Z16\0"
|
|
/* 2128 */ "b16\0"
|
|
/* 2132 */ "d16\0"
|
|
/* 2136 */ "h16\0"
|
|
/* 2140 */ "q16\0"
|
|
/* 2144 */ "s16\0"
|
|
/* 2148 */ "w16\0"
|
|
/* 2152 */ "x16\0"
|
|
/* 2156 */ "z16\0"
|
|
/* 2160 */ "D23_D24_D25_D26\0"
|
|
/* 2176 */ "Q23_Q24_Q25_Q26\0"
|
|
/* 2192 */ "Z23_Z24_Z25_Z26\0"
|
|
/* 2208 */ "Z18_Z26\0"
|
|
/* 2216 */ "b26\0"
|
|
/* 2220 */ "d26\0"
|
|
/* 2224 */ "h26\0"
|
|
/* 2228 */ "q26\0"
|
|
/* 2232 */ "s26\0"
|
|
/* 2236 */ "w26\0"
|
|
/* 2240 */ "x26\0"
|
|
/* 2244 */ "z26\0"
|
|
/* 2248 */ "D3_D4_D5_D6\0"
|
|
/* 2260 */ "P5_P6\0"
|
|
/* 2266 */ "Q3_Q4_Q5_Q6\0"
|
|
/* 2278 */ "Z3_Z4_Z5_Z6\0"
|
|
/* 2290 */ "b6\0"
|
|
/* 2293 */ "d6\0"
|
|
/* 2296 */ "h6\0"
|
|
/* 2299 */ "pn6\0"
|
|
/* 2303 */ "p6\0"
|
|
/* 2306 */ "q6\0"
|
|
/* 2309 */ "s6\0"
|
|
/* 2312 */ "w6\0"
|
|
/* 2315 */ "x6\0"
|
|
/* 2318 */ "z6\0"
|
|
/* 2321 */ "D14_D15_D16_D17\0"
|
|
/* 2337 */ "Q14_Q15_Q16_Q17\0"
|
|
/* 2353 */ "W16_W17\0"
|
|
/* 2361 */ "X10_X11_X12_X13_X14_X15_X16_X17\0"
|
|
/* 2393 */ "Z14_Z15_Z16_Z17\0"
|
|
/* 2409 */ "b17\0"
|
|
/* 2413 */ "d17\0"
|
|
/* 2417 */ "h17\0"
|
|
/* 2421 */ "q17\0"
|
|
/* 2425 */ "s17\0"
|
|
/* 2429 */ "w17\0"
|
|
/* 2433 */ "x17\0"
|
|
/* 2437 */ "z17\0"
|
|
/* 2441 */ "D24_D25_D26_D27\0"
|
|
/* 2457 */ "Q24_Q25_Q26_Q27\0"
|
|
/* 2473 */ "W26_W27\0"
|
|
/* 2481 */ "X20_X21_X22_X23_X24_X25_X26_X27\0"
|
|
/* 2513 */ "Z24_Z25_Z26_Z27\0"
|
|
/* 2529 */ "Z19_Z27\0"
|
|
/* 2537 */ "b27\0"
|
|
/* 2541 */ "d27\0"
|
|
/* 2545 */ "h27\0"
|
|
/* 2549 */ "q27\0"
|
|
/* 2553 */ "s27\0"
|
|
/* 2557 */ "w27\0"
|
|
/* 2561 */ "x27\0"
|
|
/* 2565 */ "z27\0"
|
|
/* 2569 */ "D4_D5_D6_D7\0"
|
|
/* 2581 */ "P6_P7\0"
|
|
/* 2587 */ "Q4_Q5_Q6_Q7\0"
|
|
/* 2599 */ "W6_W7\0"
|
|
/* 2605 */ "X0_X1_X2_X3_X4_X5_X6_X7\0"
|
|
/* 2629 */ "Z4_Z5_Z6_Z7\0"
|
|
/* 2641 */ "b7\0"
|
|
/* 2644 */ "d7\0"
|
|
/* 2647 */ "h7\0"
|
|
/* 2650 */ "pn7\0"
|
|
/* 2654 */ "p7\0"
|
|
/* 2657 */ "q7\0"
|
|
/* 2660 */ "s7\0"
|
|
/* 2663 */ "w7\0"
|
|
/* 2666 */ "x7\0"
|
|
/* 2669 */ "z7\0"
|
|
/* 2672 */ "D15_D16_D17_D18\0"
|
|
/* 2688 */ "Q15_Q16_Q17_Q18\0"
|
|
/* 2704 */ "Z15_Z16_Z17_Z18\0"
|
|
/* 2720 */ "b18\0"
|
|
/* 2724 */ "d18\0"
|
|
/* 2728 */ "h18\0"
|
|
/* 2732 */ "q18\0"
|
|
/* 2736 */ "s18\0"
|
|
/* 2740 */ "w18\0"
|
|
/* 2744 */ "x18\0"
|
|
/* 2748 */ "z18\0"
|
|
/* 2752 */ "D25_D26_D27_D28\0"
|
|
/* 2768 */ "Q25_Q26_Q27_Q28\0"
|
|
/* 2784 */ "Z20_Z28\0"
|
|
/* 2792 */ "Z16_Z20_Z24_Z28\0"
|
|
/* 2808 */ "Z25_Z26_Z27_Z28\0"
|
|
/* 2824 */ "b28\0"
|
|
/* 2828 */ "d28\0"
|
|
/* 2832 */ "h28\0"
|
|
/* 2836 */ "q28\0"
|
|
/* 2840 */ "s28\0"
|
|
/* 2844 */ "w28\0"
|
|
/* 2848 */ "x28\0"
|
|
/* 2852 */ "z28\0"
|
|
/* 2856 */ "D5_D6_D7_D8\0"
|
|
/* 2868 */ "P7_P8\0"
|
|
/* 2874 */ "Q5_Q6_Q7_Q8\0"
|
|
/* 2886 */ "Z0_Z8\0"
|
|
/* 2892 */ "Z5_Z6_Z7_Z8\0"
|
|
/* 2904 */ "b8\0"
|
|
/* 2907 */ "d8\0"
|
|
/* 2910 */ "h8\0"
|
|
/* 2913 */ "pn8\0"
|
|
/* 2917 */ "p8\0"
|
|
/* 2920 */ "q8\0"
|
|
/* 2923 */ "s8\0"
|
|
/* 2926 */ "w8\0"
|
|
/* 2929 */ "x8\0"
|
|
/* 2932 */ "z8\0"
|
|
/* 2935 */ "D16_D17_D18_D19\0"
|
|
/* 2951 */ "Q16_Q17_Q18_Q19\0"
|
|
/* 2967 */ "W18_W19\0"
|
|
/* 2975 */ "X12_X13_X14_X15_X16_X17_X18_X19\0"
|
|
/* 3007 */ "Z16_Z17_Z18_Z19\0"
|
|
/* 3023 */ "b19\0"
|
|
/* 3027 */ "d19\0"
|
|
/* 3031 */ "h19\0"
|
|
/* 3035 */ "q19\0"
|
|
/* 3039 */ "s19\0"
|
|
/* 3043 */ "w19\0"
|
|
/* 3047 */ "x19\0"
|
|
/* 3051 */ "z19\0"
|
|
/* 3055 */ "D26_D27_D28_D29\0"
|
|
/* 3071 */ "Q26_Q27_Q28_Q29\0"
|
|
/* 3087 */ "W28_W29\0"
|
|
/* 3095 */ "Z21_Z29\0"
|
|
/* 3103 */ "Z17_Z21_Z25_Z29\0"
|
|
/* 3119 */ "Z26_Z27_Z28_Z29\0"
|
|
/* 3135 */ "b29\0"
|
|
/* 3139 */ "d29\0"
|
|
/* 3143 */ "h29\0"
|
|
/* 3147 */ "q29\0"
|
|
/* 3151 */ "s29\0"
|
|
/* 3155 */ "w29\0"
|
|
/* 3159 */ "x29\0"
|
|
/* 3163 */ "z29\0"
|
|
/* 3167 */ "D6_D7_D8_D9\0"
|
|
/* 3179 */ "P8_P9\0"
|
|
/* 3185 */ "Q6_Q7_Q8_Q9\0"
|
|
/* 3197 */ "W8_W9\0"
|
|
/* 3203 */ "X2_X3_X4_X5_X6_X7_X8_X9\0"
|
|
/* 3227 */ "Z1_Z9\0"
|
|
/* 3233 */ "Z6_Z7_Z8_Z9\0"
|
|
/* 3245 */ "b9\0"
|
|
/* 3248 */ "d9\0"
|
|
/* 3251 */ "h9\0"
|
|
/* 3254 */ "pn9\0"
|
|
/* 3258 */ "p9\0"
|
|
/* 3261 */ "q9\0"
|
|
/* 3264 */ "s9\0"
|
|
/* 3267 */ "w9\0"
|
|
/* 3270 */ "x9\0"
|
|
/* 3273 */ "z9\0"
|
|
/* 3276 */ "X22_X23_X24_X25_X26_X27_X28_FP\0"
|
|
/* 3307 */ "W30_WZR\0"
|
|
/* 3315 */ "LR_XZR\0"
|
|
/* 3322 */ "X\0"
|
|
/* 3324 */ "Y\0"
|
|
/* 3326 */ "Z\0"
|
|
/* 3328 */ "za\0"
|
|
/* 3331 */ "za0.b\0"
|
|
/* 3337 */ "za0.d\0"
|
|
/* 3343 */ "za1.d\0"
|
|
/* 3349 */ "za2.d\0"
|
|
/* 3355 */ "za3.d\0"
|
|
/* 3361 */ "za4.d\0"
|
|
/* 3367 */ "za5.d\0"
|
|
/* 3373 */ "za6.d\0"
|
|
/* 3379 */ "za7.d\0"
|
|
/* 3385 */ "vg\0"
|
|
/* 3388 */ "za0.h\0"
|
|
/* 3394 */ "za1.h\0"
|
|
/* 3400 */ "wsp\0"
|
|
/* 3404 */ "za10.q\0"
|
|
/* 3411 */ "za0.q\0"
|
|
/* 3417 */ "za11.q\0"
|
|
/* 3424 */ "za1.q\0"
|
|
/* 3430 */ "za12.q\0"
|
|
/* 3437 */ "za2.q\0"
|
|
/* 3443 */ "za13.q\0"
|
|
/* 3450 */ "za3.q\0"
|
|
/* 3456 */ "za14.q\0"
|
|
/* 3463 */ "za4.q\0"
|
|
/* 3469 */ "za15.q\0"
|
|
/* 3476 */ "za5.q\0"
|
|
/* 3482 */ "za6.q\0"
|
|
/* 3488 */ "za7.q\0"
|
|
/* 3494 */ "za8.q\0"
|
|
/* 3500 */ "za9.q\0"
|
|
/* 3506 */ "fpcr\0"
|
|
/* 3511 */ "ffr\0"
|
|
/* 3515 */ "wzr\0"
|
|
/* 3519 */ "xzr\0"
|
|
/* 3523 */ "za0.s\0"
|
|
/* 3529 */ "za1.s\0"
|
|
/* 3535 */ "za2.s\0"
|
|
/* 3541 */ "za3.s\0"
|
|
/* 3547 */ "nzcv\0"
|
|
};
|
|
static const uint16_t RegAsmOffsetNoRegAltName[] = {
|
|
3511, 3159, 3506, 270, 3547, 3401, 3385, 3400, 3515, 3519, 3322, 3324, 3328, 3326,
|
|
330, 773, 1043, 1401, 1680, 2049, 2290, 2641, 2904, 3245, 53, 456, 877, 1186,
|
|
1509, 1826, 2128, 2409, 2720, 3023, 142, 585, 966, 1315, 1606, 1963, 2216, 2537,
|
|
2824, 3135, 246, 689, 333, 776, 1046, 1404, 1683, 2052, 2293, 2644, 2907, 3248,
|
|
57, 460, 881, 1190, 1513, 1830, 2132, 2413, 2724, 3027, 146, 589, 970, 1319,
|
|
1610, 1967, 2220, 2541, 2828, 3139, 250, 693, 336, 779, 1049, 1407, 1686, 2055,
|
|
2296, 2647, 2910, 3251, 61, 464, 885, 1194, 1517, 1834, 2136, 2417, 2728, 3031,
|
|
150, 593, 974, 1323, 1614, 1971, 2224, 2545, 2832, 3143, 254, 697, 343, 786,
|
|
1056, 1414, 1693, 2062, 2303, 2654, 2917, 3258, 70, 473, 894, 1203, 1526, 1843,
|
|
339, 782, 1052, 1410, 1689, 2058, 2299, 2650, 2913, 3254, 65, 468, 889, 1198,
|
|
1521, 1838, 346, 789, 1059, 1417, 1696, 2065, 2306, 2657, 2920, 3261, 74, 477,
|
|
898, 1207, 1530, 1847, 2140, 2421, 2732, 3035, 154, 597, 978, 1327, 1618, 1975,
|
|
2228, 2549, 2836, 3147, 258, 701, 349, 792, 1062, 1420, 1699, 2068, 2309, 2660,
|
|
2923, 3264, 78, 481, 902, 1211, 1534, 1851, 2144, 2425, 2736, 3039, 158, 601,
|
|
982, 1331, 1622, 1979, 2232, 2553, 2840, 3151, 262, 705, 356, 795, 1065, 1423,
|
|
1702, 2071, 2312, 2663, 2926, 3267, 82, 485, 906, 1215, 1538, 1855, 2148, 2429,
|
|
2740, 3043, 162, 605, 986, 1335, 1626, 1983, 2236, 2557, 2844, 3155, 266, 359,
|
|
798, 1068, 1426, 1705, 2074, 2315, 2666, 2929, 3270, 86, 489, 910, 1219, 1542,
|
|
1859, 2152, 2433, 2744, 3047, 166, 609, 990, 1339, 1630, 1987, 2240, 2561, 2848,
|
|
362, 801, 1071, 1429, 1708, 2077, 2318, 2669, 2932, 3273, 90, 493, 914, 1223,
|
|
1546, 1863, 2156, 2437, 2748, 3051, 170, 613, 994, 1343, 1634, 1991, 2244, 2565,
|
|
2852, 3163, 274, 709, 3331, 3337, 3343, 3349, 3355, 3361, 3367, 3373, 3379, 3388,
|
|
3394, 3411, 3424, 3437, 3450, 3463, 3476, 3482, 3488, 3494, 3500, 3404, 3417, 3430,
|
|
3443, 3456, 3469, 3523, 3529, 3535, 3541, 352, 721, 1005, 1353, 1644, 2001, 2254,
|
|
2575, 2862, 3173, 6, 371, 811, 1082, 1440, 1719, 2088, 2329, 2680, 2943, 102,
|
|
505, 926, 1235, 1558, 1875, 2168, 2449, 2760, 3063, 182, 625, 286, 1347, 1638,
|
|
1995, 2248, 2569, 2856, 3167, 0, 365, 804, 1074, 1432, 1711, 2080, 2321, 2672,
|
|
2935, 94, 497, 918, 1227, 1550, 1867, 2160, 2441, 2752, 3055, 174, 617, 278,
|
|
713, 998, 1002, 1350, 1641, 1998, 2251, 2572, 2859, 3170, 3, 368, 807, 1078,
|
|
1436, 1715, 2084, 2325, 2676, 2939, 98, 501, 922, 1231, 1554, 1871, 2164, 2445,
|
|
2756, 3059, 178, 621, 282, 717, 727, 1011, 1359, 1650, 2007, 2260, 2581, 2868,
|
|
3179, 13, 379, 819, 1090, 1448, 1727, 293, 741, 1024, 1371, 1662, 2019, 2272,
|
|
2593, 2880, 3191, 26, 393, 834, 1106, 1464, 1743, 2104, 2345, 2696, 2959, 118,
|
|
521, 942, 1251, 1574, 1891, 2184, 2465, 2776, 3079, 198, 641, 308, 1365, 1656,
|
|
2013, 2266, 2587, 2874, 3185, 20, 387, 827, 1098, 1456, 1735, 2096, 2337, 2688,
|
|
2951, 110, 513, 934, 1243, 1566, 1883, 2176, 2457, 2768, 3071, 190, 633, 300,
|
|
733, 1017, 1021, 1368, 1659, 2016, 2269, 2590, 2877, 3188, 23, 390, 830, 1102,
|
|
1460, 1739, 2100, 2341, 2692, 2955, 114, 517, 938, 1247, 1570, 1887, 2180, 2461,
|
|
2772, 3075, 194, 637, 304, 737, 3276, 2605, 3203, 409, 1122, 1759, 2361, 2975,
|
|
537, 1267, 1907, 2481, 3307, 747, 1377, 2025, 2599, 3197, 401, 1114, 1751, 2353,
|
|
2967, 529, 1259, 1899, 2473, 3087, 3315, 3300, 753, 1383, 2031, 2623, 3221, 427,
|
|
1142, 1781, 2385, 2999, 561, 1291, 1931, 2505, 767, 1037, 1395, 1674, 2043, 2284,
|
|
2635, 2898, 3239, 46, 441, 849, 1158, 1494, 1811, 2120, 2401, 2712, 3015, 134,
|
|
577, 958, 1307, 1590, 1947, 2200, 2521, 2816, 3127, 238, 657, 323, 1389, 1668,
|
|
2037, 2278, 2629, 2892, 3233, 40, 435, 842, 1150, 1486, 1803, 2112, 2393, 2704,
|
|
3007, 126, 569, 950, 1299, 1582, 1939, 2192, 2513, 2808, 3119, 230, 649, 315,
|
|
759, 1030, 1034, 1392, 1671, 2040, 2281, 2632, 2895, 3236, 43, 438, 845, 1154,
|
|
1490, 1807, 2116, 2397, 2708, 3011, 130, 573, 954, 1303, 1586, 1943, 2196, 2517,
|
|
2812, 3123, 234, 653, 319, 763, 1598, 1955, 2208, 2529, 2784, 3095, 206, 665,
|
|
2886, 3227, 33, 449, 857, 1166, 1502, 1819, 2792, 3103, 214, 673, 864, 1173,
|
|
1472, 1789,
|
|
};
|
|
|
|
static const char AsmStrsvlist1[] = {
|
|
/* 0 */ "\0"
|
|
};
|
|
static const uint8_t RegAsmOffsetvlist1[] = {
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0,
|
|
};
|
|
|
|
static const char AsmStrsvreg[] = {
|
|
/* 0 */ "v10\0"
|
|
/* 4 */ "v20\0"
|
|
/* 8 */ "v30\0"
|
|
/* 12 */ "v0\0"
|
|
/* 15 */ "v11\0"
|
|
/* 19 */ "v21\0"
|
|
/* 23 */ "v31\0"
|
|
/* 27 */ "v1\0"
|
|
/* 30 */ "v12\0"
|
|
/* 34 */ "v22\0"
|
|
/* 38 */ "v2\0"
|
|
/* 41 */ "v13\0"
|
|
/* 45 */ "v23\0"
|
|
/* 49 */ "v3\0"
|
|
/* 52 */ "v14\0"
|
|
/* 56 */ "v24\0"
|
|
/* 60 */ "v4\0"
|
|
/* 63 */ "v15\0"
|
|
/* 67 */ "v25\0"
|
|
/* 71 */ "v5\0"
|
|
/* 74 */ "v16\0"
|
|
/* 78 */ "v26\0"
|
|
/* 82 */ "v6\0"
|
|
/* 85 */ "v17\0"
|
|
/* 89 */ "v27\0"
|
|
/* 93 */ "v7\0"
|
|
/* 96 */ "v18\0"
|
|
/* 100 */ "v28\0"
|
|
/* 104 */ "v8\0"
|
|
/* 107 */ "v19\0"
|
|
/* 111 */ "v29\0"
|
|
/* 115 */ "v9\0"
|
|
};
|
|
static const uint8_t RegAsmOffsetvreg[] = {
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115,
|
|
0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45,
|
|
56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15,
|
|
30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67,
|
|
78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71,
|
|
82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107,
|
|
4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27,
|
|
38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63,
|
|
74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111,
|
|
8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15,
|
|
30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67,
|
|
78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71,
|
|
82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107,
|
|
4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27,
|
|
38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63,
|
|
74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111,
|
|
8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15,
|
|
30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67,
|
|
78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3,
|
|
};
|
|
|
|
switch(AltIdx) {
|
|
default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL);
|
|
case AArch64_NoRegAltName:
|
|
CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
|
|
"Invalid alt name index for register!", NULL);
|
|
return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
|
|
case AArch64_vlist1:
|
|
CS_ASSERT_RET_VAL(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) &&
|
|
"Invalid alt name index for register!", NULL);
|
|
return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
|
|
case AArch64_vreg:
|
|
CS_ASSERT_RET_VAL(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) &&
|
|
"Invalid alt name index for register!", NULL);
|
|
return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
|
|
}
|
|
#else
|
|
return NULL;
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
|
|
unsigned PredicateIndex);
|
|
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
|
|
#ifndef CAPSTONE_DIET
|
|
static const PatternsForOpcode OpToPatterns[] = {
|
|
{AArch64_ADDPT_shift, 0, 1 },
|
|
{AArch64_ADDSWri, 1, 1 },
|
|
{AArch64_ADDSWrs, 2, 3 },
|
|
{AArch64_ADDSWrx, 5, 3 },
|
|
{AArch64_ADDSXri, 8, 1 },
|
|
{AArch64_ADDSXrs, 9, 3 },
|
|
{AArch64_ADDSXrx, 12, 1 },
|
|
{AArch64_ADDSXrx64, 13, 3 },
|
|
{AArch64_ADDWri, 16, 2 },
|
|
{AArch64_ADDWrs, 18, 1 },
|
|
{AArch64_ADDWrx, 19, 2 },
|
|
{AArch64_ADDXri, 21, 2 },
|
|
{AArch64_ADDXrs, 23, 1 },
|
|
{AArch64_ADDXrx64, 24, 2 },
|
|
{AArch64_ANDSWri, 26, 1 },
|
|
{AArch64_ANDSWrs, 27, 3 },
|
|
{AArch64_ANDSXri, 30, 1 },
|
|
{AArch64_ANDSXrs, 31, 3 },
|
|
{AArch64_ANDS_PPzPP, 34, 1 },
|
|
{AArch64_ANDWrs, 35, 1 },
|
|
{AArch64_ANDXrs, 36, 1 },
|
|
{AArch64_AND_PPzPP, 37, 1 },
|
|
{AArch64_AND_ZI, 38, 3 },
|
|
{AArch64_AUTIA1716, 41, 1 },
|
|
{AArch64_AUTIASP, 42, 1 },
|
|
{AArch64_AUTIAZ, 43, 1 },
|
|
{AArch64_AUTIB1716, 44, 1 },
|
|
{AArch64_AUTIBSP, 45, 1 },
|
|
{AArch64_AUTIBZ, 46, 1 },
|
|
{AArch64_BICSWrs, 47, 1 },
|
|
{AArch64_BICSXrs, 48, 1 },
|
|
{AArch64_BICWrs, 49, 1 },
|
|
{AArch64_BICXrs, 50, 1 },
|
|
{AArch64_CHKFEAT, 51, 1 },
|
|
{AArch64_CLREX, 52, 1 },
|
|
{AArch64_CNTB_XPiI, 53, 2 },
|
|
{AArch64_CNTD_XPiI, 55, 2 },
|
|
{AArch64_CNTH_XPiI, 57, 2 },
|
|
{AArch64_CNTW_XPiI, 59, 2 },
|
|
{AArch64_CPY_ZPmI_B, 61, 1 },
|
|
{AArch64_CPY_ZPmI_D, 62, 1 },
|
|
{AArch64_CPY_ZPmI_H, 63, 1 },
|
|
{AArch64_CPY_ZPmI_S, 64, 1 },
|
|
{AArch64_CPY_ZPmR_B, 65, 1 },
|
|
{AArch64_CPY_ZPmR_D, 66, 1 },
|
|
{AArch64_CPY_ZPmR_H, 67, 1 },
|
|
{AArch64_CPY_ZPmR_S, 68, 1 },
|
|
{AArch64_CPY_ZPmV_B, 69, 1 },
|
|
{AArch64_CPY_ZPmV_D, 70, 1 },
|
|
{AArch64_CPY_ZPmV_H, 71, 1 },
|
|
{AArch64_CPY_ZPmV_S, 72, 1 },
|
|
{AArch64_CPY_ZPzI_B, 73, 1 },
|
|
{AArch64_CPY_ZPzI_D, 74, 1 },
|
|
{AArch64_CPY_ZPzI_H, 75, 1 },
|
|
{AArch64_CPY_ZPzI_S, 76, 1 },
|
|
{AArch64_CSINCWr, 77, 2 },
|
|
{AArch64_CSINCXr, 79, 2 },
|
|
{AArch64_CSINVWr, 81, 2 },
|
|
{AArch64_CSINVXr, 83, 2 },
|
|
{AArch64_CSNEGWr, 85, 1 },
|
|
{AArch64_CSNEGXr, 86, 1 },
|
|
{AArch64_DCPS1, 87, 1 },
|
|
{AArch64_DCPS2, 88, 1 },
|
|
{AArch64_DCPS3, 89, 1 },
|
|
{AArch64_DECB_XPiI, 90, 2 },
|
|
{AArch64_DECD_XPiI, 92, 2 },
|
|
{AArch64_DECD_ZPiI, 94, 2 },
|
|
{AArch64_DECH_XPiI, 96, 2 },
|
|
{AArch64_DECH_ZPiI, 98, 2 },
|
|
{AArch64_DECW_XPiI, 100, 2 },
|
|
{AArch64_DECW_ZPiI, 102, 2 },
|
|
{AArch64_DSB, 104, 3 },
|
|
{AArch64_DUPM_ZI, 107, 6 },
|
|
{AArch64_DUP_ZI_B, 113, 1 },
|
|
{AArch64_DUP_ZI_D, 114, 2 },
|
|
{AArch64_DUP_ZI_H, 116, 2 },
|
|
{AArch64_DUP_ZI_S, 118, 2 },
|
|
{AArch64_DUP_ZR_B, 120, 1 },
|
|
{AArch64_DUP_ZR_D, 121, 1 },
|
|
{AArch64_DUP_ZR_H, 122, 1 },
|
|
{AArch64_DUP_ZR_S, 123, 1 },
|
|
{AArch64_DUP_ZZI_B, 124, 2 },
|
|
{AArch64_DUP_ZZI_D, 126, 2 },
|
|
{AArch64_DUP_ZZI_H, 128, 2 },
|
|
{AArch64_DUP_ZZI_Q, 130, 2 },
|
|
{AArch64_DUP_ZZI_S, 132, 2 },
|
|
{AArch64_EONWrs, 134, 1 },
|
|
{AArch64_EONXrs, 135, 1 },
|
|
{AArch64_EORS_PPzPP, 136, 1 },
|
|
{AArch64_EORWrs, 137, 1 },
|
|
{AArch64_EORXrs, 138, 1 },
|
|
{AArch64_EOR_PPzPP, 139, 1 },
|
|
{AArch64_EOR_ZI, 140, 3 },
|
|
{AArch64_EXTRACT_ZPMXI_H_B, 143, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_D, 144, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_H, 145, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_Q, 146, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_S, 147, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_B, 148, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_D, 149, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_H, 150, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_Q, 151, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_S, 152, 1 },
|
|
{AArch64_EXTRWrri, 153, 1 },
|
|
{AArch64_EXTRXrri, 154, 1 },
|
|
{AArch64_FCPY_ZPmI_D, 155, 1 },
|
|
{AArch64_FCPY_ZPmI_H, 156, 1 },
|
|
{AArch64_FCPY_ZPmI_S, 157, 1 },
|
|
{AArch64_FDUP_ZI_D, 158, 1 },
|
|
{AArch64_FDUP_ZI_H, 159, 1 },
|
|
{AArch64_FDUP_ZI_S, 160, 1 },
|
|
{AArch64_GCSPOPM, 161, 1 },
|
|
{AArch64_GLD1B_D_IMM_REAL, 162, 1 },
|
|
{AArch64_GLD1B_S_IMM_REAL, 163, 1 },
|
|
{AArch64_GLD1D_IMM_REAL, 164, 1 },
|
|
{AArch64_GLD1H_D_IMM_REAL, 165, 1 },
|
|
{AArch64_GLD1H_S_IMM_REAL, 166, 1 },
|
|
{AArch64_GLD1Q, 167, 1 },
|
|
{AArch64_GLD1SB_D_IMM_REAL, 168, 1 },
|
|
{AArch64_GLD1SB_S_IMM_REAL, 169, 1 },
|
|
{AArch64_GLD1SH_D_IMM_REAL, 170, 1 },
|
|
{AArch64_GLD1SH_S_IMM_REAL, 171, 1 },
|
|
{AArch64_GLD1SW_D_IMM_REAL, 172, 1 },
|
|
{AArch64_GLD1W_D_IMM_REAL, 173, 1 },
|
|
{AArch64_GLD1W_IMM_REAL, 174, 1 },
|
|
{AArch64_GLDFF1B_D_IMM_REAL, 175, 1 },
|
|
{AArch64_GLDFF1B_S_IMM_REAL, 176, 1 },
|
|
{AArch64_GLDFF1D_IMM_REAL, 177, 1 },
|
|
{AArch64_GLDFF1H_D_IMM_REAL, 178, 1 },
|
|
{AArch64_GLDFF1H_S_IMM_REAL, 179, 1 },
|
|
{AArch64_GLDFF1SB_D_IMM_REAL, 180, 1 },
|
|
{AArch64_GLDFF1SB_S_IMM_REAL, 181, 1 },
|
|
{AArch64_GLDFF1SH_D_IMM_REAL, 182, 1 },
|
|
{AArch64_GLDFF1SH_S_IMM_REAL, 183, 1 },
|
|
{AArch64_GLDFF1SW_D_IMM_REAL, 184, 1 },
|
|
{AArch64_GLDFF1W_D_IMM_REAL, 185, 1 },
|
|
{AArch64_GLDFF1W_IMM_REAL, 186, 1 },
|
|
{AArch64_HINT, 187, 14 },
|
|
{AArch64_INCB_XPiI, 201, 2 },
|
|
{AArch64_INCD_XPiI, 203, 2 },
|
|
{AArch64_INCD_ZPiI, 205, 2 },
|
|
{AArch64_INCH_XPiI, 207, 2 },
|
|
{AArch64_INCH_ZPiI, 209, 2 },
|
|
{AArch64_INCW_XPiI, 211, 2 },
|
|
{AArch64_INCW_ZPiI, 213, 2 },
|
|
{AArch64_INSERT_MXIPZ_H_B, 215, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_D, 216, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_H, 217, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_Q, 218, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_S, 219, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_B, 220, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_D, 221, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_H, 222, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_Q, 223, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_S, 224, 1 },
|
|
{AArch64_INSvi16gpr, 225, 1 },
|
|
{AArch64_INSvi16lane, 226, 1 },
|
|
{AArch64_INSvi32gpr, 227, 1 },
|
|
{AArch64_INSvi32lane, 228, 1 },
|
|
{AArch64_INSvi64gpr, 229, 1 },
|
|
{AArch64_INSvi64lane, 230, 1 },
|
|
{AArch64_INSvi8gpr, 231, 1 },
|
|
{AArch64_INSvi8lane, 232, 1 },
|
|
{AArch64_IRG, 233, 1 },
|
|
{AArch64_ISB, 234, 1 },
|
|
{AArch64_LD1B_2Z_IMM, 235, 1 },
|
|
{AArch64_LD1B_2Z_STRIDED_IMM, 236, 1 },
|
|
{AArch64_LD1B_4Z_IMM, 237, 1 },
|
|
{AArch64_LD1B_4Z_STRIDED_IMM, 238, 1 },
|
|
{AArch64_LD1B_D_IMM, 239, 1 },
|
|
{AArch64_LD1B_H_IMM, 240, 1 },
|
|
{AArch64_LD1B_IMM, 241, 1 },
|
|
{AArch64_LD1B_S_IMM, 242, 1 },
|
|
{AArch64_LD1D_2Z_IMM, 243, 1 },
|
|
{AArch64_LD1D_2Z_STRIDED_IMM, 244, 1 },
|
|
{AArch64_LD1D_4Z_IMM, 245, 1 },
|
|
{AArch64_LD1D_4Z_STRIDED_IMM, 246, 1 },
|
|
{AArch64_LD1D_IMM, 247, 1 },
|
|
{AArch64_LD1D_Q_IMM, 248, 1 },
|
|
{AArch64_LD1Fourv16b_POST, 249, 1 },
|
|
{AArch64_LD1Fourv1d_POST, 250, 1 },
|
|
{AArch64_LD1Fourv2d_POST, 251, 1 },
|
|
{AArch64_LD1Fourv2s_POST, 252, 1 },
|
|
{AArch64_LD1Fourv4h_POST, 253, 1 },
|
|
{AArch64_LD1Fourv4s_POST, 254, 1 },
|
|
{AArch64_LD1Fourv8b_POST, 255, 1 },
|
|
{AArch64_LD1Fourv8h_POST, 256, 1 },
|
|
{AArch64_LD1H_2Z_IMM, 257, 1 },
|
|
{AArch64_LD1H_2Z_STRIDED_IMM, 258, 1 },
|
|
{AArch64_LD1H_4Z_IMM, 259, 1 },
|
|
{AArch64_LD1H_4Z_STRIDED_IMM, 260, 1 },
|
|
{AArch64_LD1H_D_IMM, 261, 1 },
|
|
{AArch64_LD1H_IMM, 262, 1 },
|
|
{AArch64_LD1H_S_IMM, 263, 1 },
|
|
{AArch64_LD1Onev16b_POST, 264, 1 },
|
|
{AArch64_LD1Onev1d_POST, 265, 1 },
|
|
{AArch64_LD1Onev2d_POST, 266, 1 },
|
|
{AArch64_LD1Onev2s_POST, 267, 1 },
|
|
{AArch64_LD1Onev4h_POST, 268, 1 },
|
|
{AArch64_LD1Onev4s_POST, 269, 1 },
|
|
{AArch64_LD1Onev8b_POST, 270, 1 },
|
|
{AArch64_LD1Onev8h_POST, 271, 1 },
|
|
{AArch64_LD1RB_D_IMM, 272, 1 },
|
|
{AArch64_LD1RB_H_IMM, 273, 1 },
|
|
{AArch64_LD1RB_IMM, 274, 1 },
|
|
{AArch64_LD1RB_S_IMM, 275, 1 },
|
|
{AArch64_LD1RD_IMM, 276, 1 },
|
|
{AArch64_LD1RH_D_IMM, 277, 1 },
|
|
{AArch64_LD1RH_IMM, 278, 1 },
|
|
{AArch64_LD1RH_S_IMM, 279, 1 },
|
|
{AArch64_LD1RO_B_IMM, 280, 1 },
|
|
{AArch64_LD1RO_D_IMM, 281, 1 },
|
|
{AArch64_LD1RO_H_IMM, 282, 1 },
|
|
{AArch64_LD1RO_W_IMM, 283, 1 },
|
|
{AArch64_LD1RQ_B_IMM, 284, 1 },
|
|
{AArch64_LD1RQ_D_IMM, 285, 1 },
|
|
{AArch64_LD1RQ_H_IMM, 286, 1 },
|
|
{AArch64_LD1RQ_W_IMM, 287, 1 },
|
|
{AArch64_LD1RSB_D_IMM, 288, 1 },
|
|
{AArch64_LD1RSB_H_IMM, 289, 1 },
|
|
{AArch64_LD1RSB_S_IMM, 290, 1 },
|
|
{AArch64_LD1RSH_D_IMM, 291, 1 },
|
|
{AArch64_LD1RSH_S_IMM, 292, 1 },
|
|
{AArch64_LD1RSW_IMM, 293, 1 },
|
|
{AArch64_LD1RW_D_IMM, 294, 1 },
|
|
{AArch64_LD1RW_IMM, 295, 1 },
|
|
{AArch64_LD1Rv16b_POST, 296, 1 },
|
|
{AArch64_LD1Rv1d_POST, 297, 1 },
|
|
{AArch64_LD1Rv2d_POST, 298, 1 },
|
|
{AArch64_LD1Rv2s_POST, 299, 1 },
|
|
{AArch64_LD1Rv4h_POST, 300, 1 },
|
|
{AArch64_LD1Rv4s_POST, 301, 1 },
|
|
{AArch64_LD1Rv8b_POST, 302, 1 },
|
|
{AArch64_LD1Rv8h_POST, 303, 1 },
|
|
{AArch64_LD1SB_D_IMM, 304, 1 },
|
|
{AArch64_LD1SB_H_IMM, 305, 1 },
|
|
{AArch64_LD1SB_S_IMM, 306, 1 },
|
|
{AArch64_LD1SH_D_IMM, 307, 1 },
|
|
{AArch64_LD1SH_S_IMM, 308, 1 },
|
|
{AArch64_LD1SW_D_IMM, 309, 1 },
|
|
{AArch64_LD1Threev16b_POST, 310, 1 },
|
|
{AArch64_LD1Threev1d_POST, 311, 1 },
|
|
{AArch64_LD1Threev2d_POST, 312, 1 },
|
|
{AArch64_LD1Threev2s_POST, 313, 1 },
|
|
{AArch64_LD1Threev4h_POST, 314, 1 },
|
|
{AArch64_LD1Threev4s_POST, 315, 1 },
|
|
{AArch64_LD1Threev8b_POST, 316, 1 },
|
|
{AArch64_LD1Threev8h_POST, 317, 1 },
|
|
{AArch64_LD1Twov16b_POST, 318, 1 },
|
|
{AArch64_LD1Twov1d_POST, 319, 1 },
|
|
{AArch64_LD1Twov2d_POST, 320, 1 },
|
|
{AArch64_LD1Twov2s_POST, 321, 1 },
|
|
{AArch64_LD1Twov4h_POST, 322, 1 },
|
|
{AArch64_LD1Twov4s_POST, 323, 1 },
|
|
{AArch64_LD1Twov8b_POST, 324, 1 },
|
|
{AArch64_LD1Twov8h_POST, 325, 1 },
|
|
{AArch64_LD1W_2Z_IMM, 326, 1 },
|
|
{AArch64_LD1W_2Z_STRIDED_IMM, 327, 1 },
|
|
{AArch64_LD1W_4Z_IMM, 328, 1 },
|
|
{AArch64_LD1W_4Z_STRIDED_IMM, 329, 1 },
|
|
{AArch64_LD1W_D_IMM, 330, 1 },
|
|
{AArch64_LD1W_IMM, 331, 1 },
|
|
{AArch64_LD1W_Q_IMM, 332, 1 },
|
|
{AArch64_LD1_MXIPXX_H_B, 333, 1 },
|
|
{AArch64_LD1_MXIPXX_H_D, 334, 1 },
|
|
{AArch64_LD1_MXIPXX_H_H, 335, 1 },
|
|
{AArch64_LD1_MXIPXX_H_Q, 336, 1 },
|
|
{AArch64_LD1_MXIPXX_H_S, 337, 1 },
|
|
{AArch64_LD1_MXIPXX_V_B, 338, 1 },
|
|
{AArch64_LD1_MXIPXX_V_D, 339, 1 },
|
|
{AArch64_LD1_MXIPXX_V_H, 340, 1 },
|
|
{AArch64_LD1_MXIPXX_V_Q, 341, 1 },
|
|
{AArch64_LD1_MXIPXX_V_S, 342, 1 },
|
|
{AArch64_LD1i16_POST, 343, 1 },
|
|
{AArch64_LD1i32_POST, 344, 1 },
|
|
{AArch64_LD1i64_POST, 345, 1 },
|
|
{AArch64_LD1i8_POST, 346, 1 },
|
|
{AArch64_LD2B_IMM, 347, 1 },
|
|
{AArch64_LD2D_IMM, 348, 1 },
|
|
{AArch64_LD2H_IMM, 349, 1 },
|
|
{AArch64_LD2Q_IMM, 350, 1 },
|
|
{AArch64_LD2Rv16b_POST, 351, 1 },
|
|
{AArch64_LD2Rv1d_POST, 352, 1 },
|
|
{AArch64_LD2Rv2d_POST, 353, 1 },
|
|
{AArch64_LD2Rv2s_POST, 354, 1 },
|
|
{AArch64_LD2Rv4h_POST, 355, 1 },
|
|
{AArch64_LD2Rv4s_POST, 356, 1 },
|
|
{AArch64_LD2Rv8b_POST, 357, 1 },
|
|
{AArch64_LD2Rv8h_POST, 358, 1 },
|
|
{AArch64_LD2Twov16b_POST, 359, 1 },
|
|
{AArch64_LD2Twov2d_POST, 360, 1 },
|
|
{AArch64_LD2Twov2s_POST, 361, 1 },
|
|
{AArch64_LD2Twov4h_POST, 362, 1 },
|
|
{AArch64_LD2Twov4s_POST, 363, 1 },
|
|
{AArch64_LD2Twov8b_POST, 364, 1 },
|
|
{AArch64_LD2Twov8h_POST, 365, 1 },
|
|
{AArch64_LD2W_IMM, 366, 1 },
|
|
{AArch64_LD2i16_POST, 367, 1 },
|
|
{AArch64_LD2i32_POST, 368, 1 },
|
|
{AArch64_LD2i64_POST, 369, 1 },
|
|
{AArch64_LD2i8_POST, 370, 1 },
|
|
{AArch64_LD3B_IMM, 371, 1 },
|
|
{AArch64_LD3D_IMM, 372, 1 },
|
|
{AArch64_LD3H_IMM, 373, 1 },
|
|
{AArch64_LD3Q_IMM, 374, 1 },
|
|
{AArch64_LD3Rv16b_POST, 375, 1 },
|
|
{AArch64_LD3Rv1d_POST, 376, 1 },
|
|
{AArch64_LD3Rv2d_POST, 377, 1 },
|
|
{AArch64_LD3Rv2s_POST, 378, 1 },
|
|
{AArch64_LD3Rv4h_POST, 379, 1 },
|
|
{AArch64_LD3Rv4s_POST, 380, 1 },
|
|
{AArch64_LD3Rv8b_POST, 381, 1 },
|
|
{AArch64_LD3Rv8h_POST, 382, 1 },
|
|
{AArch64_LD3Threev16b_POST, 383, 1 },
|
|
{AArch64_LD3Threev2d_POST, 384, 1 },
|
|
{AArch64_LD3Threev2s_POST, 385, 1 },
|
|
{AArch64_LD3Threev4h_POST, 386, 1 },
|
|
{AArch64_LD3Threev4s_POST, 387, 1 },
|
|
{AArch64_LD3Threev8b_POST, 388, 1 },
|
|
{AArch64_LD3Threev8h_POST, 389, 1 },
|
|
{AArch64_LD3W_IMM, 390, 1 },
|
|
{AArch64_LD3i16_POST, 391, 1 },
|
|
{AArch64_LD3i32_POST, 392, 1 },
|
|
{AArch64_LD3i64_POST, 393, 1 },
|
|
{AArch64_LD3i8_POST, 394, 1 },
|
|
{AArch64_LD4B_IMM, 395, 1 },
|
|
{AArch64_LD4D_IMM, 396, 1 },
|
|
{AArch64_LD4Fourv16b_POST, 397, 1 },
|
|
{AArch64_LD4Fourv2d_POST, 398, 1 },
|
|
{AArch64_LD4Fourv2s_POST, 399, 1 },
|
|
{AArch64_LD4Fourv4h_POST, 400, 1 },
|
|
{AArch64_LD4Fourv4s_POST, 401, 1 },
|
|
{AArch64_LD4Fourv8b_POST, 402, 1 },
|
|
{AArch64_LD4Fourv8h_POST, 403, 1 },
|
|
{AArch64_LD4H_IMM, 404, 1 },
|
|
{AArch64_LD4Q_IMM, 405, 1 },
|
|
{AArch64_LD4Rv16b_POST, 406, 1 },
|
|
{AArch64_LD4Rv1d_POST, 407, 1 },
|
|
{AArch64_LD4Rv2d_POST, 408, 1 },
|
|
{AArch64_LD4Rv2s_POST, 409, 1 },
|
|
{AArch64_LD4Rv4h_POST, 410, 1 },
|
|
{AArch64_LD4Rv4s_POST, 411, 1 },
|
|
{AArch64_LD4Rv8b_POST, 412, 1 },
|
|
{AArch64_LD4Rv8h_POST, 413, 1 },
|
|
{AArch64_LD4W_IMM, 414, 1 },
|
|
{AArch64_LD4i16_POST, 415, 1 },
|
|
{AArch64_LD4i32_POST, 416, 1 },
|
|
{AArch64_LD4i64_POST, 417, 1 },
|
|
{AArch64_LD4i8_POST, 418, 1 },
|
|
{AArch64_LDADDB, 419, 1 },
|
|
{AArch64_LDADDH, 420, 1 },
|
|
{AArch64_LDADDLB, 421, 1 },
|
|
{AArch64_LDADDLH, 422, 1 },
|
|
{AArch64_LDADDLW, 423, 1 },
|
|
{AArch64_LDADDLX, 424, 1 },
|
|
{AArch64_LDADDW, 425, 1 },
|
|
{AArch64_LDADDX, 426, 1 },
|
|
{AArch64_LDAPURBi, 427, 1 },
|
|
{AArch64_LDAPURHi, 428, 1 },
|
|
{AArch64_LDAPURSBWi, 429, 1 },
|
|
{AArch64_LDAPURSBXi, 430, 1 },
|
|
{AArch64_LDAPURSHWi, 431, 1 },
|
|
{AArch64_LDAPURSHXi, 432, 1 },
|
|
{AArch64_LDAPURSWi, 433, 1 },
|
|
{AArch64_LDAPURXi, 434, 1 },
|
|
{AArch64_LDAPURbi, 435, 1 },
|
|
{AArch64_LDAPURdi, 436, 1 },
|
|
{AArch64_LDAPURhi, 437, 1 },
|
|
{AArch64_LDAPURi, 438, 1 },
|
|
{AArch64_LDAPURqi, 439, 1 },
|
|
{AArch64_LDAPURsi, 440, 1 },
|
|
{AArch64_LDCLRB, 441, 1 },
|
|
{AArch64_LDCLRH, 442, 1 },
|
|
{AArch64_LDCLRLB, 443, 1 },
|
|
{AArch64_LDCLRLH, 444, 1 },
|
|
{AArch64_LDCLRLW, 445, 1 },
|
|
{AArch64_LDCLRLX, 446, 1 },
|
|
{AArch64_LDCLRW, 447, 1 },
|
|
{AArch64_LDCLRX, 448, 1 },
|
|
{AArch64_LDEORB, 449, 1 },
|
|
{AArch64_LDEORH, 450, 1 },
|
|
{AArch64_LDEORLB, 451, 1 },
|
|
{AArch64_LDEORLH, 452, 1 },
|
|
{AArch64_LDEORLW, 453, 1 },
|
|
{AArch64_LDEORLX, 454, 1 },
|
|
{AArch64_LDEORW, 455, 1 },
|
|
{AArch64_LDEORX, 456, 1 },
|
|
{AArch64_LDFF1B_D_REAL, 457, 1 },
|
|
{AArch64_LDFF1B_H_REAL, 458, 1 },
|
|
{AArch64_LDFF1B_REAL, 459, 1 },
|
|
{AArch64_LDFF1B_S_REAL, 460, 1 },
|
|
{AArch64_LDFF1D_REAL, 461, 1 },
|
|
{AArch64_LDFF1H_D_REAL, 462, 1 },
|
|
{AArch64_LDFF1H_REAL, 463, 1 },
|
|
{AArch64_LDFF1H_S_REAL, 464, 1 },
|
|
{AArch64_LDFF1SB_D_REAL, 465, 1 },
|
|
{AArch64_LDFF1SB_H_REAL, 466, 1 },
|
|
{AArch64_LDFF1SB_S_REAL, 467, 1 },
|
|
{AArch64_LDFF1SH_D_REAL, 468, 1 },
|
|
{AArch64_LDFF1SH_S_REAL, 469, 1 },
|
|
{AArch64_LDFF1SW_D_REAL, 470, 1 },
|
|
{AArch64_LDFF1W_D_REAL, 471, 1 },
|
|
{AArch64_LDFF1W_REAL, 472, 1 },
|
|
{AArch64_LDG, 473, 1 },
|
|
{AArch64_LDNF1B_D_IMM_REAL, 474, 1 },
|
|
{AArch64_LDNF1B_H_IMM_REAL, 475, 1 },
|
|
{AArch64_LDNF1B_IMM_REAL, 476, 1 },
|
|
{AArch64_LDNF1B_S_IMM_REAL, 477, 1 },
|
|
{AArch64_LDNF1D_IMM_REAL, 478, 1 },
|
|
{AArch64_LDNF1H_D_IMM_REAL, 479, 1 },
|
|
{AArch64_LDNF1H_IMM_REAL, 480, 1 },
|
|
{AArch64_LDNF1H_S_IMM_REAL, 481, 1 },
|
|
{AArch64_LDNF1SB_D_IMM_REAL, 482, 1 },
|
|
{AArch64_LDNF1SB_H_IMM_REAL, 483, 1 },
|
|
{AArch64_LDNF1SB_S_IMM_REAL, 484, 1 },
|
|
{AArch64_LDNF1SH_D_IMM_REAL, 485, 1 },
|
|
{AArch64_LDNF1SH_S_IMM_REAL, 486, 1 },
|
|
{AArch64_LDNF1SW_D_IMM_REAL, 487, 1 },
|
|
{AArch64_LDNF1W_D_IMM_REAL, 488, 1 },
|
|
{AArch64_LDNF1W_IMM_REAL, 489, 1 },
|
|
{AArch64_LDNPDi, 490, 1 },
|
|
{AArch64_LDNPQi, 491, 1 },
|
|
{AArch64_LDNPSi, 492, 1 },
|
|
{AArch64_LDNPWi, 493, 1 },
|
|
{AArch64_LDNPXi, 494, 1 },
|
|
{AArch64_LDNT1B_2Z_IMM, 495, 1 },
|
|
{AArch64_LDNT1B_2Z_STRIDED_IMM, 496, 1 },
|
|
{AArch64_LDNT1B_4Z_IMM, 497, 1 },
|
|
{AArch64_LDNT1B_4Z_STRIDED_IMM, 498, 1 },
|
|
{AArch64_LDNT1B_ZRI, 499, 1 },
|
|
{AArch64_LDNT1B_ZZR_D_REAL, 500, 1 },
|
|
{AArch64_LDNT1B_ZZR_S_REAL, 501, 1 },
|
|
{AArch64_LDNT1D_2Z_IMM, 502, 1 },
|
|
{AArch64_LDNT1D_2Z_STRIDED_IMM, 503, 1 },
|
|
{AArch64_LDNT1D_4Z_IMM, 504, 1 },
|
|
{AArch64_LDNT1D_4Z_STRIDED_IMM, 505, 1 },
|
|
{AArch64_LDNT1D_ZRI, 506, 1 },
|
|
{AArch64_LDNT1D_ZZR_D_REAL, 507, 1 },
|
|
{AArch64_LDNT1H_2Z_IMM, 508, 1 },
|
|
{AArch64_LDNT1H_2Z_STRIDED_IMM, 509, 1 },
|
|
{AArch64_LDNT1H_4Z_IMM, 510, 1 },
|
|
{AArch64_LDNT1H_4Z_STRIDED_IMM, 511, 1 },
|
|
{AArch64_LDNT1H_ZRI, 512, 1 },
|
|
{AArch64_LDNT1H_ZZR_D_REAL, 513, 1 },
|
|
{AArch64_LDNT1H_ZZR_S_REAL, 514, 1 },
|
|
{AArch64_LDNT1SB_ZZR_D_REAL, 515, 1 },
|
|
{AArch64_LDNT1SB_ZZR_S_REAL, 516, 1 },
|
|
{AArch64_LDNT1SH_ZZR_D_REAL, 517, 1 },
|
|
{AArch64_LDNT1SH_ZZR_S_REAL, 518, 1 },
|
|
{AArch64_LDNT1SW_ZZR_D_REAL, 519, 1 },
|
|
{AArch64_LDNT1W_2Z_IMM, 520, 1 },
|
|
{AArch64_LDNT1W_2Z_STRIDED_IMM, 521, 1 },
|
|
{AArch64_LDNT1W_4Z_IMM, 522, 1 },
|
|
{AArch64_LDNT1W_4Z_STRIDED_IMM, 523, 1 },
|
|
{AArch64_LDNT1W_ZRI, 524, 1 },
|
|
{AArch64_LDNT1W_ZZR_D_REAL, 525, 1 },
|
|
{AArch64_LDNT1W_ZZR_S_REAL, 526, 1 },
|
|
{AArch64_LDPDi, 527, 1 },
|
|
{AArch64_LDPQi, 528, 1 },
|
|
{AArch64_LDPSWi, 529, 1 },
|
|
{AArch64_LDPSi, 530, 1 },
|
|
{AArch64_LDPWi, 531, 1 },
|
|
{AArch64_LDPXi, 532, 1 },
|
|
{AArch64_LDRAAindexed, 533, 1 },
|
|
{AArch64_LDRABindexed, 534, 1 },
|
|
{AArch64_LDRBBroX, 535, 1 },
|
|
{AArch64_LDRBBui, 536, 1 },
|
|
{AArch64_LDRBroX, 537, 1 },
|
|
{AArch64_LDRBui, 538, 1 },
|
|
{AArch64_LDRDroX, 539, 1 },
|
|
{AArch64_LDRDui, 540, 1 },
|
|
{AArch64_LDRHHroX, 541, 1 },
|
|
{AArch64_LDRHHui, 542, 1 },
|
|
{AArch64_LDRHroX, 543, 1 },
|
|
{AArch64_LDRHui, 544, 1 },
|
|
{AArch64_LDRQroX, 545, 1 },
|
|
{AArch64_LDRQui, 546, 1 },
|
|
{AArch64_LDRSBWroX, 547, 1 },
|
|
{AArch64_LDRSBWui, 548, 1 },
|
|
{AArch64_LDRSBXroX, 549, 1 },
|
|
{AArch64_LDRSBXui, 550, 1 },
|
|
{AArch64_LDRSHWroX, 551, 1 },
|
|
{AArch64_LDRSHWui, 552, 1 },
|
|
{AArch64_LDRSHXroX, 553, 1 },
|
|
{AArch64_LDRSHXui, 554, 1 },
|
|
{AArch64_LDRSWroX, 555, 1 },
|
|
{AArch64_LDRSWui, 556, 1 },
|
|
{AArch64_LDRSroX, 557, 1 },
|
|
{AArch64_LDRSui, 558, 1 },
|
|
{AArch64_LDRWroX, 559, 1 },
|
|
{AArch64_LDRWui, 560, 1 },
|
|
{AArch64_LDRXroX, 561, 1 },
|
|
{AArch64_LDRXui, 562, 1 },
|
|
{AArch64_LDR_PXI, 563, 1 },
|
|
{AArch64_LDR_ZA, 564, 1 },
|
|
{AArch64_LDR_ZXI, 565, 1 },
|
|
{AArch64_LDSETB, 566, 1 },
|
|
{AArch64_LDSETH, 567, 1 },
|
|
{AArch64_LDSETLB, 568, 1 },
|
|
{AArch64_LDSETLH, 569, 1 },
|
|
{AArch64_LDSETLW, 570, 1 },
|
|
{AArch64_LDSETLX, 571, 1 },
|
|
{AArch64_LDSETW, 572, 1 },
|
|
{AArch64_LDSETX, 573, 1 },
|
|
{AArch64_LDSMAXB, 574, 1 },
|
|
{AArch64_LDSMAXH, 575, 1 },
|
|
{AArch64_LDSMAXLB, 576, 1 },
|
|
{AArch64_LDSMAXLH, 577, 1 },
|
|
{AArch64_LDSMAXLW, 578, 1 },
|
|
{AArch64_LDSMAXLX, 579, 1 },
|
|
{AArch64_LDSMAXW, 580, 1 },
|
|
{AArch64_LDSMAXX, 581, 1 },
|
|
{AArch64_LDSMINB, 582, 1 },
|
|
{AArch64_LDSMINH, 583, 1 },
|
|
{AArch64_LDSMINLB, 584, 1 },
|
|
{AArch64_LDSMINLH, 585, 1 },
|
|
{AArch64_LDSMINLW, 586, 1 },
|
|
{AArch64_LDSMINLX, 587, 1 },
|
|
{AArch64_LDSMINW, 588, 1 },
|
|
{AArch64_LDSMINX, 589, 1 },
|
|
{AArch64_LDTRBi, 590, 1 },
|
|
{AArch64_LDTRHi, 591, 1 },
|
|
{AArch64_LDTRSBWi, 592, 1 },
|
|
{AArch64_LDTRSBXi, 593, 1 },
|
|
{AArch64_LDTRSHWi, 594, 1 },
|
|
{AArch64_LDTRSHXi, 595, 1 },
|
|
{AArch64_LDTRSWi, 596, 1 },
|
|
{AArch64_LDTRWi, 597, 1 },
|
|
{AArch64_LDTRXi, 598, 1 },
|
|
{AArch64_LDUMAXB, 599, 1 },
|
|
{AArch64_LDUMAXH, 600, 1 },
|
|
{AArch64_LDUMAXLB, 601, 1 },
|
|
{AArch64_LDUMAXLH, 602, 1 },
|
|
{AArch64_LDUMAXLW, 603, 1 },
|
|
{AArch64_LDUMAXLX, 604, 1 },
|
|
{AArch64_LDUMAXW, 605, 1 },
|
|
{AArch64_LDUMAXX, 606, 1 },
|
|
{AArch64_LDUMINB, 607, 1 },
|
|
{AArch64_LDUMINH, 608, 1 },
|
|
{AArch64_LDUMINLB, 609, 1 },
|
|
{AArch64_LDUMINLH, 610, 1 },
|
|
{AArch64_LDUMINLW, 611, 1 },
|
|
{AArch64_LDUMINLX, 612, 1 },
|
|
{AArch64_LDUMINW, 613, 1 },
|
|
{AArch64_LDUMINX, 614, 1 },
|
|
{AArch64_LDURBBi, 615, 1 },
|
|
{AArch64_LDURBi, 616, 1 },
|
|
{AArch64_LDURDi, 617, 1 },
|
|
{AArch64_LDURHHi, 618, 1 },
|
|
{AArch64_LDURHi, 619, 1 },
|
|
{AArch64_LDURQi, 620, 1 },
|
|
{AArch64_LDURSBWi, 621, 1 },
|
|
{AArch64_LDURSBXi, 622, 1 },
|
|
{AArch64_LDURSHWi, 623, 1 },
|
|
{AArch64_LDURSHXi, 624, 1 },
|
|
{AArch64_LDURSWi, 625, 1 },
|
|
{AArch64_LDURSi, 626, 1 },
|
|
{AArch64_LDURWi, 627, 1 },
|
|
{AArch64_LDURXi, 628, 1 },
|
|
{AArch64_MADDWrrr, 629, 1 },
|
|
{AArch64_MADDXrrr, 630, 1 },
|
|
{AArch64_MOVA_2ZMXI_H_B, 631, 1 },
|
|
{AArch64_MOVA_2ZMXI_H_D, 632, 1 },
|
|
{AArch64_MOVA_2ZMXI_H_H, 633, 1 },
|
|
{AArch64_MOVA_2ZMXI_H_S, 634, 1 },
|
|
{AArch64_MOVA_2ZMXI_V_B, 635, 1 },
|
|
{AArch64_MOVA_2ZMXI_V_D, 636, 1 },
|
|
{AArch64_MOVA_2ZMXI_V_H, 637, 1 },
|
|
{AArch64_MOVA_2ZMXI_V_S, 638, 1 },
|
|
{AArch64_MOVA_4ZMXI_H_B, 639, 1 },
|
|
{AArch64_MOVA_4ZMXI_H_D, 640, 1 },
|
|
{AArch64_MOVA_4ZMXI_H_H, 641, 1 },
|
|
{AArch64_MOVA_4ZMXI_H_S, 642, 1 },
|
|
{AArch64_MOVA_4ZMXI_V_B, 643, 1 },
|
|
{AArch64_MOVA_4ZMXI_V_D, 644, 1 },
|
|
{AArch64_MOVA_4ZMXI_V_H, 645, 1 },
|
|
{AArch64_MOVA_4ZMXI_V_S, 646, 1 },
|
|
{AArch64_MOVA_MXI2Z_H_B, 647, 1 },
|
|
{AArch64_MOVA_MXI2Z_H_D, 648, 1 },
|
|
{AArch64_MOVA_MXI2Z_H_H, 649, 1 },
|
|
{AArch64_MOVA_MXI2Z_H_S, 650, 1 },
|
|
{AArch64_MOVA_MXI2Z_V_B, 651, 1 },
|
|
{AArch64_MOVA_MXI2Z_V_D, 652, 1 },
|
|
{AArch64_MOVA_MXI2Z_V_H, 653, 1 },
|
|
{AArch64_MOVA_MXI2Z_V_S, 654, 1 },
|
|
{AArch64_MOVA_MXI4Z_H_B, 655, 1 },
|
|
{AArch64_MOVA_MXI4Z_H_D, 656, 1 },
|
|
{AArch64_MOVA_MXI4Z_H_H, 657, 1 },
|
|
{AArch64_MOVA_MXI4Z_H_S, 658, 1 },
|
|
{AArch64_MOVA_MXI4Z_V_B, 659, 1 },
|
|
{AArch64_MOVA_MXI4Z_V_D, 660, 1 },
|
|
{AArch64_MOVA_MXI4Z_V_H, 661, 1 },
|
|
{AArch64_MOVA_MXI4Z_V_S, 662, 1 },
|
|
{AArch64_MOVA_VG2_2ZMXI, 663, 1 },
|
|
{AArch64_MOVA_VG2_MXI2Z, 664, 1 },
|
|
{AArch64_MOVA_VG4_4ZMXI, 665, 1 },
|
|
{AArch64_MOVA_VG4_MXI4Z, 666, 1 },
|
|
{AArch64_MOVT, 667, 1 },
|
|
{AArch64_MSRpstatesvcrImm1, 668, 6 },
|
|
{AArch64_MSUBWrrr, 674, 1 },
|
|
{AArch64_MSUBXrrr, 675, 1 },
|
|
{AArch64_NOTv16i8, 676, 1 },
|
|
{AArch64_NOTv8i8, 677, 1 },
|
|
{AArch64_ORNWrs, 678, 3 },
|
|
{AArch64_ORNXrs, 681, 3 },
|
|
{AArch64_ORRS_PPzPP, 684, 1 },
|
|
{AArch64_ORRWrs, 685, 2 },
|
|
{AArch64_ORRXrs, 687, 2 },
|
|
{AArch64_ORR_PPzPP, 689, 1 },
|
|
{AArch64_ORR_ZI, 690, 3 },
|
|
{AArch64_ORR_ZZZ, 693, 1 },
|
|
{AArch64_ORRv16i8, 694, 1 },
|
|
{AArch64_ORRv8i8, 695, 1 },
|
|
{AArch64_PACIA1716, 696, 1 },
|
|
{AArch64_PACIASP, 697, 1 },
|
|
{AArch64_PACIAZ, 698, 1 },
|
|
{AArch64_PACIB1716, 699, 1 },
|
|
{AArch64_PACIBSP, 700, 1 },
|
|
{AArch64_PACIBZ, 701, 1 },
|
|
{AArch64_PACM, 702, 1 },
|
|
{AArch64_PMOV_PZI_B, 703, 1 },
|
|
{AArch64_PMOV_ZIP_B, 704, 1 },
|
|
{AArch64_PRFB_D_PZI, 705, 1 },
|
|
{AArch64_PRFB_PRI, 706, 1 },
|
|
{AArch64_PRFB_S_PZI, 707, 1 },
|
|
{AArch64_PRFD_D_PZI, 708, 1 },
|
|
{AArch64_PRFD_PRI, 709, 1 },
|
|
{AArch64_PRFD_S_PZI, 710, 1 },
|
|
{AArch64_PRFH_D_PZI, 711, 1 },
|
|
{AArch64_PRFH_PRI, 712, 1 },
|
|
{AArch64_PRFH_S_PZI, 713, 1 },
|
|
{AArch64_PRFMroX, 714, 1 },
|
|
{AArch64_PRFMui, 715, 1 },
|
|
{AArch64_PRFUMi, 716, 1 },
|
|
{AArch64_PRFW_D_PZI, 717, 1 },
|
|
{AArch64_PRFW_PRI, 718, 1 },
|
|
{AArch64_PRFW_S_PZI, 719, 1 },
|
|
{AArch64_PTRUES_B, 720, 1 },
|
|
{AArch64_PTRUES_D, 721, 1 },
|
|
{AArch64_PTRUES_H, 722, 1 },
|
|
{AArch64_PTRUES_S, 723, 1 },
|
|
{AArch64_PTRUE_B, 724, 1 },
|
|
{AArch64_PTRUE_D, 725, 1 },
|
|
{AArch64_PTRUE_H, 726, 1 },
|
|
{AArch64_PTRUE_S, 727, 1 },
|
|
{AArch64_RET, 728, 1 },
|
|
{AArch64_SBCSWr, 729, 1 },
|
|
{AArch64_SBCSXr, 730, 1 },
|
|
{AArch64_SBCWr, 731, 1 },
|
|
{AArch64_SBCXr, 732, 1 },
|
|
{AArch64_SBFMWri, 733, 3 },
|
|
{AArch64_SBFMXri, 736, 4 },
|
|
{AArch64_SEL_PPPP, 740, 1 },
|
|
{AArch64_SEL_ZPZZ_B, 741, 1 },
|
|
{AArch64_SEL_ZPZZ_D, 742, 1 },
|
|
{AArch64_SEL_ZPZZ_H, 743, 1 },
|
|
{AArch64_SEL_ZPZZ_S, 744, 1 },
|
|
{AArch64_SMADDLrrr, 745, 1 },
|
|
{AArch64_SMSUBLrrr, 746, 1 },
|
|
{AArch64_SQDECB_XPiI, 747, 2 },
|
|
{AArch64_SQDECB_XPiWdI, 749, 2 },
|
|
{AArch64_SQDECD_XPiI, 751, 2 },
|
|
{AArch64_SQDECD_XPiWdI, 753, 2 },
|
|
{AArch64_SQDECD_ZPiI, 755, 2 },
|
|
{AArch64_SQDECH_XPiI, 757, 2 },
|
|
{AArch64_SQDECH_XPiWdI, 759, 2 },
|
|
{AArch64_SQDECH_ZPiI, 761, 2 },
|
|
{AArch64_SQDECW_XPiI, 763, 2 },
|
|
{AArch64_SQDECW_XPiWdI, 765, 2 },
|
|
{AArch64_SQDECW_ZPiI, 767, 2 },
|
|
{AArch64_SQINCB_XPiI, 769, 2 },
|
|
{AArch64_SQINCB_XPiWdI, 771, 2 },
|
|
{AArch64_SQINCD_XPiI, 773, 2 },
|
|
{AArch64_SQINCD_XPiWdI, 775, 2 },
|
|
{AArch64_SQINCD_ZPiI, 777, 2 },
|
|
{AArch64_SQINCH_XPiI, 779, 2 },
|
|
{AArch64_SQINCH_XPiWdI, 781, 2 },
|
|
{AArch64_SQINCH_ZPiI, 783, 2 },
|
|
{AArch64_SQINCW_XPiI, 785, 2 },
|
|
{AArch64_SQINCW_XPiWdI, 787, 2 },
|
|
{AArch64_SQINCW_ZPiI, 789, 2 },
|
|
{AArch64_SST1B_D_IMM, 791, 1 },
|
|
{AArch64_SST1B_S_IMM, 792, 1 },
|
|
{AArch64_SST1D_IMM, 793, 1 },
|
|
{AArch64_SST1H_D_IMM, 794, 1 },
|
|
{AArch64_SST1H_S_IMM, 795, 1 },
|
|
{AArch64_SST1Q, 796, 1 },
|
|
{AArch64_SST1W_D_IMM, 797, 1 },
|
|
{AArch64_SST1W_IMM, 798, 1 },
|
|
{AArch64_ST1B_2Z_IMM, 799, 1 },
|
|
{AArch64_ST1B_2Z_STRIDED_IMM, 800, 1 },
|
|
{AArch64_ST1B_4Z_IMM, 801, 1 },
|
|
{AArch64_ST1B_4Z_STRIDED_IMM, 802, 1 },
|
|
{AArch64_ST1B_D_IMM, 803, 1 },
|
|
{AArch64_ST1B_H_IMM, 804, 1 },
|
|
{AArch64_ST1B_IMM, 805, 1 },
|
|
{AArch64_ST1B_S_IMM, 806, 1 },
|
|
{AArch64_ST1D_2Z_IMM, 807, 1 },
|
|
{AArch64_ST1D_2Z_STRIDED_IMM, 808, 1 },
|
|
{AArch64_ST1D_4Z_IMM, 809, 1 },
|
|
{AArch64_ST1D_4Z_STRIDED_IMM, 810, 1 },
|
|
{AArch64_ST1D_IMM, 811, 1 },
|
|
{AArch64_ST1D_Q_IMM, 812, 1 },
|
|
{AArch64_ST1Fourv16b_POST, 813, 1 },
|
|
{AArch64_ST1Fourv1d_POST, 814, 1 },
|
|
{AArch64_ST1Fourv2d_POST, 815, 1 },
|
|
{AArch64_ST1Fourv2s_POST, 816, 1 },
|
|
{AArch64_ST1Fourv4h_POST, 817, 1 },
|
|
{AArch64_ST1Fourv4s_POST, 818, 1 },
|
|
{AArch64_ST1Fourv8b_POST, 819, 1 },
|
|
{AArch64_ST1Fourv8h_POST, 820, 1 },
|
|
{AArch64_ST1H_2Z_IMM, 821, 1 },
|
|
{AArch64_ST1H_2Z_STRIDED_IMM, 822, 1 },
|
|
{AArch64_ST1H_4Z_IMM, 823, 1 },
|
|
{AArch64_ST1H_4Z_STRIDED_IMM, 824, 1 },
|
|
{AArch64_ST1H_D_IMM, 825, 1 },
|
|
{AArch64_ST1H_IMM, 826, 1 },
|
|
{AArch64_ST1H_S_IMM, 827, 1 },
|
|
{AArch64_ST1Onev16b_POST, 828, 1 },
|
|
{AArch64_ST1Onev1d_POST, 829, 1 },
|
|
{AArch64_ST1Onev2d_POST, 830, 1 },
|
|
{AArch64_ST1Onev2s_POST, 831, 1 },
|
|
{AArch64_ST1Onev4h_POST, 832, 1 },
|
|
{AArch64_ST1Onev4s_POST, 833, 1 },
|
|
{AArch64_ST1Onev8b_POST, 834, 1 },
|
|
{AArch64_ST1Onev8h_POST, 835, 1 },
|
|
{AArch64_ST1Threev16b_POST, 836, 1 },
|
|
{AArch64_ST1Threev1d_POST, 837, 1 },
|
|
{AArch64_ST1Threev2d_POST, 838, 1 },
|
|
{AArch64_ST1Threev2s_POST, 839, 1 },
|
|
{AArch64_ST1Threev4h_POST, 840, 1 },
|
|
{AArch64_ST1Threev4s_POST, 841, 1 },
|
|
{AArch64_ST1Threev8b_POST, 842, 1 },
|
|
{AArch64_ST1Threev8h_POST, 843, 1 },
|
|
{AArch64_ST1Twov16b_POST, 844, 1 },
|
|
{AArch64_ST1Twov1d_POST, 845, 1 },
|
|
{AArch64_ST1Twov2d_POST, 846, 1 },
|
|
{AArch64_ST1Twov2s_POST, 847, 1 },
|
|
{AArch64_ST1Twov4h_POST, 848, 1 },
|
|
{AArch64_ST1Twov4s_POST, 849, 1 },
|
|
{AArch64_ST1Twov8b_POST, 850, 1 },
|
|
{AArch64_ST1Twov8h_POST, 851, 1 },
|
|
{AArch64_ST1W_2Z_IMM, 852, 1 },
|
|
{AArch64_ST1W_2Z_STRIDED_IMM, 853, 1 },
|
|
{AArch64_ST1W_4Z_IMM, 854, 1 },
|
|
{AArch64_ST1W_4Z_STRIDED_IMM, 855, 1 },
|
|
{AArch64_ST1W_D_IMM, 856, 1 },
|
|
{AArch64_ST1W_IMM, 857, 1 },
|
|
{AArch64_ST1W_Q_IMM, 858, 1 },
|
|
{AArch64_ST1_MXIPXX_H_B, 859, 1 },
|
|
{AArch64_ST1_MXIPXX_H_D, 860, 1 },
|
|
{AArch64_ST1_MXIPXX_H_H, 861, 1 },
|
|
{AArch64_ST1_MXIPXX_H_Q, 862, 1 },
|
|
{AArch64_ST1_MXIPXX_H_S, 863, 1 },
|
|
{AArch64_ST1_MXIPXX_V_B, 864, 1 },
|
|
{AArch64_ST1_MXIPXX_V_D, 865, 1 },
|
|
{AArch64_ST1_MXIPXX_V_H, 866, 1 },
|
|
{AArch64_ST1_MXIPXX_V_Q, 867, 1 },
|
|
{AArch64_ST1_MXIPXX_V_S, 868, 1 },
|
|
{AArch64_ST1i16_POST, 869, 1 },
|
|
{AArch64_ST1i32_POST, 870, 1 },
|
|
{AArch64_ST1i64_POST, 871, 1 },
|
|
{AArch64_ST1i8_POST, 872, 1 },
|
|
{AArch64_ST2B_IMM, 873, 1 },
|
|
{AArch64_ST2D_IMM, 874, 1 },
|
|
{AArch64_ST2Gi, 875, 1 },
|
|
{AArch64_ST2H_IMM, 876, 1 },
|
|
{AArch64_ST2Q_IMM, 877, 1 },
|
|
{AArch64_ST2Twov16b_POST, 878, 1 },
|
|
{AArch64_ST2Twov2d_POST, 879, 1 },
|
|
{AArch64_ST2Twov2s_POST, 880, 1 },
|
|
{AArch64_ST2Twov4h_POST, 881, 1 },
|
|
{AArch64_ST2Twov4s_POST, 882, 1 },
|
|
{AArch64_ST2Twov8b_POST, 883, 1 },
|
|
{AArch64_ST2Twov8h_POST, 884, 1 },
|
|
{AArch64_ST2W_IMM, 885, 1 },
|
|
{AArch64_ST2i16_POST, 886, 1 },
|
|
{AArch64_ST2i32_POST, 887, 1 },
|
|
{AArch64_ST2i64_POST, 888, 1 },
|
|
{AArch64_ST2i8_POST, 889, 1 },
|
|
{AArch64_ST3B_IMM, 890, 1 },
|
|
{AArch64_ST3D_IMM, 891, 1 },
|
|
{AArch64_ST3H_IMM, 892, 1 },
|
|
{AArch64_ST3Q_IMM, 893, 1 },
|
|
{AArch64_ST3Threev16b_POST, 894, 1 },
|
|
{AArch64_ST3Threev2d_POST, 895, 1 },
|
|
{AArch64_ST3Threev2s_POST, 896, 1 },
|
|
{AArch64_ST3Threev4h_POST, 897, 1 },
|
|
{AArch64_ST3Threev4s_POST, 898, 1 },
|
|
{AArch64_ST3Threev8b_POST, 899, 1 },
|
|
{AArch64_ST3Threev8h_POST, 900, 1 },
|
|
{AArch64_ST3W_IMM, 901, 1 },
|
|
{AArch64_ST3i16_POST, 902, 1 },
|
|
{AArch64_ST3i32_POST, 903, 1 },
|
|
{AArch64_ST3i64_POST, 904, 1 },
|
|
{AArch64_ST3i8_POST, 905, 1 },
|
|
{AArch64_ST4B_IMM, 906, 1 },
|
|
{AArch64_ST4D_IMM, 907, 1 },
|
|
{AArch64_ST4Fourv16b_POST, 908, 1 },
|
|
{AArch64_ST4Fourv2d_POST, 909, 1 },
|
|
{AArch64_ST4Fourv2s_POST, 910, 1 },
|
|
{AArch64_ST4Fourv4h_POST, 911, 1 },
|
|
{AArch64_ST4Fourv4s_POST, 912, 1 },
|
|
{AArch64_ST4Fourv8b_POST, 913, 1 },
|
|
{AArch64_ST4Fourv8h_POST, 914, 1 },
|
|
{AArch64_ST4H_IMM, 915, 1 },
|
|
{AArch64_ST4Q_IMM, 916, 1 },
|
|
{AArch64_ST4W_IMM, 917, 1 },
|
|
{AArch64_ST4i16_POST, 918, 1 },
|
|
{AArch64_ST4i32_POST, 919, 1 },
|
|
{AArch64_ST4i64_POST, 920, 1 },
|
|
{AArch64_ST4i8_POST, 921, 1 },
|
|
{AArch64_STGPi, 922, 1 },
|
|
{AArch64_STGi, 923, 1 },
|
|
{AArch64_STLURBi, 924, 1 },
|
|
{AArch64_STLURHi, 925, 1 },
|
|
{AArch64_STLURWi, 926, 1 },
|
|
{AArch64_STLURXi, 927, 1 },
|
|
{AArch64_STLURbi, 928, 1 },
|
|
{AArch64_STLURdi, 929, 1 },
|
|
{AArch64_STLURhi, 930, 1 },
|
|
{AArch64_STLURqi, 931, 1 },
|
|
{AArch64_STLURsi, 932, 1 },
|
|
{AArch64_STNPDi, 933, 1 },
|
|
{AArch64_STNPQi, 934, 1 },
|
|
{AArch64_STNPSi, 935, 1 },
|
|
{AArch64_STNPWi, 936, 1 },
|
|
{AArch64_STNPXi, 937, 1 },
|
|
{AArch64_STNT1B_2Z_IMM, 938, 1 },
|
|
{AArch64_STNT1B_2Z_STRIDED_IMM, 939, 1 },
|
|
{AArch64_STNT1B_4Z_IMM, 940, 1 },
|
|
{AArch64_STNT1B_4Z_STRIDED_IMM, 941, 1 },
|
|
{AArch64_STNT1B_ZRI, 942, 1 },
|
|
{AArch64_STNT1B_ZZR_D_REAL, 943, 1 },
|
|
{AArch64_STNT1B_ZZR_S_REAL, 944, 1 },
|
|
{AArch64_STNT1D_2Z_IMM, 945, 1 },
|
|
{AArch64_STNT1D_2Z_STRIDED_IMM, 946, 1 },
|
|
{AArch64_STNT1D_4Z_IMM, 947, 1 },
|
|
{AArch64_STNT1D_4Z_STRIDED_IMM, 948, 1 },
|
|
{AArch64_STNT1D_ZRI, 949, 1 },
|
|
{AArch64_STNT1D_ZZR_D_REAL, 950, 1 },
|
|
{AArch64_STNT1H_2Z_IMM, 951, 1 },
|
|
{AArch64_STNT1H_2Z_STRIDED_IMM, 952, 1 },
|
|
{AArch64_STNT1H_4Z_IMM, 953, 1 },
|
|
{AArch64_STNT1H_4Z_STRIDED_IMM, 954, 1 },
|
|
{AArch64_STNT1H_ZRI, 955, 1 },
|
|
{AArch64_STNT1H_ZZR_D_REAL, 956, 1 },
|
|
{AArch64_STNT1H_ZZR_S_REAL, 957, 1 },
|
|
{AArch64_STNT1W_2Z_IMM, 958, 1 },
|
|
{AArch64_STNT1W_2Z_STRIDED_IMM, 959, 1 },
|
|
{AArch64_STNT1W_4Z_IMM, 960, 1 },
|
|
{AArch64_STNT1W_4Z_STRIDED_IMM, 961, 1 },
|
|
{AArch64_STNT1W_ZRI, 962, 1 },
|
|
{AArch64_STNT1W_ZZR_D_REAL, 963, 1 },
|
|
{AArch64_STNT1W_ZZR_S_REAL, 964, 1 },
|
|
{AArch64_STPDi, 965, 1 },
|
|
{AArch64_STPQi, 966, 1 },
|
|
{AArch64_STPSi, 967, 1 },
|
|
{AArch64_STPWi, 968, 1 },
|
|
{AArch64_STPXi, 969, 1 },
|
|
{AArch64_STRBBroX, 970, 1 },
|
|
{AArch64_STRBBui, 971, 1 },
|
|
{AArch64_STRBroX, 972, 1 },
|
|
{AArch64_STRBui, 973, 1 },
|
|
{AArch64_STRDroX, 974, 1 },
|
|
{AArch64_STRDui, 975, 1 },
|
|
{AArch64_STRHHroX, 976, 1 },
|
|
{AArch64_STRHHui, 977, 1 },
|
|
{AArch64_STRHroX, 978, 1 },
|
|
{AArch64_STRHui, 979, 1 },
|
|
{AArch64_STRQroX, 980, 1 },
|
|
{AArch64_STRQui, 981, 1 },
|
|
{AArch64_STRSroX, 982, 1 },
|
|
{AArch64_STRSui, 983, 1 },
|
|
{AArch64_STRWroX, 984, 1 },
|
|
{AArch64_STRWui, 985, 1 },
|
|
{AArch64_STRXroX, 986, 1 },
|
|
{AArch64_STRXui, 987, 1 },
|
|
{AArch64_STR_PXI, 988, 1 },
|
|
{AArch64_STR_ZA, 989, 1 },
|
|
{AArch64_STR_ZXI, 990, 1 },
|
|
{AArch64_STTRBi, 991, 1 },
|
|
{AArch64_STTRHi, 992, 1 },
|
|
{AArch64_STTRWi, 993, 1 },
|
|
{AArch64_STTRXi, 994, 1 },
|
|
{AArch64_STURBBi, 995, 1 },
|
|
{AArch64_STURBi, 996, 1 },
|
|
{AArch64_STURDi, 997, 1 },
|
|
{AArch64_STURHHi, 998, 1 },
|
|
{AArch64_STURHi, 999, 1 },
|
|
{AArch64_STURQi, 1000, 1 },
|
|
{AArch64_STURSi, 1001, 1 },
|
|
{AArch64_STURWi, 1002, 1 },
|
|
{AArch64_STURXi, 1003, 1 },
|
|
{AArch64_STZ2Gi, 1004, 1 },
|
|
{AArch64_STZGi, 1005, 1 },
|
|
{AArch64_SUBPT_shift, 1006, 1 },
|
|
{AArch64_SUBSWri, 1007, 1 },
|
|
{AArch64_SUBSWrs, 1008, 5 },
|
|
{AArch64_SUBSWrx, 1013, 3 },
|
|
{AArch64_SUBSXri, 1016, 1 },
|
|
{AArch64_SUBSXrs, 1017, 5 },
|
|
{AArch64_SUBSXrx, 1022, 1 },
|
|
{AArch64_SUBSXrx64, 1023, 3 },
|
|
{AArch64_SUBWrs, 1026, 3 },
|
|
{AArch64_SUBWrx, 1029, 2 },
|
|
{AArch64_SUBXrs, 1031, 3 },
|
|
{AArch64_SUBXrx64, 1034, 2 },
|
|
{AArch64_SYSPxt_XZR, 1036, 1 },
|
|
{AArch64_SYSxt, 1037, 1 },
|
|
{AArch64_UBFMWri, 1038, 3 },
|
|
{AArch64_UBFMXri, 1041, 4 },
|
|
{AArch64_UMADDLrrr, 1045, 1 },
|
|
{AArch64_UMOVvi32, 1046, 1 },
|
|
{AArch64_UMOVvi32_idx0, 1047, 1 },
|
|
{AArch64_UMOVvi64, 1048, 1 },
|
|
{AArch64_UMOVvi64_idx0, 1049, 1 },
|
|
{AArch64_UMSUBLrrr, 1050, 1 },
|
|
{AArch64_UQDECB_WPiI, 1051, 2 },
|
|
{AArch64_UQDECB_XPiI, 1053, 2 },
|
|
{AArch64_UQDECD_WPiI, 1055, 2 },
|
|
{AArch64_UQDECD_XPiI, 1057, 2 },
|
|
{AArch64_UQDECD_ZPiI, 1059, 2 },
|
|
{AArch64_UQDECH_WPiI, 1061, 2 },
|
|
{AArch64_UQDECH_XPiI, 1063, 2 },
|
|
{AArch64_UQDECH_ZPiI, 1065, 2 },
|
|
{AArch64_UQDECW_WPiI, 1067, 2 },
|
|
{AArch64_UQDECW_XPiI, 1069, 2 },
|
|
{AArch64_UQDECW_ZPiI, 1071, 2 },
|
|
{AArch64_UQINCB_WPiI, 1073, 2 },
|
|
{AArch64_UQINCB_XPiI, 1075, 2 },
|
|
{AArch64_UQINCD_WPiI, 1077, 2 },
|
|
{AArch64_UQINCD_XPiI, 1079, 2 },
|
|
{AArch64_UQINCD_ZPiI, 1081, 2 },
|
|
{AArch64_UQINCH_WPiI, 1083, 2 },
|
|
{AArch64_UQINCH_XPiI, 1085, 2 },
|
|
{AArch64_UQINCH_ZPiI, 1087, 2 },
|
|
{AArch64_UQINCW_WPiI, 1089, 2 },
|
|
{AArch64_UQINCW_XPiI, 1091, 2 },
|
|
{AArch64_UQINCW_ZPiI, 1093, 2 },
|
|
{AArch64_XPACLRI, 1095, 1 },
|
|
{AArch64_ZERO_M, 1096, 15 },
|
|
{0}, };
|
|
|
|
static const AliasPattern Patterns[] = {
|
|
// AArch64_ADDPT_shift - 0
|
|
{0, 0, 4, 7 },
|
|
// AArch64_ADDSWri - 1
|
|
{17, 7, 4, 2 },
|
|
// AArch64_ADDSWrs - 2
|
|
{30, 9, 4, 4 },
|
|
{41, 13, 4, 3 },
|
|
{56, 16, 4, 4 },
|
|
// AArch64_ADDSWrx - 5
|
|
{30, 20, 4, 4 },
|
|
{72, 24, 4, 3 },
|
|
{56, 27, 4, 4 },
|
|
// AArch64_ADDSXri - 8
|
|
{17, 31, 4, 2 },
|
|
// AArch64_ADDSXrs - 9
|
|
{30, 33, 4, 4 },
|
|
{41, 37, 4, 3 },
|
|
{56, 40, 4, 4 },
|
|
// AArch64_ADDSXrx - 12
|
|
{72, 44, 4, 3 },
|
|
// AArch64_ADDSXrx64 - 13
|
|
{30, 47, 4, 4 },
|
|
{72, 51, 4, 3 },
|
|
{56, 54, 4, 4 },
|
|
// AArch64_ADDWri - 16
|
|
{87, 58, 4, 4 },
|
|
{87, 62, 4, 4 },
|
|
// AArch64_ADDWrs - 18
|
|
{98, 66, 4, 4 },
|
|
// AArch64_ADDWrx - 19
|
|
{98, 70, 4, 4 },
|
|
{98, 74, 4, 4 },
|
|
// AArch64_ADDXri - 21
|
|
{87, 78, 4, 4 },
|
|
{87, 82, 4, 4 },
|
|
// AArch64_ADDXrs - 23
|
|
{98, 86, 4, 4 },
|
|
// AArch64_ADDXrx64 - 24
|
|
{98, 90, 4, 4 },
|
|
{98, 94, 4, 4 },
|
|
// AArch64_ANDSWri - 26
|
|
{113, 98, 3, 2 },
|
|
// AArch64_ANDSWrs - 27
|
|
{126, 100, 4, 4 },
|
|
{137, 104, 4, 3 },
|
|
{152, 107, 4, 4 },
|
|
// AArch64_ANDSXri - 30
|
|
{168, 111, 3, 2 },
|
|
// AArch64_ANDSXrs - 31
|
|
{126, 113, 4, 4 },
|
|
{137, 117, 4, 3 },
|
|
{152, 120, 4, 4 },
|
|
// AArch64_ANDS_PPzPP - 34
|
|
{181, 124, 4, 8 },
|
|
// AArch64_ANDWrs - 35
|
|
{205, 132, 4, 4 },
|
|
// AArch64_ANDXrs - 36
|
|
{205, 136, 4, 4 },
|
|
// AArch64_AND_PPzPP - 37
|
|
{220, 140, 4, 8 },
|
|
// AArch64_AND_ZI - 38
|
|
{243, 148, 3, 7 },
|
|
{264, 155, 3, 7 },
|
|
{285, 162, 3, 7 },
|
|
// AArch64_AUTIA1716 - 41
|
|
{306, 169, 0, 3 },
|
|
// AArch64_AUTIASP - 42
|
|
{316, 172, 0, 3 },
|
|
// AArch64_AUTIAZ - 43
|
|
{324, 175, 0, 3 },
|
|
// AArch64_AUTIB1716 - 44
|
|
{331, 178, 0, 3 },
|
|
// AArch64_AUTIBSP - 45
|
|
{341, 181, 0, 3 },
|
|
// AArch64_AUTIBZ - 46
|
|
{349, 184, 0, 3 },
|
|
// AArch64_BICSWrs - 47
|
|
{356, 187, 4, 4 },
|
|
// AArch64_BICSXrs - 48
|
|
{356, 191, 4, 4 },
|
|
// AArch64_BICWrs - 49
|
|
{372, 195, 4, 4 },
|
|
// AArch64_BICXrs - 50
|
|
{372, 199, 4, 4 },
|
|
// AArch64_CHKFEAT - 51
|
|
{387, 203, 0, 3 },
|
|
// AArch64_CLREX - 52
|
|
{399, 206, 1, 1 },
|
|
// AArch64_CNTB_XPiI - 53
|
|
{405, 207, 3, 7 },
|
|
{413, 214, 3, 7 },
|
|
// AArch64_CNTD_XPiI - 55
|
|
{427, 221, 3, 7 },
|
|
{435, 228, 3, 7 },
|
|
// AArch64_CNTH_XPiI - 57
|
|
{449, 235, 3, 7 },
|
|
{457, 242, 3, 7 },
|
|
// AArch64_CNTW_XPiI - 59
|
|
{471, 249, 3, 7 },
|
|
{479, 256, 3, 7 },
|
|
// AArch64_CPY_ZPmI_B - 61
|
|
{493, 263, 5, 7 },
|
|
// AArch64_CPY_ZPmI_D - 62
|
|
{516, 270, 5, 7 },
|
|
// AArch64_CPY_ZPmI_H - 63
|
|
{539, 277, 5, 7 },
|
|
// AArch64_CPY_ZPmI_S - 64
|
|
{562, 284, 5, 7 },
|
|
// AArch64_CPY_ZPmR_B - 65
|
|
{585, 291, 4, 8 },
|
|
// AArch64_CPY_ZPmR_D - 66
|
|
{606, 299, 4, 8 },
|
|
// AArch64_CPY_ZPmR_H - 67
|
|
{627, 307, 4, 8 },
|
|
// AArch64_CPY_ZPmR_S - 68
|
|
{648, 315, 4, 8 },
|
|
// AArch64_CPY_ZPmV_B - 69
|
|
{585, 323, 4, 8 },
|
|
// AArch64_CPY_ZPmV_D - 70
|
|
{606, 331, 4, 8 },
|
|
// AArch64_CPY_ZPmV_H - 71
|
|
{627, 339, 4, 8 },
|
|
// AArch64_CPY_ZPmV_S - 72
|
|
{648, 347, 4, 8 },
|
|
// AArch64_CPY_ZPzI_B - 73
|
|
{669, 355, 4, 6 },
|
|
// AArch64_CPY_ZPzI_D - 74
|
|
{692, 361, 4, 6 },
|
|
// AArch64_CPY_ZPzI_H - 75
|
|
{715, 367, 4, 6 },
|
|
// AArch64_CPY_ZPzI_S - 76
|
|
{738, 373, 4, 6 },
|
|
// AArch64_CSINCWr - 77
|
|
{761, 379, 4, 4 },
|
|
{775, 383, 4, 4 },
|
|
// AArch64_CSINCXr - 79
|
|
{761, 387, 4, 4 },
|
|
{775, 391, 4, 4 },
|
|
// AArch64_CSINVWr - 81
|
|
{793, 395, 4, 4 },
|
|
{808, 399, 4, 4 },
|
|
// AArch64_CSINVXr - 83
|
|
{793, 403, 4, 4 },
|
|
{808, 407, 4, 4 },
|
|
// AArch64_CSNEGWr - 85
|
|
{826, 411, 4, 4 },
|
|
// AArch64_CSNEGXr - 86
|
|
{826, 415, 4, 4 },
|
|
// AArch64_DCPS1 - 87
|
|
{844, 419, 1, 1 },
|
|
// AArch64_DCPS2 - 88
|
|
{850, 420, 1, 1 },
|
|
// AArch64_DCPS3 - 89
|
|
{856, 421, 1, 4 },
|
|
// AArch64_DECB_XPiI - 90
|
|
{862, 425, 4, 8 },
|
|
{870, 433, 4, 8 },
|
|
// AArch64_DECD_XPiI - 92
|
|
{884, 441, 4, 8 },
|
|
{892, 449, 4, 8 },
|
|
// AArch64_DECD_ZPiI - 94
|
|
{906, 457, 4, 8 },
|
|
{916, 465, 4, 8 },
|
|
// AArch64_DECH_XPiI - 96
|
|
{932, 473, 4, 8 },
|
|
{940, 481, 4, 8 },
|
|
// AArch64_DECH_ZPiI - 98
|
|
{954, 489, 4, 8 },
|
|
{964, 497, 4, 8 },
|
|
// AArch64_DECW_XPiI - 100
|
|
{980, 505, 4, 8 },
|
|
{988, 513, 4, 8 },
|
|
// AArch64_DECW_ZPiI - 102
|
|
{1002, 521, 4, 8 },
|
|
{1012, 529, 4, 8 },
|
|
// AArch64_DSB - 104
|
|
{1028, 537, 1, 1 },
|
|
{1033, 538, 1, 1 },
|
|
{1039, 539, 1, 4 },
|
|
// AArch64_DUPM_ZI - 107
|
|
{1043, 543, 2, 6 },
|
|
{1058, 549, 2, 6 },
|
|
{1073, 555, 2, 6 },
|
|
{1088, 561, 2, 6 },
|
|
{1104, 567, 2, 6 },
|
|
{1120, 573, 2, 6 },
|
|
// AArch64_DUP_ZI_B - 113
|
|
{1136, 579, 3, 5 },
|
|
// AArch64_DUP_ZI_D - 114
|
|
{1151, 584, 3, 5 },
|
|
{1166, 589, 3, 7 },
|
|
// AArch64_DUP_ZI_H - 116
|
|
{1182, 596, 3, 5 },
|
|
{1197, 601, 3, 7 },
|
|
// AArch64_DUP_ZI_S - 118
|
|
{1213, 608, 3, 5 },
|
|
{1228, 613, 3, 7 },
|
|
// AArch64_DUP_ZR_B - 120
|
|
{1244, 620, 2, 6 },
|
|
// AArch64_DUP_ZR_D - 121
|
|
{1257, 626, 2, 6 },
|
|
// AArch64_DUP_ZR_H - 122
|
|
{1270, 632, 2, 6 },
|
|
// AArch64_DUP_ZR_S - 123
|
|
{1283, 638, 2, 6 },
|
|
// AArch64_DUP_ZZI_B - 124
|
|
{1296, 644, 3, 7 },
|
|
{1311, 651, 3, 6 },
|
|
// AArch64_DUP_ZZI_D - 126
|
|
{1330, 657, 3, 7 },
|
|
{1345, 664, 3, 6 },
|
|
// AArch64_DUP_ZZI_H - 128
|
|
{1364, 670, 3, 7 },
|
|
{1379, 677, 3, 6 },
|
|
// AArch64_DUP_ZZI_Q - 130
|
|
{1398, 683, 3, 7 },
|
|
{1413, 690, 3, 6 },
|
|
// AArch64_DUP_ZZI_S - 132
|
|
{1432, 696, 3, 7 },
|
|
{1447, 703, 3, 6 },
|
|
// AArch64_EONWrs - 134
|
|
{1466, 709, 4, 4 },
|
|
// AArch64_EONXrs - 135
|
|
{1466, 713, 4, 4 },
|
|
// AArch64_EORS_PPzPP - 136
|
|
{1481, 717, 4, 8 },
|
|
// AArch64_EORWrs - 137
|
|
{1505, 725, 4, 4 },
|
|
// AArch64_EORXrs - 138
|
|
{1505, 729, 4, 4 },
|
|
// AArch64_EOR_PPzPP - 139
|
|
{1520, 733, 4, 8 },
|
|
// AArch64_EOR_ZI - 140
|
|
{1543, 741, 3, 7 },
|
|
{1564, 748, 3, 7 },
|
|
{1585, 755, 3, 7 },
|
|
// AArch64_EXTRACT_ZPMXI_H_B - 143
|
|
{1606, 762, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_H_D - 144
|
|
{1639, 770, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_H_H - 145
|
|
{1672, 778, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_H_Q - 146
|
|
{1705, 786, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_H_S - 147
|
|
{1738, 794, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_V_B - 148
|
|
{1771, 802, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_V_D - 149
|
|
{1804, 810, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_V_H - 150
|
|
{1837, 818, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_V_Q - 151
|
|
{1870, 826, 6, 8 },
|
|
// AArch64_EXTRACT_ZPMXI_V_S - 152
|
|
{1903, 834, 6, 8 },
|
|
// AArch64_EXTRWrri - 153
|
|
{1936, 842, 4, 3 },
|
|
// AArch64_EXTRXrri - 154
|
|
{1936, 845, 4, 3 },
|
|
// AArch64_FCPY_ZPmI_D - 155
|
|
{1951, 848, 4, 7 },
|
|
// AArch64_FCPY_ZPmI_H - 156
|
|
{1975, 855, 4, 7 },
|
|
// AArch64_FCPY_ZPmI_S - 157
|
|
{1999, 862, 4, 7 },
|
|
// AArch64_FDUP_ZI_D - 158
|
|
{2023, 869, 2, 5 },
|
|
// AArch64_FDUP_ZI_H - 159
|
|
{2039, 874, 2, 5 },
|
|
// AArch64_FDUP_ZI_S - 160
|
|
{2055, 879, 2, 5 },
|
|
// AArch64_GCSPOPM - 161
|
|
{2071, 884, 1, 4 },
|
|
// AArch64_GLD1B_D_IMM_REAL - 162
|
|
{2079, 888, 4, 7 },
|
|
// AArch64_GLD1B_S_IMM_REAL - 163
|
|
{2105, 895, 4, 7 },
|
|
// AArch64_GLD1D_IMM_REAL - 164
|
|
{2131, 902, 4, 7 },
|
|
// AArch64_GLD1H_D_IMM_REAL - 165
|
|
{2157, 909, 4, 7 },
|
|
// AArch64_GLD1H_S_IMM_REAL - 166
|
|
{2183, 916, 4, 7 },
|
|
// AArch64_GLD1Q - 167
|
|
{2209, 923, 4, 7 },
|
|
// AArch64_GLD1SB_D_IMM_REAL - 168
|
|
{2235, 930, 4, 7 },
|
|
// AArch64_GLD1SB_S_IMM_REAL - 169
|
|
{2262, 937, 4, 7 },
|
|
// AArch64_GLD1SH_D_IMM_REAL - 170
|
|
{2289, 944, 4, 7 },
|
|
// AArch64_GLD1SH_S_IMM_REAL - 171
|
|
{2316, 951, 4, 7 },
|
|
// AArch64_GLD1SW_D_IMM_REAL - 172
|
|
{2343, 958, 4, 7 },
|
|
// AArch64_GLD1W_D_IMM_REAL - 173
|
|
{2370, 965, 4, 7 },
|
|
// AArch64_GLD1W_IMM_REAL - 174
|
|
{2396, 972, 4, 7 },
|
|
// AArch64_GLDFF1B_D_IMM_REAL - 175
|
|
{2422, 979, 4, 7 },
|
|
// AArch64_GLDFF1B_S_IMM_REAL - 176
|
|
{2450, 986, 4, 7 },
|
|
// AArch64_GLDFF1D_IMM_REAL - 177
|
|
{2478, 993, 4, 7 },
|
|
// AArch64_GLDFF1H_D_IMM_REAL - 178
|
|
{2506, 1000, 4, 7 },
|
|
// AArch64_GLDFF1H_S_IMM_REAL - 179
|
|
{2534, 1007, 4, 7 },
|
|
// AArch64_GLDFF1SB_D_IMM_REAL - 180
|
|
{2562, 1014, 4, 7 },
|
|
// AArch64_GLDFF1SB_S_IMM_REAL - 181
|
|
{2591, 1021, 4, 7 },
|
|
// AArch64_GLDFF1SH_D_IMM_REAL - 182
|
|
{2620, 1028, 4, 7 },
|
|
// AArch64_GLDFF1SH_S_IMM_REAL - 183
|
|
{2649, 1035, 4, 7 },
|
|
// AArch64_GLDFF1SW_D_IMM_REAL - 184
|
|
{2678, 1042, 4, 7 },
|
|
// AArch64_GLDFF1W_D_IMM_REAL - 185
|
|
{2707, 1049, 4, 7 },
|
|
// AArch64_GLDFF1W_IMM_REAL - 186
|
|
{2735, 1056, 4, 7 },
|
|
// AArch64_HINT - 187
|
|
{2763, 1063, 1, 1 },
|
|
{2767, 1064, 1, 1 },
|
|
{2773, 1065, 1, 1 },
|
|
{2777, 1066, 1, 1 },
|
|
{2781, 1067, 1, 1 },
|
|
{2785, 1068, 1, 1 },
|
|
{2790, 1069, 1, 1 },
|
|
{2794, 1070, 1, 4 },
|
|
{2798, 1074, 1, 1 },
|
|
{2803, 1075, 1, 4 },
|
|
{2807, 1079, 1, 4 },
|
|
{2816, 1083, 1, 4 },
|
|
{2825, 1087, 1, 4 },
|
|
{2836, 1091, 1, 4 },
|
|
// AArch64_INCB_XPiI - 201
|
|
{2843, 1095, 4, 8 },
|
|
{2851, 1103, 4, 8 },
|
|
// AArch64_INCD_XPiI - 203
|
|
{2865, 1111, 4, 8 },
|
|
{2873, 1119, 4, 8 },
|
|
// AArch64_INCD_ZPiI - 205
|
|
{2887, 1127, 4, 8 },
|
|
{2897, 1135, 4, 8 },
|
|
// AArch64_INCH_XPiI - 207
|
|
{2913, 1143, 4, 8 },
|
|
{2921, 1151, 4, 8 },
|
|
// AArch64_INCH_ZPiI - 209
|
|
{2935, 1159, 4, 8 },
|
|
{2945, 1167, 4, 8 },
|
|
// AArch64_INCW_XPiI - 211
|
|
{2961, 1175, 4, 8 },
|
|
{2969, 1183, 4, 8 },
|
|
// AArch64_INCW_ZPiI - 213
|
|
{2983, 1191, 4, 8 },
|
|
{2993, 1199, 4, 8 },
|
|
// AArch64_INSERT_MXIPZ_H_B - 215
|
|
{3009, 1207, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_H_D - 216
|
|
{3042, 1216, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_H_H - 217
|
|
{3075, 1225, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_H_Q - 218
|
|
{3108, 1234, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_H_S - 219
|
|
{3141, 1243, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_V_B - 220
|
|
{3174, 1252, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_V_D - 221
|
|
{3207, 1261, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_V_H - 222
|
|
{3240, 1270, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_V_Q - 223
|
|
{3273, 1279, 6, 9 },
|
|
// AArch64_INSERT_MXIPZ_V_S - 224
|
|
{3306, 1288, 6, 9 },
|
|
// AArch64_INSvi16gpr - 225
|
|
{3339, 1297, 4, 7 },
|
|
// AArch64_INSvi16lane - 226
|
|
{3358, 1304, 5, 7 },
|
|
// AArch64_INSvi32gpr - 227
|
|
{3385, 1311, 4, 7 },
|
|
// AArch64_INSvi32lane - 228
|
|
{3404, 1318, 5, 7 },
|
|
// AArch64_INSvi64gpr - 229
|
|
{3431, 1325, 4, 7 },
|
|
// AArch64_INSvi64lane - 230
|
|
{3450, 1332, 5, 7 },
|
|
// AArch64_INSvi8gpr - 231
|
|
{3477, 1339, 4, 7 },
|
|
// AArch64_INSvi8lane - 232
|
|
{3496, 1346, 5, 7 },
|
|
// AArch64_IRG - 233
|
|
{3523, 1353, 3, 6 },
|
|
// AArch64_ISB - 234
|
|
{3534, 1359, 1, 1 },
|
|
// AArch64_LD1B_2Z_IMM - 235
|
|
{3538, 1360, 4, 8 },
|
|
// AArch64_LD1B_2Z_STRIDED_IMM - 236
|
|
{3562, 1368, 4, 7 },
|
|
// AArch64_LD1B_4Z_IMM - 237
|
|
{3538, 1375, 4, 8 },
|
|
// AArch64_LD1B_4Z_STRIDED_IMM - 238
|
|
{3586, 1383, 4, 7 },
|
|
// AArch64_LD1B_D_IMM - 239
|
|
{3610, 1390, 4, 8 },
|
|
// AArch64_LD1B_H_IMM - 240
|
|
{3634, 1398, 4, 8 },
|
|
// AArch64_LD1B_IMM - 241
|
|
{3658, 1406, 4, 8 },
|
|
// AArch64_LD1B_S_IMM - 242
|
|
{3682, 1414, 4, 8 },
|
|
// AArch64_LD1D_2Z_IMM - 243
|
|
{3706, 1422, 4, 8 },
|
|
// AArch64_LD1D_2Z_STRIDED_IMM - 244
|
|
{3730, 1430, 4, 7 },
|
|
// AArch64_LD1D_4Z_IMM - 245
|
|
{3706, 1437, 4, 8 },
|
|
// AArch64_LD1D_4Z_STRIDED_IMM - 246
|
|
{3730, 1445, 4, 7 },
|
|
// AArch64_LD1D_IMM - 247
|
|
{3754, 1452, 4, 8 },
|
|
// AArch64_LD1D_Q_IMM - 248
|
|
{3778, 1460, 4, 7 },
|
|
// AArch64_LD1Fourv16b_POST - 249
|
|
{3802, 1467, 4, 7 },
|
|
// AArch64_LD1Fourv1d_POST - 250
|
|
{3822, 1474, 4, 7 },
|
|
// AArch64_LD1Fourv2d_POST - 251
|
|
{3842, 1481, 4, 7 },
|
|
// AArch64_LD1Fourv2s_POST - 252
|
|
{3862, 1488, 4, 7 },
|
|
// AArch64_LD1Fourv4h_POST - 253
|
|
{3882, 1495, 4, 7 },
|
|
// AArch64_LD1Fourv4s_POST - 254
|
|
{3902, 1502, 4, 7 },
|
|
// AArch64_LD1Fourv8b_POST - 255
|
|
{3922, 1509, 4, 7 },
|
|
// AArch64_LD1Fourv8h_POST - 256
|
|
{3942, 1516, 4, 7 },
|
|
// AArch64_LD1H_2Z_IMM - 257
|
|
{3962, 1523, 4, 8 },
|
|
// AArch64_LD1H_2Z_STRIDED_IMM - 258
|
|
{3986, 1531, 4, 7 },
|
|
// AArch64_LD1H_4Z_IMM - 259
|
|
{3962, 1538, 4, 8 },
|
|
// AArch64_LD1H_4Z_STRIDED_IMM - 260
|
|
{4010, 1546, 4, 7 },
|
|
// AArch64_LD1H_D_IMM - 261
|
|
{4034, 1553, 4, 8 },
|
|
// AArch64_LD1H_IMM - 262
|
|
{4058, 1561, 4, 8 },
|
|
// AArch64_LD1H_S_IMM - 263
|
|
{4082, 1569, 4, 8 },
|
|
// AArch64_LD1Onev16b_POST - 264
|
|
{4106, 1577, 4, 7 },
|
|
// AArch64_LD1Onev1d_POST - 265
|
|
{4126, 1584, 4, 7 },
|
|
// AArch64_LD1Onev2d_POST - 266
|
|
{4145, 1591, 4, 7 },
|
|
// AArch64_LD1Onev2s_POST - 267
|
|
{4165, 1598, 4, 7 },
|
|
// AArch64_LD1Onev4h_POST - 268
|
|
{4184, 1605, 4, 7 },
|
|
// AArch64_LD1Onev4s_POST - 269
|
|
{4203, 1612, 4, 7 },
|
|
// AArch64_LD1Onev8b_POST - 270
|
|
{4223, 1619, 4, 7 },
|
|
// AArch64_LD1Onev8h_POST - 271
|
|
{4242, 1626, 4, 7 },
|
|
// AArch64_LD1RB_D_IMM - 272
|
|
{4262, 1633, 4, 8 },
|
|
// AArch64_LD1RB_H_IMM - 273
|
|
{4287, 1641, 4, 8 },
|
|
// AArch64_LD1RB_IMM - 274
|
|
{4312, 1649, 4, 8 },
|
|
// AArch64_LD1RB_S_IMM - 275
|
|
{4337, 1657, 4, 8 },
|
|
// AArch64_LD1RD_IMM - 276
|
|
{4362, 1665, 4, 8 },
|
|
// AArch64_LD1RH_D_IMM - 277
|
|
{4387, 1673, 4, 8 },
|
|
// AArch64_LD1RH_IMM - 278
|
|
{4412, 1681, 4, 8 },
|
|
// AArch64_LD1RH_S_IMM - 279
|
|
{4437, 1689, 4, 8 },
|
|
// AArch64_LD1RO_B_IMM - 280
|
|
{4462, 1697, 4, 10 },
|
|
// AArch64_LD1RO_D_IMM - 281
|
|
{4488, 1707, 4, 10 },
|
|
// AArch64_LD1RO_H_IMM - 282
|
|
{4514, 1717, 4, 10 },
|
|
// AArch64_LD1RO_W_IMM - 283
|
|
{4540, 1727, 4, 10 },
|
|
// AArch64_LD1RQ_B_IMM - 284
|
|
{4566, 1737, 4, 8 },
|
|
// AArch64_LD1RQ_D_IMM - 285
|
|
{4592, 1745, 4, 8 },
|
|
// AArch64_LD1RQ_H_IMM - 286
|
|
{4618, 1753, 4, 8 },
|
|
// AArch64_LD1RQ_W_IMM - 287
|
|
{4644, 1761, 4, 8 },
|
|
// AArch64_LD1RSB_D_IMM - 288
|
|
{4670, 1769, 4, 8 },
|
|
// AArch64_LD1RSB_H_IMM - 289
|
|
{4696, 1777, 4, 8 },
|
|
// AArch64_LD1RSB_S_IMM - 290
|
|
{4722, 1785, 4, 8 },
|
|
// AArch64_LD1RSH_D_IMM - 291
|
|
{4748, 1793, 4, 8 },
|
|
// AArch64_LD1RSH_S_IMM - 292
|
|
{4774, 1801, 4, 8 },
|
|
// AArch64_LD1RSW_IMM - 293
|
|
{4800, 1809, 4, 8 },
|
|
// AArch64_LD1RW_D_IMM - 294
|
|
{4826, 1817, 4, 8 },
|
|
// AArch64_LD1RW_IMM - 295
|
|
{4851, 1825, 4, 8 },
|
|
// AArch64_LD1Rv16b_POST - 296
|
|
{4876, 1833, 4, 7 },
|
|
// AArch64_LD1Rv1d_POST - 297
|
|
{4896, 1840, 4, 7 },
|
|
// AArch64_LD1Rv2d_POST - 298
|
|
{4916, 1847, 4, 7 },
|
|
// AArch64_LD1Rv2s_POST - 299
|
|
{4936, 1854, 4, 7 },
|
|
// AArch64_LD1Rv4h_POST - 300
|
|
{4956, 1861, 4, 7 },
|
|
// AArch64_LD1Rv4s_POST - 301
|
|
{4976, 1868, 4, 7 },
|
|
// AArch64_LD1Rv8b_POST - 302
|
|
{4996, 1875, 4, 7 },
|
|
// AArch64_LD1Rv8h_POST - 303
|
|
{5016, 1882, 4, 7 },
|
|
// AArch64_LD1SB_D_IMM - 304
|
|
{5036, 1889, 4, 8 },
|
|
// AArch64_LD1SB_H_IMM - 305
|
|
{5061, 1897, 4, 8 },
|
|
// AArch64_LD1SB_S_IMM - 306
|
|
{5086, 1905, 4, 8 },
|
|
// AArch64_LD1SH_D_IMM - 307
|
|
{5111, 1913, 4, 8 },
|
|
// AArch64_LD1SH_S_IMM - 308
|
|
{5136, 1921, 4, 8 },
|
|
// AArch64_LD1SW_D_IMM - 309
|
|
{5161, 1929, 4, 8 },
|
|
// AArch64_LD1Threev16b_POST - 310
|
|
{5186, 1937, 4, 7 },
|
|
// AArch64_LD1Threev1d_POST - 311
|
|
{5206, 1944, 4, 7 },
|
|
// AArch64_LD1Threev2d_POST - 312
|
|
{5226, 1951, 4, 7 },
|
|
// AArch64_LD1Threev2s_POST - 313
|
|
{5246, 1958, 4, 7 },
|
|
// AArch64_LD1Threev4h_POST - 314
|
|
{5266, 1965, 4, 7 },
|
|
// AArch64_LD1Threev4s_POST - 315
|
|
{5286, 1972, 4, 7 },
|
|
// AArch64_LD1Threev8b_POST - 316
|
|
{5306, 1979, 4, 7 },
|
|
// AArch64_LD1Threev8h_POST - 317
|
|
{5326, 1986, 4, 7 },
|
|
// AArch64_LD1Twov16b_POST - 318
|
|
{5346, 1993, 4, 7 },
|
|
// AArch64_LD1Twov1d_POST - 319
|
|
{5366, 2000, 4, 7 },
|
|
// AArch64_LD1Twov2d_POST - 320
|
|
{5386, 2007, 4, 7 },
|
|
// AArch64_LD1Twov2s_POST - 321
|
|
{5406, 2014, 4, 7 },
|
|
// AArch64_LD1Twov4h_POST - 322
|
|
{5426, 2021, 4, 7 },
|
|
// AArch64_LD1Twov4s_POST - 323
|
|
{5446, 2028, 4, 7 },
|
|
// AArch64_LD1Twov8b_POST - 324
|
|
{5466, 2035, 4, 7 },
|
|
// AArch64_LD1Twov8h_POST - 325
|
|
{5486, 2042, 4, 7 },
|
|
// AArch64_LD1W_2Z_IMM - 326
|
|
{5506, 2049, 4, 8 },
|
|
// AArch64_LD1W_2Z_STRIDED_IMM - 327
|
|
{5530, 2057, 4, 7 },
|
|
// AArch64_LD1W_4Z_IMM - 328
|
|
{5506, 2064, 4, 8 },
|
|
// AArch64_LD1W_4Z_STRIDED_IMM - 329
|
|
{5530, 2072, 4, 7 },
|
|
// AArch64_LD1W_D_IMM - 330
|
|
{5554, 2079, 4, 8 },
|
|
// AArch64_LD1W_IMM - 331
|
|
{5578, 2087, 4, 8 },
|
|
// AArch64_LD1W_Q_IMM - 332
|
|
{5602, 2095, 4, 7 },
|
|
// AArch64_LD1_MXIPXX_H_B - 333
|
|
{5626, 2102, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_H_D - 334
|
|
{5662, 2111, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_H_H - 335
|
|
{5698, 2120, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_H_Q - 336
|
|
{5734, 2129, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_H_S - 337
|
|
{5770, 2138, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_V_B - 338
|
|
{5806, 2147, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_V_D - 339
|
|
{5842, 2156, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_V_H - 340
|
|
{5878, 2165, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_V_Q - 341
|
|
{5914, 2174, 6, 9 },
|
|
// AArch64_LD1_MXIPXX_V_S - 342
|
|
{5950, 2183, 6, 9 },
|
|
// AArch64_LD1i16_POST - 343
|
|
{5986, 2192, 6, 9 },
|
|
// AArch64_LD1i32_POST - 344
|
|
{6009, 2201, 6, 9 },
|
|
// AArch64_LD1i64_POST - 345
|
|
{6032, 2210, 6, 9 },
|
|
// AArch64_LD1i8_POST - 346
|
|
{6055, 2219, 6, 9 },
|
|
// AArch64_LD2B_IMM - 347
|
|
{6078, 2228, 4, 8 },
|
|
// AArch64_LD2D_IMM - 348
|
|
{6102, 2236, 4, 8 },
|
|
// AArch64_LD2H_IMM - 349
|
|
{6126, 2244, 4, 8 },
|
|
// AArch64_LD2Q_IMM - 350
|
|
{6150, 2252, 4, 8 },
|
|
// AArch64_LD2Rv16b_POST - 351
|
|
{6174, 2260, 4, 7 },
|
|
// AArch64_LD2Rv1d_POST - 352
|
|
{6194, 2267, 4, 7 },
|
|
// AArch64_LD2Rv2d_POST - 353
|
|
{6215, 2274, 4, 7 },
|
|
// AArch64_LD2Rv2s_POST - 354
|
|
{6236, 2281, 4, 7 },
|
|
// AArch64_LD2Rv4h_POST - 355
|
|
{6256, 2288, 4, 7 },
|
|
// AArch64_LD2Rv4s_POST - 356
|
|
{6276, 2295, 4, 7 },
|
|
// AArch64_LD2Rv8b_POST - 357
|
|
{6296, 2302, 4, 7 },
|
|
// AArch64_LD2Rv8h_POST - 358
|
|
{6316, 2309, 4, 7 },
|
|
// AArch64_LD2Twov16b_POST - 359
|
|
{6336, 2316, 4, 7 },
|
|
// AArch64_LD2Twov2d_POST - 360
|
|
{6356, 2323, 4, 7 },
|
|
// AArch64_LD2Twov2s_POST - 361
|
|
{6376, 2330, 4, 7 },
|
|
// AArch64_LD2Twov4h_POST - 362
|
|
{6396, 2337, 4, 7 },
|
|
// AArch64_LD2Twov4s_POST - 363
|
|
{6416, 2344, 4, 7 },
|
|
// AArch64_LD2Twov8b_POST - 364
|
|
{6436, 2351, 4, 7 },
|
|
// AArch64_LD2Twov8h_POST - 365
|
|
{6456, 2358, 4, 7 },
|
|
// AArch64_LD2W_IMM - 366
|
|
{6476, 2365, 4, 8 },
|
|
// AArch64_LD2i16_POST - 367
|
|
{6500, 2373, 6, 9 },
|
|
// AArch64_LD2i32_POST - 368
|
|
{6523, 2382, 6, 9 },
|
|
// AArch64_LD2i64_POST - 369
|
|
{6546, 2391, 6, 9 },
|
|
// AArch64_LD2i8_POST - 370
|
|
{6570, 2400, 6, 9 },
|
|
// AArch64_LD3B_IMM - 371
|
|
{6593, 2409, 4, 8 },
|
|
// AArch64_LD3D_IMM - 372
|
|
{6617, 2417, 4, 8 },
|
|
// AArch64_LD3H_IMM - 373
|
|
{6641, 2425, 4, 8 },
|
|
// AArch64_LD3Q_IMM - 374
|
|
{6665, 2433, 4, 8 },
|
|
// AArch64_LD3Rv16b_POST - 375
|
|
{6689, 2441, 4, 7 },
|
|
// AArch64_LD3Rv1d_POST - 376
|
|
{6709, 2448, 4, 7 },
|
|
// AArch64_LD3Rv2d_POST - 377
|
|
{6730, 2455, 4, 7 },
|
|
// AArch64_LD3Rv2s_POST - 378
|
|
{6751, 2462, 4, 7 },
|
|
// AArch64_LD3Rv4h_POST - 379
|
|
{6772, 2469, 4, 7 },
|
|
// AArch64_LD3Rv4s_POST - 380
|
|
{6792, 2476, 4, 7 },
|
|
// AArch64_LD3Rv8b_POST - 381
|
|
{6813, 2483, 4, 7 },
|
|
// AArch64_LD3Rv8h_POST - 382
|
|
{6833, 2490, 4, 7 },
|
|
// AArch64_LD3Threev16b_POST - 383
|
|
{6853, 2497, 4, 7 },
|
|
// AArch64_LD3Threev2d_POST - 384
|
|
{6873, 2504, 4, 7 },
|
|
// AArch64_LD3Threev2s_POST - 385
|
|
{6893, 2511, 4, 7 },
|
|
// AArch64_LD3Threev4h_POST - 386
|
|
{6913, 2518, 4, 7 },
|
|
// AArch64_LD3Threev4s_POST - 387
|
|
{6933, 2525, 4, 7 },
|
|
// AArch64_LD3Threev8b_POST - 388
|
|
{6953, 2532, 4, 7 },
|
|
// AArch64_LD3Threev8h_POST - 389
|
|
{6973, 2539, 4, 7 },
|
|
// AArch64_LD3W_IMM - 390
|
|
{6993, 2546, 4, 8 },
|
|
// AArch64_LD3i16_POST - 391
|
|
{7017, 2554, 6, 9 },
|
|
// AArch64_LD3i32_POST - 392
|
|
{7040, 2563, 6, 9 },
|
|
// AArch64_LD3i64_POST - 393
|
|
{7064, 2572, 6, 9 },
|
|
// AArch64_LD3i8_POST - 394
|
|
{7088, 2581, 6, 9 },
|
|
// AArch64_LD4B_IMM - 395
|
|
{7111, 2590, 4, 8 },
|
|
// AArch64_LD4D_IMM - 396
|
|
{7135, 2598, 4, 8 },
|
|
// AArch64_LD4Fourv16b_POST - 397
|
|
{7159, 2606, 4, 7 },
|
|
// AArch64_LD4Fourv2d_POST - 398
|
|
{7179, 2613, 4, 7 },
|
|
// AArch64_LD4Fourv2s_POST - 399
|
|
{7199, 2620, 4, 7 },
|
|
// AArch64_LD4Fourv4h_POST - 400
|
|
{7219, 2627, 4, 7 },
|
|
// AArch64_LD4Fourv4s_POST - 401
|
|
{7239, 2634, 4, 7 },
|
|
// AArch64_LD4Fourv8b_POST - 402
|
|
{7259, 2641, 4, 7 },
|
|
// AArch64_LD4Fourv8h_POST - 403
|
|
{7279, 2648, 4, 7 },
|
|
// AArch64_LD4H_IMM - 404
|
|
{7299, 2655, 4, 8 },
|
|
// AArch64_LD4Q_IMM - 405
|
|
{7323, 2663, 4, 8 },
|
|
// AArch64_LD4Rv16b_POST - 406
|
|
{7347, 2671, 4, 7 },
|
|
// AArch64_LD4Rv1d_POST - 407
|
|
{7367, 2678, 4, 7 },
|
|
// AArch64_LD4Rv2d_POST - 408
|
|
{7388, 2685, 4, 7 },
|
|
// AArch64_LD4Rv2s_POST - 409
|
|
{7409, 2692, 4, 7 },
|
|
// AArch64_LD4Rv4h_POST - 410
|
|
{7430, 2699, 4, 7 },
|
|
// AArch64_LD4Rv4s_POST - 411
|
|
{7450, 2706, 4, 7 },
|
|
// AArch64_LD4Rv8b_POST - 412
|
|
{7471, 2713, 4, 7 },
|
|
// AArch64_LD4Rv8h_POST - 413
|
|
{7491, 2720, 4, 7 },
|
|
// AArch64_LD4W_IMM - 414
|
|
{7511, 2727, 4, 8 },
|
|
// AArch64_LD4i16_POST - 415
|
|
{7535, 2735, 6, 9 },
|
|
// AArch64_LD4i32_POST - 416
|
|
{7558, 2744, 6, 9 },
|
|
// AArch64_LD4i64_POST - 417
|
|
{7582, 2753, 6, 9 },
|
|
// AArch64_LD4i8_POST - 418
|
|
{7606, 2762, 6, 9 },
|
|
// AArch64_LDADDB - 419
|
|
{7629, 2771, 3, 6 },
|
|
// AArch64_LDADDH - 420
|
|
{7645, 2777, 3, 6 },
|
|
// AArch64_LDADDLB - 421
|
|
{7661, 2783, 3, 6 },
|
|
// AArch64_LDADDLH - 422
|
|
{7678, 2789, 3, 6 },
|
|
// AArch64_LDADDLW - 423
|
|
{7695, 2795, 3, 6 },
|
|
// AArch64_LDADDLX - 424
|
|
{7695, 2801, 3, 6 },
|
|
// AArch64_LDADDW - 425
|
|
{7711, 2807, 3, 6 },
|
|
// AArch64_LDADDX - 426
|
|
{7711, 2813, 3, 6 },
|
|
// AArch64_LDAPURBi - 427
|
|
{7726, 2819, 3, 6 },
|
|
// AArch64_LDAPURHi - 428
|
|
{7743, 2825, 3, 6 },
|
|
// AArch64_LDAPURSBWi - 429
|
|
{7760, 2831, 3, 6 },
|
|
// AArch64_LDAPURSBXi - 430
|
|
{7760, 2837, 3, 6 },
|
|
// AArch64_LDAPURSHWi - 431
|
|
{7778, 2843, 3, 6 },
|
|
// AArch64_LDAPURSHXi - 432
|
|
{7778, 2849, 3, 6 },
|
|
// AArch64_LDAPURSWi - 433
|
|
{7796, 2855, 3, 6 },
|
|
// AArch64_LDAPURXi - 434
|
|
{7814, 2861, 3, 6 },
|
|
// AArch64_LDAPURbi - 435
|
|
{7814, 2867, 3, 9 },
|
|
// AArch64_LDAPURdi - 436
|
|
{7814, 2876, 3, 9 },
|
|
// AArch64_LDAPURhi - 437
|
|
{7814, 2885, 3, 9 },
|
|
// AArch64_LDAPURi - 438
|
|
{7814, 2894, 3, 6 },
|
|
// AArch64_LDAPURqi - 439
|
|
{7814, 2900, 3, 9 },
|
|
// AArch64_LDAPURsi - 440
|
|
{7814, 2909, 3, 9 },
|
|
// AArch64_LDCLRB - 441
|
|
{7830, 2918, 3, 6 },
|
|
// AArch64_LDCLRH - 442
|
|
{7846, 2924, 3, 6 },
|
|
// AArch64_LDCLRLB - 443
|
|
{7862, 2930, 3, 6 },
|
|
// AArch64_LDCLRLH - 444
|
|
{7879, 2936, 3, 6 },
|
|
// AArch64_LDCLRLW - 445
|
|
{7896, 2942, 3, 6 },
|
|
// AArch64_LDCLRLX - 446
|
|
{7896, 2948, 3, 6 },
|
|
// AArch64_LDCLRW - 447
|
|
{7912, 2954, 3, 6 },
|
|
// AArch64_LDCLRX - 448
|
|
{7912, 2960, 3, 6 },
|
|
// AArch64_LDEORB - 449
|
|
{7927, 2966, 3, 6 },
|
|
// AArch64_LDEORH - 450
|
|
{7943, 2972, 3, 6 },
|
|
// AArch64_LDEORLB - 451
|
|
{7959, 2978, 3, 6 },
|
|
// AArch64_LDEORLH - 452
|
|
{7976, 2984, 3, 6 },
|
|
// AArch64_LDEORLW - 453
|
|
{7993, 2990, 3, 6 },
|
|
// AArch64_LDEORLX - 454
|
|
{7993, 2996, 3, 6 },
|
|
// AArch64_LDEORW - 455
|
|
{8009, 3002, 3, 6 },
|
|
// AArch64_LDEORX - 456
|
|
{8009, 3008, 3, 6 },
|
|
// AArch64_LDFF1B_D_REAL - 457
|
|
{8024, 3014, 4, 7 },
|
|
// AArch64_LDFF1B_H_REAL - 458
|
|
{8050, 3021, 4, 7 },
|
|
// AArch64_LDFF1B_REAL - 459
|
|
{8076, 3028, 4, 7 },
|
|
// AArch64_LDFF1B_S_REAL - 460
|
|
{8102, 3035, 4, 7 },
|
|
// AArch64_LDFF1D_REAL - 461
|
|
{8128, 3042, 4, 7 },
|
|
// AArch64_LDFF1H_D_REAL - 462
|
|
{8154, 3049, 4, 7 },
|
|
// AArch64_LDFF1H_REAL - 463
|
|
{8180, 3056, 4, 7 },
|
|
// AArch64_LDFF1H_S_REAL - 464
|
|
{8206, 3063, 4, 7 },
|
|
// AArch64_LDFF1SB_D_REAL - 465
|
|
{8232, 3070, 4, 7 },
|
|
// AArch64_LDFF1SB_H_REAL - 466
|
|
{8259, 3077, 4, 7 },
|
|
// AArch64_LDFF1SB_S_REAL - 467
|
|
{8286, 3084, 4, 7 },
|
|
// AArch64_LDFF1SH_D_REAL - 468
|
|
{8313, 3091, 4, 7 },
|
|
// AArch64_LDFF1SH_S_REAL - 469
|
|
{8340, 3098, 4, 7 },
|
|
// AArch64_LDFF1SW_D_REAL - 470
|
|
{8367, 3105, 4, 7 },
|
|
// AArch64_LDFF1W_D_REAL - 471
|
|
{8394, 3112, 4, 7 },
|
|
// AArch64_LDFF1W_REAL - 472
|
|
{8420, 3119, 4, 7 },
|
|
// AArch64_LDG - 473
|
|
{8446, 3126, 4, 7 },
|
|
// AArch64_LDNF1B_D_IMM_REAL - 474
|
|
{8459, 3133, 4, 7 },
|
|
// AArch64_LDNF1B_H_IMM_REAL - 475
|
|
{8485, 3140, 4, 7 },
|
|
// AArch64_LDNF1B_IMM_REAL - 476
|
|
{8511, 3147, 4, 7 },
|
|
// AArch64_LDNF1B_S_IMM_REAL - 477
|
|
{8537, 3154, 4, 7 },
|
|
// AArch64_LDNF1D_IMM_REAL - 478
|
|
{8563, 3161, 4, 7 },
|
|
// AArch64_LDNF1H_D_IMM_REAL - 479
|
|
{8589, 3168, 4, 7 },
|
|
// AArch64_LDNF1H_IMM_REAL - 480
|
|
{8615, 3175, 4, 7 },
|
|
// AArch64_LDNF1H_S_IMM_REAL - 481
|
|
{8641, 3182, 4, 7 },
|
|
// AArch64_LDNF1SB_D_IMM_REAL - 482
|
|
{8667, 3189, 4, 7 },
|
|
// AArch64_LDNF1SB_H_IMM_REAL - 483
|
|
{8694, 3196, 4, 7 },
|
|
// AArch64_LDNF1SB_S_IMM_REAL - 484
|
|
{8721, 3203, 4, 7 },
|
|
// AArch64_LDNF1SH_D_IMM_REAL - 485
|
|
{8748, 3210, 4, 7 },
|
|
// AArch64_LDNF1SH_S_IMM_REAL - 486
|
|
{8775, 3217, 4, 7 },
|
|
// AArch64_LDNF1SW_D_IMM_REAL - 487
|
|
{8802, 3224, 4, 7 },
|
|
// AArch64_LDNF1W_D_IMM_REAL - 488
|
|
{8829, 3231, 4, 7 },
|
|
// AArch64_LDNF1W_IMM_REAL - 489
|
|
{8855, 3238, 4, 7 },
|
|
// AArch64_LDNPDi - 490
|
|
{8881, 3245, 4, 7 },
|
|
// AArch64_LDNPQi - 491
|
|
{8881, 3252, 4, 7 },
|
|
// AArch64_LDNPSi - 492
|
|
{8881, 3259, 4, 7 },
|
|
// AArch64_LDNPWi - 493
|
|
{8881, 3266, 4, 4 },
|
|
// AArch64_LDNPXi - 494
|
|
{8881, 3270, 4, 4 },
|
|
// AArch64_LDNT1B_2Z_IMM - 495
|
|
{8899, 3274, 4, 8 },
|
|
// AArch64_LDNT1B_2Z_STRIDED_IMM - 496
|
|
{8925, 3282, 4, 7 },
|
|
// AArch64_LDNT1B_4Z_IMM - 497
|
|
{8899, 3289, 4, 8 },
|
|
// AArch64_LDNT1B_4Z_STRIDED_IMM - 498
|
|
{8951, 3297, 4, 7 },
|
|
// AArch64_LDNT1B_ZRI - 499
|
|
{8977, 3304, 4, 8 },
|
|
// AArch64_LDNT1B_ZZR_D_REAL - 500
|
|
{9003, 3312, 4, 7 },
|
|
// AArch64_LDNT1B_ZZR_S_REAL - 501
|
|
{9031, 3319, 4, 7 },
|
|
// AArch64_LDNT1D_2Z_IMM - 502
|
|
{9059, 3326, 4, 8 },
|
|
// AArch64_LDNT1D_2Z_STRIDED_IMM - 503
|
|
{9085, 3334, 4, 7 },
|
|
// AArch64_LDNT1D_4Z_IMM - 504
|
|
{9059, 3341, 4, 8 },
|
|
// AArch64_LDNT1D_4Z_STRIDED_IMM - 505
|
|
{9085, 3349, 4, 7 },
|
|
// AArch64_LDNT1D_ZRI - 506
|
|
{9111, 3356, 4, 8 },
|
|
// AArch64_LDNT1D_ZZR_D_REAL - 507
|
|
{9137, 3364, 4, 7 },
|
|
// AArch64_LDNT1H_2Z_IMM - 508
|
|
{9165, 3371, 4, 8 },
|
|
// AArch64_LDNT1H_2Z_STRIDED_IMM - 509
|
|
{9191, 3379, 4, 7 },
|
|
// AArch64_LDNT1H_4Z_IMM - 510
|
|
{9165, 3386, 4, 8 },
|
|
// AArch64_LDNT1H_4Z_STRIDED_IMM - 511
|
|
{9217, 3394, 4, 7 },
|
|
// AArch64_LDNT1H_ZRI - 512
|
|
{9243, 3401, 4, 8 },
|
|
// AArch64_LDNT1H_ZZR_D_REAL - 513
|
|
{9269, 3409, 4, 7 },
|
|
// AArch64_LDNT1H_ZZR_S_REAL - 514
|
|
{9297, 3416, 4, 7 },
|
|
// AArch64_LDNT1SB_ZZR_D_REAL - 515
|
|
{9325, 3423, 4, 7 },
|
|
// AArch64_LDNT1SB_ZZR_S_REAL - 516
|
|
{9354, 3430, 4, 7 },
|
|
// AArch64_LDNT1SH_ZZR_D_REAL - 517
|
|
{9383, 3437, 4, 7 },
|
|
// AArch64_LDNT1SH_ZZR_S_REAL - 518
|
|
{9412, 3444, 4, 7 },
|
|
// AArch64_LDNT1SW_ZZR_D_REAL - 519
|
|
{9441, 3451, 4, 7 },
|
|
// AArch64_LDNT1W_2Z_IMM - 520
|
|
{9470, 3458, 4, 8 },
|
|
// AArch64_LDNT1W_2Z_STRIDED_IMM - 521
|
|
{9496, 3466, 4, 7 },
|
|
// AArch64_LDNT1W_4Z_IMM - 522
|
|
{9470, 3473, 4, 8 },
|
|
// AArch64_LDNT1W_4Z_STRIDED_IMM - 523
|
|
{9496, 3481, 4, 7 },
|
|
// AArch64_LDNT1W_ZRI - 524
|
|
{9522, 3488, 4, 8 },
|
|
// AArch64_LDNT1W_ZZR_D_REAL - 525
|
|
{9548, 3496, 4, 7 },
|
|
// AArch64_LDNT1W_ZZR_S_REAL - 526
|
|
{9576, 3503, 4, 7 },
|
|
// AArch64_LDPDi - 527
|
|
{9604, 3510, 4, 7 },
|
|
// AArch64_LDPQi - 528
|
|
{9604, 3517, 4, 7 },
|
|
// AArch64_LDPSWi - 529
|
|
{9621, 3524, 4, 4 },
|
|
// AArch64_LDPSi - 530
|
|
{9604, 3528, 4, 7 },
|
|
// AArch64_LDPWi - 531
|
|
{9604, 3535, 4, 4 },
|
|
// AArch64_LDPXi - 532
|
|
{9604, 3539, 4, 4 },
|
|
// AArch64_LDRAAindexed - 533
|
|
{9640, 3543, 3, 6 },
|
|
// AArch64_LDRABindexed - 534
|
|
{9655, 3549, 3, 6 },
|
|
// AArch64_LDRBBroX - 535
|
|
{9670, 3555, 5, 5 },
|
|
// AArch64_LDRBBui - 536
|
|
{9688, 3560, 3, 3 },
|
|
// AArch64_LDRBroX - 537
|
|
{9702, 3563, 5, 8 },
|
|
// AArch64_LDRBui - 538
|
|
{9719, 3571, 3, 6 },
|
|
// AArch64_LDRDroX - 539
|
|
{9702, 3577, 5, 8 },
|
|
// AArch64_LDRDui - 540
|
|
{9719, 3585, 3, 6 },
|
|
// AArch64_LDRHHroX - 541
|
|
{9732, 3591, 5, 5 },
|
|
// AArch64_LDRHHui - 542
|
|
{9750, 3596, 3, 3 },
|
|
// AArch64_LDRHroX - 543
|
|
{9702, 3599, 5, 8 },
|
|
// AArch64_LDRHui - 544
|
|
{9719, 3607, 3, 6 },
|
|
// AArch64_LDRQroX - 545
|
|
{9702, 3613, 5, 8 },
|
|
// AArch64_LDRQui - 546
|
|
{9719, 3621, 3, 6 },
|
|
// AArch64_LDRSBWroX - 547
|
|
{9764, 3627, 5, 5 },
|
|
// AArch64_LDRSBWui - 548
|
|
{9783, 3632, 3, 3 },
|
|
// AArch64_LDRSBXroX - 549
|
|
{9764, 3635, 5, 5 },
|
|
// AArch64_LDRSBXui - 550
|
|
{9783, 3640, 3, 3 },
|
|
// AArch64_LDRSHWroX - 551
|
|
{9798, 3643, 5, 5 },
|
|
// AArch64_LDRSHWui - 552
|
|
{9817, 3648, 3, 3 },
|
|
// AArch64_LDRSHXroX - 553
|
|
{9798, 3651, 5, 5 },
|
|
// AArch64_LDRSHXui - 554
|
|
{9817, 3656, 3, 3 },
|
|
// AArch64_LDRSWroX - 555
|
|
{9832, 3659, 5, 5 },
|
|
// AArch64_LDRSWui - 556
|
|
{9851, 3664, 3, 3 },
|
|
// AArch64_LDRSroX - 557
|
|
{9702, 3667, 5, 8 },
|
|
// AArch64_LDRSui - 558
|
|
{9719, 3675, 3, 6 },
|
|
// AArch64_LDRWroX - 559
|
|
{9702, 3681, 5, 5 },
|
|
// AArch64_LDRWui - 560
|
|
{9719, 3686, 3, 3 },
|
|
// AArch64_LDRXroX - 561
|
|
{9702, 3689, 5, 5 },
|
|
// AArch64_LDRXui - 562
|
|
{9719, 3694, 3, 3 },
|
|
// AArch64_LDR_PXI - 563
|
|
{9866, 3697, 3, 7 },
|
|
// AArch64_LDR_ZA - 564
|
|
{9881, 3704, 5, 8 },
|
|
// AArch64_LDR_ZXI - 565
|
|
{9866, 3712, 3, 7 },
|
|
// AArch64_LDSETB - 566
|
|
{9906, 3719, 3, 6 },
|
|
// AArch64_LDSETH - 567
|
|
{9922, 3725, 3, 6 },
|
|
// AArch64_LDSETLB - 568
|
|
{9938, 3731, 3, 6 },
|
|
// AArch64_LDSETLH - 569
|
|
{9955, 3737, 3, 6 },
|
|
// AArch64_LDSETLW - 570
|
|
{9972, 3743, 3, 6 },
|
|
// AArch64_LDSETLX - 571
|
|
{9972, 3749, 3, 6 },
|
|
// AArch64_LDSETW - 572
|
|
{9988, 3755, 3, 6 },
|
|
// AArch64_LDSETX - 573
|
|
{9988, 3761, 3, 6 },
|
|
// AArch64_LDSMAXB - 574
|
|
{10003, 3767, 3, 6 },
|
|
// AArch64_LDSMAXH - 575
|
|
{10020, 3773, 3, 6 },
|
|
// AArch64_LDSMAXLB - 576
|
|
{10037, 3779, 3, 6 },
|
|
// AArch64_LDSMAXLH - 577
|
|
{10055, 3785, 3, 6 },
|
|
// AArch64_LDSMAXLW - 578
|
|
{10073, 3791, 3, 6 },
|
|
// AArch64_LDSMAXLX - 579
|
|
{10073, 3797, 3, 6 },
|
|
// AArch64_LDSMAXW - 580
|
|
{10090, 3803, 3, 6 },
|
|
// AArch64_LDSMAXX - 581
|
|
{10090, 3809, 3, 6 },
|
|
// AArch64_LDSMINB - 582
|
|
{10106, 3815, 3, 6 },
|
|
// AArch64_LDSMINH - 583
|
|
{10123, 3821, 3, 6 },
|
|
// AArch64_LDSMINLB - 584
|
|
{10140, 3827, 3, 6 },
|
|
// AArch64_LDSMINLH - 585
|
|
{10158, 3833, 3, 6 },
|
|
// AArch64_LDSMINLW - 586
|
|
{10176, 3839, 3, 6 },
|
|
// AArch64_LDSMINLX - 587
|
|
{10176, 3845, 3, 6 },
|
|
// AArch64_LDSMINW - 588
|
|
{10193, 3851, 3, 6 },
|
|
// AArch64_LDSMINX - 589
|
|
{10193, 3857, 3, 6 },
|
|
// AArch64_LDTRBi - 590
|
|
{10209, 3863, 3, 3 },
|
|
// AArch64_LDTRHi - 591
|
|
{10224, 3866, 3, 3 },
|
|
// AArch64_LDTRSBWi - 592
|
|
{10239, 3869, 3, 3 },
|
|
// AArch64_LDTRSBXi - 593
|
|
{10239, 3872, 3, 3 },
|
|
// AArch64_LDTRSHWi - 594
|
|
{10255, 3875, 3, 3 },
|
|
// AArch64_LDTRSHXi - 595
|
|
{10255, 3878, 3, 3 },
|
|
// AArch64_LDTRSWi - 596
|
|
{10271, 3881, 3, 3 },
|
|
// AArch64_LDTRWi - 597
|
|
{10287, 3884, 3, 3 },
|
|
// AArch64_LDTRXi - 598
|
|
{10287, 3887, 3, 3 },
|
|
// AArch64_LDUMAXB - 599
|
|
{10301, 3890, 3, 6 },
|
|
// AArch64_LDUMAXH - 600
|
|
{10318, 3896, 3, 6 },
|
|
// AArch64_LDUMAXLB - 601
|
|
{10335, 3902, 3, 6 },
|
|
// AArch64_LDUMAXLH - 602
|
|
{10353, 3908, 3, 6 },
|
|
// AArch64_LDUMAXLW - 603
|
|
{10371, 3914, 3, 6 },
|
|
// AArch64_LDUMAXLX - 604
|
|
{10371, 3920, 3, 6 },
|
|
// AArch64_LDUMAXW - 605
|
|
{10388, 3926, 3, 6 },
|
|
// AArch64_LDUMAXX - 606
|
|
{10388, 3932, 3, 6 },
|
|
// AArch64_LDUMINB - 607
|
|
{10404, 3938, 3, 6 },
|
|
// AArch64_LDUMINH - 608
|
|
{10421, 3944, 3, 6 },
|
|
// AArch64_LDUMINLB - 609
|
|
{10438, 3950, 3, 6 },
|
|
// AArch64_LDUMINLH - 610
|
|
{10456, 3956, 3, 6 },
|
|
// AArch64_LDUMINLW - 611
|
|
{10474, 3962, 3, 6 },
|
|
// AArch64_LDUMINLX - 612
|
|
{10474, 3968, 3, 6 },
|
|
// AArch64_LDUMINW - 613
|
|
{10491, 3974, 3, 6 },
|
|
// AArch64_LDUMINX - 614
|
|
{10491, 3980, 3, 6 },
|
|
// AArch64_LDURBBi - 615
|
|
{10507, 3986, 3, 3 },
|
|
// AArch64_LDURBi - 616
|
|
{10522, 3989, 3, 6 },
|
|
// AArch64_LDURDi - 617
|
|
{10522, 3995, 3, 6 },
|
|
// AArch64_LDURHHi - 618
|
|
{10536, 4001, 3, 3 },
|
|
// AArch64_LDURHi - 619
|
|
{10522, 4004, 3, 6 },
|
|
// AArch64_LDURQi - 620
|
|
{10522, 4010, 3, 6 },
|
|
// AArch64_LDURSBWi - 621
|
|
{10551, 4016, 3, 3 },
|
|
// AArch64_LDURSBXi - 622
|
|
{10551, 4019, 3, 3 },
|
|
// AArch64_LDURSHWi - 623
|
|
{10567, 4022, 3, 3 },
|
|
// AArch64_LDURSHXi - 624
|
|
{10567, 4025, 3, 3 },
|
|
// AArch64_LDURSWi - 625
|
|
{10583, 4028, 3, 3 },
|
|
// AArch64_LDURSi - 626
|
|
{10522, 4031, 3, 6 },
|
|
// AArch64_LDURWi - 627
|
|
{10522, 4037, 3, 3 },
|
|
// AArch64_LDURXi - 628
|
|
{10522, 4040, 3, 3 },
|
|
// AArch64_MADDWrrr - 629
|
|
{10599, 4043, 4, 4 },
|
|
// AArch64_MADDXrrr - 630
|
|
{10599, 4047, 4, 4 },
|
|
// AArch64_MOVA_2ZMXI_H_B - 631
|
|
{10614, 4051, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_H_D - 632
|
|
{10639, 4057, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_H_H - 633
|
|
{10664, 4063, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_H_S - 634
|
|
{10689, 4069, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_V_B - 635
|
|
{10714, 4075, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_V_D - 636
|
|
{10739, 4081, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_V_H - 637
|
|
{10764, 4087, 4, 6 },
|
|
// AArch64_MOVA_2ZMXI_V_S - 638
|
|
{10789, 4093, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_H_B - 639
|
|
{10814, 4099, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_H_D - 640
|
|
{10839, 4105, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_H_H - 641
|
|
{10864, 4111, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_H_S - 642
|
|
{10889, 4117, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_V_B - 643
|
|
{10914, 4123, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_V_D - 644
|
|
{10939, 4129, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_V_H - 645
|
|
{10964, 4135, 4, 6 },
|
|
// AArch64_MOVA_4ZMXI_V_S - 646
|
|
{10989, 4141, 4, 6 },
|
|
// AArch64_MOVA_MXI2Z_H_B - 647
|
|
{11014, 4147, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_H_D - 648
|
|
{11039, 4155, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_H_H - 649
|
|
{11064, 4163, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_H_S - 650
|
|
{11089, 4171, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_V_B - 651
|
|
{11114, 4179, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_V_D - 652
|
|
{11139, 4187, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_V_H - 653
|
|
{11164, 4195, 5, 8 },
|
|
// AArch64_MOVA_MXI2Z_V_S - 654
|
|
{11189, 4203, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_H_B - 655
|
|
{11214, 4211, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_H_D - 656
|
|
{11239, 4219, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_H_H - 657
|
|
{11264, 4227, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_H_S - 658
|
|
{11289, 4235, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_V_B - 659
|
|
{11314, 4243, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_V_D - 660
|
|
{11339, 4251, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_V_H - 661
|
|
{11364, 4259, 5, 8 },
|
|
// AArch64_MOVA_MXI4Z_V_S - 662
|
|
{11389, 4267, 5, 8 },
|
|
// AArch64_MOVA_VG2_2ZMXI - 663
|
|
{11414, 4275, 4, 6 },
|
|
// AArch64_MOVA_VG2_MXI2Z - 664
|
|
{11445, 4281, 5, 8 },
|
|
// AArch64_MOVA_VG4_4ZMXI - 665
|
|
{11476, 4289, 4, 6 },
|
|
// AArch64_MOVA_VG4_MXI4Z - 666
|
|
{11507, 4295, 5, 8 },
|
|
// AArch64_MOVT - 667
|
|
{11538, 4303, 3, 9 },
|
|
// AArch64_MSRpstatesvcrImm1 - 668
|
|
{11552, 4312, 2, 2 },
|
|
{11560, 4314, 2, 2 },
|
|
{11571, 4316, 2, 2 },
|
|
{11582, 4318, 2, 2 },
|
|
{11589, 4320, 2, 2 },
|
|
{11599, 4322, 2, 2 },
|
|
// AArch64_MSUBWrrr - 674
|
|
{11609, 4324, 4, 4 },
|
|
// AArch64_MSUBXrrr - 675
|
|
{11609, 4328, 4, 4 },
|
|
// AArch64_NOTv16i8 - 676
|
|
{11625, 4332, 2, 2 },
|
|
// AArch64_NOTv8i8 - 677
|
|
{11648, 4334, 2, 2 },
|
|
// AArch64_ORNWrs - 678
|
|
{11669, 4336, 4, 4 },
|
|
{11680, 4340, 4, 3 },
|
|
{11695, 4343, 4, 4 },
|
|
// AArch64_ORNXrs - 681
|
|
{11669, 4347, 4, 4 },
|
|
{11680, 4351, 4, 3 },
|
|
{11695, 4354, 4, 4 },
|
|
// AArch64_ORRS_PPzPP - 684
|
|
{11710, 4358, 4, 8 },
|
|
// AArch64_ORRWrs - 685
|
|
{11726, 4366, 4, 4 },
|
|
{11737, 4370, 4, 4 },
|
|
// AArch64_ORRXrs - 687
|
|
{11726, 4374, 4, 4 },
|
|
{11737, 4378, 4, 4 },
|
|
// AArch64_ORR_PPzPP - 689
|
|
{11752, 4382, 4, 8 },
|
|
// AArch64_ORR_ZI - 690
|
|
{11767, 4390, 3, 7 },
|
|
{11788, 4397, 3, 7 },
|
|
{11809, 4404, 3, 7 },
|
|
// AArch64_ORR_ZZZ - 693
|
|
{11830, 4411, 3, 7 },
|
|
// AArch64_ORRv16i8 - 694
|
|
{11845, 4418, 3, 3 },
|
|
// AArch64_ORRv8i8 - 695
|
|
{11868, 4421, 3, 3 },
|
|
// AArch64_PACIA1716 - 696
|
|
{11889, 4424, 0, 3 },
|
|
// AArch64_PACIASP - 697
|
|
{11899, 4427, 0, 3 },
|
|
// AArch64_PACIAZ - 698
|
|
{11907, 4430, 0, 3 },
|
|
// AArch64_PACIB1716 - 699
|
|
{11914, 4433, 0, 3 },
|
|
// AArch64_PACIBSP - 700
|
|
{11924, 4436, 0, 3 },
|
|
// AArch64_PACIBZ - 701
|
|
{11932, 4439, 0, 3 },
|
|
// AArch64_PACM - 702
|
|
{11939, 4442, 0, 3 },
|
|
// AArch64_PMOV_PZI_B - 703
|
|
{11944, 4445, 3, 7 },
|
|
// AArch64_PMOV_ZIP_B - 704
|
|
{11960, 4452, 4, 8 },
|
|
// AArch64_PRFB_D_PZI - 705
|
|
{11976, 4460, 4, 7 },
|
|
// AArch64_PRFB_PRI - 706
|
|
{12000, 4467, 4, 8 },
|
|
// AArch64_PRFB_S_PZI - 707
|
|
{12022, 4475, 4, 7 },
|
|
// AArch64_PRFD_D_PZI - 708
|
|
{12046, 4482, 4, 7 },
|
|
// AArch64_PRFD_PRI - 709
|
|
{12070, 4489, 4, 8 },
|
|
// AArch64_PRFD_S_PZI - 710
|
|
{12092, 4497, 4, 7 },
|
|
// AArch64_PRFH_D_PZI - 711
|
|
{12116, 4504, 4, 7 },
|
|
// AArch64_PRFH_PRI - 712
|
|
{12140, 4511, 4, 8 },
|
|
// AArch64_PRFH_S_PZI - 713
|
|
{12162, 4519, 4, 7 },
|
|
// AArch64_PRFMroX - 714
|
|
{12186, 4526, 5, 5 },
|
|
// AArch64_PRFMui - 715
|
|
{12206, 4531, 3, 3 },
|
|
// AArch64_PRFUMi - 716
|
|
{12222, 4534, 3, 3 },
|
|
// AArch64_PRFW_D_PZI - 717
|
|
{12239, 4537, 4, 7 },
|
|
// AArch64_PRFW_PRI - 718
|
|
{12263, 4544, 4, 8 },
|
|
// AArch64_PRFW_S_PZI - 719
|
|
{12285, 4552, 4, 7 },
|
|
// AArch64_PTRUES_B - 720
|
|
{12309, 4559, 2, 6 },
|
|
// AArch64_PTRUES_D - 721
|
|
{12321, 4565, 2, 6 },
|
|
// AArch64_PTRUES_H - 722
|
|
{12333, 4571, 2, 6 },
|
|
// AArch64_PTRUES_S - 723
|
|
{12345, 4577, 2, 6 },
|
|
// AArch64_PTRUE_B - 724
|
|
{12357, 4583, 2, 6 },
|
|
// AArch64_PTRUE_D - 725
|
|
{12368, 4589, 2, 6 },
|
|
// AArch64_PTRUE_H - 726
|
|
{12379, 4595, 2, 6 },
|
|
// AArch64_PTRUE_S - 727
|
|
{12390, 4601, 2, 6 },
|
|
// AArch64_RET - 728
|
|
{12401, 4607, 1, 1 },
|
|
// AArch64_SBCSWr - 729
|
|
{12405, 4608, 3, 3 },
|
|
// AArch64_SBCSXr - 730
|
|
{12405, 4611, 3, 3 },
|
|
// AArch64_SBCWr - 731
|
|
{12417, 4614, 3, 3 },
|
|
// AArch64_SBCXr - 732
|
|
{12417, 4617, 3, 3 },
|
|
// AArch64_SBFMWri - 733
|
|
{12428, 4620, 4, 4 },
|
|
{12443, 4624, 4, 4 },
|
|
{12455, 4628, 4, 4 },
|
|
// AArch64_SBFMXri - 736
|
|
{12428, 4632, 4, 4 },
|
|
{12443, 4636, 4, 4 },
|
|
{12455, 4640, 4, 4 },
|
|
{12467, 4644, 4, 4 },
|
|
// AArch64_SEL_PPPP - 740
|
|
{12479, 4648, 4, 8 },
|
|
// AArch64_SEL_ZPZZ_B - 741
|
|
{12479, 4656, 4, 8 },
|
|
// AArch64_SEL_ZPZZ_D - 742
|
|
{12502, 4664, 4, 8 },
|
|
// AArch64_SEL_ZPZZ_H - 743
|
|
{12525, 4672, 4, 8 },
|
|
// AArch64_SEL_ZPZZ_S - 744
|
|
{12548, 4680, 4, 8 },
|
|
// AArch64_SMADDLrrr - 745
|
|
{12571, 4688, 4, 4 },
|
|
// AArch64_SMSUBLrrr - 746
|
|
{12588, 4692, 4, 4 },
|
|
// AArch64_SQDECB_XPiI - 747
|
|
{12606, 4696, 4, 8 },
|
|
{12616, 4704, 4, 8 },
|
|
// AArch64_SQDECB_XPiWdI - 749
|
|
{12632, 4712, 4, 8 },
|
|
{12648, 4720, 4, 8 },
|
|
// AArch64_SQDECD_XPiI - 751
|
|
{12670, 4728, 4, 8 },
|
|
{12680, 4736, 4, 8 },
|
|
// AArch64_SQDECD_XPiWdI - 753
|
|
{12696, 4744, 4, 8 },
|
|
{12712, 4752, 4, 8 },
|
|
// AArch64_SQDECD_ZPiI - 755
|
|
{12734, 4760, 4, 8 },
|
|
{12746, 4768, 4, 8 },
|
|
// AArch64_SQDECH_XPiI - 757
|
|
{12764, 4776, 4, 8 },
|
|
{12774, 4784, 4, 8 },
|
|
// AArch64_SQDECH_XPiWdI - 759
|
|
{12790, 4792, 4, 8 },
|
|
{12806, 4800, 4, 8 },
|
|
// AArch64_SQDECH_ZPiI - 761
|
|
{12828, 4808, 4, 8 },
|
|
{12840, 4816, 4, 8 },
|
|
// AArch64_SQDECW_XPiI - 763
|
|
{12858, 4824, 4, 8 },
|
|
{12868, 4832, 4, 8 },
|
|
// AArch64_SQDECW_XPiWdI - 765
|
|
{12884, 4840, 4, 8 },
|
|
{12900, 4848, 4, 8 },
|
|
// AArch64_SQDECW_ZPiI - 767
|
|
{12922, 4856, 4, 8 },
|
|
{12934, 4864, 4, 8 },
|
|
// AArch64_SQINCB_XPiI - 769
|
|
{12952, 4872, 4, 8 },
|
|
{12962, 4880, 4, 8 },
|
|
// AArch64_SQINCB_XPiWdI - 771
|
|
{12978, 4888, 4, 8 },
|
|
{12994, 4896, 4, 8 },
|
|
// AArch64_SQINCD_XPiI - 773
|
|
{13016, 4904, 4, 8 },
|
|
{13026, 4912, 4, 8 },
|
|
// AArch64_SQINCD_XPiWdI - 775
|
|
{13042, 4920, 4, 8 },
|
|
{13058, 4928, 4, 8 },
|
|
// AArch64_SQINCD_ZPiI - 777
|
|
{13080, 4936, 4, 8 },
|
|
{13092, 4944, 4, 8 },
|
|
// AArch64_SQINCH_XPiI - 779
|
|
{13110, 4952, 4, 8 },
|
|
{13120, 4960, 4, 8 },
|
|
// AArch64_SQINCH_XPiWdI - 781
|
|
{13136, 4968, 4, 8 },
|
|
{13152, 4976, 4, 8 },
|
|
// AArch64_SQINCH_ZPiI - 783
|
|
{13174, 4984, 4, 8 },
|
|
{13186, 4992, 4, 8 },
|
|
// AArch64_SQINCW_XPiI - 785
|
|
{13204, 5000, 4, 8 },
|
|
{13214, 5008, 4, 8 },
|
|
// AArch64_SQINCW_XPiWdI - 787
|
|
{13230, 5016, 4, 8 },
|
|
{13246, 5024, 4, 8 },
|
|
// AArch64_SQINCW_ZPiI - 789
|
|
{13268, 5032, 4, 8 },
|
|
{13280, 5040, 4, 8 },
|
|
// AArch64_SST1B_D_IMM - 791
|
|
{13298, 5048, 4, 7 },
|
|
// AArch64_SST1B_S_IMM - 792
|
|
{13322, 5055, 4, 7 },
|
|
// AArch64_SST1D_IMM - 793
|
|
{13346, 5062, 4, 7 },
|
|
// AArch64_SST1H_D_IMM - 794
|
|
{13370, 5069, 4, 7 },
|
|
// AArch64_SST1H_S_IMM - 795
|
|
{13394, 5076, 4, 7 },
|
|
// AArch64_SST1Q - 796
|
|
{13418, 5083, 4, 7 },
|
|
// AArch64_SST1W_D_IMM - 797
|
|
{13442, 5090, 4, 7 },
|
|
// AArch64_SST1W_IMM - 798
|
|
{13466, 5097, 4, 7 },
|
|
// AArch64_ST1B_2Z_IMM - 799
|
|
{13490, 5104, 4, 8 },
|
|
// AArch64_ST1B_2Z_STRIDED_IMM - 800
|
|
{13512, 5112, 4, 7 },
|
|
// AArch64_ST1B_4Z_IMM - 801
|
|
{13490, 5119, 4, 8 },
|
|
// AArch64_ST1B_4Z_STRIDED_IMM - 802
|
|
{13534, 5127, 4, 7 },
|
|
// AArch64_ST1B_D_IMM - 803
|
|
{13556, 5134, 4, 8 },
|
|
// AArch64_ST1B_H_IMM - 804
|
|
{13578, 5142, 4, 8 },
|
|
// AArch64_ST1B_IMM - 805
|
|
{13600, 5150, 4, 8 },
|
|
// AArch64_ST1B_S_IMM - 806
|
|
{13622, 5158, 4, 8 },
|
|
// AArch64_ST1D_2Z_IMM - 807
|
|
{13644, 5166, 4, 8 },
|
|
// AArch64_ST1D_2Z_STRIDED_IMM - 808
|
|
{13666, 5174, 4, 7 },
|
|
// AArch64_ST1D_4Z_IMM - 809
|
|
{13644, 5181, 4, 8 },
|
|
// AArch64_ST1D_4Z_STRIDED_IMM - 810
|
|
{13666, 5189, 4, 7 },
|
|
// AArch64_ST1D_IMM - 811
|
|
{13688, 5196, 4, 8 },
|
|
// AArch64_ST1D_Q_IMM - 812
|
|
{13710, 5204, 4, 7 },
|
|
// AArch64_ST1Fourv16b_POST - 813
|
|
{13732, 5211, 4, 7 },
|
|
// AArch64_ST1Fourv1d_POST - 814
|
|
{13752, 5218, 4, 7 },
|
|
// AArch64_ST1Fourv2d_POST - 815
|
|
{13772, 5225, 4, 7 },
|
|
// AArch64_ST1Fourv2s_POST - 816
|
|
{13792, 5232, 4, 7 },
|
|
// AArch64_ST1Fourv4h_POST - 817
|
|
{13812, 5239, 4, 7 },
|
|
// AArch64_ST1Fourv4s_POST - 818
|
|
{13832, 5246, 4, 7 },
|
|
// AArch64_ST1Fourv8b_POST - 819
|
|
{13852, 5253, 4, 7 },
|
|
// AArch64_ST1Fourv8h_POST - 820
|
|
{13872, 5260, 4, 7 },
|
|
// AArch64_ST1H_2Z_IMM - 821
|
|
{13892, 5267, 4, 8 },
|
|
// AArch64_ST1H_2Z_STRIDED_IMM - 822
|
|
{13914, 5275, 4, 7 },
|
|
// AArch64_ST1H_4Z_IMM - 823
|
|
{13892, 5282, 4, 8 },
|
|
// AArch64_ST1H_4Z_STRIDED_IMM - 824
|
|
{13936, 5290, 4, 7 },
|
|
// AArch64_ST1H_D_IMM - 825
|
|
{13958, 5297, 4, 8 },
|
|
// AArch64_ST1H_IMM - 826
|
|
{13980, 5305, 4, 8 },
|
|
// AArch64_ST1H_S_IMM - 827
|
|
{14002, 5313, 4, 8 },
|
|
// AArch64_ST1Onev16b_POST - 828
|
|
{14024, 5321, 4, 7 },
|
|
// AArch64_ST1Onev1d_POST - 829
|
|
{14044, 5328, 4, 7 },
|
|
// AArch64_ST1Onev2d_POST - 830
|
|
{14063, 5335, 4, 7 },
|
|
// AArch64_ST1Onev2s_POST - 831
|
|
{14083, 5342, 4, 7 },
|
|
// AArch64_ST1Onev4h_POST - 832
|
|
{14102, 5349, 4, 7 },
|
|
// AArch64_ST1Onev4s_POST - 833
|
|
{14121, 5356, 4, 7 },
|
|
// AArch64_ST1Onev8b_POST - 834
|
|
{14141, 5363, 4, 7 },
|
|
// AArch64_ST1Onev8h_POST - 835
|
|
{14160, 5370, 4, 7 },
|
|
// AArch64_ST1Threev16b_POST - 836
|
|
{14180, 5377, 4, 7 },
|
|
// AArch64_ST1Threev1d_POST - 837
|
|
{14200, 5384, 4, 7 },
|
|
// AArch64_ST1Threev2d_POST - 838
|
|
{14220, 5391, 4, 7 },
|
|
// AArch64_ST1Threev2s_POST - 839
|
|
{14240, 5398, 4, 7 },
|
|
// AArch64_ST1Threev4h_POST - 840
|
|
{14260, 5405, 4, 7 },
|
|
// AArch64_ST1Threev4s_POST - 841
|
|
{14280, 5412, 4, 7 },
|
|
// AArch64_ST1Threev8b_POST - 842
|
|
{14300, 5419, 4, 7 },
|
|
// AArch64_ST1Threev8h_POST - 843
|
|
{14320, 5426, 4, 7 },
|
|
// AArch64_ST1Twov16b_POST - 844
|
|
{14340, 5433, 4, 7 },
|
|
// AArch64_ST1Twov1d_POST - 845
|
|
{14360, 5440, 4, 7 },
|
|
// AArch64_ST1Twov2d_POST - 846
|
|
{14380, 5447, 4, 7 },
|
|
// AArch64_ST1Twov2s_POST - 847
|
|
{14400, 5454, 4, 7 },
|
|
// AArch64_ST1Twov4h_POST - 848
|
|
{14420, 5461, 4, 7 },
|
|
// AArch64_ST1Twov4s_POST - 849
|
|
{14440, 5468, 4, 7 },
|
|
// AArch64_ST1Twov8b_POST - 850
|
|
{14460, 5475, 4, 7 },
|
|
// AArch64_ST1Twov8h_POST - 851
|
|
{14480, 5482, 4, 7 },
|
|
// AArch64_ST1W_2Z_IMM - 852
|
|
{14500, 5489, 4, 8 },
|
|
// AArch64_ST1W_2Z_STRIDED_IMM - 853
|
|
{14522, 5497, 4, 7 },
|
|
// AArch64_ST1W_4Z_IMM - 854
|
|
{14500, 5504, 4, 8 },
|
|
// AArch64_ST1W_4Z_STRIDED_IMM - 855
|
|
{14522, 5512, 4, 7 },
|
|
// AArch64_ST1W_D_IMM - 856
|
|
{14544, 5519, 4, 8 },
|
|
// AArch64_ST1W_IMM - 857
|
|
{14566, 5527, 4, 8 },
|
|
// AArch64_ST1W_Q_IMM - 858
|
|
{14588, 5535, 4, 7 },
|
|
// AArch64_ST1_MXIPXX_H_B - 859
|
|
{14610, 5542, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_H_D - 860
|
|
{14644, 5551, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_H_H - 861
|
|
{14678, 5560, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_H_Q - 862
|
|
{14712, 5569, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_H_S - 863
|
|
{14746, 5578, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_V_B - 864
|
|
{14780, 5587, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_V_D - 865
|
|
{14814, 5596, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_V_H - 866
|
|
{14848, 5605, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_V_Q - 867
|
|
{14882, 5614, 6, 9 },
|
|
// AArch64_ST1_MXIPXX_V_S - 868
|
|
{14916, 5623, 6, 9 },
|
|
// AArch64_ST1i16_POST - 869
|
|
{14950, 5632, 5, 8 },
|
|
// AArch64_ST1i32_POST - 870
|
|
{14973, 5640, 5, 8 },
|
|
// AArch64_ST1i64_POST - 871
|
|
{14996, 5648, 5, 8 },
|
|
// AArch64_ST1i8_POST - 872
|
|
{15019, 5656, 5, 8 },
|
|
// AArch64_ST2B_IMM - 873
|
|
{15042, 5664, 4, 8 },
|
|
// AArch64_ST2D_IMM - 874
|
|
{15064, 5672, 4, 8 },
|
|
// AArch64_ST2Gi - 875
|
|
{15086, 5680, 3, 6 },
|
|
// AArch64_ST2H_IMM - 876
|
|
{15100, 5686, 4, 8 },
|
|
// AArch64_ST2Q_IMM - 877
|
|
{15122, 5694, 4, 8 },
|
|
// AArch64_ST2Twov16b_POST - 878
|
|
{15144, 5702, 4, 7 },
|
|
// AArch64_ST2Twov2d_POST - 879
|
|
{15164, 5709, 4, 7 },
|
|
// AArch64_ST2Twov2s_POST - 880
|
|
{15184, 5716, 4, 7 },
|
|
// AArch64_ST2Twov4h_POST - 881
|
|
{15204, 5723, 4, 7 },
|
|
// AArch64_ST2Twov4s_POST - 882
|
|
{15224, 5730, 4, 7 },
|
|
// AArch64_ST2Twov8b_POST - 883
|
|
{15244, 5737, 4, 7 },
|
|
// AArch64_ST2Twov8h_POST - 884
|
|
{15264, 5744, 4, 7 },
|
|
// AArch64_ST2W_IMM - 885
|
|
{15284, 5751, 4, 8 },
|
|
// AArch64_ST2i16_POST - 886
|
|
{15306, 5759, 5, 8 },
|
|
// AArch64_ST2i32_POST - 887
|
|
{15329, 5767, 5, 8 },
|
|
// AArch64_ST2i64_POST - 888
|
|
{15352, 5775, 5, 8 },
|
|
// AArch64_ST2i8_POST - 889
|
|
{15376, 5783, 5, 8 },
|
|
// AArch64_ST3B_IMM - 890
|
|
{15399, 5791, 4, 8 },
|
|
// AArch64_ST3D_IMM - 891
|
|
{15421, 5799, 4, 8 },
|
|
// AArch64_ST3H_IMM - 892
|
|
{15443, 5807, 4, 8 },
|
|
// AArch64_ST3Q_IMM - 893
|
|
{15465, 5815, 4, 8 },
|
|
// AArch64_ST3Threev16b_POST - 894
|
|
{15487, 5823, 4, 7 },
|
|
// AArch64_ST3Threev2d_POST - 895
|
|
{15507, 5830, 4, 7 },
|
|
// AArch64_ST3Threev2s_POST - 896
|
|
{15527, 5837, 4, 7 },
|
|
// AArch64_ST3Threev4h_POST - 897
|
|
{15547, 5844, 4, 7 },
|
|
// AArch64_ST3Threev4s_POST - 898
|
|
{15567, 5851, 4, 7 },
|
|
// AArch64_ST3Threev8b_POST - 899
|
|
{15587, 5858, 4, 7 },
|
|
// AArch64_ST3Threev8h_POST - 900
|
|
{15607, 5865, 4, 7 },
|
|
// AArch64_ST3W_IMM - 901
|
|
{15627, 5872, 4, 8 },
|
|
// AArch64_ST3i16_POST - 902
|
|
{15649, 5880, 5, 8 },
|
|
// AArch64_ST3i32_POST - 903
|
|
{15672, 5888, 5, 8 },
|
|
// AArch64_ST3i64_POST - 904
|
|
{15696, 5896, 5, 8 },
|
|
// AArch64_ST3i8_POST - 905
|
|
{15720, 5904, 5, 8 },
|
|
// AArch64_ST4B_IMM - 906
|
|
{15743, 5912, 4, 8 },
|
|
// AArch64_ST4D_IMM - 907
|
|
{15765, 5920, 4, 8 },
|
|
// AArch64_ST4Fourv16b_POST - 908
|
|
{15787, 5928, 4, 7 },
|
|
// AArch64_ST4Fourv2d_POST - 909
|
|
{15807, 5935, 4, 7 },
|
|
// AArch64_ST4Fourv2s_POST - 910
|
|
{15827, 5942, 4, 7 },
|
|
// AArch64_ST4Fourv4h_POST - 911
|
|
{15847, 5949, 4, 7 },
|
|
// AArch64_ST4Fourv4s_POST - 912
|
|
{15867, 5956, 4, 7 },
|
|
// AArch64_ST4Fourv8b_POST - 913
|
|
{15887, 5963, 4, 7 },
|
|
// AArch64_ST4Fourv8h_POST - 914
|
|
{15907, 5970, 4, 7 },
|
|
// AArch64_ST4H_IMM - 915
|
|
{15927, 5977, 4, 8 },
|
|
// AArch64_ST4Q_IMM - 916
|
|
{15949, 5985, 4, 8 },
|
|
// AArch64_ST4W_IMM - 917
|
|
{15971, 5993, 4, 8 },
|
|
// AArch64_ST4i16_POST - 918
|
|
{15993, 6001, 5, 8 },
|
|
// AArch64_ST4i32_POST - 919
|
|
{16016, 6009, 5, 8 },
|
|
// AArch64_ST4i64_POST - 920
|
|
{16040, 6017, 5, 8 },
|
|
// AArch64_ST4i8_POST - 921
|
|
{16064, 6025, 5, 8 },
|
|
// AArch64_STGPi - 922
|
|
{16087, 6033, 4, 7 },
|
|
// AArch64_STGi - 923
|
|
{16105, 6040, 3, 6 },
|
|
// AArch64_STLURBi - 924
|
|
{16118, 6046, 3, 6 },
|
|
// AArch64_STLURHi - 925
|
|
{16134, 6052, 3, 6 },
|
|
// AArch64_STLURWi - 926
|
|
{16150, 6058, 3, 6 },
|
|
// AArch64_STLURXi - 927
|
|
{16150, 6064, 3, 6 },
|
|
// AArch64_STLURbi - 928
|
|
{16150, 6070, 3, 9 },
|
|
// AArch64_STLURdi - 929
|
|
{16150, 6079, 3, 9 },
|
|
// AArch64_STLURhi - 930
|
|
{16150, 6088, 3, 9 },
|
|
// AArch64_STLURqi - 931
|
|
{16150, 6097, 3, 9 },
|
|
// AArch64_STLURsi - 932
|
|
{16150, 6106, 3, 9 },
|
|
// AArch64_STNPDi - 933
|
|
{16165, 6115, 4, 7 },
|
|
// AArch64_STNPQi - 934
|
|
{16165, 6122, 4, 7 },
|
|
// AArch64_STNPSi - 935
|
|
{16165, 6129, 4, 7 },
|
|
// AArch64_STNPWi - 936
|
|
{16165, 6136, 4, 4 },
|
|
// AArch64_STNPXi - 937
|
|
{16165, 6140, 4, 4 },
|
|
// AArch64_STNT1B_2Z_IMM - 938
|
|
{16183, 6144, 4, 8 },
|
|
// AArch64_STNT1B_2Z_STRIDED_IMM - 939
|
|
{16207, 6152, 4, 7 },
|
|
// AArch64_STNT1B_4Z_IMM - 940
|
|
{16183, 6159, 4, 8 },
|
|
// AArch64_STNT1B_4Z_STRIDED_IMM - 941
|
|
{16231, 6167, 4, 7 },
|
|
// AArch64_STNT1B_ZRI - 942
|
|
{16255, 6174, 4, 8 },
|
|
// AArch64_STNT1B_ZZR_D_REAL - 943
|
|
{16279, 6182, 4, 7 },
|
|
// AArch64_STNT1B_ZZR_S_REAL - 944
|
|
{16305, 6189, 4, 7 },
|
|
// AArch64_STNT1D_2Z_IMM - 945
|
|
{16331, 6196, 4, 8 },
|
|
// AArch64_STNT1D_2Z_STRIDED_IMM - 946
|
|
{16355, 6204, 4, 7 },
|
|
// AArch64_STNT1D_4Z_IMM - 947
|
|
{16331, 6211, 4, 8 },
|
|
// AArch64_STNT1D_4Z_STRIDED_IMM - 948
|
|
{16355, 6219, 4, 7 },
|
|
// AArch64_STNT1D_ZRI - 949
|
|
{16379, 6226, 4, 8 },
|
|
// AArch64_STNT1D_ZZR_D_REAL - 950
|
|
{16403, 6234, 4, 7 },
|
|
// AArch64_STNT1H_2Z_IMM - 951
|
|
{16429, 6241, 4, 8 },
|
|
// AArch64_STNT1H_2Z_STRIDED_IMM - 952
|
|
{16453, 6249, 4, 7 },
|
|
// AArch64_STNT1H_4Z_IMM - 953
|
|
{16429, 6256, 4, 8 },
|
|
// AArch64_STNT1H_4Z_STRIDED_IMM - 954
|
|
{16477, 6264, 4, 7 },
|
|
// AArch64_STNT1H_ZRI - 955
|
|
{16501, 6271, 4, 8 },
|
|
// AArch64_STNT1H_ZZR_D_REAL - 956
|
|
{16525, 6279, 4, 7 },
|
|
// AArch64_STNT1H_ZZR_S_REAL - 957
|
|
{16551, 6286, 4, 7 },
|
|
// AArch64_STNT1W_2Z_IMM - 958
|
|
{16577, 6293, 4, 8 },
|
|
// AArch64_STNT1W_2Z_STRIDED_IMM - 959
|
|
{16601, 6301, 4, 7 },
|
|
// AArch64_STNT1W_4Z_IMM - 960
|
|
{16577, 6308, 4, 8 },
|
|
// AArch64_STNT1W_4Z_STRIDED_IMM - 961
|
|
{16601, 6316, 4, 7 },
|
|
// AArch64_STNT1W_ZRI - 962
|
|
{16625, 6323, 4, 8 },
|
|
// AArch64_STNT1W_ZZR_D_REAL - 963
|
|
{16649, 6331, 4, 7 },
|
|
// AArch64_STNT1W_ZZR_S_REAL - 964
|
|
{16675, 6338, 4, 7 },
|
|
// AArch64_STPDi - 965
|
|
{16701, 6345, 4, 7 },
|
|
// AArch64_STPQi - 966
|
|
{16701, 6352, 4, 7 },
|
|
// AArch64_STPSi - 967
|
|
{16701, 6359, 4, 7 },
|
|
// AArch64_STPWi - 968
|
|
{16701, 6366, 4, 4 },
|
|
// AArch64_STPXi - 969
|
|
{16701, 6370, 4, 4 },
|
|
// AArch64_STRBBroX - 970
|
|
{16718, 6374, 5, 5 },
|
|
// AArch64_STRBBui - 971
|
|
{16736, 6379, 3, 3 },
|
|
// AArch64_STRBroX - 972
|
|
{16750, 6382, 5, 8 },
|
|
// AArch64_STRBui - 973
|
|
{16767, 6390, 3, 6 },
|
|
// AArch64_STRDroX - 974
|
|
{16750, 6396, 5, 8 },
|
|
// AArch64_STRDui - 975
|
|
{16767, 6404, 3, 6 },
|
|
// AArch64_STRHHroX - 976
|
|
{16780, 6410, 5, 5 },
|
|
// AArch64_STRHHui - 977
|
|
{16798, 6415, 3, 3 },
|
|
// AArch64_STRHroX - 978
|
|
{16750, 6418, 5, 8 },
|
|
// AArch64_STRHui - 979
|
|
{16767, 6426, 3, 6 },
|
|
// AArch64_STRQroX - 980
|
|
{16750, 6432, 5, 8 },
|
|
// AArch64_STRQui - 981
|
|
{16767, 6440, 3, 6 },
|
|
// AArch64_STRSroX - 982
|
|
{16750, 6446, 5, 8 },
|
|
// AArch64_STRSui - 983
|
|
{16767, 6454, 3, 6 },
|
|
// AArch64_STRWroX - 984
|
|
{16750, 6460, 5, 5 },
|
|
// AArch64_STRWui - 985
|
|
{16767, 6465, 3, 3 },
|
|
// AArch64_STRXroX - 986
|
|
{16750, 6468, 5, 5 },
|
|
// AArch64_STRXui - 987
|
|
{16767, 6473, 3, 3 },
|
|
// AArch64_STR_PXI - 988
|
|
{16812, 6476, 3, 7 },
|
|
// AArch64_STR_ZA - 989
|
|
{16827, 6483, 5, 8 },
|
|
// AArch64_STR_ZXI - 990
|
|
{16812, 6491, 3, 7 },
|
|
// AArch64_STTRBi - 991
|
|
{16852, 6498, 3, 3 },
|
|
// AArch64_STTRHi - 992
|
|
{16867, 6501, 3, 3 },
|
|
// AArch64_STTRWi - 993
|
|
{16882, 6504, 3, 3 },
|
|
// AArch64_STTRXi - 994
|
|
{16882, 6507, 3, 3 },
|
|
// AArch64_STURBBi - 995
|
|
{16896, 6510, 3, 3 },
|
|
// AArch64_STURBi - 996
|
|
{16911, 6513, 3, 6 },
|
|
// AArch64_STURDi - 997
|
|
{16911, 6519, 3, 6 },
|
|
// AArch64_STURHHi - 998
|
|
{16925, 6525, 3, 3 },
|
|
// AArch64_STURHi - 999
|
|
{16911, 6528, 3, 6 },
|
|
// AArch64_STURQi - 1000
|
|
{16911, 6534, 3, 6 },
|
|
// AArch64_STURSi - 1001
|
|
{16911, 6540, 3, 6 },
|
|
// AArch64_STURWi - 1002
|
|
{16911, 6546, 3, 3 },
|
|
// AArch64_STURXi - 1003
|
|
{16911, 6549, 3, 3 },
|
|
// AArch64_STZ2Gi - 1004
|
|
{16940, 6552, 3, 6 },
|
|
// AArch64_STZGi - 1005
|
|
{16955, 6558, 3, 6 },
|
|
// AArch64_SUBPT_shift - 1006
|
|
{16969, 6564, 4, 7 },
|
|
// AArch64_SUBSWri - 1007
|
|
{16986, 6571, 4, 2 },
|
|
// AArch64_SUBSWrs - 1008
|
|
{16999, 6573, 4, 4 },
|
|
{17010, 6577, 4, 3 },
|
|
{17025, 6580, 4, 4 },
|
|
{17037, 6584, 4, 3 },
|
|
{17053, 6587, 4, 4 },
|
|
// AArch64_SUBSWrx - 1013
|
|
{16999, 6591, 4, 4 },
|
|
{17069, 6595, 4, 3 },
|
|
{17053, 6598, 4, 4 },
|
|
// AArch64_SUBSXri - 1016
|
|
{16986, 6602, 4, 2 },
|
|
// AArch64_SUBSXrs - 1017
|
|
{16999, 6604, 4, 4 },
|
|
{17010, 6608, 4, 3 },
|
|
{17025, 6611, 4, 4 },
|
|
{17037, 6615, 4, 3 },
|
|
{17053, 6618, 4, 4 },
|
|
// AArch64_SUBSXrx - 1022
|
|
{17069, 6622, 4, 3 },
|
|
// AArch64_SUBSXrx64 - 1023
|
|
{16999, 6625, 4, 4 },
|
|
{17069, 6629, 4, 3 },
|
|
{17053, 6632, 4, 4 },
|
|
// AArch64_SUBWrs - 1026
|
|
{17084, 6636, 4, 4 },
|
|
{17095, 6640, 4, 3 },
|
|
{17110, 6643, 4, 4 },
|
|
// AArch64_SUBWrx - 1029
|
|
{17110, 6647, 4, 4 },
|
|
{17110, 6651, 4, 4 },
|
|
// AArch64_SUBXrs - 1031
|
|
{17084, 6655, 4, 4 },
|
|
{17095, 6659, 4, 3 },
|
|
{17110, 6662, 4, 4 },
|
|
// AArch64_SUBXrx64 - 1034
|
|
{17110, 6666, 4, 4 },
|
|
{17110, 6670, 4, 4 },
|
|
// AArch64_SYSPxt_XZR - 1036
|
|
{17125, 6674, 5, 8 },
|
|
// AArch64_SYSxt - 1037
|
|
{17149, 6682, 5, 5 },
|
|
// AArch64_UBFMWri - 1038
|
|
{17172, 6687, 4, 4 },
|
|
{17187, 6691, 4, 4 },
|
|
{17199, 6695, 4, 4 },
|
|
// AArch64_UBFMXri - 1041
|
|
{17172, 6699, 4, 4 },
|
|
{17187, 6703, 4, 4 },
|
|
{17199, 6707, 4, 4 },
|
|
{17211, 6711, 4, 4 },
|
|
// AArch64_UMADDLrrr - 1045
|
|
{17223, 6715, 4, 4 },
|
|
// AArch64_UMOVvi32 - 1046
|
|
{17240, 6719, 3, 5 },
|
|
// AArch64_UMOVvi32_idx0 - 1047
|
|
{17240, 6724, 3, 6 },
|
|
// AArch64_UMOVvi64 - 1048
|
|
{17259, 6730, 3, 5 },
|
|
// AArch64_UMOVvi64_idx0 - 1049
|
|
{17259, 6735, 3, 6 },
|
|
// AArch64_UMSUBLrrr - 1050
|
|
{17278, 6741, 4, 4 },
|
|
// AArch64_UQDECB_WPiI - 1051
|
|
{17296, 6745, 4, 8 },
|
|
{17306, 6753, 4, 8 },
|
|
// AArch64_UQDECB_XPiI - 1053
|
|
{17296, 6761, 4, 8 },
|
|
{17306, 6769, 4, 8 },
|
|
// AArch64_UQDECD_WPiI - 1055
|
|
{17322, 6777, 4, 8 },
|
|
{17332, 6785, 4, 8 },
|
|
// AArch64_UQDECD_XPiI - 1057
|
|
{17322, 6793, 4, 8 },
|
|
{17332, 6801, 4, 8 },
|
|
// AArch64_UQDECD_ZPiI - 1059
|
|
{17348, 6809, 4, 8 },
|
|
{17360, 6817, 4, 8 },
|
|
// AArch64_UQDECH_WPiI - 1061
|
|
{17378, 6825, 4, 8 },
|
|
{17388, 6833, 4, 8 },
|
|
// AArch64_UQDECH_XPiI - 1063
|
|
{17378, 6841, 4, 8 },
|
|
{17388, 6849, 4, 8 },
|
|
// AArch64_UQDECH_ZPiI - 1065
|
|
{17404, 6857, 4, 8 },
|
|
{17416, 6865, 4, 8 },
|
|
// AArch64_UQDECW_WPiI - 1067
|
|
{17434, 6873, 4, 8 },
|
|
{17444, 6881, 4, 8 },
|
|
// AArch64_UQDECW_XPiI - 1069
|
|
{17434, 6889, 4, 8 },
|
|
{17444, 6897, 4, 8 },
|
|
// AArch64_UQDECW_ZPiI - 1071
|
|
{17460, 6905, 4, 8 },
|
|
{17472, 6913, 4, 8 },
|
|
// AArch64_UQINCB_WPiI - 1073
|
|
{17490, 6921, 4, 8 },
|
|
{17500, 6929, 4, 8 },
|
|
// AArch64_UQINCB_XPiI - 1075
|
|
{17490, 6937, 4, 8 },
|
|
{17500, 6945, 4, 8 },
|
|
// AArch64_UQINCD_WPiI - 1077
|
|
{17516, 6953, 4, 8 },
|
|
{17526, 6961, 4, 8 },
|
|
// AArch64_UQINCD_XPiI - 1079
|
|
{17516, 6969, 4, 8 },
|
|
{17526, 6977, 4, 8 },
|
|
// AArch64_UQINCD_ZPiI - 1081
|
|
{17542, 6985, 4, 8 },
|
|
{17554, 6993, 4, 8 },
|
|
// AArch64_UQINCH_WPiI - 1083
|
|
{17572, 7001, 4, 8 },
|
|
{17582, 7009, 4, 8 },
|
|
// AArch64_UQINCH_XPiI - 1085
|
|
{17572, 7017, 4, 8 },
|
|
{17582, 7025, 4, 8 },
|
|
// AArch64_UQINCH_ZPiI - 1087
|
|
{17598, 7033, 4, 8 },
|
|
{17610, 7041, 4, 8 },
|
|
// AArch64_UQINCW_WPiI - 1089
|
|
{17628, 7049, 4, 8 },
|
|
{17638, 7057, 4, 8 },
|
|
// AArch64_UQINCW_XPiI - 1091
|
|
{17628, 7065, 4, 8 },
|
|
{17638, 7073, 4, 8 },
|
|
// AArch64_UQINCW_ZPiI - 1093
|
|
{17654, 7081, 4, 8 },
|
|
{17666, 7089, 4, 8 },
|
|
// AArch64_XPACLRI - 1095
|
|
{17684, 7097, 0, 3 },
|
|
// AArch64_ZERO_M - 1096
|
|
{17692, 7100, 1, 4 },
|
|
{17702, 7104, 1, 4 },
|
|
{17715, 7108, 1, 4 },
|
|
{17728, 7112, 1, 4 },
|
|
{17741, 7116, 1, 4 },
|
|
{17754, 7120, 1, 4 },
|
|
{17767, 7124, 1, 4 },
|
|
{17780, 7128, 1, 4 },
|
|
{17799, 7132, 1, 4 },
|
|
{17818, 7136, 1, 4 },
|
|
{17837, 7140, 1, 4 },
|
|
{17856, 7144, 1, 4 },
|
|
{17881, 7148, 1, 4 },
|
|
{17906, 7152, 1, 4 },
|
|
{17931, 7156, 1, 4 },
|
|
{0}, };
|
|
|
|
static const AliasPatternCond Conds[] = {
|
|
// (ADDPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 0
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureCPA},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 7
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
// (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 9
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 13
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 16
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 20
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 24
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 27
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 31
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
// (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 33
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 37
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 40
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 44
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 47
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 51
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 54
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 58
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 62
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 66
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 70
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 74
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 78
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 82
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 86
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 90
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 94
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 98
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 100
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 104
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 107
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 111
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 113
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 117
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 120
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 124
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 132
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 136
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 140
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 148
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 155
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 162
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIA1716) - 169
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIASP) - 172
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIAZ) - 175
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIB1716) - 178
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIBSP) - 181
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIBZ) - 184
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 187
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 191
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 195
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 199
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (CHKFEAT) - 203
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureCHK},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CLREX 15) - 206
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
// (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 207
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 214
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 221
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 228
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 235
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 242
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 249
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 256
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 263
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 270
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 277
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 284
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 291
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 299
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 307
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 315
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 323
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 331
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 339
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 347
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 355
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 361
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 367
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 373
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 379
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 383
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 387
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 391
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 395
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 399
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 403
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 407
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 411
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 415
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (DCPS1 0) - 419
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (DCPS2 0) - 420
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (DCPS3 0) - 421
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureEL3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 425
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 433
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 441
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 449
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 457
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 465
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 473
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 481
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 489
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 497
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 505
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 513
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 521
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 529
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DSB 0) - 537
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (DSB 4) - 538
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
// (DSB { 1, 1, 0, 0 }) - 539
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_HasV8_0rOps},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 543
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 5},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 549
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 6},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 555
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 7},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 561
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 567
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 573
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 579
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 584
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_D ZPR64:$Zd, 0, 0) - 589
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 596
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_H ZPR16:$Zd, 0, 0) - 601
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 608
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_S ZPR32:$Zd, 0, 0) - 613
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 620
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 626
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 632
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 638
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 644
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 651
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 657
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 664
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 670
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 677
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 683
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 690
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 696
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 703
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 709
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 713
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 717
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 725
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 729
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 733
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 741
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 748
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 755
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 762
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 770
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 778
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 786
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 794
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 802
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 810
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 818
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 826
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 834
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 842
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 845
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 848
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 855
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 862
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 869
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 874
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 879
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GCSPOPM XZR) - 884
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureGCS},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 888
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 895
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 902
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 909
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 916
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 923
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 930
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 937
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 944
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 951
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 958
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 965
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 972
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 979
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 986
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 993
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1000
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1007
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1014
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1021
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1028
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1035
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1042
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1049
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1056
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (HINT { 0, 0, 0 }) - 1063
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (HINT { 0, 0, 1 }) - 1064
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (HINT { 0, 1, 0 }) - 1065
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
// (HINT { 0, 1, 1 }) - 1066
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
// (HINT { 1, 0, 0 }) - 1067
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
// (HINT { 1, 0, 1 }) - 1068
|
|
{AliasPatternCond_K_Imm, (uint32_t)5},
|
|
// (HINT { 1, 1, 0 }) - 1069
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
// (HINT { 1, 0, 0, 0, 0 }) - 1070
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRAS},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (HINT 20) - 1074
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
// (HINT 32) - 1075
|
|
{AliasPatternCond_K_Imm, (uint32_t)32},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureBranchTargetId},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (HINT btihint_op:$op) - 1079
|
|
{AliasPatternCond_K_Custom, 8},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureBranchTargetId},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (HINT psbhint_op:$op) - 1083
|
|
{AliasPatternCond_K_Custom, 9},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSPE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (HINT 19) - 1087
|
|
{AliasPatternCond_K_Imm, (uint32_t)19},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureGCS},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (HINT 22) - 1091
|
|
{AliasPatternCond_K_Imm, (uint32_t)22},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureCLRBHB},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1095
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1103
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1111
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1119
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1127
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 1135
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1143
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1151
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1159
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 1167
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1175
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1183
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1191
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 1199
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1207
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1216
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1225
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1234
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1243
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1252
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1261
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1270
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1279
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1288
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1297
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 1304
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1311
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 1318
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1325
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 1332
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1339
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 1346
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1353
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ISB 15) - 1359
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
// (LD1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1360
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1368
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1375
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1383
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1390
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1398
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1406
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1414
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1422
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1430
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1437
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1445
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1452
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1460
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1467
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1474
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1481
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1488
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1495
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1502
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1509
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1516
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1523
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1531
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1538
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1546
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1553
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1561
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1569
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1577
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1584
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1591
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1598
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1605
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1612
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1619
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1626
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1633
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1641
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1649
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1657
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1665
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1673
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1681
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1689
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1697
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMatMulFP64},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1707
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMatMulFP64},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1717
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMatMulFP64},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1727
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMatMulFP64},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1737
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1745
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1753
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1761
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1769
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1777
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1785
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1793
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1801
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1809
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1817
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1825
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1833
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1840
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1847
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1854
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1861
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1868
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1875
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1882
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1889
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1897
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1905
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1913
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1921
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1929
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1937
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1944
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1951
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1958
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1965
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1972
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1979
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1986
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1993
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2000
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2007
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2014
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2021
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2028
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2035
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2042
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2049
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2057
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2064
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2072
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2079
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2087
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2095
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2102
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2111
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2120
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2129
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2138
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2147
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2156
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2165
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2174
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2183
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 2192
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 2201
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 2210
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 2219
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2228
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2236
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2244
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2252
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2260
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2267
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2274
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2281
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2288
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2295
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2302
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2309
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2316
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2323
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2330
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2337
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2344
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2351
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2358
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2365
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 2373
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 2382
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 2391
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 2400
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2409
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2417
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2425
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2433
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2441
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 2448
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2455
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2462
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2469
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2476
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2483
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2490
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2497
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2504
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2511
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2518
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2525
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2532
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2539
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2546
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 2554
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 2563
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 2572
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 2581
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2590
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2598
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2606
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2613
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2620
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2627
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2634
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2641
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2648
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2655
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2663
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2671
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2678
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2685
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2692
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2699
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2706
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2713
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2720
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2727
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 2735
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 2744
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 2753
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 2762
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2771
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2777
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2783
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2789
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2795
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2801
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2807
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2813
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2819
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2825
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2831
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2837
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2843
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2849
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2855
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2861
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 2867
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 2876
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 2885
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2894
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 2900
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDAPURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 2909
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2918
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2924
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2930
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2936
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2942
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2948
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2954
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2960
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2966
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2972
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2978
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2984
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2990
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2996
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3002
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3008
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3014
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3021
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3028
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3035
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3042
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3049
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3056
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3063
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3070
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3077
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3084
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3091
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3098
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3105
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3112
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3119
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 3126
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3133
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3140
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3147
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3154
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3161
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3168
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3175
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3182
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3189
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3196
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3203
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3210
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3217
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3224
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3231
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3238
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3245
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3252
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3259
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3266
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3270
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3274
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3282
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3289
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3297
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3304
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3312
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3319
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3326
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3334
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3341
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3349
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3356
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3364
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3371
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3379
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3386
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3394
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3401
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3409
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3416
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3423
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3430
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3437
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3444
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3451
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3458
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3466
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3473
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3481
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3488
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3496
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3503
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3510
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3517
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3524
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3528
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3535
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3539
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3543
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3549
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3555
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 3560
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3563
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3571
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3577
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3585
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3591
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 3596
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3599
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3607
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3613
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3621
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3627
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3635
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3640
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3643
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3648
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3651
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3656
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3659
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 3664
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3667
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3675
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3681
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3686
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3689
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3694
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 3697
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 3704
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3712
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3719
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3725
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3731
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3737
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3743
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3749
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3755
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3761
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3767
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3773
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3779
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3785
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3791
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3797
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3803
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3809
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3815
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3821
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3827
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3833
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3839
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3845
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3851
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3857
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3863
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3866
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3869
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3872
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3875
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3878
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 3881
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3884
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3887
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3890
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3896
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3902
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3908
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3914
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3920
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3926
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3932
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3938
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3944
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3950
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3956
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3962
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3968
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3974
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3980
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureLSE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3986
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3989
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3995
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4001
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4004
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4010
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4016
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4019
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4022
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4025
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 4028
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4031
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4037
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 4040
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4043
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
// (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4047
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (MOVA_2ZMXI_H_B ZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4051
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_H_D ZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4057
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_H_H ZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4063
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_H_S ZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4069
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_V_B ZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 4075
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_V_D ZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 4081
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_V_H ZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4087
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_2ZMXI_V_S ZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4093
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_H_B ZZZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4099
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_H_D ZZZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4105
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_H_H ZZZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4111
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_H_S ZZZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4117
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_V_B ZZZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4123
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_V_D ZZZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4129
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_V_H ZZZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4135
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_4ZMXI_V_S ZZZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4141
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4147
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4155
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4163
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4171
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4179
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4187
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4195
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI2Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4203
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4211
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4219
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4227
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4235
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4243
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4251
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4259
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_MXI4Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4267
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_VG2_2ZMXI ZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4275
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_8_11RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_VG2_MXI2Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZ_d_mul_r:$Zn) - 4281
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_8_11RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_VG4_4ZMXI ZZZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4289
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_8_11RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVA_VG4_MXI4Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZZZ_d_mul_r:$Zn) - 4295
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_8_11RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MOVT ZTR:$ZTt, 0, ZPRAny:$Zt) - 4303
|
|
{AliasPatternCond_K_RegClass, AArch64_ZTRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME_LUTv2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 4312
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 4314
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 4316
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 4318
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 4320
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 4322
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4324
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
// (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4328
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (NOTv16i8 V128:$Vd, V128:$Vn) - 4332
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
// (NOTv8i8 V64:$Vd, V64:$Vn) - 4334
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
// (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 4336
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 4340
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4343
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 4347
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 4351
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4354
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4358
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4366
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4370
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4374
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4378
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4382
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 4390
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 4397
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 4404
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 4411
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 4418
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 4421
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (PACIA1716) - 4424
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PACIASP) - 4427
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PACIAZ) - 4430
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PACIB1716) - 4433
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PACIBSP) - 4436
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PACIBZ) - 4439
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PACM) - 4442
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuthLR},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PMOV_PZI_B PPR8:$Pd, ZPRAny:$Zn, 0) - 4445
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PMOV_ZIP_B ZPRAny:$Zd, 0, PPR8:$Pn) - 4452
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4460
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4467
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4475
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4482
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4489
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4497
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4504
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4511
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4519
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4526
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 4531
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 4534
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4537
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4544
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4552
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4559
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4565
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4571
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4577
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4583
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4589
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4595
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4601
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (RET LR) - 4607
|
|
{AliasPatternCond_K_Reg, AArch64_LR},
|
|
// (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 4608
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 4611
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SBCWr GPR32:$dst, WZR, GPR32:$src) - 4614
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SBCXr GPR64:$dst, XZR, GPR64:$src) - 4617
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4620
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4624
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
// (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4628
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)63},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4636
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4640
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4644
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 4648
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 4656
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 4664
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 4672
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 4680
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4688
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4692
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4696
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4704
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4712
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4720
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4728
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4736
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4744
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4752
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4760
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4768
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4776
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4784
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4792
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4800
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4808
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4816
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4824
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4832
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4840
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4848
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4856
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4864
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4872
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4880
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4888
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4896
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4904
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4912
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4920
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4928
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4936
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4944
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4952
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4960
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4968
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4976
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4984
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4992
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 5000
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 5008
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 5016
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 5024
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 5032
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 5040
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5048
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5055
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5062
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5069
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5076
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 5083
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5090
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5097
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5104
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5112
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5119
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5127
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5134
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5142
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5150
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5158
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5166
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5174
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5181
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5189
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5196
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5204
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5211
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 5218
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5225
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5232
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5239
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5246
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5253
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5260
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5267
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5275
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5282
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5290
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5297
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5305
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5313
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 5321
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 5328
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 5335
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 5342
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 5349
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 5356
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 5363
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 5370
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5377
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 5384
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5391
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5398
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5405
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5412
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5419
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5426
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5433
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 5440
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5447
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5454
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5461
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5468
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5475
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5482
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5489
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5497
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5504
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5512
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5519
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5527
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5535
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5542
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5551
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5560
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5569
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5578
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5587
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5596
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5605
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5614
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5623
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 5632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 5640
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 5648
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 5656
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5664
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5672
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 5680
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5686
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5694
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5702
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5709
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5716
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5723
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5730
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5737
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5744
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5751
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 5759
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 5767
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 5775
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 5783
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5791
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5799
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5807
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5815
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5823
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5830
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5837
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5844
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5851
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5858
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5865
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5872
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 5880
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 5888
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 5896
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 5904
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5912
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5920
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5928
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5935
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5942
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5949
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5956
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5963
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5970
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5977
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5985
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2p1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5993
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 6001
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 6009
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 6017
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 6025
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6033
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6040
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6046
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6052
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6058
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6064
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC_IMMO},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 6070
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 6079
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 6088
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 6097
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STLURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 6106
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureRCPC3},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6115
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6122
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6129
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6136
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6140
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6144
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_2Z_STRIDED_IMM ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6152
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6159
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_4Z_STRIDED_IMM ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6167
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6174
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6182
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6189
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6196
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_2Z_STRIDED_IMM ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6204
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6211
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_4Z_STRIDED_IMM ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6219
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6226
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6234
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6241
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_2Z_STRIDED_IMM ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6249
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6256
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_4Z_STRIDED_IMM ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6264
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6271
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6279
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6286
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6293
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2Mul2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_2Z_STRIDED_IMM ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6301
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6308
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4Mul4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2p1},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_4Z_STRIDED_IMM ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6316
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4StridedRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PNR_p8to15RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6323
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6331
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6338
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE2},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6345
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6352
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6359
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6366
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6370
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6374
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6379
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6382
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6390
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6396
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6404
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6410
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6415
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6418
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6426
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6432
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6440
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6446
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6454
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6460
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6465
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6468
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 6473
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 6476
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 6483
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 6491
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6498
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6501
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6504
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6507
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6510
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6513
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6519
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6525
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6528
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6534
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6540
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureFPARMv8},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6546
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 6549
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (STZ2Gi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6552
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STZGi GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6558
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureMTE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SUBPT_shift GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0) - 6564
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureCPA},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 6571
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
// (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 6573
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6577
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 6580
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 6584
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 6587
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 6591
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 6595
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 6598
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 6602
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
// (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 6604
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 6608
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 6611
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 6615
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 6618
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 6622
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 6625
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 6629
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 6636
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 6640
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 6643
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 6647
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 6651
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
// (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 6655
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 6659
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 6662
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 6666
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6670
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
// (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6674
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureD128},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6682
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 6687
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 6691
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
// (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 6695
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 6699
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)63},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 6703
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 6707
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 6711
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6715
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 6719
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 6724
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 6730
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 6735
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6741
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6745
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6753
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6761
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6769
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6777
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6785
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6793
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6801
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6809
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 6817
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6825
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6833
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6841
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6849
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6857
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 6865
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6873
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6881
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6889
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6897
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6905
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 6913
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6921
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6929
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6937
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6945
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6953
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6961
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6969
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6977
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6985
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 6993
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7001
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7009
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7017
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7025
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7033
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 7041
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7049
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 7057
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 7065
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 7073
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 7081
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 7089
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (XPACLRI) - 7097
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeaturePAuth},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 7100
|
|
{AliasPatternCond_K_Imm, (uint32_t)255},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 7104
|
|
{AliasPatternCond_K_Imm, (uint32_t)85},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 7108
|
|
{AliasPatternCond_K_Imm, (uint32_t)170},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 7112
|
|
{AliasPatternCond_K_Imm, (uint32_t)17},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 7116
|
|
{AliasPatternCond_K_Imm, (uint32_t)34},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 7120
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 7124
|
|
{AliasPatternCond_K_Imm, (uint32_t)136},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 7128
|
|
{AliasPatternCond_K_Imm, (uint32_t)51},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 7132
|
|
{AliasPatternCond_K_Imm, (uint32_t)153},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 7136
|
|
{AliasPatternCond_K_Imm, (uint32_t)102},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 7140
|
|
{AliasPatternCond_K_Imm, (uint32_t)204},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 7144
|
|
{AliasPatternCond_K_Imm, (uint32_t)119},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 7148
|
|
{AliasPatternCond_K_Imm, (uint32_t)187},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 7152
|
|
{AliasPatternCond_K_Imm, (uint32_t)221},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 7156
|
|
{AliasPatternCond_K_Imm, (uint32_t)238},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureAll},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSME},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
{0}, };
|
|
|
|
static const char AsmStrings[] =
|
|
/* 0 */ "addpt $\x01, $\x02, $\x03\0"
|
|
/* 17 */ "cmn $\x02, $\xFF\x03\x01\0"
|
|
/* 30 */ "cmn $\x02, $\x03\0"
|
|
/* 41 */ "cmn $\x02, $\x03$\xFF\x04\x02\0"
|
|
/* 56 */ "adds $\x01, $\x02, $\x03\0"
|
|
/* 72 */ "cmn $\x02, $\x03$\xFF\x04\x03\0"
|
|
/* 87 */ "mov $\x01, $\x02\0"
|
|
/* 98 */ "add $\x01, $\x02, $\x03\0"
|
|
/* 113 */ "tst $\x02, $\xFF\x03\x04\0"
|
|
/* 126 */ "tst $\x02, $\x03\0"
|
|
/* 137 */ "tst $\x02, $\x03$\xFF\x04\x02\0"
|
|
/* 152 */ "ands $\x01, $\x02, $\x03\0"
|
|
/* 168 */ "tst $\x02, $\xFF\x03\x05\0"
|
|
/* 181 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 205 */ "and $\x01, $\x02, $\x03\0"
|
|
/* 220 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 243 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
|
|
/* 264 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
|
|
/* 285 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
|
|
/* 306 */ "autia1716\0"
|
|
/* 316 */ "autiasp\0"
|
|
/* 324 */ "autiaz\0"
|
|
/* 331 */ "autib1716\0"
|
|
/* 341 */ "autibsp\0"
|
|
/* 349 */ "autibz\0"
|
|
/* 356 */ "bics $\x01, $\x02, $\x03\0"
|
|
/* 372 */ "bic $\x01, $\x02, $\x03\0"
|
|
/* 387 */ "chkfeat x16\0"
|
|
/* 399 */ "clrex\0"
|
|
/* 405 */ "cntb $\x01\0"
|
|
/* 413 */ "cntb $\x01, $\xFF\x02\x0E\0"
|
|
/* 427 */ "cntd $\x01\0"
|
|
/* 435 */ "cntd $\x01, $\xFF\x02\x0E\0"
|
|
/* 449 */ "cnth $\x01\0"
|
|
/* 457 */ "cnth $\x01, $\xFF\x02\x0E\0"
|
|
/* 471 */ "cntw $\x01\0"
|
|
/* 479 */ "cntw $\x01, $\xFF\x02\x0E\0"
|
|
/* 493 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0"
|
|
/* 516 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0"
|
|
/* 539 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0"
|
|
/* 562 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0"
|
|
/* 585 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 606 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 627 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 648 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 669 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0"
|
|
/* 692 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0"
|
|
/* 715 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0"
|
|
/* 738 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0"
|
|
/* 761 */ "cset $\x01, $\xFF\x04\x14\0"
|
|
/* 775 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0"
|
|
/* 793 */ "csetm $\x01, $\xFF\x04\x14\0"
|
|
/* 808 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0"
|
|
/* 826 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0"
|
|
/* 844 */ "dcps1\0"
|
|
/* 850 */ "dcps2\0"
|
|
/* 856 */ "dcps3\0"
|
|
/* 862 */ "decb $\x01\0"
|
|
/* 870 */ "decb $\x01, $\xFF\x03\x0E\0"
|
|
/* 884 */ "decd $\x01\0"
|
|
/* 892 */ "decd $\x01, $\xFF\x03\x0E\0"
|
|
/* 906 */ "decd $\xFF\x01\x10\0"
|
|
/* 916 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 932 */ "dech $\x01\0"
|
|
/* 940 */ "dech $\x01, $\xFF\x03\x0E\0"
|
|
/* 954 */ "dech $\xFF\x01\x09\0"
|
|
/* 964 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 980 */ "decw $\x01\0"
|
|
/* 988 */ "decw $\x01, $\xFF\x03\x0E\0"
|
|
/* 1002 */ "decw $\xFF\x01\x0B\0"
|
|
/* 1012 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 1028 */ "ssbb\0"
|
|
/* 1033 */ "pssbb\0"
|
|
/* 1039 */ "dfb\0"
|
|
/* 1043 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0"
|
|
/* 1058 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0"
|
|
/* 1073 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0"
|
|
/* 1088 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0"
|
|
/* 1104 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0"
|
|
/* 1120 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0"
|
|
/* 1136 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0"
|
|
/* 1151 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0"
|
|
/* 1166 */ "fmov $\xFF\x01\x10, #0.0\0"
|
|
/* 1182 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0"
|
|
/* 1197 */ "fmov $\xFF\x01\x09, #0.0\0"
|
|
/* 1213 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0"
|
|
/* 1228 */ "fmov $\xFF\x01\x0B, #0.0\0"
|
|
/* 1244 */ "mov $\xFF\x01\x06, $\x02\0"
|
|
/* 1257 */ "mov $\xFF\x01\x10, $\x02\0"
|
|
/* 1270 */ "mov $\xFF\x01\x09, $\x02\0"
|
|
/* 1283 */ "mov $\xFF\x01\x0B, $\x02\0"
|
|
/* 1296 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0"
|
|
/* 1311 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0"
|
|
/* 1330 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0"
|
|
/* 1345 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0"
|
|
/* 1364 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0"
|
|
/* 1379 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0"
|
|
/* 1398 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0"
|
|
/* 1413 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0"
|
|
/* 1432 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0"
|
|
/* 1447 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0"
|
|
/* 1466 */ "eon $\x01, $\x02, $\x03\0"
|
|
/* 1481 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 1505 */ "eor $\x01, $\x02, $\x03\0"
|
|
/* 1520 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 1543 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
|
|
/* 1564 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
|
|
/* 1585 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
|
|
/* 1606 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1639 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1672 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1705 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1738 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1771 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1804 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1837 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1870 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1903 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0"
|
|
/* 1936 */ "ror $\x01, $\x02, $\x04\0"
|
|
/* 1951 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0"
|
|
/* 1975 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0"
|
|
/* 1999 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0"
|
|
/* 2023 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0"
|
|
/* 2039 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0"
|
|
/* 2055 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0"
|
|
/* 2071 */ "gcspopm\0"
|
|
/* 2079 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2105 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2131 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2157 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2183 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2209 */ "ld1q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2235 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2262 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2289 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2316 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2343 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2370 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2396 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2422 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2450 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2478 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2506 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2534 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2562 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2591 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2620 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2649 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2678 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2707 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2735 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2763 */ "nop\0"
|
|
/* 2767 */ "yield\0"
|
|
/* 2773 */ "wfe\0"
|
|
/* 2777 */ "wfi\0"
|
|
/* 2781 */ "sev\0"
|
|
/* 2785 */ "sevl\0"
|
|
/* 2790 */ "dgh\0"
|
|
/* 2794 */ "esb\0"
|
|
/* 2798 */ "csdb\0"
|
|
/* 2803 */ "bti\0"
|
|
/* 2807 */ "bti $\xFF\x01\x26\0"
|
|
/* 2816 */ "psb $\xFF\x01\x27\0"
|
|
/* 2825 */ "gcsb dsync\0"
|
|
/* 2836 */ "clrbhb\0"
|
|
/* 2843 */ "incb $\x01\0"
|
|
/* 2851 */ "incb $\x01, $\xFF\x03\x0E\0"
|
|
/* 2865 */ "incd $\x01\0"
|
|
/* 2873 */ "incd $\x01, $\xFF\x03\x0E\0"
|
|
/* 2887 */ "incd $\xFF\x01\x10\0"
|
|
/* 2897 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 2913 */ "inch $\x01\0"
|
|
/* 2921 */ "inch $\x01, $\xFF\x03\x0E\0"
|
|
/* 2935 */ "inch $\xFF\x01\x09\0"
|
|
/* 2945 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 2961 */ "incw $\x01\0"
|
|
/* 2969 */ "incw $\x01, $\xFF\x03\x0E\0"
|
|
/* 2983 */ "incw $\xFF\x01\x0B\0"
|
|
/* 2993 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 3009 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0"
|
|
/* 3042 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0"
|
|
/* 3075 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0"
|
|
/* 3108 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0"
|
|
/* 3141 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0"
|
|
/* 3174 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0"
|
|
/* 3207 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0"
|
|
/* 3240 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0"
|
|
/* 3273 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0"
|
|
/* 3306 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0"
|
|
/* 3339 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0"
|
|
/* 3358 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19\0"
|
|
/* 3385 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0"
|
|
/* 3404 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19\0"
|
|
/* 3431 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0"
|
|
/* 3450 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19\0"
|
|
/* 3477 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0"
|
|
/* 3496 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19\0"
|
|
/* 3523 */ "irg $\x01, $\x02\0"
|
|
/* 3534 */ "isb\0"
|
|
/* 3538 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 3562 */ "ld1b $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 3586 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 3610 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3634 */ "ld1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3658 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3682 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3706 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 3730 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 3754 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3778 */ "ld1d $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3802 */ "ld1 $\xFF\x02\x2C, [$\x01], #64\0"
|
|
/* 3822 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 3842 */ "ld1 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 3862 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 3882 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 3902 */ "ld1 $\xFF\x02\x31, [$\x01], #64\0"
|
|
/* 3922 */ "ld1 $\xFF\x02\x32, [$\x01], #32\0"
|
|
/* 3942 */ "ld1 $\xFF\x02\x33, [$\x01], #64\0"
|
|
/* 3962 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 3986 */ "ld1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 4010 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 4034 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4058 */ "ld1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4082 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4106 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 4126 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0"
|
|
/* 4145 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0"
|
|
/* 4165 */ "ld1 $\xFF\x02\x2F, [$\x01], #8\0"
|
|
/* 4184 */ "ld1 $\xFF\x02\x30, [$\x01], #8\0"
|
|
/* 4203 */ "ld1 $\xFF\x02\x31, [$\x01], #16\0"
|
|
/* 4223 */ "ld1 $\xFF\x02\x32, [$\x01], #8\0"
|
|
/* 4242 */ "ld1 $\xFF\x02\x33, [$\x01], #16\0"
|
|
/* 4262 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4287 */ "ld1rb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4312 */ "ld1rb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4337 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4362 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4387 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4412 */ "ld1rh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4437 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4462 */ "ld1rob $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4488 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4514 */ "ld1roh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4540 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4566 */ "ld1rqb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4592 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4618 */ "ld1rqh $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4644 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4670 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4696 */ "ld1rsb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4722 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4748 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4774 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4800 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4826 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4851 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4876 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0"
|
|
/* 4896 */ "ld1r $\xFF\x02\x2D, [$\x01], #8\0"
|
|
/* 4916 */ "ld1r $\xFF\x02\x2E, [$\x01], #8\0"
|
|
/* 4936 */ "ld1r $\xFF\x02\x2F, [$\x01], #4\0"
|
|
/* 4956 */ "ld1r $\xFF\x02\x30, [$\x01], #2\0"
|
|
/* 4976 */ "ld1r $\xFF\x02\x31, [$\x01], #4\0"
|
|
/* 4996 */ "ld1r $\xFF\x02\x32, [$\x01], #1\0"
|
|
/* 5016 */ "ld1r $\xFF\x02\x33, [$\x01], #2\0"
|
|
/* 5036 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5061 */ "ld1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5086 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5111 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5136 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5161 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5186 */ "ld1 $\xFF\x02\x2C, [$\x01], #48\0"
|
|
/* 5206 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 5226 */ "ld1 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 5246 */ "ld1 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 5266 */ "ld1 $\xFF\x02\x30, [$\x01], #24\0"
|
|
/* 5286 */ "ld1 $\xFF\x02\x31, [$\x01], #48\0"
|
|
/* 5306 */ "ld1 $\xFF\x02\x32, [$\x01], #24\0"
|
|
/* 5326 */ "ld1 $\xFF\x02\x33, [$\x01], #48\0"
|
|
/* 5346 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 5366 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 5386 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 5406 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 5426 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0"
|
|
/* 5446 */ "ld1 $\xFF\x02\x31, [$\x01], #32\0"
|
|
/* 5466 */ "ld1 $\xFF\x02\x32, [$\x01], #16\0"
|
|
/* 5486 */ "ld1 $\xFF\x02\x33, [$\x01], #32\0"
|
|
/* 5506 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 5530 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 5554 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5578 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5602 */ "ld1w $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5626 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5662 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5698 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5734 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5770 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5806 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5842 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5878 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5914 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5950 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5986 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #2\0"
|
|
/* 6009 */ "ld1 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #4\0"
|
|
/* 6032 */ "ld1 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #8\0"
|
|
/* 6055 */ "ld1 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #1\0"
|
|
/* 6078 */ "ld2b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6102 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6126 */ "ld2h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6150 */ "ld2q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6174 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0"
|
|
/* 6194 */ "ld2r $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 6215 */ "ld2r $\xFF\x02\x2E, [$\x01], #16\0"
|
|
/* 6236 */ "ld2r $\xFF\x02\x2F, [$\x01], #8\0"
|
|
/* 6256 */ "ld2r $\xFF\x02\x30, [$\x01], #4\0"
|
|
/* 6276 */ "ld2r $\xFF\x02\x31, [$\x01], #8\0"
|
|
/* 6296 */ "ld2r $\xFF\x02\x32, [$\x01], #2\0"
|
|
/* 6316 */ "ld2r $\xFF\x02\x33, [$\x01], #4\0"
|
|
/* 6336 */ "ld2 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 6356 */ "ld2 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 6376 */ "ld2 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 6396 */ "ld2 $\xFF\x02\x30, [$\x01], #16\0"
|
|
/* 6416 */ "ld2 $\xFF\x02\x31, [$\x01], #32\0"
|
|
/* 6436 */ "ld2 $\xFF\x02\x32, [$\x01], #16\0"
|
|
/* 6456 */ "ld2 $\xFF\x02\x33, [$\x01], #32\0"
|
|
/* 6476 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6500 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #4\0"
|
|
/* 6523 */ "ld2 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #8\0"
|
|
/* 6546 */ "ld2 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #16\0"
|
|
/* 6570 */ "ld2 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #2\0"
|
|
/* 6593 */ "ld3b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6617 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6641 */ "ld3h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6665 */ "ld3q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6689 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0"
|
|
/* 6709 */ "ld3r $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 6730 */ "ld3r $\xFF\x02\x2E, [$\x01], #24\0"
|
|
/* 6751 */ "ld3r $\xFF\x02\x2F, [$\x01], #12\0"
|
|
/* 6772 */ "ld3r $\xFF\x02\x30, [$\x01], #6\0"
|
|
/* 6792 */ "ld3r $\xFF\x02\x31, [$\x01], #12\0"
|
|
/* 6813 */ "ld3r $\xFF\x02\x32, [$\x01], #3\0"
|
|
/* 6833 */ "ld3r $\xFF\x02\x33, [$\x01], #6\0"
|
|
/* 6853 */ "ld3 $\xFF\x02\x2C, [$\x01], #48\0"
|
|
/* 6873 */ "ld3 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 6893 */ "ld3 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 6913 */ "ld3 $\xFF\x02\x30, [$\x01], #24\0"
|
|
/* 6933 */ "ld3 $\xFF\x02\x31, [$\x01], #48\0"
|
|
/* 6953 */ "ld3 $\xFF\x02\x32, [$\x01], #24\0"
|
|
/* 6973 */ "ld3 $\xFF\x02\x33, [$\x01], #48\0"
|
|
/* 6993 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7017 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #6\0"
|
|
/* 7040 */ "ld3 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #12\0"
|
|
/* 7064 */ "ld3 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #24\0"
|
|
/* 7088 */ "ld3 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #3\0"
|
|
/* 7111 */ "ld4b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7135 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7159 */ "ld4 $\xFF\x02\x2C, [$\x01], #64\0"
|
|
/* 7179 */ "ld4 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 7199 */ "ld4 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 7219 */ "ld4 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 7239 */ "ld4 $\xFF\x02\x31, [$\x01], #64\0"
|
|
/* 7259 */ "ld4 $\xFF\x02\x32, [$\x01], #32\0"
|
|
/* 7279 */ "ld4 $\xFF\x02\x33, [$\x01], #64\0"
|
|
/* 7299 */ "ld4h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7323 */ "ld4q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7347 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0"
|
|
/* 7367 */ "ld4r $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 7388 */ "ld4r $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 7409 */ "ld4r $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 7430 */ "ld4r $\xFF\x02\x30, [$\x01], #8\0"
|
|
/* 7450 */ "ld4r $\xFF\x02\x31, [$\x01], #16\0"
|
|
/* 7471 */ "ld4r $\xFF\x02\x32, [$\x01], #4\0"
|
|
/* 7491 */ "ld4r $\xFF\x02\x33, [$\x01], #8\0"
|
|
/* 7511 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7535 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #8\0"
|
|
/* 7558 */ "ld4 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #16\0"
|
|
/* 7582 */ "ld4 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #32\0"
|
|
/* 7606 */ "ld4 $\xFF\x02\x2A$\xFF\x04\x19, [$\x01], #4\0"
|
|
/* 7629 */ "staddb $\x02, [$\x03]\0"
|
|
/* 7645 */ "staddh $\x02, [$\x03]\0"
|
|
/* 7661 */ "staddlb $\x02, [$\x03]\0"
|
|
/* 7678 */ "staddlh $\x02, [$\x03]\0"
|
|
/* 7695 */ "staddl $\x02, [$\x03]\0"
|
|
/* 7711 */ "stadd $\x02, [$\x03]\0"
|
|
/* 7726 */ "ldapurb $\x01, [$\x02]\0"
|
|
/* 7743 */ "ldapurh $\x01, [$\x02]\0"
|
|
/* 7760 */ "ldapursb $\x01, [$\x02]\0"
|
|
/* 7778 */ "ldapursh $\x01, [$\x02]\0"
|
|
/* 7796 */ "ldapursw $\x01, [$\x02]\0"
|
|
/* 7814 */ "ldapur $\x01, [$\x02]\0"
|
|
/* 7830 */ "stclrb $\x02, [$\x03]\0"
|
|
/* 7846 */ "stclrh $\x02, [$\x03]\0"
|
|
/* 7862 */ "stclrlb $\x02, [$\x03]\0"
|
|
/* 7879 */ "stclrlh $\x02, [$\x03]\0"
|
|
/* 7896 */ "stclrl $\x02, [$\x03]\0"
|
|
/* 7912 */ "stclr $\x02, [$\x03]\0"
|
|
/* 7927 */ "steorb $\x02, [$\x03]\0"
|
|
/* 7943 */ "steorh $\x02, [$\x03]\0"
|
|
/* 7959 */ "steorlb $\x02, [$\x03]\0"
|
|
/* 7976 */ "steorlh $\x02, [$\x03]\0"
|
|
/* 7993 */ "steorl $\x02, [$\x03]\0"
|
|
/* 8009 */ "steor $\x02, [$\x03]\0"
|
|
/* 8024 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8050 */ "ldff1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8076 */ "ldff1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8102 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8128 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8154 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8180 */ "ldff1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8206 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8232 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8259 */ "ldff1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8286 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8313 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8340 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8367 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8394 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8420 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8446 */ "ldg $\x01, [$\x03]\0"
|
|
/* 8459 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8485 */ "ldnf1b $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8511 */ "ldnf1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8537 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8563 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8589 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8615 */ "ldnf1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8641 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8667 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8694 */ "ldnf1sb $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8721 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8748 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8775 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8802 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8829 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8855 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8881 */ "ldnp $\x01, $\x02, [$\x03]\0"
|
|
/* 8899 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 8925 */ "ldnt1b $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 8951 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 8977 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 9003 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9031 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 9059 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9085 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9111 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 9137 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9165 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9191 */ "ldnt1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9217 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9243 */ "ldnt1h $\xFF\x01\x2B, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 9269 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9297 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 9325 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9354 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 9383 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9412 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 9441 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9470 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9496 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0"
|
|
/* 9522 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 9548 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 9576 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 9604 */ "ldp $\x01, $\x02, [$\x03]\0"
|
|
/* 9621 */ "ldpsw $\x01, $\x02, [$\x03]\0"
|
|
/* 9640 */ "ldraa $\x01, [$\x02]\0"
|
|
/* 9655 */ "ldrab $\x01, [$\x02]\0"
|
|
/* 9670 */ "ldrb $\x01, [$\x02, $\x03]\0"
|
|
/* 9688 */ "ldrb $\x01, [$\x02]\0"
|
|
/* 9702 */ "ldr $\x01, [$\x02, $\x03]\0"
|
|
/* 9719 */ "ldr $\x01, [$\x02]\0"
|
|
/* 9732 */ "ldrh $\x01, [$\x02, $\x03]\0"
|
|
/* 9750 */ "ldrh $\x01, [$\x02]\0"
|
|
/* 9764 */ "ldrsb $\x01, [$\x02, $\x03]\0"
|
|
/* 9783 */ "ldrsb $\x01, [$\x02]\0"
|
|
/* 9798 */ "ldrsh $\x01, [$\x02, $\x03]\0"
|
|
/* 9817 */ "ldrsh $\x01, [$\x02]\0"
|
|
/* 9832 */ "ldrsw $\x01, [$\x02, $\x03]\0"
|
|
/* 9851 */ "ldrsw $\x01, [$\x02]\0"
|
|
/* 9866 */ "ldr $\xFF\x01\x07, [$\x02]\0"
|
|
/* 9881 */ "ldr $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0"
|
|
/* 9906 */ "stsetb $\x02, [$\x03]\0"
|
|
/* 9922 */ "stseth $\x02, [$\x03]\0"
|
|
/* 9938 */ "stsetlb $\x02, [$\x03]\0"
|
|
/* 9955 */ "stsetlh $\x02, [$\x03]\0"
|
|
/* 9972 */ "stsetl $\x02, [$\x03]\0"
|
|
/* 9988 */ "stset $\x02, [$\x03]\0"
|
|
/* 10003 */ "stsmaxb $\x02, [$\x03]\0"
|
|
/* 10020 */ "stsmaxh $\x02, [$\x03]\0"
|
|
/* 10037 */ "stsmaxlb $\x02, [$\x03]\0"
|
|
/* 10055 */ "stsmaxlh $\x02, [$\x03]\0"
|
|
/* 10073 */ "stsmaxl $\x02, [$\x03]\0"
|
|
/* 10090 */ "stsmax $\x02, [$\x03]\0"
|
|
/* 10106 */ "stsminb $\x02, [$\x03]\0"
|
|
/* 10123 */ "stsminh $\x02, [$\x03]\0"
|
|
/* 10140 */ "stsminlb $\x02, [$\x03]\0"
|
|
/* 10158 */ "stsminlh $\x02, [$\x03]\0"
|
|
/* 10176 */ "stsminl $\x02, [$\x03]\0"
|
|
/* 10193 */ "stsmin $\x02, [$\x03]\0"
|
|
/* 10209 */ "ldtrb $\x01, [$\x02]\0"
|
|
/* 10224 */ "ldtrh $\x01, [$\x02]\0"
|
|
/* 10239 */ "ldtrsb $\x01, [$\x02]\0"
|
|
/* 10255 */ "ldtrsh $\x01, [$\x02]\0"
|
|
/* 10271 */ "ldtrsw $\x01, [$\x02]\0"
|
|
/* 10287 */ "ldtr $\x01, [$\x02]\0"
|
|
/* 10301 */ "stumaxb $\x02, [$\x03]\0"
|
|
/* 10318 */ "stumaxh $\x02, [$\x03]\0"
|
|
/* 10335 */ "stumaxlb $\x02, [$\x03]\0"
|
|
/* 10353 */ "stumaxlh $\x02, [$\x03]\0"
|
|
/* 10371 */ "stumaxl $\x02, [$\x03]\0"
|
|
/* 10388 */ "stumax $\x02, [$\x03]\0"
|
|
/* 10404 */ "stuminb $\x02, [$\x03]\0"
|
|
/* 10421 */ "stuminh $\x02, [$\x03]\0"
|
|
/* 10438 */ "stuminlb $\x02, [$\x03]\0"
|
|
/* 10456 */ "stuminlh $\x02, [$\x03]\0"
|
|
/* 10474 */ "stuminl $\x02, [$\x03]\0"
|
|
/* 10491 */ "stumin $\x02, [$\x03]\0"
|
|
/* 10507 */ "ldurb $\x01, [$\x02]\0"
|
|
/* 10522 */ "ldur $\x01, [$\x02]\0"
|
|
/* 10536 */ "ldurh $\x01, [$\x02]\0"
|
|
/* 10551 */ "ldursb $\x01, [$\x02]\0"
|
|
/* 10567 */ "ldursh $\x01, [$\x02]\0"
|
|
/* 10583 */ "ldursw $\x01, [$\x02]\0"
|
|
/* 10599 */ "mul $\x01, $\x02, $\x03\0"
|
|
/* 10614 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10639 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10664 */ "mov $\xFF\x01\x2B, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10689 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10714 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10739 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10764 */ "mov $\xFF\x01\x2B, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10789 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0"
|
|
/* 10814 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10839 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10864 */ "mov $\xFF\x01\x2B, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10889 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10914 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10939 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10964 */ "mov $\xFF\x01\x2B, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0"
|
|
/* 10989 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0"
|
|
/* 11014 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0"
|
|
/* 11039 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0"
|
|
/* 11064 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x2B\0"
|
|
/* 11089 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0"
|
|
/* 11114 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0"
|
|
/* 11139 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0"
|
|
/* 11164 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x2B\0"
|
|
/* 11189 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0"
|
|
/* 11214 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0"
|
|
/* 11239 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0"
|
|
/* 11264 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x2B\0"
|
|
/* 11289 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0"
|
|
/* 11314 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0"
|
|
/* 11339 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0"
|
|
/* 11364 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x2B\0"
|
|
/* 11389 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0"
|
|
/* 11414 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx2]\0"
|
|
/* 11445 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx2], $\xFF\x05\x23\0"
|
|
/* 11476 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx4]\0"
|
|
/* 11507 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx4], $\xFF\x05\x23\0"
|
|
/* 11538 */ "movt $\x01, $\xFF\x03\x07\0"
|
|
/* 11552 */ "smstart\0"
|
|
/* 11560 */ "smstart sm\0"
|
|
/* 11571 */ "smstart za\0"
|
|
/* 11582 */ "smstop\0"
|
|
/* 11589 */ "smstop sm\0"
|
|
/* 11599 */ "smstop za\0"
|
|
/* 11609 */ "mneg $\x01, $\x02, $\x03\0"
|
|
/* 11625 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0"
|
|
/* 11648 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0"
|
|
/* 11669 */ "mvn $\x01, $\x03\0"
|
|
/* 11680 */ "mvn $\x01, $\x03$\xFF\x04\x02\0"
|
|
/* 11695 */ "orn $\x01, $\x02, $\x03\0"
|
|
/* 11710 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0"
|
|
/* 11726 */ "mov $\x01, $\x03\0"
|
|
/* 11737 */ "orr $\x01, $\x02, $\x03\0"
|
|
/* 11752 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0"
|
|
/* 11767 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
|
|
/* 11788 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
|
|
/* 11809 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
|
|
/* 11830 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0"
|
|
/* 11845 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0"
|
|
/* 11868 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0"
|
|
/* 11889 */ "pacia1716\0"
|
|
/* 11899 */ "paciasp\0"
|
|
/* 11907 */ "paciaz\0"
|
|
/* 11914 */ "pacib1716\0"
|
|
/* 11924 */ "pacibsp\0"
|
|
/* 11932 */ "pacibz\0"
|
|
/* 11939 */ "pacm\0"
|
|
/* 11944 */ "pmov $\xFF\x01\x06, $\xFF\x02\x07\0"
|
|
/* 11960 */ "pmov $\xFF\x01\x07, $\xFF\x04\x06\0"
|
|
/* 11976 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 12000 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12022 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 12046 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 12070 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12092 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 12116 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 12140 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12162 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 12186 */ "prfm $\xFF\x01\x3D, [$\x02, $\x03]\0"
|
|
/* 12206 */ "prfm $\xFF\x01\x3D, [$\x02]\0"
|
|
/* 12222 */ "prfum $\xFF\x01\x3D, [$\x02]\0"
|
|
/* 12239 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 12263 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12285 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 12309 */ "ptrues $\xFF\x01\x06\0"
|
|
/* 12321 */ "ptrues $\xFF\x01\x10\0"
|
|
/* 12333 */ "ptrues $\xFF\x01\x09\0"
|
|
/* 12345 */ "ptrues $\xFF\x01\x0B\0"
|
|
/* 12357 */ "ptrue $\xFF\x01\x06\0"
|
|
/* 12368 */ "ptrue $\xFF\x01\x10\0"
|
|
/* 12379 */ "ptrue $\xFF\x01\x09\0"
|
|
/* 12390 */ "ptrue $\xFF\x01\x0B\0"
|
|
/* 12401 */ "ret\0"
|
|
/* 12405 */ "ngcs $\x01, $\x03\0"
|
|
/* 12417 */ "ngc $\x01, $\x03\0"
|
|
/* 12428 */ "asr $\x01, $\x02, $\x03\0"
|
|
/* 12443 */ "sxtb $\x01, $\x02\0"
|
|
/* 12455 */ "sxth $\x01, $\x02\0"
|
|
/* 12467 */ "sxtw $\x01, $\x02\0"
|
|
/* 12479 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0"
|
|
/* 12502 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0"
|
|
/* 12525 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0"
|
|
/* 12548 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0"
|
|
/* 12571 */ "smull $\x01, $\x02, $\x03\0"
|
|
/* 12588 */ "smnegl $\x01, $\x02, $\x03\0"
|
|
/* 12606 */ "sqdecb $\x01\0"
|
|
/* 12616 */ "sqdecb $\x01, $\xFF\x03\x0E\0"
|
|
/* 12632 */ "sqdecb $\x01, $\xFF\x02\x3E\0"
|
|
/* 12648 */ "sqdecb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 12670 */ "sqdecd $\x01\0"
|
|
/* 12680 */ "sqdecd $\x01, $\xFF\x03\x0E\0"
|
|
/* 12696 */ "sqdecd $\x01, $\xFF\x02\x3E\0"
|
|
/* 12712 */ "sqdecd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 12734 */ "sqdecd $\xFF\x01\x10\0"
|
|
/* 12746 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 12764 */ "sqdech $\x01\0"
|
|
/* 12774 */ "sqdech $\x01, $\xFF\x03\x0E\0"
|
|
/* 12790 */ "sqdech $\x01, $\xFF\x02\x3E\0"
|
|
/* 12806 */ "sqdech $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 12828 */ "sqdech $\xFF\x01\x09\0"
|
|
/* 12840 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 12858 */ "sqdecw $\x01\0"
|
|
/* 12868 */ "sqdecw $\x01, $\xFF\x03\x0E\0"
|
|
/* 12884 */ "sqdecw $\x01, $\xFF\x02\x3E\0"
|
|
/* 12900 */ "sqdecw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 12922 */ "sqdecw $\xFF\x01\x0B\0"
|
|
/* 12934 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 12952 */ "sqincb $\x01\0"
|
|
/* 12962 */ "sqincb $\x01, $\xFF\x03\x0E\0"
|
|
/* 12978 */ "sqincb $\x01, $\xFF\x02\x3E\0"
|
|
/* 12994 */ "sqincb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 13016 */ "sqincd $\x01\0"
|
|
/* 13026 */ "sqincd $\x01, $\xFF\x03\x0E\0"
|
|
/* 13042 */ "sqincd $\x01, $\xFF\x02\x3E\0"
|
|
/* 13058 */ "sqincd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 13080 */ "sqincd $\xFF\x01\x10\0"
|
|
/* 13092 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 13110 */ "sqinch $\x01\0"
|
|
/* 13120 */ "sqinch $\x01, $\xFF\x03\x0E\0"
|
|
/* 13136 */ "sqinch $\x01, $\xFF\x02\x3E\0"
|
|
/* 13152 */ "sqinch $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 13174 */ "sqinch $\xFF\x01\x09\0"
|
|
/* 13186 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 13204 */ "sqincw $\x01\0"
|
|
/* 13214 */ "sqincw $\x01, $\xFF\x03\x0E\0"
|
|
/* 13230 */ "sqincw $\x01, $\xFF\x02\x3E\0"
|
|
/* 13246 */ "sqincw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0"
|
|
/* 13268 */ "sqincw $\xFF\x01\x0B\0"
|
|
/* 13280 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 13298 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 13322 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 13346 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 13370 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 13394 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 13418 */ "st1q $\xFF\x01\x25, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 13442 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 13466 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 13490 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13512 */ "st1b $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13534 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13556 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13578 */ "st1b $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13600 */ "st1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13622 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13644 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13666 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13688 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13710 */ "st1d $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13732 */ "st1 $\xFF\x02\x2C, [$\x01], #64\0"
|
|
/* 13752 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 13772 */ "st1 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 13792 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 13812 */ "st1 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 13832 */ "st1 $\xFF\x02\x31, [$\x01], #64\0"
|
|
/* 13852 */ "st1 $\xFF\x02\x32, [$\x01], #32\0"
|
|
/* 13872 */ "st1 $\xFF\x02\x33, [$\x01], #64\0"
|
|
/* 13892 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13914 */ "st1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13936 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 13958 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13980 */ "st1h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14002 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14024 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 14044 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0"
|
|
/* 14063 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0"
|
|
/* 14083 */ "st1 $\xFF\x02\x2F, [$\x01], #8\0"
|
|
/* 14102 */ "st1 $\xFF\x02\x30, [$\x01], #8\0"
|
|
/* 14121 */ "st1 $\xFF\x02\x31, [$\x01], #16\0"
|
|
/* 14141 */ "st1 $\xFF\x02\x32, [$\x01], #8\0"
|
|
/* 14160 */ "st1 $\xFF\x02\x33, [$\x01], #16\0"
|
|
/* 14180 */ "st1 $\xFF\x02\x2C, [$\x01], #48\0"
|
|
/* 14200 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 14220 */ "st1 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 14240 */ "st1 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 14260 */ "st1 $\xFF\x02\x30, [$\x01], #24\0"
|
|
/* 14280 */ "st1 $\xFF\x02\x31, [$\x01], #48\0"
|
|
/* 14300 */ "st1 $\xFF\x02\x32, [$\x01], #24\0"
|
|
/* 14320 */ "st1 $\xFF\x02\x33, [$\x01], #48\0"
|
|
/* 14340 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 14360 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 14380 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 14400 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 14420 */ "st1 $\xFF\x02\x30, [$\x01], #16\0"
|
|
/* 14440 */ "st1 $\xFF\x02\x31, [$\x01], #32\0"
|
|
/* 14460 */ "st1 $\xFF\x02\x32, [$\x01], #16\0"
|
|
/* 14480 */ "st1 $\xFF\x02\x33, [$\x01], #32\0"
|
|
/* 14500 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 14522 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 14544 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14566 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14588 */ "st1w $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14610 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14644 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14678 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14712 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14746 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14780 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14814 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14848 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14882 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14916 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 14950 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #2\0"
|
|
/* 14973 */ "st1 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #4\0"
|
|
/* 14996 */ "st1 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #8\0"
|
|
/* 15019 */ "st1 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #1\0"
|
|
/* 15042 */ "st2b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15064 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15086 */ "st2g $\x01, [$\x02]\0"
|
|
/* 15100 */ "st2h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15122 */ "st2q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15144 */ "st2 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 15164 */ "st2 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 15184 */ "st2 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 15204 */ "st2 $\xFF\x02\x30, [$\x01], #16\0"
|
|
/* 15224 */ "st2 $\xFF\x02\x31, [$\x01], #32\0"
|
|
/* 15244 */ "st2 $\xFF\x02\x32, [$\x01], #16\0"
|
|
/* 15264 */ "st2 $\xFF\x02\x33, [$\x01], #32\0"
|
|
/* 15284 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15306 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #4\0"
|
|
/* 15329 */ "st2 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #8\0"
|
|
/* 15352 */ "st2 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #16\0"
|
|
/* 15376 */ "st2 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #2\0"
|
|
/* 15399 */ "st3b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15421 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15443 */ "st3h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15465 */ "st3q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15487 */ "st3 $\xFF\x02\x2C, [$\x01], #48\0"
|
|
/* 15507 */ "st3 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 15527 */ "st3 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 15547 */ "st3 $\xFF\x02\x30, [$\x01], #24\0"
|
|
/* 15567 */ "st3 $\xFF\x02\x31, [$\x01], #48\0"
|
|
/* 15587 */ "st3 $\xFF\x02\x32, [$\x01], #24\0"
|
|
/* 15607 */ "st3 $\xFF\x02\x33, [$\x01], #48\0"
|
|
/* 15627 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15649 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #6\0"
|
|
/* 15672 */ "st3 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #12\0"
|
|
/* 15696 */ "st3 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #24\0"
|
|
/* 15720 */ "st3 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #3\0"
|
|
/* 15743 */ "st4b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15765 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15787 */ "st4 $\xFF\x02\x2C, [$\x01], #64\0"
|
|
/* 15807 */ "st4 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 15827 */ "st4 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 15847 */ "st4 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 15867 */ "st4 $\xFF\x02\x31, [$\x01], #64\0"
|
|
/* 15887 */ "st4 $\xFF\x02\x32, [$\x01], #32\0"
|
|
/* 15907 */ "st4 $\xFF\x02\x33, [$\x01], #64\0"
|
|
/* 15927 */ "st4h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15949 */ "st4q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15971 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 15993 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #8\0"
|
|
/* 16016 */ "st4 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #16\0"
|
|
/* 16040 */ "st4 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #32\0"
|
|
/* 16064 */ "st4 $\xFF\x02\x2A$\xFF\x03\x19, [$\x01], #4\0"
|
|
/* 16087 */ "stgp $\x01, $\x02, [$\x03]\0"
|
|
/* 16105 */ "stg $\x01, [$\x02]\0"
|
|
/* 16118 */ "stlurb $\x01, [$\x02]\0"
|
|
/* 16134 */ "stlurh $\x01, [$\x02]\0"
|
|
/* 16150 */ "stlur $\x01, [$\x02]\0"
|
|
/* 16165 */ "stnp $\x01, $\x02, [$\x03]\0"
|
|
/* 16183 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16207 */ "stnt1b $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16231 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16255 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 16279 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 16305 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 16331 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16355 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16379 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 16403 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 16429 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16453 */ "stnt1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16477 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16501 */ "stnt1h $\xFF\x01\x2B, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 16525 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 16551 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 16577 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16601 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0"
|
|
/* 16625 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 16649 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 16675 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 16701 */ "stp $\x01, $\x02, [$\x03]\0"
|
|
/* 16718 */ "strb $\x01, [$\x02, $\x03]\0"
|
|
/* 16736 */ "strb $\x01, [$\x02]\0"
|
|
/* 16750 */ "str $\x01, [$\x02, $\x03]\0"
|
|
/* 16767 */ "str $\x01, [$\x02]\0"
|
|
/* 16780 */ "strh $\x01, [$\x02, $\x03]\0"
|
|
/* 16798 */ "strh $\x01, [$\x02]\0"
|
|
/* 16812 */ "str $\xFF\x01\x07, [$\x02]\0"
|
|
/* 16827 */ "str $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0"
|
|
/* 16852 */ "sttrb $\x01, [$\x02]\0"
|
|
/* 16867 */ "sttrh $\x01, [$\x02]\0"
|
|
/* 16882 */ "sttr $\x01, [$\x02]\0"
|
|
/* 16896 */ "sturb $\x01, [$\x02]\0"
|
|
/* 16911 */ "stur $\x01, [$\x02]\0"
|
|
/* 16925 */ "sturh $\x01, [$\x02]\0"
|
|
/* 16940 */ "stz2g $\x01, [$\x02]\0"
|
|
/* 16955 */ "stzg $\x01, [$\x02]\0"
|
|
/* 16969 */ "subpt $\x01, $\x02, $\x03\0"
|
|
/* 16986 */ "cmp $\x02, $\xFF\x03\x01\0"
|
|
/* 16999 */ "cmp $\x02, $\x03\0"
|
|
/* 17010 */ "cmp $\x02, $\x03$\xFF\x04\x02\0"
|
|
/* 17025 */ "negs $\x01, $\x03\0"
|
|
/* 17037 */ "negs $\x01, $\x03$\xFF\x04\x02\0"
|
|
/* 17053 */ "subs $\x01, $\x02, $\x03\0"
|
|
/* 17069 */ "cmp $\x02, $\x03$\xFF\x04\x03\0"
|
|
/* 17084 */ "neg $\x01, $\x03\0"
|
|
/* 17095 */ "neg $\x01, $\x03$\xFF\x04\x02\0"
|
|
/* 17110 */ "sub $\x01, $\x02, $\x03\0"
|
|
/* 17125 */ "sysp $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0"
|
|
/* 17149 */ "sys $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0"
|
|
/* 17172 */ "lsr $\x01, $\x02, $\x03\0"
|
|
/* 17187 */ "uxtb $\x01, $\x02\0"
|
|
/* 17199 */ "uxth $\x01, $\x02\0"
|
|
/* 17211 */ "uxtw $\x01, $\x02\0"
|
|
/* 17223 */ "umull $\x01, $\x02, $\x03\0"
|
|
/* 17240 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0"
|
|
/* 17259 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0"
|
|
/* 17278 */ "umnegl $\x01, $\x02, $\x03\0"
|
|
/* 17296 */ "uqdecb $\x01\0"
|
|
/* 17306 */ "uqdecb $\x01, $\xFF\x03\x0E\0"
|
|
/* 17322 */ "uqdecd $\x01\0"
|
|
/* 17332 */ "uqdecd $\x01, $\xFF\x03\x0E\0"
|
|
/* 17348 */ "uqdecd $\xFF\x01\x10\0"
|
|
/* 17360 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 17378 */ "uqdech $\x01\0"
|
|
/* 17388 */ "uqdech $\x01, $\xFF\x03\x0E\0"
|
|
/* 17404 */ "uqdech $\xFF\x01\x09\0"
|
|
/* 17416 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 17434 */ "uqdecw $\x01\0"
|
|
/* 17444 */ "uqdecw $\x01, $\xFF\x03\x0E\0"
|
|
/* 17460 */ "uqdecw $\xFF\x01\x0B\0"
|
|
/* 17472 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 17490 */ "uqincb $\x01\0"
|
|
/* 17500 */ "uqincb $\x01, $\xFF\x03\x0E\0"
|
|
/* 17516 */ "uqincd $\x01\0"
|
|
/* 17526 */ "uqincd $\x01, $\xFF\x03\x0E\0"
|
|
/* 17542 */ "uqincd $\xFF\x01\x10\0"
|
|
/* 17554 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 17572 */ "uqinch $\x01\0"
|
|
/* 17582 */ "uqinch $\x01, $\xFF\x03\x0E\0"
|
|
/* 17598 */ "uqinch $\xFF\x01\x09\0"
|
|
/* 17610 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 17628 */ "uqincw $\x01\0"
|
|
/* 17638 */ "uqincw $\x01, $\xFF\x03\x0E\0"
|
|
/* 17654 */ "uqincw $\xFF\x01\x0B\0"
|
|
/* 17666 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 17684 */ "xpaclri\0"
|
|
/* 17692 */ "zero {za}\0"
|
|
/* 17702 */ "zero {za0.h}\0"
|
|
/* 17715 */ "zero {za1.h}\0"
|
|
/* 17728 */ "zero {za0.s}\0"
|
|
/* 17741 */ "zero {za1.s}\0"
|
|
/* 17754 */ "zero {za2.s}\0"
|
|
/* 17767 */ "zero {za3.s}\0"
|
|
/* 17780 */ "zero {za0.s,za1.s}\0"
|
|
/* 17799 */ "zero {za0.s,za3.s}\0"
|
|
/* 17818 */ "zero {za1.s,za2.s}\0"
|
|
/* 17837 */ "zero {za2.s,za3.s}\0"
|
|
/* 17856 */ "zero {za0.s,za1.s,za2.s}\0"
|
|
/* 17881 */ "zero {za0.s,za1.s,za3.s}\0"
|
|
/* 17906 */ "zero {za0.s,za2.s,za3.s}\0"
|
|
/* 17931 */ "zero {za1.s,za2.s,za3.s}\0"
|
|
;
|
|
|
|
#ifndef NDEBUG
|
|
//static struct SortCheck {
|
|
// SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
|
|
// assert(std::is_sorted(
|
|
// OpToPatterns.begin(), OpToPatterns.end(),
|
|
// [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
|
|
// return L.Opcode < R.Opcode;
|
|
// }) &&
|
|
// "tablegen failed to sort opcode patterns");
|
|
// }
|
|
//} sortCheckVar(OpToPatterns);
|
|
#endif
|
|
|
|
AliasMatchingData M = {
|
|
OpToPatterns,
|
|
Patterns,
|
|
Conds,
|
|
AsmStrings,
|
|
AArch64InstPrinterValidateMCOperand,
|
|
};
|
|
const char *AsmString = matchAliasPatterns(MI, &M);
|
|
if (!AsmString) return false;
|
|
|
|
unsigned I = 0;
|
|
while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
|
|
AsmString[I] != '$' && AsmString[I] != '\0')
|
|
++I;
|
|
SStream_concat1(OS, '\t');
|
|
char *substr = malloc(I+1);
|
|
memcpy(substr, AsmString, I);
|
|
substr[I] = '\0';
|
|
SStream_concat0(OS, substr);
|
|
free(substr);
|
|
if (AsmString[I] != '\0') {
|
|
if (AsmString[I] == ' ' || AsmString[I] == '\t') {
|
|
SStream_concat1(OS, '\t');
|
|
++I;
|
|
}
|
|
do {
|
|
if (AsmString[I] == '$') {
|
|
++I;
|
|
if (AsmString[I] == (char)0xff) {
|
|
++I;
|
|
int OpIdx = AsmString[I++] - 1;
|
|
int PrintMethodIdx = AsmString[I++] - 1;
|
|
printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
|
|
} else
|
|
printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
|
|
} else {
|
|
SStream_concat1(OS, AsmString[I++]);
|
|
}
|
|
} while (AsmString[I] != '\0');
|
|
}
|
|
|
|
return true;
|
|
#else
|
|
return false;
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
|
|
static void printCustomAliasOperand(
|
|
MCInst *MI, uint64_t Address, unsigned OpIdx,
|
|
unsigned PrintMethodIdx,
|
|
SStream *OS) {
|
|
#ifndef CAPSTONE_DIET
|
|
switch (PrintMethodIdx) {
|
|
default:
|
|
CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
|
|
break;
|
|
case 0:
|
|
printAddSubImm(MI, OpIdx, OS);
|
|
break;
|
|
case 1:
|
|
printShifter(MI, OpIdx, OS);
|
|
break;
|
|
case 2:
|
|
printArithExtend(MI, OpIdx, OS);
|
|
break;
|
|
case 3:
|
|
printLogicalImm_int32_t(MI, OpIdx, OS);
|
|
break;
|
|
case 4:
|
|
printLogicalImm_int64_t(MI, OpIdx, OS);
|
|
break;
|
|
case 5:
|
|
printSVERegOp_b(MI, OpIdx, OS);
|
|
break;
|
|
case 6:
|
|
printSVERegOp_0(MI, OpIdx, OS);
|
|
break;
|
|
case 7:
|
|
printLogicalImm_int8_t(MI, OpIdx, OS);
|
|
break;
|
|
case 8:
|
|
printSVERegOp_h(MI, OpIdx, OS);
|
|
break;
|
|
case 9:
|
|
printLogicalImm_int16_t(MI, OpIdx, OS);
|
|
break;
|
|
case 10:
|
|
printSVERegOp_s(MI, OpIdx, OS);
|
|
break;
|
|
case 11:
|
|
printVRegOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 12:
|
|
printImm(MI, OpIdx, OS);
|
|
break;
|
|
case 13:
|
|
printSVEPattern(MI, OpIdx, OS);
|
|
break;
|
|
case 14:
|
|
printImm8OptLsl_int8_t(MI, OpIdx, OS);
|
|
break;
|
|
case 15:
|
|
printSVERegOp_d(MI, OpIdx, OS);
|
|
break;
|
|
case 16:
|
|
printImm8OptLsl_int64_t(MI, OpIdx, OS);
|
|
break;
|
|
case 17:
|
|
printImm8OptLsl_int16_t(MI, OpIdx, OS);
|
|
break;
|
|
case 18:
|
|
printImm8OptLsl_int32_t(MI, OpIdx, OS);
|
|
break;
|
|
case 19:
|
|
printInverseCondCode(MI, OpIdx, OS);
|
|
break;
|
|
case 20:
|
|
printSVELogicalImm_int16_t(MI, OpIdx, OS);
|
|
break;
|
|
case 21:
|
|
printSVELogicalImm_int32_t(MI, OpIdx, OS);
|
|
break;
|
|
case 22:
|
|
printSVELogicalImm_int64_t(MI, OpIdx, OS);
|
|
break;
|
|
case 23:
|
|
printZPRasFPR_8(MI, OpIdx, OS);
|
|
break;
|
|
case 24:
|
|
printVectorIndex_1(MI, OpIdx, OS);
|
|
break;
|
|
case 25:
|
|
printZPRasFPR_64(MI, OpIdx, OS);
|
|
break;
|
|
case 26:
|
|
printZPRasFPR_16(MI, OpIdx, OS);
|
|
break;
|
|
case 27:
|
|
printSVERegOp_q(MI, OpIdx, OS);
|
|
break;
|
|
case 28:
|
|
printZPRasFPR_128(MI, OpIdx, OS);
|
|
break;
|
|
case 29:
|
|
printZPRasFPR_32(MI, OpIdx, OS);
|
|
break;
|
|
case 30:
|
|
printMatrixTileVector_0(MI, OpIdx, OS);
|
|
break;
|
|
case 31:
|
|
printMatrixIndex_1(MI, OpIdx, OS);
|
|
break;
|
|
case 32:
|
|
printMatrixTileVector_1(MI, OpIdx, OS);
|
|
break;
|
|
case 33:
|
|
printFPImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 34:
|
|
printTypedVectorList_0_d(MI, OpIdx, OS);
|
|
break;
|
|
case 35:
|
|
printTypedVectorList_0_s(MI, OpIdx, OS);
|
|
break;
|
|
case 36:
|
|
printTypedVectorList_0_q(MI, OpIdx, OS);
|
|
break;
|
|
case 37:
|
|
printBTIHintOp(MI, OpIdx, OS);
|
|
break;
|
|
case 38:
|
|
printPSBHintOp(MI, OpIdx, OS);
|
|
break;
|
|
case 39:
|
|
printTypedVectorList_0_b(MI, OpIdx, OS);
|
|
break;
|
|
case 40:
|
|
printPredicateAsCounter_0(MI, OpIdx, OS);
|
|
break;
|
|
case 41:
|
|
printTypedVectorList_0_b(MI, OpIdx, OS);
|
|
break;
|
|
case 42:
|
|
printTypedVectorList_0_h(MI, OpIdx, OS);
|
|
break;
|
|
case 43:
|
|
printTypedVectorList_16_b(MI, OpIdx, OS);
|
|
break;
|
|
case 44:
|
|
printTypedVectorList_1_d(MI, OpIdx, OS);
|
|
break;
|
|
case 45:
|
|
printTypedVectorList_2_d(MI, OpIdx, OS);
|
|
break;
|
|
case 46:
|
|
printTypedVectorList_2_s(MI, OpIdx, OS);
|
|
break;
|
|
case 47:
|
|
printTypedVectorList_4_h(MI, OpIdx, OS);
|
|
break;
|
|
case 48:
|
|
printTypedVectorList_4_s(MI, OpIdx, OS);
|
|
break;
|
|
case 49:
|
|
printTypedVectorList_8_b(MI, OpIdx, OS);
|
|
break;
|
|
case 50:
|
|
printTypedVectorList_8_h(MI, OpIdx, OS);
|
|
break;
|
|
case 51:
|
|
printTypedVectorList_0_h(MI, OpIdx, OS);
|
|
break;
|
|
case 52:
|
|
printTypedVectorList_0_s(MI, OpIdx, OS);
|
|
break;
|
|
case 53:
|
|
printTypedVectorList_0_d(MI, OpIdx, OS);
|
|
break;
|
|
case 54:
|
|
printMatrix_0(MI, OpIdx, OS);
|
|
break;
|
|
case 55:
|
|
printImmRangeScale_2_1(MI, OpIdx, OS);
|
|
break;
|
|
case 56:
|
|
printImmRangeScale_4_3(MI, OpIdx, OS);
|
|
break;
|
|
case 57:
|
|
printMatrix_64(MI, OpIdx, OS);
|
|
break;
|
|
case 58:
|
|
printImmHex(MI, OpIdx, OS);
|
|
break;
|
|
case 59:
|
|
printPrefetchOp_1(MI, OpIdx, OS);
|
|
break;
|
|
case 60:
|
|
printPrefetchOp_0(MI, OpIdx, OS);
|
|
break;
|
|
case 61:
|
|
printGPR64as32(MI, OpIdx, OS);
|
|
break;
|
|
case 62:
|
|
printSysCROperand(MI, OpIdx, OS);
|
|
break;
|
|
}
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
|
|
static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp,
|
|
unsigned PredicateIndex) {
|
|
switch (PredicateIndex) {
|
|
default:
|
|
CS_ASSERT_RET_VAL(0 && "Unknown MCOperandPredicate kind", false);
|
|
return false;
|
|
case 1: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements_int8_t(Val);
|
|
|
|
}
|
|
case 2: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements_int16_t(Val);
|
|
|
|
}
|
|
case 3: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements_int32_t(Val);
|
|
|
|
}
|
|
case 4: {
|
|
|
|
return MCOperand_isImm(MCOp) &&
|
|
MCOperand_getImm(MCOp) != AArch64CC_AL &&
|
|
MCOperand_getImm(MCOp) != AArch64CC_NV;
|
|
|
|
}
|
|
case 5: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements_int16_t(Val) &&
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val);
|
|
|
|
}
|
|
case 6: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements_int32_t(Val) &&
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val);
|
|
|
|
}
|
|
case 7: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
int64_t Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements_int64_t(Val) &&
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val);
|
|
|
|
}
|
|
case 8: {
|
|
|
|
// "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
return AArch64BTIHint_lookupBTIByEncoding(MCOperand_getImm(MCOp) ^ 32) != NULL;
|
|
|
|
}
|
|
case 9: {
|
|
|
|
// Check, if operand is valid, to fix exhaustive aliasing in disassembly.
|
|
// "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
return AArch64PSBHint_lookupPSBByEncoding(MCOperand_getImm(MCOp)) != NULL;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|