16638 lines
455 KiB
C
16638 lines
455 KiB
C
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#include <capstone/platform.h>
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#include "../../cs_priv.h"
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/// getMnemonic - This method is automatically generated by tablegen
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/// from the instruction set description.
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static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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#ifndef CAPSTONE_DIET
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static const char AsmStrs[] = {
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/* 0 */ "#EH_SjLj_Setup\t\0"
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/* 16 */ "bctrl\n\tld 2, \0"
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/* 30 */ "bctrl\n\tlwz 2, \0"
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/* 45 */ "bc 12, \0"
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/* 53 */ "bcl 12, \0"
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/* 62 */ "bclrl 12, \0"
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/* 73 */ "bcctrl 12, \0"
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/* 85 */ "bclr 12, \0"
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/* 95 */ "bcctr 12, \0"
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/* 106 */ "mtspr 3, \0"
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/* 116 */ "mtspr 256, \0"
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/* 128 */ "ps_merge00. \0"
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/* 141 */ "ps_merge10. \0"
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/* 154 */ "ps_sum0. \0"
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/* 164 */ "ps_madds0. \0"
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/* 176 */ "ps_muls0. \0"
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/* 187 */ "ps_merge01. \0"
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/* 200 */ "ps_merge11. \0"
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/* 213 */ "ps_sum1. \0"
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/* 223 */ "ps_madds1. \0"
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/* 235 */ "ps_muls1. \0"
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/* 246 */ "dqua. \0"
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/* 253 */ "vcmpneb. \0"
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/* 263 */ "vcmpgtsb. \0"
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/* 274 */ "extsb. \0"
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/* 282 */ "vcmpequb. \0"
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/* 293 */ "ps_sub. \0"
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/* 302 */ "bcdsub. \0"
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/* 311 */ "fsub. \0"
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/* 318 */ "ps_msub. \0"
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/* 328 */ "fmsub. \0"
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/* 336 */ "ps_nmsub. \0"
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/* 347 */ "fnmsub. \0"
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/* 356 */ "vcmpgtub. \0"
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/* 367 */ "vcmpnezb. \0"
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/* 378 */ "addc. \0"
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/* 385 */ "andc. \0"
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/* 392 */ "tabortdc. \0"
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/* 403 */ "subfc. \0"
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/* 411 */ "subic. \0"
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/* 419 */ "addic. \0"
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/* 427 */ "rldic. \0"
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/* 435 */ "bcdtrunc. \0"
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/* 446 */ "bcdutrunc. \0"
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/* 458 */ "orc. \0"
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/* 464 */ "tabortwc. \0"
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/* 475 */ "srad. \0"
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/* 482 */ "denbcd. \0"
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/* 491 */ "ps_add. \0"
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/* 500 */ "bcdadd. \0"
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/* 509 */ "fadd. \0"
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/* 516 */ "ps_madd. \0"
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/* 526 */ "fmadd. \0"
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/* 534 */ "ps_nmadd. \0"
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/* 545 */ "fnmadd. \0"
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/* 554 */ "mulhd. \0"
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/* 562 */ "fcfid. \0"
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/* 570 */ "fctid. \0"
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/* 578 */ "mulld. \0"
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/* 586 */ "sld. \0"
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/* 592 */ "nand. \0"
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/* 599 */ "tend. \0"
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/* 606 */ "drrnd. \0"
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/* 614 */ "ddedpd. \0"
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/* 623 */ "srd. \0"
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/* 629 */ "vcmpgtsd. \0"
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/* 640 */ "vcmpequd. \0"
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/* 651 */ "vcmpgtud. \0"
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/* 662 */ "divd. \0"
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/* 669 */ "cntlzd. \0"
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/* 678 */ "cnttzd. \0"
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/* 687 */ "adde. \0"
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/* 694 */ "divde. \0"
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/* 702 */ "slbfee. \0"
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/* 711 */ "subfe. \0"
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/* 719 */ "addme. \0"
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/* 727 */ "subfme. \0"
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/* 736 */ "fre. \0"
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/* 742 */ "ps_rsqrte. \0"
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/* 754 */ "frsqrte. \0"
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/* 764 */ "paste. \0"
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/* 772 */ "divwe. \0"
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/* 780 */ "addze. \0"
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/* 788 */ "subfze. \0"
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/* 797 */ "subf. \0"
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/* 804 */ "mtfsf. \0"
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/* 812 */ "ps_neg. \0"
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/* 821 */ "fneg. \0"
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/* 828 */ "vcmpneh. \0"
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/* 838 */ "vcmpgtsh. \0"
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/* 849 */ "extsh. \0"
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/* 857 */ "vcmpequh. \0"
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/* 868 */ "vcmpgtuh. \0"
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/* 879 */ "vcmpnezh. \0"
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/* 890 */ "dquai. \0"
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/* 898 */ "tabortdci. \0"
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/* 910 */ "tabortwci. \0"
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/* 922 */ "sradi. \0"
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/* 930 */ "clrlsldi. \0"
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/* 941 */ "extldi. \0"
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/* 950 */ "andi. \0"
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/* 957 */ "clrrdi. \0"
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/* 966 */ "insrdi. \0"
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/* 975 */ "rotrdi. \0"
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/* 984 */ "extrdi. \0"
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/* 993 */ "mtfsfi. \0"
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/* 1002 */ "dscli. \0"
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/* 1010 */ "extswsli. \0"
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/* 1021 */ "rldimi. \0"
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/* 1030 */ "rlwimi. \0"
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/* 1039 */ "dscri. \0"
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/* 1047 */ "srawi. \0"
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/* 1055 */ "clrlslwi. \0"
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/* 1066 */ "inslwi. \0"
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/* 1075 */ "extlwi. \0"
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/* 1084 */ "clrrwi. \0"
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/* 1093 */ "insrwi. \0"
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/* 1102 */ "rotrwi. \0"
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/* 1111 */ "extrwi. \0"
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/* 1120 */ "vstribl. \0"
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/* 1130 */ "rldcl. \0"
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/* 1138 */ "rldicl. \0"
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/* 1147 */ "ps_sel. \0"
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/* 1156 */ "fsel. \0"
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/* 1163 */ "vstrihl. \0"
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/* 1173 */ "ps_mul. \0"
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/* 1182 */ "dmul. \0"
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/* 1189 */ "fmul. \0"
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/* 1196 */ "treclaim. \0"
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/* 1207 */ "frim. \0"
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/* 1214 */ "rlwinm. \0"
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/* 1223 */ "rlwnm. \0"
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/* 1231 */ "bcdcfn. \0"
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/* 1240 */ "bcdcpsgn. \0"
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/* 1251 */ "fcpsgn. \0"
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/* 1260 */ "bcdsetsgn. \0"
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/* 1272 */ "tbegin. \0"
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/* 1281 */ "frin. \0"
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/* 1288 */ "bcdctn. \0"
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/* 1297 */ "drintn. \0"
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/* 1306 */ "addco. \0"
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/* 1314 */ "subfco. \0"
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/* 1323 */ "addo. \0"
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/* 1330 */ "mulldo. \0"
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/* 1339 */ "divdo. \0"
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/* 1347 */ "addeo. \0"
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/* 1355 */ "divdeo. \0"
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/* 1364 */ "subfeo. \0"
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/* 1373 */ "addmeo. \0"
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/* 1382 */ "subfmeo. \0"
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/* 1392 */ "divweo. \0"
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/* 1401 */ "addzeo. \0"
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/* 1410 */ "subfzeo. \0"
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/* 1420 */ "subfo. \0"
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/* 1428 */ "nego. \0"
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/* 1435 */ "divduo. \0"
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/* 1444 */ "divdeuo. \0"
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/* 1454 */ "divweuo. \0"
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/* 1464 */ "divwuo. \0"
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/* 1473 */ "mullwo. \0"
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/* 1482 */ "divwo. \0"
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/* 1490 */ "xvcmpgedp. \0"
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/* 1502 */ "xvcmpeqdp. \0"
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/* 1514 */ "dctdp. \0"
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/* 1522 */ "xvcmpgtdp. \0"
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/* 1534 */ "vcmpbfp. \0"
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/* 1544 */ "vcmpgefp. \0"
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/* 1555 */ "vcmpeqfp. \0"
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/* 1566 */ "vcmpgtfp. \0"
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/* 1577 */ "frip. \0"
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/* 1584 */ "xvcmpgesp. \0"
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/* 1596 */ "xvcmpeqsp. \0"
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/* 1608 */ "drsp. \0"
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/* 1615 */ "frsp. \0"
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/* 1622 */ "xvcmpgtsp. \0"
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/* 1634 */ "dquaq. \0"
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/* 1642 */ "dsubq. \0"
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/* 1650 */ "denbcdq. \0"
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/* 1660 */ "daddq. \0"
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/* 1668 */ "drrndq. \0"
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/* 1677 */ "ddedpdq. \0"
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/* 1687 */ "dquaiq. \0"
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/* 1696 */ "dscliq. \0"
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/* 1705 */ "dscriq. \0"
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/* 1714 */ "icblq. \0"
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/* 1722 */ "dmulq. \0"
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/* 1730 */ "drintnq. \0"
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/* 1740 */ "drdpq. \0"
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/* 1748 */ "dctqpq. \0"
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/* 1757 */ "bcdcfsq. \0"
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/* 1767 */ "bcdctsq. \0"
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/* 1777 */ "vcmpgtsq. \0"
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/* 1788 */ "vcmpequq. \0"
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/* 1799 */ "vcmpgtuq. \0"
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/* 1810 */ "ddivq. \0"
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/* 1818 */ "diexq. \0"
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/* 1826 */ "dxexq. \0"
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/* 1834 */ "dcffixq. \0"
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/* 1844 */ "dctfixq. \0"
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/* 1854 */ "drintxq. \0"
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/* 1864 */ "vstribr. \0"
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/* 1874 */ "rldcr. \0"
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/* 1882 */ "rldicr. \0"
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/* 1891 */ "vstrihr. \0"
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/* 1901 */ "ps_mr. \0"
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/* 1909 */ "fmr. \0"
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/* 1915 */ "nor. \0"
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/* 1921 */ "xor. \0"
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/* 1927 */ "bcdsr. \0"
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/* 1935 */ "tsr. \0"
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/* 1941 */ "ps_abs. \0"
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/* 1950 */ "fabs. \0"
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/* 1957 */ "ps_nabs. \0"
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/* 1967 */ "fnabs. \0"
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/* 1975 */ "fsubs. \0"
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/* 1983 */ "fmsubs. \0"
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/* 1992 */ "fnmsubs. \0"
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/* 2002 */ "bcds. \0"
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/* 2009 */ "fadds. \0"
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/* 2017 */ "fmadds. \0"
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/* 2026 */ "fnmadds. \0"
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/* 2036 */ "fcfids. \0"
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/* 2045 */ "ps_res. \0"
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/* 2054 */ "fres. \0"
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/* 2061 */ "frsqrtes. \0"
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/* 2072 */ "mffs. \0"
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/* 2079 */ "andis. \0"
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/* 2087 */ "fmuls. \0"
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/* 2095 */ "fsqrts. \0"
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/* 2104 */ "bcdus. \0"
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/* 2112 */ "fcfidus. \0"
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/* 2122 */ "subfus. \0"
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/* 2131 */ "fdivs. \0"
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/* 2139 */ "tabort. \0"
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/* 2148 */ "fsqrt. \0"
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/* 2156 */ "mulhdu. \0"
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/* 2165 */ "fcfidu. \0"
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/* 2174 */ "fctidu. \0"
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/* 2183 */ "divdu. \0"
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/* 2191 */ "divdeu. \0"
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/* 2200 */ "divweu. \0"
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/* 2209 */ "mulhwu. \0"
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/* 2218 */ "fctiwu. \0"
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/* 2227 */ "divwu. \0"
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/* 2235 */ "ps_div. \0"
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/* 2244 */ "ddiv. \0"
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/* 2251 */ "fdiv. \0"
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/* 2258 */ "eqv. \0"
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/* 2264 */ "sraw. \0"
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/* 2271 */ "vcmpnew. \0"
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/* 2281 */ "mulhw. \0"
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/* 2289 */ "fctiw. \0"
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/* 2297 */ "mullw. \0"
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/* 2305 */ "slw. \0"
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/* 2311 */ "srw. \0"
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/* 2317 */ "vcmpgtsw. \0"
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/* 2328 */ "extsw. \0"
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/* 2336 */ "vcmpequw. \0"
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/* 2347 */ "vcmpgtuw. \0"
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/* 2358 */ "divw. \0"
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/* 2365 */ "vcmpnezw. \0"
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/* 2376 */ "cntlzw. \0"
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/* 2385 */ "cnttzw. \0"
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/* 2394 */ "stbcx. \0"
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/* 2402 */ "stdcx. \0"
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/* 2410 */ "sthcx. \0"
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/* 2418 */ "stqcx. \0"
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/* 2426 */ "stwcx. \0"
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/* 2434 */ "diex. \0"
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/* 2441 */ "dxex. \0"
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/* 2448 */ "dcffix. \0"
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/* 2457 */ "dctfix. \0"
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/* 2466 */ "tlbsx. \0"
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/* 2474 */ "drintx. \0"
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/* 2483 */ "fctidz. \0"
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/* 2492 */ "bcdcfz. \0"
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/* 2501 */ "friz. \0"
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/* 2508 */ "bcdctz. \0"
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/* 2517 */ "fctiduz. \0"
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/* 2527 */ "fctiwuz. \0"
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/* 2537 */ "fctiwz. \0"
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/* 2546 */ "ps_merge00 \0"
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/* 2558 */ "ps_merge10 \0"
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/* 2570 */ "mtfsb0 \0"
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/* 2578 */ "ps_sum0 \0"
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/* 2587 */ "ps_cmpo0 \0"
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/* 2597 */ "ps_madds0 \0"
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/* 2608 */ "ps_muls0 \0"
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/* 2618 */ "ps_cmpu0 \0"
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/* 2628 */ "ps_merge01 \0"
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/* 2640 */ "ps_merge11 \0"
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/* 2652 */ "mtfsb1 \0"
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/* 2660 */ "ps_sum1 \0"
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/* 2669 */ "ps_cmpo1 \0"
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/* 2679 */ "ps_madds1 \0"
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/* 2690 */ "ps_muls1 \0"
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/* 2700 */ "ps_cmpu1 \0"
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/* 2710 */ "dmxxinstfdmr512 \0"
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/* 2727 */ "dmxxextfdmr512 \0"
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/* 2743 */ "#ATOMIC_CMP_SWAP_I32 \0"
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/* 2765 */ "pmxvbf16ger2 \0"
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/* 2779 */ "pmxvf16ger2 \0"
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/* 2792 */ "pmxvi16ger2 \0"
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/* 2805 */ "pmxvi8ger4 \0"
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/* 2817 */ "#ATOMIC_CMP_SWAP_I16 \0"
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/* 2839 */ "xvcvspbf16 \0"
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/* 2851 */ "dmxxinstfdmr256 \0"
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/* 2868 */ "dmxxextfdmr256 \0"
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/* 2884 */ "#TC_RETURNa8 \0"
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/* 2898 */ "#TC_RETURNd8 \0"
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/* 2912 */ "#TC_RETURNr8 \0"
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/* 2926 */ "pmxvi4ger8 \0"
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/* 2938 */ "#BUILD_UACC \0"
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/* 2951 */ "#ADJCALLSTACKDOWN \0"
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/* 2970 */ "#ADJCALLSTACKUP \0"
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/* 2987 */ "#TC_RETURNa \0"
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/* 3000 */ "evmhegsmfaa \0"
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/* 3013 */ "evmhogsmfaa \0"
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/* 3026 */ "evmwsmfaa \0"
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/* 3037 */ "evmwssfaa \0"
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/* 3048 */ "evmhegsmiaa \0"
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/* 3061 */ "evmhogsmiaa \0"
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/* 3074 */ "evmwsmiaa \0"
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/* 3085 */ "evmhegumiaa \0"
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/* 3098 */ "evmhogumiaa \0"
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/* 3111 */ "evmwumiaa \0"
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/* 3122 */ "dcba \0"
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/* 3128 */ "bca \0"
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/* 3133 */ "evmhesmfa \0"
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/* 3144 */ "evmwhsmfa \0"
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/* 3155 */ "evmhosmfa \0"
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/* 3166 */ "evmwsmfa \0"
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/* 3176 */ "evmhessfa \0"
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/* 3187 */ "evmwhssfa \0"
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/* 3198 */ "evmhossfa \0"
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/* 3209 */ "evmwssfa \0"
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/* 3219 */ "plha \0"
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/* 3225 */ "evmhesmia \0"
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/* 3236 */ "evmwhsmia \0"
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/* 3247 */ "evmhosmia \0"
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/* 3258 */ "evmwsmia \0"
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/* 3268 */ "evmheumia \0"
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/* 3279 */ "evmwhumia \0"
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/* 3290 */ "evmwlumia \0"
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/* 3301 */ "evmhoumia \0"
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/* 3312 */ "evmwumia \0"
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/* 3322 */ "qvstfcdxia \0"
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/* 3334 */ "qvstfdxia \0"
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/* 3345 */ "qvstfcsxia \0"
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/* 3357 */ "qvstfsxia \0"
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/* 3368 */ "qvstfcduxia \0"
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/* 3381 */ "qvstfduxia \0"
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/* 3393 */ "qvstfcsuxia \0"
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/* 3406 */ "qvstfsuxia \0"
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/* 3418 */ "bla \0"
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/* 3423 */ "bcla \0"
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/* 3429 */ "pla \0"
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/* 3434 */ "evmra \0"
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/* 3441 */ "dqua \0"
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/* 3447 */ "plwa \0"
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/* 3453 */ "mtvsrwa \0"
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/* 3462 */ "qvlfiwaxa \0"
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/* 3473 */ "qvlfcdxa \0"
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/* 3483 */ "qvstfcdxa \0"
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/* 3494 */ "qvlfdxa \0"
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/* 3503 */ "qvstfdxa \0"
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/* 3513 */ "qvlfcsxa \0"
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/* 3523 */ "qvstfcsxa \0"
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/* 3534 */ "qvlfsxa \0"
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/* 3543 */ "qvstfsxa \0"
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/* 3553 */ "qvlfcduxa \0"
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/* 3564 */ "qvstfcduxa \0"
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/* 3576 */ "qvlfduxa \0"
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/* 3586 */ "qvstfduxa \0"
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/* 3597 */ "qvlfcsuxa \0"
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/* 3608 */ "qvstfcsuxa \0"
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/* 3620 */ "qvlfsuxa \0"
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/* 3630 */ "qvstfsuxa \0"
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/* 3641 */ "qvstfiwxa \0"
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/* 3652 */ "qvlfiwzxa \0"
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/* 3663 */ "vsrab \0"
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/* 3670 */ "rfebb \0"
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/* 3677 */ "vcntmbb \0"
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/* 3686 */ "xvtlsbb \0"
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/* 3695 */ "vclzlsbb \0"
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/* 3705 */ "vctzlsbb \0"
|
|
/* 3715 */ "vcmpneb \0"
|
|
/* 3724 */ "vmrghb \0"
|
|
/* 3732 */ "xxspltib \0"
|
|
/* 3742 */ "vmrglb \0"
|
|
/* 3750 */ "vclrlb \0"
|
|
/* 3758 */ "vrlb \0"
|
|
/* 3764 */ "vslb \0"
|
|
/* 3770 */ "vpmsumb \0"
|
|
/* 3779 */ "vgnb \0"
|
|
/* 3785 */ "cmpb \0"
|
|
/* 3791 */ "cmpeqb \0"
|
|
/* 3799 */ "cmprb \0"
|
|
/* 3806 */ "vclrrb \0"
|
|
/* 3814 */ "vsrb \0"
|
|
/* 3820 */ "vmulesb \0"
|
|
/* 3829 */ "vavgsb \0"
|
|
/* 3837 */ "vupkhsb \0"
|
|
/* 3846 */ "vspltisb \0"
|
|
/* 3856 */ "vupklsb \0"
|
|
/* 3865 */ "vminsb \0"
|
|
/* 3873 */ "vmulosb \0"
|
|
/* 3882 */ "vcmpgtsb \0"
|
|
/* 3892 */ "evextsb \0"
|
|
/* 3901 */ "vmaxsb \0"
|
|
/* 3909 */ "setb \0"
|
|
/* 3915 */ "mftb \0"
|
|
/* 3921 */ "vspltb \0"
|
|
/* 3929 */ "vpopcntb \0"
|
|
/* 3939 */ "vinsertb \0"
|
|
/* 3949 */ "pstb \0"
|
|
/* 3955 */ "vabsdub \0"
|
|
/* 3964 */ "vmuleub \0"
|
|
/* 3973 */ "vavgub \0"
|
|
/* 3981 */ "vminub \0"
|
|
/* 3989 */ "vmuloub \0"
|
|
/* 3998 */ "vcmpequb \0"
|
|
/* 4008 */ "ps_sub \0"
|
|
/* 4016 */ "efdsub \0"
|
|
/* 4024 */ "qvfsub \0"
|
|
/* 4032 */ "ps_msub \0"
|
|
/* 4041 */ "qvfmsub \0"
|
|
/* 4050 */ "ps_nmsub \0"
|
|
/* 4060 */ "qvfnmsub \0"
|
|
/* 4070 */ "efssub \0"
|
|
/* 4078 */ "evfssub \0"
|
|
/* 4087 */ "vextractub \0"
|
|
/* 4099 */ "vcmpgtub \0"
|
|
/* 4109 */ "vmaxub \0"
|
|
/* 4117 */ "xxblendvb \0"
|
|
/* 4128 */ "vcmpnezb \0"
|
|
/* 4138 */ "vclzb \0"
|
|
/* 4145 */ "vctzb \0"
|
|
/* 4152 */ "setnbc \0"
|
|
/* 4160 */ "setbc \0"
|
|
/* 4167 */ "xxmfacc \0"
|
|
/* 4176 */ "xxmtacc \0"
|
|
/* 4185 */ "addc \0"
|
|
/* 4191 */ "xxlandc \0"
|
|
/* 4200 */ "crandc \0"
|
|
/* 4208 */ "evandc \0"
|
|
/* 4216 */ "dtstdc \0"
|
|
/* 4224 */ "subfc \0"
|
|
/* 4231 */ "subic \0"
|
|
/* 4238 */ "addic \0"
|
|
/* 4245 */ "rldic \0"
|
|
/* 4252 */ "subfic \0"
|
|
/* 4260 */ "xsrdpic \0"
|
|
/* 4269 */ "xvrdpic \0"
|
|
/* 4278 */ "xvrspic \0"
|
|
/* 4287 */ "icblc \0"
|
|
/* 4294 */ "brinc \0"
|
|
/* 4301 */ "sync \0"
|
|
/* 4307 */ "xxlorc \0"
|
|
/* 4315 */ "crorc \0"
|
|
/* 4322 */ "evorc \0"
|
|
/* 4329 */ "sc \0"
|
|
/* 4333 */ "vextsb2d \0"
|
|
/* 4343 */ "vextsh2d \0"
|
|
/* 4353 */ "vextsw2d \0"
|
|
/* 4363 */ "#TC_RETURNd \0"
|
|
/* 4376 */ "vshasigmad \0"
|
|
/* 4388 */ "vsrad \0"
|
|
/* 4395 */ "vgbbd \0"
|
|
/* 4402 */ "vcntmbd \0"
|
|
/* 4411 */ "vprtybd \0"
|
|
/* 4420 */ "denbcd \0"
|
|
/* 4428 */ "cdtbcd \0"
|
|
/* 4436 */ "ps_add \0"
|
|
/* 4444 */ "efdadd \0"
|
|
/* 4452 */ "qvfadd \0"
|
|
/* 4460 */ "ps_madd \0"
|
|
/* 4469 */ "qvfmadd \0"
|
|
/* 4478 */ "ps_nmadd \0"
|
|
/* 4488 */ "qvfnmadd \0"
|
|
/* 4498 */ "qvfxxcpnmadd \0"
|
|
/* 4512 */ "qvfxxnpmadd \0"
|
|
/* 4525 */ "qvfxmadd \0"
|
|
/* 4535 */ "qvfxxmadd \0"
|
|
/* 4546 */ "efsadd \0"
|
|
/* 4554 */ "evfsadd \0"
|
|
/* 4563 */ "evldd \0"
|
|
/* 4570 */ "mtvsrdd \0"
|
|
/* 4579 */ "evstdd \0"
|
|
/* 4587 */ "vcfuged \0"
|
|
/* 4596 */ "efscfd \0"
|
|
/* 4604 */ "plfd \0"
|
|
/* 4610 */ "pstfd \0"
|
|
/* 4617 */ "vnegd \0"
|
|
/* 4624 */ "maddhd \0"
|
|
/* 4632 */ "mulhd \0"
|
|
/* 4639 */ "qvfcfid \0"
|
|
/* 4648 */ "efdcfsid \0"
|
|
/* 4658 */ "qvfctid \0"
|
|
/* 4667 */ "efdcfuid \0"
|
|
/* 4677 */ "tlbld \0"
|
|
/* 4684 */ "maddld \0"
|
|
/* 4692 */ "vmulld \0"
|
|
/* 4700 */ "cmpld \0"
|
|
/* 4707 */ "mfvsrld \0"
|
|
/* 4716 */ "vrld \0"
|
|
/* 4722 */ "vsld \0"
|
|
/* 4728 */ "vbpermd \0"
|
|
/* 4737 */ "vpmsumd \0"
|
|
/* 4746 */ "xxland \0"
|
|
/* 4754 */ "xxlnand \0"
|
|
/* 4763 */ "crnand \0"
|
|
/* 4771 */ "evnand \0"
|
|
/* 4779 */ "crand \0"
|
|
/* 4786 */ "evand \0"
|
|
/* 4793 */ "drrnd \0"
|
|
/* 4800 */ "ddedpd \0"
|
|
/* 4808 */ "vpdepd \0"
|
|
/* 4816 */ "cmpd \0"
|
|
/* 4822 */ "xxbrd \0"
|
|
/* 4829 */ "mtmsrd \0"
|
|
/* 4837 */ "mfvsrd \0"
|
|
/* 4845 */ "mtvsrd \0"
|
|
/* 4853 */ "vmodsd \0"
|
|
/* 4861 */ "vmulesd \0"
|
|
/* 4870 */ "vdivesd \0"
|
|
/* 4879 */ "vmulhsd \0"
|
|
/* 4888 */ "vminsd \0"
|
|
/* 4896 */ "vinsd \0"
|
|
/* 4903 */ "vmulosd \0"
|
|
/* 4912 */ "vcmpgtsd \0"
|
|
/* 4922 */ "vdivsd \0"
|
|
/* 4930 */ "vmaxsd \0"
|
|
/* 4938 */ "plxsd \0"
|
|
/* 4945 */ "pstxsd \0"
|
|
/* 4953 */ "vextractd \0"
|
|
/* 4964 */ "cbcdtd \0"
|
|
/* 4972 */ "vpopcntd \0"
|
|
/* 4982 */ "vinsertd \0"
|
|
/* 4992 */ "pstd \0"
|
|
/* 4998 */ "vpextd \0"
|
|
/* 5006 */ "vmsumcud \0"
|
|
/* 5016 */ "vmodud \0"
|
|
/* 5024 */ "vmuleud \0"
|
|
/* 5033 */ "vdiveud \0"
|
|
/* 5042 */ "vmulhud \0"
|
|
/* 5051 */ "vminud \0"
|
|
/* 5059 */ "vmuloud \0"
|
|
/* 5068 */ "vcmpequd \0"
|
|
/* 5078 */ "vcmpgtud \0"
|
|
/* 5088 */ "vdivud \0"
|
|
/* 5096 */ "vmaxud \0"
|
|
/* 5104 */ "xxblendvd \0"
|
|
/* 5115 */ "divd \0"
|
|
/* 5121 */ "vclzd \0"
|
|
/* 5128 */ "cntlzd \0"
|
|
/* 5136 */ "vctzd \0"
|
|
/* 5143 */ "cnttzd \0"
|
|
/* 5151 */ "mfbhrbe \0"
|
|
/* 5160 */ "mffsce \0"
|
|
/* 5168 */ "adde \0"
|
|
/* 5174 */ "divde \0"
|
|
/* 5181 */ "slbmfee \0"
|
|
/* 5190 */ "wrtee \0"
|
|
/* 5197 */ "subfe \0"
|
|
/* 5204 */ "evlwhe \0"
|
|
/* 5212 */ "evstwhe \0"
|
|
/* 5221 */ "slbie \0"
|
|
/* 5228 */ "tlbie \0"
|
|
/* 5235 */ "addme \0"
|
|
/* 5242 */ "subfme \0"
|
|
/* 5250 */ "tlbre \0"
|
|
/* 5257 */ "qvfre \0"
|
|
/* 5264 */ "slbmte \0"
|
|
/* 5272 */ "ps_rsqrte \0"
|
|
/* 5283 */ "qvfrsqrte \0"
|
|
/* 5294 */ "tlbwe \0"
|
|
/* 5301 */ "divwe \0"
|
|
/* 5308 */ "evstwwe \0"
|
|
/* 5317 */ "addze \0"
|
|
/* 5324 */ "subfze \0"
|
|
/* 5332 */ "dcbf \0"
|
|
/* 5338 */ "subf \0"
|
|
/* 5344 */ "evmhesmf \0"
|
|
/* 5354 */ "evmwhsmf \0"
|
|
/* 5364 */ "evmhosmf \0"
|
|
/* 5374 */ "evmwsmf \0"
|
|
/* 5383 */ "mcrf \0"
|
|
/* 5389 */ "mfocrf \0"
|
|
/* 5397 */ "mtocrf \0"
|
|
/* 5405 */ "mtcrf \0"
|
|
/* 5412 */ "efdcfsf \0"
|
|
/* 5421 */ "efscfsf \0"
|
|
/* 5430 */ "evfscfsf \0"
|
|
/* 5440 */ "mtfsf \0"
|
|
/* 5447 */ "evmhessf \0"
|
|
/* 5457 */ "evmwhssf \0"
|
|
/* 5467 */ "evmhossf \0"
|
|
/* 5477 */ "evmwssf \0"
|
|
/* 5486 */ "efdctsf \0"
|
|
/* 5495 */ "efsctsf \0"
|
|
/* 5504 */ "evfsctsf \0"
|
|
/* 5514 */ "dtstsf \0"
|
|
/* 5522 */ "efdcfuf \0"
|
|
/* 5531 */ "efscfuf \0"
|
|
/* 5540 */ "evfscfuf \0"
|
|
/* 5550 */ "efdctuf \0"
|
|
/* 5559 */ "efsctuf \0"
|
|
/* 5568 */ "dtstdg \0"
|
|
/* 5576 */ "slbieg \0"
|
|
/* 5584 */ "ps_neg \0"
|
|
/* 5592 */ "efdneg \0"
|
|
/* 5600 */ "qvfneg \0"
|
|
/* 5608 */ "efsneg \0"
|
|
/* 5616 */ "evfsneg \0"
|
|
/* 5625 */ "evneg \0"
|
|
/* 5632 */ "vsrah \0"
|
|
/* 5639 */ "vcntmbh \0"
|
|
/* 5648 */ "evldh \0"
|
|
/* 5655 */ "evstdh \0"
|
|
/* 5663 */ "vcmpneh \0"
|
|
/* 5672 */ "vmrghh \0"
|
|
/* 5680 */ "vmrglh \0"
|
|
/* 5688 */ "vrlh \0"
|
|
/* 5694 */ "vslh \0"
|
|
/* 5700 */ "vpmsumh \0"
|
|
/* 5709 */ "xxbrh \0"
|
|
/* 5716 */ "vsrh \0"
|
|
/* 5722 */ "vmulesh \0"
|
|
/* 5731 */ "vavgsh \0"
|
|
/* 5739 */ "vupkhsh \0"
|
|
/* 5748 */ "vspltish \0"
|
|
/* 5758 */ "vupklsh \0"
|
|
/* 5767 */ "vminsh \0"
|
|
/* 5775 */ "vmulosh \0"
|
|
/* 5784 */ "vcmpgtsh \0"
|
|
/* 5794 */ "evextsh \0"
|
|
/* 5803 */ "vmaxsh \0"
|
|
/* 5811 */ "vsplth \0"
|
|
/* 5819 */ "vpopcnth \0"
|
|
/* 5829 */ "vinserth \0"
|
|
/* 5839 */ "psth \0"
|
|
/* 5845 */ "vabsduh \0"
|
|
/* 5854 */ "vmuleuh \0"
|
|
/* 5863 */ "vavguh \0"
|
|
/* 5871 */ "vminuh \0"
|
|
/* 5879 */ "vmulouh \0"
|
|
/* 5888 */ "vcmpequh \0"
|
|
/* 5898 */ "vextractuh \0"
|
|
/* 5910 */ "vcmpgtuh \0"
|
|
/* 5920 */ "vmaxuh \0"
|
|
/* 5928 */ "xxblendvh \0"
|
|
/* 5939 */ "vcmpnezh \0"
|
|
/* 5949 */ "vclzh \0"
|
|
/* 5956 */ "vctzh \0"
|
|
/* 5963 */ "dquai \0"
|
|
/* 5970 */ "dcbi \0"
|
|
/* 5976 */ "icbi \0"
|
|
/* 5982 */ "vsldbi \0"
|
|
/* 5990 */ "vsrdbi \0"
|
|
/* 5998 */ "psubi \0"
|
|
/* 6005 */ "dccci \0"
|
|
/* 6012 */ "iccci \0"
|
|
/* 6019 */ "qvgpci \0"
|
|
/* 6027 */ "sradi \0"
|
|
/* 6034 */ "paddi \0"
|
|
/* 6041 */ "cmpldi \0"
|
|
/* 6049 */ "clrlsldi \0"
|
|
/* 6059 */ "extldi \0"
|
|
/* 6067 */ "xxpermdi \0"
|
|
/* 6077 */ "cmpdi \0"
|
|
/* 6084 */ "clrrdi \0"
|
|
/* 6092 */ "insrdi \0"
|
|
/* 6100 */ "rotrdi \0"
|
|
/* 6108 */ "extrdi \0"
|
|
/* 6116 */ "tdi \0"
|
|
/* 6121 */ "wrteei \0"
|
|
/* 6129 */ "mtfsfi \0"
|
|
/* 6137 */ "dtstsfi \0"
|
|
/* 6146 */ "evsplatfi \0"
|
|
/* 6157 */ "evmergehi \0"
|
|
/* 6168 */ "evmergelohi \0"
|
|
/* 6181 */ "tlbli \0"
|
|
/* 6188 */ "dscli \0"
|
|
/* 6195 */ "mulli \0"
|
|
/* 6202 */ "pli \0"
|
|
/* 6207 */ "extswsli \0"
|
|
/* 6217 */ "mtvsrbmi \0"
|
|
/* 6227 */ "vrldmi \0"
|
|
/* 6235 */ "rldimi \0"
|
|
/* 6243 */ "rlwimi \0"
|
|
/* 6251 */ "vrlqmi \0"
|
|
/* 6259 */ "evmhesmi \0"
|
|
/* 6269 */ "evmwhsmi \0"
|
|
/* 6279 */ "evmhosmi \0"
|
|
/* 6289 */ "evmwsmi \0"
|
|
/* 6298 */ "evmheumi \0"
|
|
/* 6308 */ "evmwhumi \0"
|
|
/* 6318 */ "evmwlumi \0"
|
|
/* 6328 */ "evmhoumi \0"
|
|
/* 6338 */ "evmwumi \0"
|
|
/* 6347 */ "vrlwmi \0"
|
|
/* 6355 */ "qvaligni \0"
|
|
/* 6365 */ "mffscrni \0"
|
|
/* 6375 */ "mffscdrni \0"
|
|
/* 6386 */ "vsldoi \0"
|
|
/* 6394 */ "xsrdpi \0"
|
|
/* 6402 */ "xvrdpi \0"
|
|
/* 6410 */ "xsrqpi \0"
|
|
/* 6418 */ "xvrspi \0"
|
|
/* 6426 */ "dscri \0"
|
|
/* 6433 */ "xori \0"
|
|
/* 6439 */ "efdcfsi \0"
|
|
/* 6448 */ "efscfsi \0"
|
|
/* 6457 */ "evfscfsi \0"
|
|
/* 6467 */ "efdctsi \0"
|
|
/* 6476 */ "efsctsi \0"
|
|
/* 6485 */ "evfsctsi \0"
|
|
/* 6495 */ "qvesplati \0"
|
|
/* 6506 */ "evsplati \0"
|
|
/* 6516 */ "efdcfui \0"
|
|
/* 6525 */ "efscfui \0"
|
|
/* 6534 */ "evfscfui \0"
|
|
/* 6544 */ "efdctui \0"
|
|
/* 6553 */ "efsctui \0"
|
|
/* 6562 */ "evfsctui \0"
|
|
/* 6572 */ "srawi \0"
|
|
/* 6579 */ "xxsldwi \0"
|
|
/* 6588 */ "cmplwi \0"
|
|
/* 6596 */ "evrlwi \0"
|
|
/* 6604 */ "clrlslwi \0"
|
|
/* 6614 */ "inslwi \0"
|
|
/* 6622 */ "evslwi \0"
|
|
/* 6630 */ "extlwi \0"
|
|
/* 6638 */ "cmpwi \0"
|
|
/* 6645 */ "clrrwi \0"
|
|
/* 6653 */ "insrwi \0"
|
|
/* 6661 */ "rotrwi \0"
|
|
/* 6669 */ "extrwi \0"
|
|
/* 6677 */ "lswi \0"
|
|
/* 6683 */ "stswi \0"
|
|
/* 6690 */ "twi \0"
|
|
/* 6695 */ "qvstfcdxi \0"
|
|
/* 6706 */ "qvstfdxi \0"
|
|
/* 6716 */ "qvstfcsxi \0"
|
|
/* 6727 */ "qvstfsxi \0"
|
|
/* 6737 */ "qvstfcduxi \0"
|
|
/* 6749 */ "qvstfduxi \0"
|
|
/* 6760 */ "qvstfcsuxi \0"
|
|
/* 6772 */ "qvstfsuxi \0"
|
|
/* 6783 */ "tcheck \0"
|
|
/* 6791 */ "hashchk \0"
|
|
/* 6800 */ "psq_l \0"
|
|
/* 6807 */ "dcbz_l \0"
|
|
/* 6815 */ "qvflogical \0"
|
|
/* 6827 */ "xxeval \0"
|
|
/* 6835 */ "vstribl \0"
|
|
/* 6844 */ "bcl \0"
|
|
/* 6849 */ "rldcl \0"
|
|
/* 6856 */ "rldicl \0"
|
|
/* 6864 */ "tlbiel \0"
|
|
/* 6872 */ "ps_sel \0"
|
|
/* 6880 */ "qvfsel \0"
|
|
/* 6888 */ "isel \0"
|
|
/* 6894 */ "vsel \0"
|
|
/* 6900 */ "xxsel \0"
|
|
/* 6907 */ "dcbfl \0"
|
|
/* 6914 */ "vstrihl \0"
|
|
/* 6923 */ "lxvprll \0"
|
|
/* 6932 */ "stxvprll \0"
|
|
/* 6942 */ "lxvrll \0"
|
|
/* 6950 */ "stxvrll \0"
|
|
/* 6959 */ "lxvll \0"
|
|
/* 6966 */ "stxvll \0"
|
|
/* 6974 */ "bclrl \0"
|
|
/* 6981 */ "lxvprl \0"
|
|
/* 6989 */ "stxvprl \0"
|
|
/* 6998 */ "bcctrl \0"
|
|
/* 7006 */ "lxvrl \0"
|
|
/* 7013 */ "stxvrl \0"
|
|
/* 7021 */ "mffsl \0"
|
|
/* 7028 */ "lvsl \0"
|
|
/* 7034 */ "ps_mul \0"
|
|
/* 7042 */ "efdmul \0"
|
|
/* 7050 */ "qvfmul \0"
|
|
/* 7058 */ "efsmul \0"
|
|
/* 7066 */ "evfsmul \0"
|
|
/* 7075 */ "qvfxmul \0"
|
|
/* 7084 */ "lxvl \0"
|
|
/* 7090 */ "stxvl \0"
|
|
/* 7097 */ "lvxl \0"
|
|
/* 7103 */ "stvxl \0"
|
|
/* 7110 */ "dcbzl \0"
|
|
/* 7117 */ "vexpandbm \0"
|
|
/* 7128 */ "vmsummbm \0"
|
|
/* 7138 */ "mtvsrbm \0"
|
|
/* 7147 */ "vextractbm \0"
|
|
/* 7159 */ "vsububm \0"
|
|
/* 7168 */ "vaddubm \0"
|
|
/* 7177 */ "vmsumubm \0"
|
|
/* 7187 */ "xxgenpcvbm \0"
|
|
/* 7199 */ "vexpanddm \0"
|
|
/* 7210 */ "mtvsrdm \0"
|
|
/* 7219 */ "vextractdm \0"
|
|
/* 7231 */ "vsubudm \0"
|
|
/* 7240 */ "vaddudm \0"
|
|
/* 7249 */ "vmsumudm \0"
|
|
/* 7259 */ "xxgenpcvdm \0"
|
|
/* 7271 */ "vclzdm \0"
|
|
/* 7279 */ "cntlzdm \0"
|
|
/* 7288 */ "vctzdm \0"
|
|
/* 7296 */ "cnttzdm \0"
|
|
/* 7305 */ "vexpandhm \0"
|
|
/* 7316 */ "mtvsrhm \0"
|
|
/* 7325 */ "vmsumshm \0"
|
|
/* 7335 */ "vextracthm \0"
|
|
/* 7347 */ "vsubuhm \0"
|
|
/* 7356 */ "vmladduhm \0"
|
|
/* 7367 */ "vadduhm \0"
|
|
/* 7376 */ "vmsumuhm \0"
|
|
/* 7386 */ "xxgenpcvhm \0"
|
|
/* 7398 */ "vrfim \0"
|
|
/* 7405 */ "xsrdpim \0"
|
|
/* 7414 */ "xvrdpim \0"
|
|
/* 7423 */ "xvrspim \0"
|
|
/* 7432 */ "qvfrim \0"
|
|
/* 7440 */ "vrldnm \0"
|
|
/* 7448 */ "rlwinm \0"
|
|
/* 7456 */ "vrlqnm \0"
|
|
/* 7464 */ "vrlwnm \0"
|
|
/* 7472 */ "vexpandqm \0"
|
|
/* 7483 */ "mtvsrqm \0"
|
|
/* 7492 */ "vextractqm \0"
|
|
/* 7504 */ "vsubuqm \0"
|
|
/* 7513 */ "vadduqm \0"
|
|
/* 7522 */ "vsubeuqm \0"
|
|
/* 7532 */ "vaddeuqm \0"
|
|
/* 7542 */ "qvfperm \0"
|
|
/* 7551 */ "vperm \0"
|
|
/* 7558 */ "xxperm \0"
|
|
/* 7566 */ "vpkudum \0"
|
|
/* 7575 */ "vpkuhum \0"
|
|
/* 7584 */ "vpkuwum \0"
|
|
/* 7593 */ "vexpandwm \0"
|
|
/* 7604 */ "mtvsrwm \0"
|
|
/* 7613 */ "vextractwm \0"
|
|
/* 7625 */ "vsubuwm \0"
|
|
/* 7634 */ "vadduwm \0"
|
|
/* 7643 */ "vmuluwm \0"
|
|
/* 7652 */ "xxgenpcvwm \0"
|
|
/* 7664 */ "evmhegsmfan \0"
|
|
/* 7677 */ "evmhogsmfan \0"
|
|
/* 7690 */ "evmwsmfan \0"
|
|
/* 7701 */ "evmwssfan \0"
|
|
/* 7712 */ "evmhegsmian \0"
|
|
/* 7725 */ "evmhogsmian \0"
|
|
/* 7738 */ "evmwsmian \0"
|
|
/* 7749 */ "evmhegumian \0"
|
|
/* 7762 */ "evmhogumian \0"
|
|
/* 7775 */ "evmwumian \0"
|
|
/* 7786 */ "qvftstnan \0"
|
|
/* 7797 */ "qvfcpsgn \0"
|
|
/* 7807 */ "vrfin \0"
|
|
/* 7814 */ "qvfrin \0"
|
|
/* 7822 */ "mfsrin \0"
|
|
/* 7830 */ "mtsrin \0"
|
|
/* 7838 */ "pmxvbf16ger2nn \0"
|
|
/* 7854 */ "pmxvf16ger2nn \0"
|
|
/* 7869 */ "pmxvf32gernn \0"
|
|
/* 7883 */ "pmxvf64gernn \0"
|
|
/* 7897 */ "pmxvbf16ger2pn \0"
|
|
/* 7913 */ "pmxvf16ger2pn \0"
|
|
/* 7928 */ "xscvspdpn \0"
|
|
/* 7939 */ "pmxvf32gerpn \0"
|
|
/* 7953 */ "pmxvf64gerpn \0"
|
|
/* 7967 */ "xvcvbf16spn \0"
|
|
/* 7980 */ "xscvdpspn \0"
|
|
/* 7991 */ "darn \0"
|
|
/* 7997 */ "mffscrn \0"
|
|
/* 8006 */ "mffscdrn \0"
|
|
/* 8016 */ "drintn \0"
|
|
/* 8024 */ "addco \0"
|
|
/* 8031 */ "subfco \0"
|
|
/* 8039 */ "addo \0"
|
|
/* 8045 */ "mulldo \0"
|
|
/* 8053 */ "divdo \0"
|
|
/* 8060 */ "addeo \0"
|
|
/* 8067 */ "divdeo \0"
|
|
/* 8075 */ "subfeo \0"
|
|
/* 8083 */ "addmeo \0"
|
|
/* 8091 */ "subfmeo \0"
|
|
/* 8100 */ "divweo \0"
|
|
/* 8108 */ "addzeo \0"
|
|
/* 8116 */ "subfzeo \0"
|
|
/* 8125 */ "subfo \0"
|
|
/* 8132 */ "nego \0"
|
|
/* 8138 */ "evstwho \0"
|
|
/* 8147 */ "evmergelo \0"
|
|
/* 8158 */ "evmergehilo \0"
|
|
/* 8171 */ "vslo \0"
|
|
/* 8177 */ "xscvqpdpo \0"
|
|
/* 8188 */ "dcmpo \0"
|
|
/* 8195 */ "fcmpo \0"
|
|
/* 8202 */ "xsnmsubqpo \0"
|
|
/* 8214 */ "xsmsubqpo \0"
|
|
/* 8225 */ "xssubqpo \0"
|
|
/* 8235 */ "xsnmaddqpo \0"
|
|
/* 8247 */ "xsmaddqpo \0"
|
|
/* 8258 */ "xsaddqpo \0"
|
|
/* 8268 */ "xsmulqpo \0"
|
|
/* 8278 */ "xssqrtqpo \0"
|
|
/* 8289 */ "xsdivqpo \0"
|
|
/* 8299 */ "vsro \0"
|
|
/* 8305 */ "divduo \0"
|
|
/* 8313 */ "divdeuo \0"
|
|
/* 8322 */ "divweuo \0"
|
|
/* 8331 */ "divwuo \0"
|
|
/* 8339 */ "mullwo \0"
|
|
/* 8347 */ "divwo \0"
|
|
/* 8354 */ "evstwwo \0"
|
|
/* 8363 */ "xsnmsubadp \0"
|
|
/* 8375 */ "xvnmsubadp \0"
|
|
/* 8387 */ "xsmsubadp \0"
|
|
/* 8398 */ "xvmsubadp \0"
|
|
/* 8409 */ "xsnmaddadp \0"
|
|
/* 8421 */ "xvnmaddadp \0"
|
|
/* 8433 */ "xsmaddadp \0"
|
|
/* 8444 */ "xvmaddadp \0"
|
|
/* 8455 */ "xssubdp \0"
|
|
/* 8464 */ "xvsubdp \0"
|
|
/* 8473 */ "xststdcdp \0"
|
|
/* 8484 */ "xvtstdcdp \0"
|
|
/* 8495 */ "xsmincdp \0"
|
|
/* 8505 */ "xsmaxcdp \0"
|
|
/* 8515 */ "xsadddp \0"
|
|
/* 8524 */ "xvadddp \0"
|
|
/* 8533 */ "xscvsxddp \0"
|
|
/* 8544 */ "xvcvsxddp \0"
|
|
/* 8555 */ "xscvuxddp \0"
|
|
/* 8566 */ "xvcvuxddp \0"
|
|
/* 8577 */ "xscmpgedp \0"
|
|
/* 8588 */ "xvcmpgedp \0"
|
|
/* 8599 */ "xsredp \0"
|
|
/* 8607 */ "xvredp \0"
|
|
/* 8615 */ "xsrsqrtedp \0"
|
|
/* 8627 */ "xvrsqrtedp \0"
|
|
/* 8639 */ "xsnegdp \0"
|
|
/* 8648 */ "xvnegdp \0"
|
|
/* 8657 */ "xsxsigdp \0"
|
|
/* 8667 */ "xvxsigdp \0"
|
|
/* 8677 */ "xxspltidp \0"
|
|
/* 8688 */ "xsminjdp \0"
|
|
/* 8698 */ "xsmaxjdp \0"
|
|
/* 8708 */ "xsmuldp \0"
|
|
/* 8717 */ "xvmuldp \0"
|
|
/* 8726 */ "xsnmsubmdp \0"
|
|
/* 8738 */ "xvnmsubmdp \0"
|
|
/* 8750 */ "xsmsubmdp \0"
|
|
/* 8761 */ "xvmsubmdp \0"
|
|
/* 8772 */ "xsnmaddmdp \0"
|
|
/* 8784 */ "xvnmaddmdp \0"
|
|
/* 8796 */ "xsmaddmdp \0"
|
|
/* 8807 */ "xvmaddmdp \0"
|
|
/* 8818 */ "xscpsgndp \0"
|
|
/* 8829 */ "xvcpsgndp \0"
|
|
/* 8840 */ "xsmindp \0"
|
|
/* 8849 */ "xvmindp \0"
|
|
/* 8858 */ "xscmpodp \0"
|
|
/* 8868 */ "xscvhpdp \0"
|
|
/* 8878 */ "xscvqpdp \0"
|
|
/* 8888 */ "xscvspdp \0"
|
|
/* 8898 */ "xvcvspdp \0"
|
|
/* 8908 */ "xsiexpdp \0"
|
|
/* 8918 */ "xviexpdp \0"
|
|
/* 8928 */ "xscmpexpdp \0"
|
|
/* 8940 */ "xsxexpdp \0"
|
|
/* 8950 */ "xvxexpdp \0"
|
|
/* 8960 */ "xscmpeqdp \0"
|
|
/* 8971 */ "xvcmpeqdp \0"
|
|
/* 8982 */ "xsnabsdp \0"
|
|
/* 8992 */ "xvnabsdp \0"
|
|
/* 9002 */ "xsabsdp \0"
|
|
/* 9011 */ "xvabsdp \0"
|
|
/* 9020 */ "dctdp \0"
|
|
/* 9027 */ "xscmpgtdp \0"
|
|
/* 9038 */ "xvcmpgtdp \0"
|
|
/* 9049 */ "xssqrtdp \0"
|
|
/* 9059 */ "xstsqrtdp \0"
|
|
/* 9070 */ "xvtsqrtdp \0"
|
|
/* 9081 */ "xvsqrtdp \0"
|
|
/* 9091 */ "xscmpudp \0"
|
|
/* 9101 */ "xsdivdp \0"
|
|
/* 9110 */ "xstdivdp \0"
|
|
/* 9120 */ "xvtdivdp \0"
|
|
/* 9130 */ "xvdivdp \0"
|
|
/* 9139 */ "xvcvsxwdp \0"
|
|
/* 9150 */ "xvcvuxwdp \0"
|
|
/* 9161 */ "xsmaxdp \0"
|
|
/* 9170 */ "xvmaxdp \0"
|
|
/* 9179 */ "dcbfep \0"
|
|
/* 9187 */ "icbiep \0"
|
|
/* 9195 */ "dcbzlep \0"
|
|
/* 9204 */ "dcbtep \0"
|
|
/* 9212 */ "dcbstep \0"
|
|
/* 9221 */ "dcbtstep \0"
|
|
/* 9231 */ "dcbzep \0"
|
|
/* 9239 */ "vcmpbfp \0"
|
|
/* 9248 */ "vnmsubfp \0"
|
|
/* 9258 */ "vsubfp \0"
|
|
/* 9266 */ "vmaddfp \0"
|
|
/* 9275 */ "vaddfp \0"
|
|
/* 9283 */ "vlogefp \0"
|
|
/* 9292 */ "vcmpgefp \0"
|
|
/* 9302 */ "vrefp \0"
|
|
/* 9309 */ "vexptefp \0"
|
|
/* 9319 */ "vrsqrtefp \0"
|
|
/* 9330 */ "vminfp \0"
|
|
/* 9338 */ "vcmpeqfp \0"
|
|
/* 9348 */ "vcmpgtfp \0"
|
|
/* 9358 */ "vmaxfp \0"
|
|
/* 9366 */ "xscvdphp \0"
|
|
/* 9376 */ "xvcvsphp \0"
|
|
/* 9386 */ "vrfip \0"
|
|
/* 9393 */ "xsrdpip \0"
|
|
/* 9402 */ "xvrdpip \0"
|
|
/* 9411 */ "xvrspip \0"
|
|
/* 9420 */ "qvfrip \0"
|
|
/* 9428 */ "hashchkp \0"
|
|
/* 9438 */ "dcbflp \0"
|
|
/* 9446 */ "pmxvbf16ger2np \0"
|
|
/* 9462 */ "pmxvf16ger2np \0"
|
|
/* 9477 */ "pmxvf32gernp \0"
|
|
/* 9491 */ "pmxvf64gernp \0"
|
|
/* 9505 */ "pmxvbf16ger2pp \0"
|
|
/* 9521 */ "pmxvf16ger2pp \0"
|
|
/* 9536 */ "pmxvi16ger2pp \0"
|
|
/* 9551 */ "pmxvi8ger4pp \0"
|
|
/* 9565 */ "pmxvi4ger8pp \0"
|
|
/* 9579 */ "pmxvf32gerpp \0"
|
|
/* 9593 */ "pmxvf64gerpp \0"
|
|
/* 9607 */ "pmxvi16ger2spp \0"
|
|
/* 9623 */ "pmxvi8ger4spp \0"
|
|
/* 9638 */ "xsnmsubqp \0"
|
|
/* 9649 */ "xsmsubqp \0"
|
|
/* 9659 */ "xssubqp \0"
|
|
/* 9668 */ "xststdcqp \0"
|
|
/* 9679 */ "xsmincqp \0"
|
|
/* 9689 */ "xsmaxcqp \0"
|
|
/* 9699 */ "xsnmaddqp \0"
|
|
/* 9710 */ "xsmaddqp \0"
|
|
/* 9720 */ "xsaddqp \0"
|
|
/* 9729 */ "xscvsdqp \0"
|
|
/* 9739 */ "xscvudqp \0"
|
|
/* 9749 */ "xscmpgeqp \0"
|
|
/* 9760 */ "xsnegqp \0"
|
|
/* 9769 */ "xsxsigqp \0"
|
|
/* 9779 */ "xsmulqp \0"
|
|
/* 9788 */ "xscpsgnqp \0"
|
|
/* 9799 */ "xscmpoqp \0"
|
|
/* 9809 */ "xscvdpqp \0"
|
|
/* 9819 */ "xsiexpqp \0"
|
|
/* 9829 */ "xscmpexpqp \0"
|
|
/* 9841 */ "xsxexpqp \0"
|
|
/* 9851 */ "xscmpeqqp \0"
|
|
/* 9862 */ "xscvsqqp \0"
|
|
/* 9872 */ "xscvuqqp \0"
|
|
/* 9882 */ "xsnabsqp \0"
|
|
/* 9892 */ "xsabsqp \0"
|
|
/* 9901 */ "xscmpgtqp \0"
|
|
/* 9912 */ "xssqrtqp \0"
|
|
/* 9922 */ "xscmpuqp \0"
|
|
/* 9932 */ "xsdivqp \0"
|
|
/* 9941 */ "xsnmsubasp \0"
|
|
/* 9953 */ "xvnmsubasp \0"
|
|
/* 9965 */ "xsmsubasp \0"
|
|
/* 9976 */ "xvmsubasp \0"
|
|
/* 9987 */ "xsnmaddasp \0"
|
|
/* 9999 */ "xvnmaddasp \0"
|
|
/* 10011 */ "xsmaddasp \0"
|
|
/* 10022 */ "xvmaddasp \0"
|
|
/* 10033 */ "xssubsp \0"
|
|
/* 10042 */ "xvsubsp \0"
|
|
/* 10051 */ "xststdcsp \0"
|
|
/* 10062 */ "xvtstdcsp \0"
|
|
/* 10073 */ "xsaddsp \0"
|
|
/* 10082 */ "xvaddsp \0"
|
|
/* 10091 */ "xscvsxdsp \0"
|
|
/* 10102 */ "xvcvsxdsp \0"
|
|
/* 10113 */ "xscvuxdsp \0"
|
|
/* 10124 */ "xvcvuxdsp \0"
|
|
/* 10135 */ "xvcmpgesp \0"
|
|
/* 10146 */ "xsresp \0"
|
|
/* 10154 */ "xvresp \0"
|
|
/* 10162 */ "xsrsqrtesp \0"
|
|
/* 10174 */ "xvrsqrtesp \0"
|
|
/* 10186 */ "xvnegsp \0"
|
|
/* 10195 */ "xvxsigsp \0"
|
|
/* 10205 */ "xsmulsp \0"
|
|
/* 10214 */ "xvmulsp \0"
|
|
/* 10223 */ "xsnmsubmsp \0"
|
|
/* 10235 */ "xvnmsubmsp \0"
|
|
/* 10247 */ "xsmsubmsp \0"
|
|
/* 10258 */ "xvmsubmsp \0"
|
|
/* 10269 */ "xsnmaddmsp \0"
|
|
/* 10281 */ "xvnmaddmsp \0"
|
|
/* 10293 */ "xsmaddmsp \0"
|
|
/* 10304 */ "xvmaddmsp \0"
|
|
/* 10315 */ "xvcpsgnsp \0"
|
|
/* 10326 */ "xvminsp \0"
|
|
/* 10335 */ "xscvdpsp \0"
|
|
/* 10345 */ "xvcvdpsp \0"
|
|
/* 10355 */ "xvcvhpsp \0"
|
|
/* 10365 */ "xviexpsp \0"
|
|
/* 10375 */ "xvxexpsp \0"
|
|
/* 10385 */ "xvcmpeqsp \0"
|
|
/* 10396 */ "drsp \0"
|
|
/* 10402 */ "qvfrsp \0"
|
|
/* 10410 */ "xsrsp \0"
|
|
/* 10417 */ "xvnabssp \0"
|
|
/* 10427 */ "xvabssp \0"
|
|
/* 10436 */ "plxssp \0"
|
|
/* 10444 */ "pstxssp \0"
|
|
/* 10453 */ "xvcmpgtsp \0"
|
|
/* 10464 */ "xssqrtsp \0"
|
|
/* 10474 */ "xvtsqrtsp \0"
|
|
/* 10485 */ "xvsqrtsp \0"
|
|
/* 10495 */ "xsdivsp \0"
|
|
/* 10504 */ "xvtdivsp \0"
|
|
/* 10514 */ "xvdivsp \0"
|
|
/* 10523 */ "xvcvsxwsp \0"
|
|
/* 10534 */ "xvcvuxwsp \0"
|
|
/* 10545 */ "xvmaxsp \0"
|
|
/* 10554 */ "hashstp \0"
|
|
/* 10563 */ "plxvp \0"
|
|
/* 10570 */ "pstxvp \0"
|
|
/* 10578 */ "xsrqpxp \0"
|
|
/* 10587 */ "vextsd2q \0"
|
|
/* 10597 */ "vsraq \0"
|
|
/* 10604 */ "dquaq \0"
|
|
/* 10611 */ "dsubq \0"
|
|
/* 10618 */ "vprtybq \0"
|
|
/* 10627 */ "dtstdcq \0"
|
|
/* 10636 */ "denbcdq \0"
|
|
/* 10645 */ "daddq \0"
|
|
/* 10652 */ "drrndq \0"
|
|
/* 10660 */ "ddedpdq \0"
|
|
/* 10669 */ "efdcmpeq \0"
|
|
/* 10679 */ "qvfcmpeq \0"
|
|
/* 10689 */ "efscmpeq \0"
|
|
/* 10699 */ "evfscmpeq \0"
|
|
/* 10710 */ "evcmpeq \0"
|
|
/* 10719 */ "efdtsteq \0"
|
|
/* 10729 */ "efststeq \0"
|
|
/* 10739 */ "evfststeq \0"
|
|
/* 10750 */ "dtstsfq \0"
|
|
/* 10759 */ "dtstdgq \0"
|
|
/* 10768 */ "dquaiq \0"
|
|
/* 10776 */ "dtstsfiq \0"
|
|
/* 10786 */ "dscliq \0"
|
|
/* 10794 */ "dscriq \0"
|
|
/* 10802 */ "lxvkq \0"
|
|
/* 10809 */ "vrlq \0"
|
|
/* 10815 */ "vslq \0"
|
|
/* 10821 */ "dmulq \0"
|
|
/* 10828 */ "vbpermq \0"
|
|
/* 10837 */ "drintnq \0"
|
|
/* 10846 */ "dcmpoq \0"
|
|
/* 10854 */ "drdpq \0"
|
|
/* 10861 */ "dctqpq \0"
|
|
/* 10869 */ "dcffixqq \0"
|
|
/* 10879 */ "dctfixqq \0"
|
|
/* 10889 */ "xxbrq \0"
|
|
/* 10896 */ "vsrq \0"
|
|
/* 10902 */ "vmodsq \0"
|
|
/* 10910 */ "vdivesq \0"
|
|
/* 10919 */ "vcmpsq \0"
|
|
/* 10927 */ "vcmpgtsq \0"
|
|
/* 10937 */ "vdivsq \0"
|
|
/* 10945 */ "stq \0"
|
|
/* 10950 */ "vmul10uq \0"
|
|
/* 10960 */ "vmul10cuq \0"
|
|
/* 10971 */ "vsubcuq \0"
|
|
/* 10980 */ "vaddcuq \0"
|
|
/* 10989 */ "vmul10ecuq \0"
|
|
/* 11001 */ "vsubecuq \0"
|
|
/* 11011 */ "vaddecuq \0"
|
|
/* 11021 */ "vmoduq \0"
|
|
/* 11029 */ "vmul10euq \0"
|
|
/* 11040 */ "vdiveuq \0"
|
|
/* 11049 */ "dcmpuq \0"
|
|
/* 11057 */ "vcmpuq \0"
|
|
/* 11065 */ "vcmpequq \0"
|
|
/* 11075 */ "vcmpgtuq \0"
|
|
/* 11085 */ "vdivuq \0"
|
|
/* 11093 */ "ddivq \0"
|
|
/* 11100 */ "diexq \0"
|
|
/* 11107 */ "dtstexq \0"
|
|
/* 11116 */ "dxexq \0"
|
|
/* 11123 */ "dcffixq \0"
|
|
/* 11132 */ "dctfixq \0"
|
|
/* 11141 */ "drintxq \0"
|
|
/* 11150 */ "#TC_RETURNr \0"
|
|
/* 11163 */ "mbar \0"
|
|
/* 11169 */ "vstribr \0"
|
|
/* 11178 */ "setnbcr \0"
|
|
/* 11187 */ "setbcr \0"
|
|
/* 11195 */ "mfdcr \0"
|
|
/* 11202 */ "rldcr \0"
|
|
/* 11209 */ "mtdcr \0"
|
|
/* 11216 */ "mfcr \0"
|
|
/* 11222 */ "rldicr \0"
|
|
/* 11230 */ "mfvscr \0"
|
|
/* 11238 */ "mtvscr \0"
|
|
/* 11246 */ "pmxvf32ger \0"
|
|
/* 11258 */ "pmxvf64ger \0"
|
|
/* 11270 */ "vncipher \0"
|
|
/* 11280 */ "vcipher \0"
|
|
/* 11289 */ "vstrihr \0"
|
|
/* 11298 */ "bclr \0"
|
|
/* 11304 */ "mflr \0"
|
|
/* 11310 */ "mtlr \0"
|
|
/* 11316 */ "ps_mr \0"
|
|
/* 11323 */ "qvfmr \0"
|
|
/* 11330 */ "dmmr \0"
|
|
/* 11336 */ "mfpmr \0"
|
|
/* 11343 */ "mtpmr \0"
|
|
/* 11350 */ "vpermr \0"
|
|
/* 11358 */ "xxpermr \0"
|
|
/* 11367 */ "xxlor \0"
|
|
/* 11374 */ "xxlnor \0"
|
|
/* 11382 */ "crnor \0"
|
|
/* 11389 */ "evnor \0"
|
|
/* 11396 */ "cror \0"
|
|
/* 11402 */ "evor \0"
|
|
/* 11408 */ "xxlxor \0"
|
|
/* 11416 */ "dmxor \0"
|
|
/* 11423 */ "vpermxor \0"
|
|
/* 11433 */ "crxor \0"
|
|
/* 11440 */ "evxor \0"
|
|
/* 11447 */ "mfspr \0"
|
|
/* 11454 */ "mtspr \0"
|
|
/* 11461 */ "mfsr \0"
|
|
/* 11467 */ "mfmsr \0"
|
|
/* 11474 */ "mtmsr \0"
|
|
/* 11481 */ "mtsr \0"
|
|
/* 11487 */ "lvsr \0"
|
|
/* 11493 */ "bcctr \0"
|
|
/* 11500 */ "mfctr \0"
|
|
/* 11507 */ "mtctr \0"
|
|
/* 11514 */ "pmxvi16ger2s \0"
|
|
/* 11528 */ "addg6s \0"
|
|
/* 11536 */ "ps_abs \0"
|
|
/* 11544 */ "efdabs \0"
|
|
/* 11552 */ "qvfabs \0"
|
|
/* 11560 */ "ps_nabs \0"
|
|
/* 11569 */ "efdnabs \0"
|
|
/* 11578 */ "qvfnabs \0"
|
|
/* 11587 */ "efsnabs \0"
|
|
/* 11596 */ "evfsnabs \0"
|
|
/* 11606 */ "efsabs \0"
|
|
/* 11614 */ "evfsabs \0"
|
|
/* 11623 */ "evabs \0"
|
|
/* 11630 */ "vsum4sbs \0"
|
|
/* 11640 */ "vsubsbs \0"
|
|
/* 11649 */ "vaddsbs \0"
|
|
/* 11658 */ "vsum4ubs \0"
|
|
/* 11668 */ "vsububs \0"
|
|
/* 11677 */ "vaddubs \0"
|
|
/* 11686 */ "qvfsubs \0"
|
|
/* 11695 */ "qvfmsubs \0"
|
|
/* 11705 */ "qvfnmsubs \0"
|
|
/* 11716 */ "qvfadds \0"
|
|
/* 11725 */ "qvfmadds \0"
|
|
/* 11735 */ "qvfnmadds \0"
|
|
/* 11746 */ "qvfxxcpnmadds \0"
|
|
/* 11761 */ "qvfxxnpmadds \0"
|
|
/* 11775 */ "qvfxmadds \0"
|
|
/* 11786 */ "qvfxxmadds \0"
|
|
/* 11798 */ "qvfcfids \0"
|
|
/* 11808 */ "dcbtds \0"
|
|
/* 11816 */ "dcbtstds \0"
|
|
/* 11826 */ "xscvdpsxds \0"
|
|
/* 11838 */ "xvcvdpsxds \0"
|
|
/* 11850 */ "xvcvspsxds \0"
|
|
/* 11862 */ "xscvdpuxds \0"
|
|
/* 11874 */ "xvcvdpuxds \0"
|
|
/* 11886 */ "xvcvspuxds \0"
|
|
/* 11898 */ "ps_res \0"
|
|
/* 11906 */ "qvfres \0"
|
|
/* 11914 */ "qvfrsqrtes \0"
|
|
/* 11926 */ "efdcfs \0"
|
|
/* 11934 */ "mffs \0"
|
|
/* 11940 */ "plfs \0"
|
|
/* 11946 */ "mcrfs \0"
|
|
/* 11953 */ "pstfs \0"
|
|
/* 11960 */ "vsum4shs \0"
|
|
/* 11970 */ "vsubshs \0"
|
|
/* 11979 */ "vmhaddshs \0"
|
|
/* 11990 */ "vmhraddshs \0"
|
|
/* 12002 */ "vaddshs \0"
|
|
/* 12011 */ "vmsumshs \0"
|
|
/* 12021 */ "vsubuhs \0"
|
|
/* 12030 */ "vadduhs \0"
|
|
/* 12039 */ "vmsumuhs \0"
|
|
/* 12049 */ "subis \0"
|
|
/* 12056 */ "subpcis \0"
|
|
/* 12065 */ "addpcis \0"
|
|
/* 12074 */ "addis \0"
|
|
/* 12081 */ "lis \0"
|
|
/* 12086 */ "xoris \0"
|
|
/* 12093 */ "evsrwis \0"
|
|
/* 12102 */ "icbtls \0"
|
|
/* 12110 */ "qvfmuls \0"
|
|
/* 12119 */ "qvfxmuls \0"
|
|
/* 12129 */ "evlwhos \0"
|
|
/* 12138 */ "dcbfps \0"
|
|
/* 12146 */ "dcbstps \0"
|
|
/* 12155 */ "vpksdss \0"
|
|
/* 12164 */ "vpkshss \0"
|
|
/* 12173 */ "vpkswss \0"
|
|
/* 12182 */ "evcmpgts \0"
|
|
/* 12192 */ "evcmplts \0"
|
|
/* 12202 */ "fsqrts \0"
|
|
/* 12210 */ "qvfcfidus \0"
|
|
/* 12221 */ "vpksdus \0"
|
|
/* 12230 */ "vpkudus \0"
|
|
/* 12239 */ "subfus \0"
|
|
/* 12247 */ "vpkshus \0"
|
|
/* 12256 */ "vpkuhus \0"
|
|
/* 12265 */ "vpkswus \0"
|
|
/* 12274 */ "vpkuwus \0"
|
|
/* 12283 */ "fdivs \0"
|
|
/* 12290 */ "evsrws \0"
|
|
/* 12298 */ "mtvsrws \0"
|
|
/* 12307 */ "vsum2sws \0"
|
|
/* 12317 */ "vsubsws \0"
|
|
/* 12326 */ "vaddsws \0"
|
|
/* 12335 */ "vsumsws \0"
|
|
/* 12344 */ "vsubuws \0"
|
|
/* 12353 */ "vadduws \0"
|
|
/* 12362 */ "evdivws \0"
|
|
/* 12371 */ "xscvdpsxws \0"
|
|
/* 12383 */ "xvcvdpsxws \0"
|
|
/* 12395 */ "xvcvspsxws \0"
|
|
/* 12407 */ "xscvdpuxws \0"
|
|
/* 12419 */ "xvcvdpuxws \0"
|
|
/* 12431 */ "xvcvspuxws \0"
|
|
/* 12443 */ "vctsxs \0"
|
|
/* 12451 */ "vctuxs \0"
|
|
/* 12459 */ "ldat \0"
|
|
/* 12465 */ "stdat \0"
|
|
/* 12472 */ "evlhhesplat \0"
|
|
/* 12485 */ "evlwhsplat \0"
|
|
/* 12497 */ "evlhhossplat \0"
|
|
/* 12511 */ "evlhhousplat \0"
|
|
/* 12525 */ "evlwwsplat \0"
|
|
/* 12537 */ "lwat \0"
|
|
/* 12543 */ "stwat \0"
|
|
/* 12550 */ "dcbt \0"
|
|
/* 12556 */ "icbt \0"
|
|
/* 12562 */ "dcbtct \0"
|
|
/* 12570 */ "dcbtstct \0"
|
|
/* 12580 */ "efdcmpgt \0"
|
|
/* 12590 */ "qvfcmpgt \0"
|
|
/* 12600 */ "efscmpgt \0"
|
|
/* 12610 */ "evfscmpgt \0"
|
|
/* 12621 */ "efdtstgt \0"
|
|
/* 12631 */ "efststgt \0"
|
|
/* 12641 */ "evfststgt \0"
|
|
/* 12652 */ "wait \0"
|
|
/* 12658 */ "efdcmplt \0"
|
|
/* 12668 */ "qvfcmplt \0"
|
|
/* 12678 */ "efscmplt \0"
|
|
/* 12688 */ "evfscmplt \0"
|
|
/* 12699 */ "efdtstlt \0"
|
|
/* 12709 */ "efststlt \0"
|
|
/* 12719 */ "evfststlt \0"
|
|
/* 12730 */ "crnot \0"
|
|
/* 12737 */ "fsqrt \0"
|
|
/* 12744 */ "ftsqrt \0"
|
|
/* 12752 */ "psq_st \0"
|
|
/* 12760 */ "vncipherlast \0"
|
|
/* 12774 */ "vcipherlast \0"
|
|
/* 12787 */ "dcbst \0"
|
|
/* 12794 */ "dst \0"
|
|
/* 12799 */ "hashst \0"
|
|
/* 12807 */ "dcbtst \0"
|
|
/* 12815 */ "dstst \0"
|
|
/* 12822 */ "dcbtt \0"
|
|
/* 12829 */ "dstt \0"
|
|
/* 12835 */ "dcbtstt \0"
|
|
/* 12844 */ "dststt \0"
|
|
/* 12852 */ "lhau \0"
|
|
/* 12858 */ "stbu \0"
|
|
/* 12864 */ "lfdu \0"
|
|
/* 12870 */ "stfdu \0"
|
|
/* 12877 */ "maddhdu \0"
|
|
/* 12886 */ "mulhdu \0"
|
|
/* 12894 */ "qvfcfidu \0"
|
|
/* 12904 */ "qvfctidu \0"
|
|
/* 12914 */ "ldu \0"
|
|
/* 12919 */ "stdu \0"
|
|
/* 12925 */ "divdu \0"
|
|
/* 12932 */ "divdeu \0"
|
|
/* 12940 */ "divweu \0"
|
|
/* 12948 */ "sthu \0"
|
|
/* 12954 */ "evsrwiu \0"
|
|
/* 12963 */ "psq_lu \0"
|
|
/* 12971 */ "evlwhou \0"
|
|
/* 12980 */ "dcmpu \0"
|
|
/* 12987 */ "fcmpu \0"
|
|
/* 12994 */ "lfsu \0"
|
|
/* 13000 */ "stfsu \0"
|
|
/* 13007 */ "evcmpgtu \0"
|
|
/* 13017 */ "evcmpltu \0"
|
|
/* 13027 */ "psq_stu \0"
|
|
/* 13036 */ "mulhwu \0"
|
|
/* 13044 */ "qvfctiwu \0"
|
|
/* 13054 */ "evsrwu \0"
|
|
/* 13062 */ "stwu \0"
|
|
/* 13068 */ "evdivwu \0"
|
|
/* 13077 */ "lbzu \0"
|
|
/* 13083 */ "lhzu \0"
|
|
/* 13089 */ "lwzu \0"
|
|
/* 13095 */ "scv \0"
|
|
/* 13100 */ "slbmfev \0"
|
|
/* 13109 */ "ps_div \0"
|
|
/* 13117 */ "efddiv \0"
|
|
/* 13125 */ "fdiv \0"
|
|
/* 13131 */ "efsdiv \0"
|
|
/* 13139 */ "evfsdiv \0"
|
|
/* 13148 */ "ftdiv \0"
|
|
/* 13155 */ "vslv \0"
|
|
/* 13161 */ "xxleqv \0"
|
|
/* 13169 */ "creqv \0"
|
|
/* 13176 */ "eveqv \0"
|
|
/* 13183 */ "vsrv \0"
|
|
/* 13189 */ "plxv \0"
|
|
/* 13195 */ "pstxv \0"
|
|
/* 13202 */ "vextsb2w \0"
|
|
/* 13212 */ "vextsh2w \0"
|
|
/* 13222 */ "evmhesmfaaw \0"
|
|
/* 13235 */ "evmhosmfaaw \0"
|
|
/* 13248 */ "evmhessfaaw \0"
|
|
/* 13261 */ "evmhossfaaw \0"
|
|
/* 13274 */ "evaddsmiaaw \0"
|
|
/* 13287 */ "evmhesmiaaw \0"
|
|
/* 13300 */ "evsubfsmiaaw \0"
|
|
/* 13314 */ "evmwlsmiaaw \0"
|
|
/* 13327 */ "evmhosmiaaw \0"
|
|
/* 13340 */ "evaddumiaaw \0"
|
|
/* 13353 */ "evmheumiaaw \0"
|
|
/* 13366 */ "evsubfumiaaw \0"
|
|
/* 13380 */ "evmwlumiaaw \0"
|
|
/* 13393 */ "evmhoumiaaw \0"
|
|
/* 13406 */ "evaddssiaaw \0"
|
|
/* 13419 */ "evmhessiaaw \0"
|
|
/* 13432 */ "evsubfssiaaw \0"
|
|
/* 13446 */ "evmwlssiaaw \0"
|
|
/* 13459 */ "evmhossiaaw \0"
|
|
/* 13472 */ "evaddusiaaw \0"
|
|
/* 13485 */ "evmheusiaaw \0"
|
|
/* 13498 */ "evsubfusiaaw \0"
|
|
/* 13512 */ "evmwlusiaaw \0"
|
|
/* 13525 */ "evmhousiaaw \0"
|
|
/* 13538 */ "vshasigmaw \0"
|
|
/* 13550 */ "vsraw \0"
|
|
/* 13557 */ "vcntmbw \0"
|
|
/* 13566 */ "vprtybw \0"
|
|
/* 13575 */ "evaddw \0"
|
|
/* 13583 */ "evldw \0"
|
|
/* 13590 */ "evrndw \0"
|
|
/* 13598 */ "evstdw \0"
|
|
/* 13606 */ "vmrgew \0"
|
|
/* 13614 */ "vcmpnew \0"
|
|
/* 13623 */ "evsubfw \0"
|
|
/* 13632 */ "evsubifw \0"
|
|
/* 13642 */ "vnegw \0"
|
|
/* 13649 */ "vmrghw \0"
|
|
/* 13657 */ "xxmrghw \0"
|
|
/* 13666 */ "mulhw \0"
|
|
/* 13673 */ "evaddiw \0"
|
|
/* 13682 */ "qvfctiw \0"
|
|
/* 13691 */ "xxspltiw \0"
|
|
/* 13701 */ "vmrglw \0"
|
|
/* 13709 */ "xxmrglw \0"
|
|
/* 13718 */ "mullw \0"
|
|
/* 13725 */ "cmplw \0"
|
|
/* 13732 */ "evrlw \0"
|
|
/* 13739 */ "evslw \0"
|
|
/* 13746 */ "lmw \0"
|
|
/* 13751 */ "stmw \0"
|
|
/* 13757 */ "vpmsumw \0"
|
|
/* 13766 */ "evmhesmfanw \0"
|
|
/* 13779 */ "evmhosmfanw \0"
|
|
/* 13792 */ "evmhessfanw \0"
|
|
/* 13805 */ "evmhossfanw \0"
|
|
/* 13818 */ "evmhesmianw \0"
|
|
/* 13831 */ "evmwlsmianw \0"
|
|
/* 13844 */ "evmhosmianw \0"
|
|
/* 13857 */ "evmheumianw \0"
|
|
/* 13870 */ "evmwlumianw \0"
|
|
/* 13883 */ "evmhoumianw \0"
|
|
/* 13896 */ "evmhessianw \0"
|
|
/* 13909 */ "evmwlssianw \0"
|
|
/* 13922 */ "evmhossianw \0"
|
|
/* 13935 */ "evmheusianw \0"
|
|
/* 13948 */ "evmwlusianw \0"
|
|
/* 13961 */ "evmhousianw \0"
|
|
/* 13974 */ "vmrgow \0"
|
|
/* 13982 */ "cmpw \0"
|
|
/* 13988 */ "xxbrw \0"
|
|
/* 13995 */ "vsrw \0"
|
|
/* 14001 */ "vmodsw \0"
|
|
/* 14009 */ "vmulesw \0"
|
|
/* 14018 */ "vdivesw \0"
|
|
/* 14027 */ "vavgsw \0"
|
|
/* 14035 */ "vupkhsw \0"
|
|
/* 14044 */ "vmulhsw \0"
|
|
/* 14053 */ "vspltisw \0"
|
|
/* 14063 */ "vupklsw \0"
|
|
/* 14072 */ "evcntlsw \0"
|
|
/* 14082 */ "vminsw \0"
|
|
/* 14090 */ "vinsw \0"
|
|
/* 14097 */ "vmulosw \0"
|
|
/* 14106 */ "vcmpgtsw \0"
|
|
/* 14116 */ "extsw \0"
|
|
/* 14123 */ "vdivsw \0"
|
|
/* 14131 */ "vmaxsw \0"
|
|
/* 14139 */ "vspltw \0"
|
|
/* 14147 */ "xxspltw \0"
|
|
/* 14156 */ "vpopcntw \0"
|
|
/* 14166 */ "vinsertw \0"
|
|
/* 14176 */ "xxinsertw \0"
|
|
/* 14187 */ "pstw \0"
|
|
/* 14193 */ "vsubcuw \0"
|
|
/* 14202 */ "vaddcuw \0"
|
|
/* 14211 */ "vmoduw \0"
|
|
/* 14219 */ "vabsduw \0"
|
|
/* 14228 */ "vmuleuw \0"
|
|
/* 14237 */ "vdiveuw \0"
|
|
/* 14246 */ "vavguw \0"
|
|
/* 14254 */ "vmulhuw \0"
|
|
/* 14263 */ "vminuw \0"
|
|
/* 14271 */ "vmulouw \0"
|
|
/* 14280 */ "vcmpequw \0"
|
|
/* 14290 */ "vextractuw \0"
|
|
/* 14302 */ "xxextractuw \0"
|
|
/* 14315 */ "vcmpgtuw \0"
|
|
/* 14325 */ "vdivuw \0"
|
|
/* 14333 */ "vmaxuw \0"
|
|
/* 14341 */ "xxblendvw \0"
|
|
/* 14352 */ "divw \0"
|
|
/* 14358 */ "vcmpnezw \0"
|
|
/* 14368 */ "vclzw \0"
|
|
/* 14375 */ "evcntlzw \0"
|
|
/* 14385 */ "vctzw \0"
|
|
/* 14392 */ "cnttzw \0"
|
|
/* 14400 */ "lxvd2x \0"
|
|
/* 14408 */ "stxvd2x \0"
|
|
/* 14417 */ "lxvw4x \0"
|
|
/* 14425 */ "stxvw4x \0"
|
|
/* 14434 */ "lxvb16x \0"
|
|
/* 14443 */ "stxvb16x \0"
|
|
/* 14453 */ "lxvh8x \0"
|
|
/* 14461 */ "stxvh8x \0"
|
|
/* 14470 */ "lhax \0"
|
|
/* 14476 */ "tlbivax \0"
|
|
/* 14485 */ "qvlfiwax \0"
|
|
/* 14495 */ "lxsiwax \0"
|
|
/* 14504 */ "lwax \0"
|
|
/* 14510 */ "lvebx \0"
|
|
/* 14517 */ "stvebx \0"
|
|
/* 14525 */ "stxsibx \0"
|
|
/* 14534 */ "lxvrbx \0"
|
|
/* 14542 */ "stxvrbx \0"
|
|
/* 14551 */ "stbx \0"
|
|
/* 14557 */ "xxsplti32dx \0"
|
|
/* 14570 */ "qvlfcdx \0"
|
|
/* 14579 */ "qvstfcdx \0"
|
|
/* 14589 */ "evlddx \0"
|
|
/* 14597 */ "evstddx \0"
|
|
/* 14606 */ "qvlfdx \0"
|
|
/* 14614 */ "qvstfdx \0"
|
|
/* 14623 */ "qvlpcldx \0"
|
|
/* 14633 */ "qvlpcrdx \0"
|
|
/* 14643 */ "lxvrdx \0"
|
|
/* 14651 */ "stxvrdx \0"
|
|
/* 14660 */ "lxsdx \0"
|
|
/* 14667 */ "stxsdx \0"
|
|
/* 14675 */ "stdx \0"
|
|
/* 14681 */ "addex \0"
|
|
/* 14688 */ "evlwhex \0"
|
|
/* 14697 */ "evstwhex \0"
|
|
/* 14707 */ "diex \0"
|
|
/* 14713 */ "dtstex \0"
|
|
/* 14721 */ "evstwwex \0"
|
|
/* 14731 */ "dxex \0"
|
|
/* 14737 */ "evldhx \0"
|
|
/* 14745 */ "evstdhx \0"
|
|
/* 14754 */ "lvehx \0"
|
|
/* 14761 */ "stvehx \0"
|
|
/* 14769 */ "stxsihx \0"
|
|
/* 14778 */ "lxvrhx \0"
|
|
/* 14786 */ "stxvrhx \0"
|
|
/* 14795 */ "sthx \0"
|
|
/* 14801 */ "stbcix \0"
|
|
/* 14809 */ "ldcix \0"
|
|
/* 14816 */ "stdcix \0"
|
|
/* 14824 */ "sthcix \0"
|
|
/* 14832 */ "stwcix \0"
|
|
/* 14840 */ "lbzcix \0"
|
|
/* 14848 */ "lhzcix \0"
|
|
/* 14856 */ "lwzcix \0"
|
|
/* 14864 */ "dcffix \0"
|
|
/* 14872 */ "dctfix \0"
|
|
/* 14880 */ "xsrqpix \0"
|
|
/* 14889 */ "psq_lx \0"
|
|
/* 14897 */ "vinsblx \0"
|
|
/* 14906 */ "vextublx \0"
|
|
/* 14916 */ "vinsdlx \0"
|
|
/* 14925 */ "vinshlx \0"
|
|
/* 14934 */ "vextuhlx \0"
|
|
/* 14944 */ "tlbilx \0"
|
|
/* 14952 */ "vinsbvlx \0"
|
|
/* 14962 */ "vextdubvlx \0"
|
|
/* 14974 */ "vextddvlx \0"
|
|
/* 14985 */ "vinshvlx \0"
|
|
/* 14995 */ "vextduhvlx \0"
|
|
/* 15007 */ "vinswvlx \0"
|
|
/* 15017 */ "vextduwvlx \0"
|
|
/* 15029 */ "vinswlx \0"
|
|
/* 15038 */ "vextuwlx \0"
|
|
/* 15048 */ "xxpermx \0"
|
|
/* 15057 */ "vsbox \0"
|
|
/* 15064 */ "evstwhox \0"
|
|
/* 15074 */ "evstwwox \0"
|
|
/* 15084 */ "lbepx \0"
|
|
/* 15091 */ "stbepx \0"
|
|
/* 15099 */ "lfdepx \0"
|
|
/* 15107 */ "stfdepx \0"
|
|
/* 15116 */ "lhepx \0"
|
|
/* 15123 */ "sthepx \0"
|
|
/* 15131 */ "lwepx \0"
|
|
/* 15138 */ "stwepx \0"
|
|
/* 15146 */ "vupkhpx \0"
|
|
/* 15155 */ "vpkpx \0"
|
|
/* 15162 */ "vupklpx \0"
|
|
/* 15171 */ "lxsspx \0"
|
|
/* 15179 */ "stxsspx \0"
|
|
/* 15188 */ "lxvpx \0"
|
|
/* 15195 */ "stxvpx \0"
|
|
/* 15203 */ "lbarx \0"
|
|
/* 15210 */ "ldarx \0"
|
|
/* 15217 */ "lharx \0"
|
|
/* 15224 */ "lqarx \0"
|
|
/* 15231 */ "lwarx \0"
|
|
/* 15238 */ "ldbrx \0"
|
|
/* 15245 */ "stdbrx \0"
|
|
/* 15253 */ "lhbrx \0"
|
|
/* 15260 */ "sthbrx \0"
|
|
/* 15268 */ "vinsbrx \0"
|
|
/* 15277 */ "vextubrx \0"
|
|
/* 15287 */ "lwbrx \0"
|
|
/* 15294 */ "stwbrx \0"
|
|
/* 15302 */ "vinsdrx \0"
|
|
/* 15311 */ "vinshrx \0"
|
|
/* 15320 */ "vextuhrx \0"
|
|
/* 15330 */ "vinsbvrx \0"
|
|
/* 15340 */ "vextdubvrx \0"
|
|
/* 15352 */ "vextddvrx \0"
|
|
/* 15363 */ "vinshvrx \0"
|
|
/* 15373 */ "vextduhvrx \0"
|
|
/* 15385 */ "vinswvrx \0"
|
|
/* 15395 */ "vextduwvrx \0"
|
|
/* 15407 */ "vinswrx \0"
|
|
/* 15416 */ "vextuwrx \0"
|
|
/* 15426 */ "mcrxrx \0"
|
|
/* 15434 */ "tlbsx \0"
|
|
/* 15441 */ "qvlfcsx \0"
|
|
/* 15450 */ "qvstfcsx \0"
|
|
/* 15460 */ "lxvdsx \0"
|
|
/* 15468 */ "vcfsx \0"
|
|
/* 15475 */ "qvlfsx \0"
|
|
/* 15483 */ "qvstfsx \0"
|
|
/* 15492 */ "qvlpclsx \0"
|
|
/* 15502 */ "evlwhosx \0"
|
|
/* 15512 */ "qvlpcrsx \0"
|
|
/* 15522 */ "lxvwsx \0"
|
|
/* 15530 */ "evlhhesplatx \0"
|
|
/* 15544 */ "evlwhsplatx \0"
|
|
/* 15557 */ "evlhhossplatx \0"
|
|
/* 15572 */ "evlhhousplatx \0"
|
|
/* 15587 */ "evlwwsplatx \0"
|
|
/* 15600 */ "drintx \0"
|
|
/* 15608 */ "psq_stx \0"
|
|
/* 15617 */ "lhaux \0"
|
|
/* 15624 */ "lwaux \0"
|
|
/* 15631 */ "stbux \0"
|
|
/* 15638 */ "qvlfcdux \0"
|
|
/* 15648 */ "qvstfcdux \0"
|
|
/* 15659 */ "qvlfdux \0"
|
|
/* 15668 */ "qvstfdux \0"
|
|
/* 15678 */ "ldux \0"
|
|
/* 15684 */ "stdux \0"
|
|
/* 15691 */ "vcfux \0"
|
|
/* 15698 */ "sthux \0"
|
|
/* 15705 */ "psq_lux \0"
|
|
/* 15714 */ "evlwhoux \0"
|
|
/* 15724 */ "qvlfcsux \0"
|
|
/* 15734 */ "qvstfcsux \0"
|
|
/* 15745 */ "qvlfsux \0"
|
|
/* 15754 */ "qvstfsux \0"
|
|
/* 15764 */ "psq_stux \0"
|
|
/* 15774 */ "stwux \0"
|
|
/* 15781 */ "lbzux \0"
|
|
/* 15788 */ "lhzux \0"
|
|
/* 15795 */ "lwzux \0"
|
|
/* 15802 */ "lvx \0"
|
|
/* 15807 */ "stvx \0"
|
|
/* 15813 */ "lxvx \0"
|
|
/* 15819 */ "stxvx \0"
|
|
/* 15826 */ "evldwx \0"
|
|
/* 15834 */ "evstdwx \0"
|
|
/* 15843 */ "lvewx \0"
|
|
/* 15850 */ "stvewx \0"
|
|
/* 15858 */ "qvstfiwx \0"
|
|
/* 15868 */ "stxsiwx \0"
|
|
/* 15877 */ "lxvrwx \0"
|
|
/* 15885 */ "stxvrwx \0"
|
|
/* 15894 */ "stwx \0"
|
|
/* 15900 */ "lxsibzx \0"
|
|
/* 15909 */ "lbzx \0"
|
|
/* 15915 */ "lxsihzx \0"
|
|
/* 15924 */ "lhzx \0"
|
|
/* 15930 */ "qvlfiwzx \0"
|
|
/* 15940 */ "lxsiwzx \0"
|
|
/* 15949 */ "lwzx \0"
|
|
/* 15955 */ "copy \0"
|
|
/* 15961 */ "dcbz \0"
|
|
/* 15967 */ "plbz \0"
|
|
/* 15973 */ "xxsetaccz \0"
|
|
/* 15984 */ "efdctsidz \0"
|
|
/* 15995 */ "qvfctidz \0"
|
|
/* 16005 */ "efdctuidz \0"
|
|
/* 16016 */ "xscvqpsdz \0"
|
|
/* 16027 */ "xscvqpudz \0"
|
|
/* 16038 */ "plhz \0"
|
|
/* 16044 */ "vrfiz \0"
|
|
/* 16051 */ "xsrdpiz \0"
|
|
/* 16060 */ "xvrdpiz \0"
|
|
/* 16069 */ "xvrspiz \0"
|
|
/* 16078 */ "qvfriz \0"
|
|
/* 16086 */ "efdctsiz \0"
|
|
/* 16096 */ "efsctsiz \0"
|
|
/* 16106 */ "evfsctsiz \0"
|
|
/* 16117 */ "efdctuiz \0"
|
|
/* 16127 */ "efsctuiz \0"
|
|
/* 16137 */ "xscvqpsqz \0"
|
|
/* 16148 */ "xscvqpuqz \0"
|
|
/* 16159 */ "dmsetdmrz \0"
|
|
/* 16170 */ "qvfctiduz \0"
|
|
/* 16181 */ "qvfctiwuz \0"
|
|
/* 16192 */ "qvfctiwz \0"
|
|
/* 16202 */ "plwz \0"
|
|
/* 16208 */ "mfvsrwz \0"
|
|
/* 16217 */ "mtvsrwz \0"
|
|
/* 16226 */ "xscvqpswz \0"
|
|
/* 16237 */ "xscvqpuwz \0"
|
|
/* 16248 */ "evsel crD,\0"
|
|
/* 16259 */ "# XRay Function Patchable RET.\0"
|
|
/* 16290 */ "# XRay Typed Event Log.\0"
|
|
/* 16314 */ "# XRay Custom Event Log.\0"
|
|
/* 16339 */ "# XRay Function Enter.\0"
|
|
/* 16362 */ "# XRay Tail Call Exit.\0"
|
|
/* 16385 */ "# XRay Function Exit.\0"
|
|
/* 16407 */ "trechkpt.\0"
|
|
/* 16417 */ "ori 1, 1, 0\0"
|
|
/* 16429 */ "ori 2, 2, 0\0"
|
|
/* 16441 */ "#ADDISdtprelHA32\0"
|
|
/* 16458 */ "#ATOMIC_LOAD_SUB_I32\0"
|
|
/* 16479 */ "#ATOMIC_LOAD_ADD_I32\0"
|
|
/* 16500 */ "#ATOMIC_LOAD_NAND_I32\0"
|
|
/* 16522 */ "#ATOMIC_LOAD_AND_I32\0"
|
|
/* 16543 */ "#ATOMIC_LOAD_UMIN_I32\0"
|
|
/* 16565 */ "#ATOMIC_LOAD_MIN_I32\0"
|
|
/* 16586 */ "#ATOMIC_SWAP_I32\0"
|
|
/* 16603 */ "#ATOMIC_LOAD_XOR_I32\0"
|
|
/* 16624 */ "#ATOMIC_LOAD_OR_I32\0"
|
|
/* 16644 */ "#ATOMIC_LOAD_UMAX_I32\0"
|
|
/* 16666 */ "#ATOMIC_LOAD_MAX_I32\0"
|
|
/* 16687 */ "#ADDItlsgdL32\0"
|
|
/* 16701 */ "#ADDItlsldL32\0"
|
|
/* 16715 */ "#LDgotTprelL32\0"
|
|
/* 16730 */ "#ADDIdtprelL32\0"
|
|
/* 16745 */ "#EH_SJLJ_LONGJMP32\0"
|
|
/* 16764 */ "#EH_SJLJ_SETJMP32\0"
|
|
/* 16782 */ "#ADDItlsgdLADDR32\0"
|
|
/* 16800 */ "#ADDItlsldLADDR32\0"
|
|
/* 16818 */ "GETtlsldADDR32\0"
|
|
/* 16833 */ "GETtlsADDR32\0"
|
|
/* 16846 */ "#PROBED_ALLOCA_32\0"
|
|
/* 16864 */ "#PREPARE_PROBED_ALLOCA_32\0"
|
|
/* 16890 */ "#PROBED_STACKALLOC_32\0"
|
|
/* 16912 */ "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32\0"
|
|
/* 16955 */ "#DFLOADf32\0"
|
|
/* 16966 */ "#XFLOADf32\0"
|
|
/* 16977 */ "#DFSTOREf32\0"
|
|
/* 16989 */ "#XFSTOREf32\0"
|
|
/* 17001 */ "#ATOMIC_LOAD_SUB_I64\0"
|
|
/* 17022 */ "#ATOMIC_LOAD_ADD_I64\0"
|
|
/* 17043 */ "#ATOMIC_LOAD_NAND_I64\0"
|
|
/* 17065 */ "#ATOMIC_LOAD_UMIN_I64\0"
|
|
/* 17087 */ "#ATOMIC_LOAD_MIN_I64\0"
|
|
/* 17108 */ "#ATOMIC_SWAP_I64\0"
|
|
/* 17125 */ "#ATOMIC_CMP_SWAP_I64\0"
|
|
/* 17146 */ "#ATOMIC_LOAD_XOR_I64\0"
|
|
/* 17167 */ "#ATOMIC_LOAD_OR_I64\0"
|
|
/* 17187 */ "#ATOMIC_LOAD_UMAX_I64\0"
|
|
/* 17209 */ "#ATOMIC_LOAD_MAX_I64\0"
|
|
/* 17230 */ "#EH_SJLJ_LONGJMP64\0"
|
|
/* 17249 */ "#EH_SJLJ_SETJMP64\0"
|
|
/* 17267 */ "#PROBED_ALLOCA_64\0"
|
|
/* 17285 */ "#PREPARE_PROBED_ALLOCA_64\0"
|
|
/* 17311 */ "#PROBED_STACKALLOC_64\0"
|
|
/* 17333 */ "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64\0"
|
|
/* 17376 */ "#DFLOADf64\0"
|
|
/* 17387 */ "#XFLOADf64\0"
|
|
/* 17398 */ "#DFSTOREf64\0"
|
|
/* 17410 */ "#XFSTOREf64\0"
|
|
/* 17422 */ "#ATOMIC_LOAD_AND_i64\0"
|
|
/* 17443 */ "#SELECT_CC_SPE4\0"
|
|
/* 17459 */ "#SELECT_SPE4\0"
|
|
/* 17472 */ "#SELECT_CC_F4\0"
|
|
/* 17486 */ "#SELECT_F4\0"
|
|
/* 17497 */ "#SELECT_CC_I4\0"
|
|
/* 17511 */ "#SELECT_I4\0"
|
|
/* 17522 */ "crxor 6, 6, 6\0"
|
|
/* 17536 */ "creqv 6, 6, 6\0"
|
|
/* 17550 */ "#SELECT_CC_F16\0"
|
|
/* 17565 */ "#SELECT_F16\0"
|
|
/* 17577 */ "#ATOMIC_LOAD_SUB_I16\0"
|
|
/* 17598 */ "#ATOMIC_LOAD_ADD_I16\0"
|
|
/* 17619 */ "#ATOMIC_LOAD_NAND_I16\0"
|
|
/* 17641 */ "#ATOMIC_LOAD_AND_I16\0"
|
|
/* 17662 */ "#ATOMIC_LOAD_UMIN_I16\0"
|
|
/* 17684 */ "#ATOMIC_LOAD_MIN_I16\0"
|
|
/* 17705 */ "#ATOMIC_SWAP_I16\0"
|
|
/* 17722 */ "#ATOMIC_LOAD_XOR_I16\0"
|
|
/* 17743 */ "#ATOMIC_LOAD_OR_I16\0"
|
|
/* 17763 */ "#ATOMIC_LOAD_UMAX_I16\0"
|
|
/* 17785 */ "#ATOMIC_LOAD_MAX_I16\0"
|
|
/* 17806 */ "#ATOMIC_LOAD_SUB_I128\0"
|
|
/* 17828 */ "#ATOMIC_LOAD_ADD_I128\0"
|
|
/* 17850 */ "#ATOMIC_LOAD_NAND_I128\0"
|
|
/* 17873 */ "#ATOMIC_LOAD_AND_I128\0"
|
|
/* 17895 */ "#ATOMIC_SWAP_I128\0"
|
|
/* 17913 */ "#ATOMIC_CMP_SWAP_I128\0"
|
|
/* 17935 */ "#ATOMIC_LOAD_XOR_I128\0"
|
|
/* 17957 */ "#ATOMIC_LOAD_OR_I128\0"
|
|
/* 17978 */ "#ADDIStocHA8\0"
|
|
/* 17991 */ "#DYNALLOC8\0"
|
|
/* 18002 */ "#CFENCE8\0"
|
|
/* 18011 */ "#SELECT_CC_F8\0"
|
|
/* 18025 */ "#SELECT_F8\0"
|
|
/* 18036 */ "#ATOMIC_LOAD_SUB_I8\0"
|
|
/* 18056 */ "#SELECT_CC_I8\0"
|
|
/* 18070 */ "#ATOMIC_LOAD_ADD_I8\0"
|
|
/* 18090 */ "#ATOMIC_LOAD_NAND_I8\0"
|
|
/* 18111 */ "#ATOMIC_LOAD_AND_I8\0"
|
|
/* 18131 */ "#ATOMIC_LOAD_UMIN_I8\0"
|
|
/* 18152 */ "#ATOMIC_LOAD_MIN_I8\0"
|
|
/* 18172 */ "#ATOMIC_CMP_SWAP_I8\0"
|
|
/* 18192 */ "ATOMIC_LOAD_XOR_I8\0"
|
|
/* 18211 */ "#ATOMIC_LOAD_OR_I8\0"
|
|
/* 18230 */ "#SELECT_I8\0"
|
|
/* 18241 */ "#ATOMIC_LOAD_UMAX_I8\0"
|
|
/* 18262 */ "#ATOMIC_LOAD_MAX_I8\0"
|
|
/* 18282 */ "#MovePCtoLR8\0"
|
|
/* 18295 */ "#DYNAREAOFFSET8\0"
|
|
/* 18311 */ "#ANDI_rec_1_EQ_BIT8\0"
|
|
/* 18331 */ "#ANDI_rec_1_GT_BIT8\0"
|
|
/* 18351 */ "#TLSGDAIX8\0"
|
|
/* 18362 */ "#ADDItoc8\0"
|
|
/* 18372 */ "#ATOMIC_SWAP_i8\0"
|
|
/* 18388 */ "#ADDIStocHA\0"
|
|
/* 18400 */ "#ADDIStlsgdHA\0"
|
|
/* 18414 */ "#ADDIStlsldHA\0"
|
|
/* 18428 */ "#ADDISgotTprelHA\0"
|
|
/* 18445 */ "#ADDISdtprelHA\0"
|
|
/* 18460 */ "#ReadTB\0"
|
|
/* 18468 */ "#RESTORE_UACC\0"
|
|
/* 18482 */ "#SPILL_UACC\0"
|
|
/* 18494 */ "#RESTORE_WACC\0"
|
|
/* 18508 */ "#SPILL_WACC\0"
|
|
/* 18520 */ "#RESTORE_ACC\0"
|
|
/* 18533 */ "#SPILL_ACC\0"
|
|
/* 18544 */ "#DYNALLOC\0"
|
|
/* 18554 */ "#SELECT_CC_QBRC\0"
|
|
/* 18570 */ "#SELECT_QBRC\0"
|
|
/* 18583 */ "#SELECT_CC_QFRC\0"
|
|
/* 18599 */ "#SELECT_QFRC\0"
|
|
/* 18612 */ "#SELECT_CC_VSFRC\0"
|
|
/* 18629 */ "#SELECT_VSFRC\0"
|
|
/* 18643 */ "#SELECT_CC_VRRC\0"
|
|
/* 18659 */ "#SELECT_VRRC\0"
|
|
/* 18672 */ "#SELECT_CC_QSRC\0"
|
|
/* 18688 */ "#SELECT_QSRC\0"
|
|
/* 18701 */ "#SELECT_CC_VSSRC\0"
|
|
/* 18718 */ "#SELECT_VSSRC\0"
|
|
/* 18732 */ "#SELECT_CC_VSRC\0"
|
|
/* 18748 */ "#SELECT_VSRC\0"
|
|
/* 18761 */ "#SPILLTOVSR_LD\0"
|
|
/* 18776 */ "LIFETIME_END\0"
|
|
/* 18789 */ "#SETRND\0"
|
|
/* 18797 */ "#BUILD_QUADWORD\0"
|
|
/* 18813 */ "#RESTORE_QUADWORD\0"
|
|
/* 18831 */ "#SPILL_QUADWORD\0"
|
|
/* 18847 */ "#SPLIT_QUADWORD\0"
|
|
/* 18863 */ "PSEUDO_PROBE\0"
|
|
/* 18876 */ "#FENCE\0"
|
|
/* 18883 */ "#CFENCE\0"
|
|
/* 18891 */ "BUNDLE\0"
|
|
/* 18898 */ "#SELECT_CC_SPE\0"
|
|
/* 18913 */ "#SELECT_SPE\0"
|
|
/* 18925 */ "DBG_VALUE\0"
|
|
/* 18935 */ "DBG_INSTR_REF\0"
|
|
/* 18949 */ "DBG_PHI\0"
|
|
/* 18957 */ "#LDtocJTI\0"
|
|
/* 18967 */ "DBG_LABEL\0"
|
|
/* 18977 */ "#GETtlsldADDRPCREL\0"
|
|
/* 18996 */ "#GETtlsADDRPCREL\0"
|
|
/* 19013 */ "#LDtocL\0"
|
|
/* 19021 */ "#ADDItocL\0"
|
|
/* 19031 */ "#LWZtocL\0"
|
|
/* 19040 */ "#ADDItlsgdL\0"
|
|
/* 19052 */ "#ADDItlsldL\0"
|
|
/* 19064 */ "#LDgotTprelL\0"
|
|
/* 19077 */ "#ADDIdtprelL\0"
|
|
/* 19090 */ "#SETFLM\0"
|
|
/* 19098 */ "#LQX_PSEUDO\0"
|
|
/* 19110 */ "#STQX_PSEUDO\0"
|
|
/* 19123 */ "#PPCEIEIO\0"
|
|
/* 19133 */ "#UNENCODED_NOP\0"
|
|
/* 19148 */ "#UpdateGBR\0"
|
|
/* 19159 */ "#RESTORE_CR\0"
|
|
/* 19171 */ "#SPILL_CR\0"
|
|
/* 19181 */ "#ADDItlsgdLADDR\0"
|
|
/* 19197 */ "#ADDItlsldLADDR\0"
|
|
/* 19213 */ "#GETtlsldADDR\0"
|
|
/* 19227 */ "#GETtlsADDR\0"
|
|
/* 19239 */ "#KILL_PAIR\0"
|
|
/* 19250 */ "#MovePCtoLR\0"
|
|
/* 19262 */ "#MoveGOTtoLR\0"
|
|
/* 19275 */ "#TCHECK_RET\0"
|
|
/* 19287 */ "#TBEGIN_RET\0"
|
|
/* 19299 */ "#DYNAREAOFFSET\0"
|
|
/* 19314 */ "#RESTORE_CRBIT\0"
|
|
/* 19329 */ "#SPILL_CRBIT\0"
|
|
/* 19342 */ "#ANDI_rec_1_EQ_BIT\0"
|
|
/* 19361 */ "#ANDI_rec_1_GT_BIT\0"
|
|
/* 19380 */ "#PPC32GOT\0"
|
|
/* 19390 */ "#PPC32PICGOT\0"
|
|
/* 19403 */ "#LDtocCPT\0"
|
|
/* 19413 */ "LIFETIME_START\0"
|
|
/* 19428 */ "DBG_VALUE_LIST\0"
|
|
/* 19443 */ "#SPILLTOVSR_ST\0"
|
|
/* 19458 */ "#LIWAX\0"
|
|
/* 19465 */ "#SPILLTOVSR_LDX\0"
|
|
/* 19481 */ "GETtlsADDR32AIX\0"
|
|
/* 19497 */ "GETtlsTpointer32AIX\0"
|
|
/* 19517 */ "GETtlsADDR64AIX\0"
|
|
/* 19533 */ "#TLSGDAIX\0"
|
|
/* 19543 */ "#SPILLTOVSR_STX\0"
|
|
/* 19559 */ "#STIWX\0"
|
|
/* 19566 */ "#LIWZX\0"
|
|
/* 19573 */ "bca\0"
|
|
/* 19577 */ "slbia\0"
|
|
/* 19583 */ "tlbia\0"
|
|
/* 19589 */ "bcla\0"
|
|
/* 19594 */ "clrbhrb\0"
|
|
/* 19602 */ "bc\0"
|
|
/* 19605 */ "slbsync\0"
|
|
/* 19613 */ "tlbsync\0"
|
|
/* 19621 */ "msgsync\0"
|
|
/* 19629 */ "isync\0"
|
|
/* 19635 */ "msync\0"
|
|
/* 19641 */ "#LDtoc\0"
|
|
/* 19648 */ "#ADDItoc\0"
|
|
/* 19657 */ "#LWZtoc\0"
|
|
/* 19665 */ "hrfid\0"
|
|
/* 19671 */ "tlbre\0"
|
|
/* 19677 */ "tlbwe\0"
|
|
/* 19683 */ "#SETRNDi\0"
|
|
/* 19692 */ "rfci\0"
|
|
/* 19697 */ "rfmci\0"
|
|
/* 19703 */ "rfdi\0"
|
|
/* 19708 */ "rfi\0"
|
|
/* 19712 */ "bcl\0"
|
|
/* 19716 */ "#PADDIdtprel\0"
|
|
/* 19729 */ "# FEntry call\0"
|
|
/* 19743 */ "dssall\0"
|
|
/* 19750 */ "blrl\0"
|
|
/* 19755 */ "bctrl\0"
|
|
/* 19761 */ "attn\0"
|
|
/* 19766 */ "eieio\0"
|
|
/* 19772 */ "nap\0"
|
|
/* 19776 */ "trap\0"
|
|
/* 19781 */ "nop\0"
|
|
/* 19785 */ "#DecreaseCTR8loop\0"
|
|
/* 19803 */ "#DecreaseCTRloop\0"
|
|
/* 19820 */ "stop\0"
|
|
/* 19825 */ "blr\0"
|
|
/* 19829 */ "bctr\0"
|
|
/* 19834 */ "cpabort\0"
|
|
};
|
|
#endif // CAPSTONE_DIET
|
|
|
|
static const uint32_t OpInfo0[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
18926U, // DBG_VALUE
|
|
19429U, // DBG_VALUE_LIST
|
|
18936U, // DBG_INSTR_REF
|
|
18950U, // DBG_PHI
|
|
18968U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
18892U, // BUNDLE
|
|
19414U, // LIFETIME_START
|
|
18777U, // LIFETIME_END
|
|
18864U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
19730U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
16340U, // PATCHABLE_FUNCTION_ENTER
|
|
16260U, // PATCHABLE_RET
|
|
16386U, // PATCHABLE_FUNCTION_EXIT
|
|
16363U, // PATCHABLE_TAIL_CALL
|
|
16315U, // PATCHABLE_EVENT_CALL
|
|
16291U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
17914U, // ATOMIC_CMP_SWAP_I128
|
|
17829U, // ATOMIC_LOAD_ADD_I128
|
|
17874U, // ATOMIC_LOAD_AND_I128
|
|
17851U, // ATOMIC_LOAD_NAND_I128
|
|
17958U, // ATOMIC_LOAD_OR_I128
|
|
17807U, // ATOMIC_LOAD_SUB_I128
|
|
17936U, // ATOMIC_LOAD_XOR_I128
|
|
17896U, // ATOMIC_SWAP_I128
|
|
18798U, // BUILD_QUADWORD
|
|
35707U, // BUILD_UACC
|
|
18884U, // CFENCE
|
|
18003U, // CFENCE8
|
|
2147522466U, // CLRLSLDI
|
|
2147517347U, // CLRLSLDI_rec
|
|
2147523021U, // CLRLSLWI
|
|
2147517472U, // CLRLSLWI_rec
|
|
2147522501U, // CLRRDI
|
|
2147517374U, // CLRRDI_rec
|
|
2147523062U, // CLRRWI
|
|
2147517501U, // CLRRWI_rec
|
|
1121020U, // DCBFL
|
|
1123551U, // DCBFLP
|
|
1126251U, // DCBFPS
|
|
1119445U, // DCBFx
|
|
1126259U, // DCBSTPS
|
|
33632531U, // DCBTCT
|
|
33631777U, // DCBTDS
|
|
33632539U, // DCBTSTCT
|
|
33631785U, // DCBTSTDS
|
|
1126948U, // DCBTSTT
|
|
1126920U, // DCBTSTx
|
|
1126935U, // DCBTT
|
|
1126663U, // DCBTx
|
|
16956U, // DFLOADf32
|
|
17377U, // DFLOADf64
|
|
16978U, // DFSTOREf32
|
|
17399U, // DFSTOREf64
|
|
2147522476U, // EXTLDI
|
|
2147517358U, // EXTLDI_rec
|
|
2147523047U, // EXTLWI
|
|
2147517492U, // EXTLWI_rec
|
|
2147522525U, // EXTRDI
|
|
2147517401U, // EXTRDI_rec
|
|
2147523086U, // EXTRWI
|
|
2147517528U, // EXTRWI_rec
|
|
2147523031U, // INSLWI
|
|
2147517483U, // INSLWI_rec
|
|
2147522509U, // INSRDI
|
|
2147517383U, // INSRDI_rec
|
|
2147523070U, // INSRWI
|
|
2147517510U, // INSRWI_rec
|
|
19240U, // KILL_PAIR
|
|
67145052U, // LAx
|
|
100702249U, // LI
|
|
100702249U, // LI8
|
|
100708146U, // LIS
|
|
100708146U, // LIS8
|
|
19459U, // LIWAX
|
|
19567U, // LIWZX
|
|
2147522415U, // PSUBI
|
|
2147522660U, // RLWIMIbm
|
|
2147517447U, // RLWIMIbm_rec
|
|
2147523865U, // RLWINMbm
|
|
2147517631U, // RLWINMbm_rec
|
|
2147523882U, // RLWNMbm
|
|
2147517640U, // RLWNMbm_rec
|
|
2147522517U, // ROTRDI
|
|
2147517392U, // ROTRDI_rec
|
|
2147523078U, // ROTRWI
|
|
2147517519U, // ROTRWI_rec
|
|
2147522470U, // SLDI
|
|
2147517351U, // SLDI_rec
|
|
2147523025U, // SLWI
|
|
2147517476U, // SLWI_rec
|
|
18762U, // SPILLTOVSR_LD
|
|
19466U, // SPILLTOVSR_LDX
|
|
19444U, // SPILLTOVSR_ST
|
|
19544U, // SPILLTOVSR_STX
|
|
2147522511U, // SRDI
|
|
2147517385U, // SRDI_rec
|
|
2147523072U, // SRWI
|
|
2147517512U, // SRWI_rec
|
|
19560U, // STIWX
|
|
2147522416U, // SUBI
|
|
2147520648U, // SUBIC
|
|
2147516828U, // SUBIC_rec
|
|
2147528466U, // SUBIS
|
|
100708121U, // SUBPCIS
|
|
16967U, // XFLOADf32
|
|
17388U, // XFLOADf64
|
|
16990U, // XFSTOREf32
|
|
17411U, // XFSTOREf64
|
|
2147520856U, // ADD4
|
|
2147524456U, // ADD4O
|
|
2147517740U, // ADD4O_rec
|
|
2147520856U, // ADD4TLS
|
|
2147516911U, // ADD4_rec
|
|
2147520856U, // ADD8
|
|
2147524456U, // ADD8O
|
|
2147517740U, // ADD8O_rec
|
|
2147520856U, // ADD8TLS
|
|
2147520856U, // ADD8TLS_
|
|
2147516911U, // ADD8_rec
|
|
2147520602U, // ADDC
|
|
2147520602U, // ADDC8
|
|
2147524441U, // ADDC8O
|
|
2147517723U, // ADDC8O_rec
|
|
2147516795U, // ADDC8_rec
|
|
2147524441U, // ADDCO
|
|
2147517723U, // ADDCO_rec
|
|
2147516795U, // ADDC_rec
|
|
2147521585U, // ADDE
|
|
2147521585U, // ADDE8
|
|
2147524477U, // ADDE8O
|
|
2147517764U, // ADDE8O_rec
|
|
2147517104U, // ADDE8_rec
|
|
2147524477U, // ADDEO
|
|
2147517764U, // ADDEO_rec
|
|
2147531098U, // ADDEX
|
|
2147531098U, // ADDEX8
|
|
2147517104U, // ADDE_rec
|
|
2147527945U, // ADDG6S
|
|
2147527945U, // ADDG6S8
|
|
2147522452U, // ADDI
|
|
2147522452U, // ADDI8
|
|
2147520655U, // ADDIC
|
|
2147520655U, // ADDIC8
|
|
2147516836U, // ADDIC_rec
|
|
2147528491U, // ADDIS
|
|
2147528491U, // ADDIS8
|
|
18446U, // ADDISdtprelHA
|
|
16442U, // ADDISdtprelHA32
|
|
18429U, // ADDISgotTprelHA
|
|
18401U, // ADDIStlsgdHA
|
|
18415U, // ADDIStlsldHA
|
|
18389U, // ADDIStocHA
|
|
17979U, // ADDIStocHA8
|
|
19078U, // ADDIdtprelL
|
|
16731U, // ADDIdtprelL32
|
|
19041U, // ADDItlsgdL
|
|
16688U, // ADDItlsgdL32
|
|
19182U, // ADDItlsgdLADDR
|
|
16783U, // ADDItlsgdLADDR32
|
|
19053U, // ADDItlsldL
|
|
16702U, // ADDItlsldL32
|
|
19198U, // ADDItlsldLADDR
|
|
16801U, // ADDItlsldLADDR32
|
|
19649U, // ADDItoc
|
|
18363U, // ADDItoc8
|
|
19022U, // ADDItocL
|
|
38004U, // ADDME
|
|
38004U, // ADDME8
|
|
40852U, // ADDME8O
|
|
34142U, // ADDME8O_rec
|
|
33488U, // ADDME8_rec
|
|
40852U, // ADDMEO
|
|
34142U, // ADDMEO_rec
|
|
33488U, // ADDME_rec
|
|
44834U, // ADDPCIS
|
|
38086U, // ADDZE
|
|
38086U, // ADDZE8
|
|
40877U, // ADDZE8O
|
|
34170U, // ADDZE8O_rec
|
|
33549U, // ADDZE8_rec
|
|
40877U, // ADDZEO
|
|
34170U, // ADDZEO_rec
|
|
33549U, // ADDZE_rec
|
|
101256U, // ADJCALLSTACKDOWN
|
|
101275U, // ADJCALLSTACKUP
|
|
2147521166U, // AND
|
|
2147521166U, // AND8
|
|
2147517010U, // AND8_rec
|
|
2147520611U, // ANDC
|
|
2147520611U, // ANDC8
|
|
2147516802U, // ANDC8_rec
|
|
2147516802U, // ANDC_rec
|
|
2147517367U, // ANDI8_rec
|
|
2147518496U, // ANDIS8_rec
|
|
2147518496U, // ANDIS_rec
|
|
2147517367U, // ANDI_rec
|
|
19343U, // ANDI_rec_1_EQ_BIT
|
|
18312U, // ANDI_rec_1_EQ_BIT8
|
|
19362U, // ANDI_rec_1_GT_BIT
|
|
18332U, // ANDI_rec_1_GT_BIT8
|
|
2147517010U, // AND_rec
|
|
136350466U, // ATOMIC_CMP_SWAP_I16
|
|
136350392U, // ATOMIC_CMP_SWAP_I32
|
|
17126U, // ATOMIC_CMP_SWAP_I64
|
|
18173U, // ATOMIC_CMP_SWAP_I8
|
|
17599U, // ATOMIC_LOAD_ADD_I16
|
|
16480U, // ATOMIC_LOAD_ADD_I32
|
|
17023U, // ATOMIC_LOAD_ADD_I64
|
|
18071U, // ATOMIC_LOAD_ADD_I8
|
|
17642U, // ATOMIC_LOAD_AND_I16
|
|
16523U, // ATOMIC_LOAD_AND_I32
|
|
17423U, // ATOMIC_LOAD_AND_I64
|
|
18112U, // ATOMIC_LOAD_AND_I8
|
|
17786U, // ATOMIC_LOAD_MAX_I16
|
|
16667U, // ATOMIC_LOAD_MAX_I32
|
|
17210U, // ATOMIC_LOAD_MAX_I64
|
|
18263U, // ATOMIC_LOAD_MAX_I8
|
|
17685U, // ATOMIC_LOAD_MIN_I16
|
|
16566U, // ATOMIC_LOAD_MIN_I32
|
|
17088U, // ATOMIC_LOAD_MIN_I64
|
|
18153U, // ATOMIC_LOAD_MIN_I8
|
|
17620U, // ATOMIC_LOAD_NAND_I16
|
|
16501U, // ATOMIC_LOAD_NAND_I32
|
|
17044U, // ATOMIC_LOAD_NAND_I64
|
|
18091U, // ATOMIC_LOAD_NAND_I8
|
|
17744U, // ATOMIC_LOAD_OR_I16
|
|
16625U, // ATOMIC_LOAD_OR_I32
|
|
17168U, // ATOMIC_LOAD_OR_I64
|
|
18212U, // ATOMIC_LOAD_OR_I8
|
|
17578U, // ATOMIC_LOAD_SUB_I16
|
|
16459U, // ATOMIC_LOAD_SUB_I32
|
|
17002U, // ATOMIC_LOAD_SUB_I64
|
|
18037U, // ATOMIC_LOAD_SUB_I8
|
|
17764U, // ATOMIC_LOAD_UMAX_I16
|
|
16645U, // ATOMIC_LOAD_UMAX_I32
|
|
17188U, // ATOMIC_LOAD_UMAX_I64
|
|
18242U, // ATOMIC_LOAD_UMAX_I8
|
|
17663U, // ATOMIC_LOAD_UMIN_I16
|
|
16544U, // ATOMIC_LOAD_UMIN_I32
|
|
17066U, // ATOMIC_LOAD_UMIN_I64
|
|
18132U, // ATOMIC_LOAD_UMIN_I8
|
|
17723U, // ATOMIC_LOAD_XOR_I16
|
|
16604U, // ATOMIC_LOAD_XOR_I32
|
|
17147U, // ATOMIC_LOAD_XOR_I64
|
|
18193U, // ATOMIC_LOAD_XOR_I8
|
|
17706U, // ATOMIC_SWAP_I16
|
|
16587U, // ATOMIC_SWAP_I32
|
|
17109U, // ATOMIC_SWAP_I64
|
|
18373U, // ATOMIC_SWAP_I8
|
|
19762U, // ATTN
|
|
1183316U, // B
|
|
1215541U, // BA
|
|
167804974U, // BC
|
|
3361937U, // BCC
|
|
4410513U, // BCCA
|
|
5459089U, // BCCCTR
|
|
5459089U, // BCCCTR8
|
|
6507665U, // BCCCTRL
|
|
6507665U, // BCCCTRL8
|
|
7556241U, // BCCL
|
|
8604817U, // BCCLA
|
|
9653393U, // BCCLR
|
|
10701969U, // BCCLRL
|
|
11567200U, // BCCTR
|
|
11567200U, // BCCTR8
|
|
11567178U, // BCCTRL
|
|
11567178U, // BCCTRL8
|
|
2147516917U, // BCDADD_rec
|
|
2147517648U, // BCDCFN_rec
|
|
2147518174U, // BCDCFSQ_rec
|
|
2147518909U, // BCDCFZ_rec
|
|
2147517657U, // BCDCPSGN_rec
|
|
34057U, // BCDCTN_rec
|
|
34536U, // BCDCTSQ_rec
|
|
2147518925U, // BCDCTZ_rec
|
|
2147517677U, // BCDSETSGN_rec
|
|
2147518344U, // BCDSR_rec
|
|
2147516719U, // BCDSUB_rec
|
|
2147518419U, // BCDS_rec
|
|
2147516852U, // BCDTRUNC_rec
|
|
2147518521U, // BCDUS_rec
|
|
2147516863U, // BCDUTRUNC_rec
|
|
167804982U, // BCL
|
|
11567190U, // BCLR
|
|
11567167U, // BCLRL
|
|
19830U, // BCTR
|
|
19830U, // BCTR8
|
|
19756U, // BCTRL
|
|
19756U, // BCTRL8
|
|
229393U, // BCTRL8_LDinto_toc
|
|
229393U, // BCTRL8_LDinto_toc_RM
|
|
19756U, // BCTRL8_RM
|
|
229407U, // BCTRL_LWZinto_toc
|
|
229407U, // BCTRL_LWZinto_toc_RM
|
|
19756U, // BCTRL_RM
|
|
1186489U, // BL
|
|
1186489U, // BL8
|
|
12720825U, // BL8_NOP
|
|
12720825U, // BL8_NOP_RM
|
|
12851897U, // BL8_NOP_TLS
|
|
1186489U, // BL8_NOTOC
|
|
1186489U, // BL8_NOTOC_RM
|
|
1317561U, // BL8_NOTOC_TLS
|
|
1186489U, // BL8_RM
|
|
1317561U, // BL8_TLS
|
|
1317561U, // BL8_TLS_
|
|
1215835U, // BLA
|
|
1215835U, // BLA8
|
|
12750171U, // BLA8_NOP
|
|
12750171U, // BLA8_NOP_RM
|
|
1215835U, // BLA8_RM
|
|
1215835U, // BLA_RM
|
|
19826U, // BLR
|
|
19826U, // BLR8
|
|
19751U, // BLRL
|
|
12720825U, // BL_NOP
|
|
12720825U, // BL_NOP_RM
|
|
1186489U, // BL_RM
|
|
1317561U, // BL_TLS
|
|
2147521146U, // BPERMD
|
|
37593U, // BRD
|
|
38480U, // BRH
|
|
38480U, // BRH8
|
|
2147520711U, // BRINC
|
|
46759U, // BRW
|
|
46759U, // BRW8
|
|
37733U, // CBCDTD
|
|
37733U, // CBCDTD8
|
|
37197U, // CDTBCD
|
|
37197U, // CDTBCD8
|
|
2147521005U, // CFUGED
|
|
19595U, // CLRBHRB
|
|
2147520202U, // CMPB
|
|
2147520202U, // CMPB8
|
|
2147521233U, // CMPD
|
|
2147522494U, // CMPDI
|
|
2147520208U, // CMPEQB
|
|
2147521117U, // CMPLD
|
|
2147522458U, // CMPLDI
|
|
2147530142U, // CMPLW
|
|
2147523005U, // CMPLWI
|
|
2348846808U, // CMPRB
|
|
2348846808U, // CMPRB8
|
|
2147530399U, // CMPW
|
|
2147523055U, // CMPWI
|
|
37897U, // CNTLZD
|
|
2147523696U, // CNTLZDM
|
|
33438U, // CNTLZD_rec
|
|
47146U, // CNTLZW
|
|
47146U, // CNTLZW8
|
|
35145U, // CNTLZW8_rec
|
|
35145U, // CNTLZW_rec
|
|
37912U, // CNTTZD
|
|
2147523713U, // CNTTZDM
|
|
33447U, // CNTTZD_rec
|
|
47161U, // CNTTZW
|
|
47161U, // CNTTZW8
|
|
35154U, // CNTTZW8_rec
|
|
35154U, // CNTTZW_rec
|
|
19835U, // CP_ABORT
|
|
48724U, // CP_COPY
|
|
48724U, // CP_COPY8
|
|
2147517181U, // CP_PASTE8_rec
|
|
2147517181U, // CP_PASTE_rec
|
|
17537U, // CR6SET
|
|
17523U, // CR6UNSET
|
|
2147521196U, // CRAND
|
|
2147520617U, // CRANDC
|
|
2147529586U, // CREQV
|
|
2147521180U, // CRNAND
|
|
2147527799U, // CRNOR
|
|
45499U, // CRNOT
|
|
2147527813U, // CROR
|
|
2147520732U, // CRORC
|
|
2382410610U, // CRSET
|
|
2382408874U, // CRUNSET
|
|
2147527850U, // CRXOR
|
|
3361937U, // CTRL_DEP
|
|
2147520863U, // DADD
|
|
2147527062U, // DADDQ
|
|
2147518077U, // DADDQ_rec
|
|
2147516919U, // DADD_rec
|
|
268476216U, // DARN
|
|
1117235U, // DCBA
|
|
13931733U, // DCBF
|
|
1123292U, // DCBFEP
|
|
1120083U, // DCBI
|
|
1126900U, // DCBST
|
|
1123325U, // DCBSTEP
|
|
14987527U, // DCBT
|
|
336885U, // DCBTEP
|
|
14987784U, // DCBTST
|
|
336902U, // DCBTSTEP
|
|
1130074U, // DCBZ
|
|
1123344U, // DCBZEP
|
|
1121223U, // DCBZL
|
|
1123308U, // DCBZLEP
|
|
38774U, // DCCCI
|
|
47633U, // DCFFIX
|
|
43892U, // DCFFIXQ
|
|
43638U, // DCFFIXQQ
|
|
34603U, // DCFFIXQ_rec
|
|
35217U, // DCFFIX_rec
|
|
2147524605U, // DCMPO
|
|
2147527263U, // DCMPOQ
|
|
2147529397U, // DCMPU
|
|
2147527466U, // DCMPUQ
|
|
41789U, // DCTDP
|
|
34283U, // DCTDP_rec
|
|
47641U, // DCTFIX
|
|
43901U, // DCTFIXQ
|
|
43648U, // DCTFIXQQ
|
|
34613U, // DCTFIXQ_rec
|
|
35226U, // DCTFIX_rec
|
|
43630U, // DCTQPQ
|
|
34517U, // DCTQPQ_rec
|
|
365249U, // DDEDPD
|
|
371109U, // DDEDPDQ
|
|
362126U, // DDEDPDQ_rec
|
|
361063U, // DDEDPD_rec
|
|
2147529536U, // DDIV
|
|
2147527510U, // DDIVQ
|
|
2147518227U, // DDIVQ_rec
|
|
2147518661U, // DDIV_rec
|
|
1446213U, // DENBCD
|
|
1452429U, // DENBCDQ
|
|
1443443U, // DENBCDQ_rec
|
|
1442275U, // DENBCD_rec
|
|
2147531124U, // DIEX
|
|
2147527517U, // DIEXQ
|
|
2147518235U, // DIEXQ_rec
|
|
2147518851U, // DIEX_rec
|
|
2147521532U, // DIVD
|
|
2147521591U, // DIVDE
|
|
2147524484U, // DIVDEO
|
|
2147517772U, // DIVDEO_rec
|
|
2147529349U, // DIVDEU
|
|
2147524730U, // DIVDEUO
|
|
2147517861U, // DIVDEUO_rec
|
|
2147518608U, // DIVDEU_rec
|
|
2147517111U, // DIVDE_rec
|
|
2147524470U, // DIVDO
|
|
2147517756U, // DIVDO_rec
|
|
2147529342U, // DIVDU
|
|
2147524722U, // DIVDUO
|
|
2147517852U, // DIVDUO_rec
|
|
2147518600U, // DIVDU_rec
|
|
2147517079U, // DIVD_rec
|
|
2147530769U, // DIVW
|
|
2147521718U, // DIVWE
|
|
2147524517U, // DIVWEO
|
|
2147517809U, // DIVWEO_rec
|
|
2147529357U, // DIVWEU
|
|
2147524739U, // DIVWEUO
|
|
2147517871U, // DIVWEUO_rec
|
|
2147518617U, // DIVWEU_rec
|
|
2147517189U, // DIVWE_rec
|
|
2147524764U, // DIVWO
|
|
2147517899U, // DIVWO_rec
|
|
2147529487U, // DIVWU
|
|
2147524748U, // DIVWUO
|
|
2147517881U, // DIVWUO_rec
|
|
2147518644U, // DIVWU_rec
|
|
2147518775U, // DIVW_rec
|
|
44099U, // DMMR
|
|
1097504U, // DMSETDMRZ
|
|
2147523461U, // DMUL
|
|
2147527238U, // DMULQ
|
|
2147518139U, // DMULQ_rec
|
|
2147517599U, // DMUL_rec
|
|
302034073U, // DMXOR
|
|
2382793525U, // DMXXEXTFDMR256
|
|
11995816U, // DMXXEXTFDMR512
|
|
16190120U, // DMXXEXTFDMR512_HI
|
|
2147519268U, // DMXXINSTFDMR256
|
|
2147519127U, // DMXXINSTFDMR512
|
|
2147519127U, // DMXXINSTFDMR512_HI
|
|
2147519858U, // DQUA
|
|
497484U, // DQUAI
|
|
502289U, // DQUAIQ
|
|
493208U, // DQUAIQ_rec
|
|
492411U, // DQUAI_rec
|
|
2147527021U, // DQUAQ
|
|
2147518051U, // DQUAQ_rec
|
|
2147516663U, // DQUA_rec
|
|
43623U, // DRDPQ
|
|
34509U, // DRDPQ_rec
|
|
335945553U, // DRINTN
|
|
335948374U, // DRINTNQ
|
|
335939267U, // DRINTNQ_rec
|
|
335938834U, // DRINTN_rec
|
|
335953137U, // DRINTX
|
|
335948678U, // DRINTXQ
|
|
335939391U, // DRINTXQ_rec
|
|
335940011U, // DRINTX_rec
|
|
2147521210U, // DRRND
|
|
2147527069U, // DRRNDQ
|
|
2147518085U, // DRRNDQ_rec
|
|
2147517023U, // DRRND_rec
|
|
43165U, // DRSP
|
|
34377U, // DRSP_rec
|
|
2147522605U, // DSCLI
|
|
2147527203U, // DSCLIQ
|
|
2147518113U, // DSCLIQ_rec
|
|
2147517419U, // DSCLI_rec
|
|
2147522843U, // DSCRI
|
|
2147527211U, // DSCRIQ
|
|
2147518122U, // DSCRIQ_rec
|
|
2147517456U, // DSCRI_rec
|
|
1585024U, // DSS
|
|
19744U, // DSSALL
|
|
2449912315U, // DST
|
|
2449912315U, // DST64
|
|
2449912336U, // DSTST
|
|
2449912336U, // DSTST64
|
|
2449912365U, // DSTSTT
|
|
2449912365U, // DSTSTT64
|
|
2449912350U, // DSTT
|
|
2449912350U, // DSTT64
|
|
2147520435U, // DSUB
|
|
2147527028U, // DSUBQ
|
|
2147518059U, // DSUBQ_rec
|
|
2147516721U, // DSUB_rec
|
|
2147520633U, // DTSTDC
|
|
2147527044U, // DTSTDCQ
|
|
2147521985U, // DTSTDG
|
|
2147527176U, // DTSTDGQ
|
|
2147531130U, // DTSTEX
|
|
2147527524U, // DTSTEXQ
|
|
2147521931U, // DTSTSF
|
|
369137658U, // DTSTSFI
|
|
369142297U, // DTSTSFIQ
|
|
2147527167U, // DTSTSFQ
|
|
47500U, // DXEX
|
|
43885U, // DXEXQ
|
|
34595U, // DXEXQ_rec
|
|
35210U, // DXEX_rec
|
|
18545U, // DYNALLOC
|
|
17992U, // DYNALLOC8
|
|
19300U, // DYNAREAOFFSET
|
|
18296U, // DYNAREAOFFSET8
|
|
19786U, // DecreaseCTR8loop
|
|
19804U, // DecreaseCTRloop
|
|
44313U, // EFDABS
|
|
2147520861U, // EFDADD
|
|
44695U, // EFDCFS
|
|
38181U, // EFDCFSF
|
|
39208U, // EFDCFSI
|
|
37417U, // EFDCFSID
|
|
38291U, // EFDCFUF
|
|
39285U, // EFDCFUI
|
|
37436U, // EFDCFUID
|
|
2147527086U, // EFDCMPEQ
|
|
2147528997U, // EFDCMPGT
|
|
2147529075U, // EFDCMPLT
|
|
38255U, // EFDCTSF
|
|
39236U, // EFDCTSI
|
|
48753U, // EFDCTSIDZ
|
|
48855U, // EFDCTSIZ
|
|
38319U, // EFDCTUF
|
|
39313U, // EFDCTUI
|
|
48774U, // EFDCTUIDZ
|
|
48886U, // EFDCTUIZ
|
|
2147529534U, // EFDDIV
|
|
2147523459U, // EFDMUL
|
|
44338U, // EFDNABS
|
|
38361U, // EFDNEG
|
|
2147520433U, // EFDSUB
|
|
2147527136U, // EFDTSTEQ
|
|
2147529038U, // EFDTSTGT
|
|
2147529116U, // EFDTSTLT
|
|
44375U, // EFSABS
|
|
2147520963U, // EFSADD
|
|
37365U, // EFSCFD
|
|
38190U, // EFSCFSF
|
|
39217U, // EFSCFSI
|
|
38300U, // EFSCFUF
|
|
39294U, // EFSCFUI
|
|
2147527106U, // EFSCMPEQ
|
|
2147529017U, // EFSCMPGT
|
|
2147529095U, // EFSCMPLT
|
|
38264U, // EFSCTSF
|
|
39245U, // EFSCTSI
|
|
48865U, // EFSCTSIZ
|
|
38328U, // EFSCTUF
|
|
39322U, // EFSCTUI
|
|
48896U, // EFSCTUIZ
|
|
2147529548U, // EFSDIV
|
|
2147523475U, // EFSMUL
|
|
44356U, // EFSNABS
|
|
38377U, // EFSNEG
|
|
2147520487U, // EFSSUB
|
|
2147527146U, // EFSTSTEQ
|
|
2147529048U, // EFSTSTGT
|
|
2147529126U, // EFSTSTLT
|
|
16746U, // EH_SjLj_LongJmp32
|
|
17231U, // EH_SjLj_LongJmp64
|
|
16765U, // EH_SjLj_SetJmp32
|
|
17250U, // EH_SjLj_SetJmp64
|
|
1179649U, // EH_SjLj_Setup
|
|
2147529581U, // EQV
|
|
2147529581U, // EQV8
|
|
2147518675U, // EQV8_rec
|
|
2147518675U, // EQV_rec
|
|
44392U, // EVABS
|
|
2181084522U, // EVADDIW
|
|
46043U, // EVADDSMIAAW
|
|
46175U, // EVADDSSIAAW
|
|
46109U, // EVADDUMIAAW
|
|
46241U, // EVADDUSIAAW
|
|
2147529992U, // EVADDW
|
|
2147521203U, // EVAND
|
|
2147520625U, // EVANDC
|
|
2147527127U, // EVCMPEQ
|
|
2147528599U, // EVCMPGTS
|
|
2147529424U, // EVCMPGTU
|
|
2147528609U, // EVCMPLTS
|
|
2147529434U, // EVCMPLTU
|
|
46841U, // EVCNTLSW
|
|
47144U, // EVCNTLZW
|
|
2147528779U, // EVDIVWS
|
|
2147529485U, // EVDIVWU
|
|
2147529593U, // EVEQV
|
|
36661U, // EVEXTSB
|
|
38563U, // EVEXTSH
|
|
44383U, // EVFSABS
|
|
2147520971U, // EVFSADD
|
|
38199U, // EVFSCFSF
|
|
39226U, // EVFSCFSI
|
|
38309U, // EVFSCFUF
|
|
39303U, // EVFSCFUI
|
|
2147527116U, // EVFSCMPEQ
|
|
2147529027U, // EVFSCMPGT
|
|
2147529105U, // EVFSCMPLT
|
|
38273U, // EVFSCTSF
|
|
39254U, // EVFSCTSI
|
|
48875U, // EVFSCTSIZ
|
|
38273U, // EVFSCTUF
|
|
39331U, // EVFSCTUI
|
|
48875U, // EVFSCTUIZ
|
|
2147529556U, // EVFSDIV
|
|
2147523483U, // EVFSMUL
|
|
44365U, // EVFSNABS
|
|
38385U, // EVFSNEG
|
|
2147520495U, // EVFSSUB
|
|
2147527156U, // EVFSTSTEQ
|
|
2147529058U, // EVFSTSTGT
|
|
2147529136U, // EVFSTSTLT
|
|
67146196U, // EVLDD
|
|
134265086U, // EVLDDX
|
|
67147281U, // EVLDH
|
|
134265234U, // EVLDHX
|
|
67155216U, // EVLDW
|
|
134266323U, // EVLDWX
|
|
67154105U, // EVLHHESPLAT
|
|
134266027U, // EVLHHESPLATX
|
|
67154130U, // EVLHHOSSPLAT
|
|
134266054U, // EVLHHOSSPLATX
|
|
67154144U, // EVLHHOUSPLAT
|
|
134266069U, // EVLHHOUSPLATX
|
|
67146837U, // EVLWHE
|
|
134265185U, // EVLWHEX
|
|
67153762U, // EVLWHOS
|
|
134265999U, // EVLWHOSX
|
|
67154604U, // EVLWHOU
|
|
134266211U, // EVLWHOUX
|
|
67154118U, // EVLWHSPLAT
|
|
134266041U, // EVLWHSPLATX
|
|
67154158U, // EVLWWSPLAT
|
|
134266084U, // EVLWWSPLATX
|
|
2147522574U, // EVMERGEHI
|
|
2147524575U, // EVMERGEHILO
|
|
2147524564U, // EVMERGELO
|
|
2147522585U, // EVMERGELOHI
|
|
2147519417U, // EVMHEGSMFAA
|
|
2147524081U, // EVMHEGSMFAN
|
|
2147519465U, // EVMHEGSMIAA
|
|
2147524129U, // EVMHEGSMIAN
|
|
2147519502U, // EVMHEGUMIAA
|
|
2147524166U, // EVMHEGUMIAN
|
|
2147521761U, // EVMHESMF
|
|
2147519550U, // EVMHESMFA
|
|
2147529639U, // EVMHESMFAAW
|
|
2147530183U, // EVMHESMFANW
|
|
2147522676U, // EVMHESMI
|
|
2147519642U, // EVMHESMIA
|
|
2147529704U, // EVMHESMIAAW
|
|
2147530235U, // EVMHESMIANW
|
|
2147521864U, // EVMHESSF
|
|
2147519593U, // EVMHESSFA
|
|
2147529665U, // EVMHESSFAAW
|
|
2147530209U, // EVMHESSFANW
|
|
2147529836U, // EVMHESSIAAW
|
|
2147530313U, // EVMHESSIANW
|
|
2147522715U, // EVMHEUMI
|
|
2147519685U, // EVMHEUMIA
|
|
2147529770U, // EVMHEUMIAAW
|
|
2147530274U, // EVMHEUMIANW
|
|
2147529902U, // EVMHEUSIAAW
|
|
2147530352U, // EVMHEUSIANW
|
|
2147519430U, // EVMHOGSMFAA
|
|
2147524094U, // EVMHOGSMFAN
|
|
2147519478U, // EVMHOGSMIAA
|
|
2147524142U, // EVMHOGSMIAN
|
|
2147519515U, // EVMHOGUMIAA
|
|
2147524179U, // EVMHOGUMIAN
|
|
2147521781U, // EVMHOSMF
|
|
2147519572U, // EVMHOSMFA
|
|
2147529652U, // EVMHOSMFAAW
|
|
2147530196U, // EVMHOSMFANW
|
|
2147522696U, // EVMHOSMI
|
|
2147519664U, // EVMHOSMIA
|
|
2147529744U, // EVMHOSMIAAW
|
|
2147530261U, // EVMHOSMIANW
|
|
2147521884U, // EVMHOSSF
|
|
2147519615U, // EVMHOSSFA
|
|
2147529678U, // EVMHOSSFAAW
|
|
2147530222U, // EVMHOSSFANW
|
|
2147529876U, // EVMHOSSIAAW
|
|
2147530339U, // EVMHOSSIANW
|
|
2147522745U, // EVMHOUMI
|
|
2147519718U, // EVMHOUMIA
|
|
2147529810U, // EVMHOUMIAAW
|
|
2147530300U, // EVMHOUMIANW
|
|
2147529942U, // EVMHOUSIAAW
|
|
2147530378U, // EVMHOUSIANW
|
|
36203U, // EVMRA
|
|
2147521771U, // EVMWHSMF
|
|
2147519561U, // EVMWHSMFA
|
|
2147522686U, // EVMWHSMI
|
|
2147519653U, // EVMWHSMIA
|
|
2147521874U, // EVMWHSSF
|
|
2147519604U, // EVMWHSSFA
|
|
2147522725U, // EVMWHUMI
|
|
2147519696U, // EVMWHUMIA
|
|
2147529731U, // EVMWLSMIAAW
|
|
2147530248U, // EVMWLSMIANW
|
|
2147529863U, // EVMWLSSIAAW
|
|
2147530326U, // EVMWLSSIANW
|
|
2147522735U, // EVMWLUMI
|
|
2147519707U, // EVMWLUMIA
|
|
2147529797U, // EVMWLUMIAAW
|
|
2147530287U, // EVMWLUMIANW
|
|
2147529929U, // EVMWLUSIAAW
|
|
2147530365U, // EVMWLUSIANW
|
|
2147521791U, // EVMWSMF
|
|
2147519583U, // EVMWSMFA
|
|
2147519443U, // EVMWSMFAA
|
|
2147524107U, // EVMWSMFAN
|
|
2147522706U, // EVMWSMI
|
|
2147519675U, // EVMWSMIA
|
|
2147519491U, // EVMWSMIAA
|
|
2147524155U, // EVMWSMIAN
|
|
2147521894U, // EVMWSSF
|
|
2147519626U, // EVMWSSFA
|
|
2147519454U, // EVMWSSFAA
|
|
2147524118U, // EVMWSSFAN
|
|
2147522755U, // EVMWUMI
|
|
2147519729U, // EVMWUMIA
|
|
2147519528U, // EVMWUMIAA
|
|
2147524192U, // EVMWUMIAN
|
|
2147521188U, // EVNAND
|
|
38394U, // EVNEG
|
|
2147527806U, // EVNOR
|
|
2147527819U, // EVOR
|
|
2147520739U, // EVORC
|
|
2147530149U, // EVRLW
|
|
2147523013U, // EVRLWI
|
|
46359U, // EVRNDW
|
|
2164309881U, // EVSEL
|
|
2147530156U, // EVSLW
|
|
2147523039U, // EVSLWI
|
|
402692099U, // EVSPLATFI
|
|
402692459U, // EVSPLATI
|
|
2147528510U, // EVSRWIS
|
|
2147529371U, // EVSRWIU
|
|
2147528707U, // EVSRWS
|
|
2147529471U, // EVSRWU
|
|
67146212U, // EVSTDD
|
|
134265094U, // EVSTDDX
|
|
67147288U, // EVSTDH
|
|
134265242U, // EVSTDHX
|
|
67155231U, // EVSTDW
|
|
134266331U, // EVSTDWX
|
|
67146845U, // EVSTWHE
|
|
134265194U, // EVSTWHEX
|
|
67149771U, // EVSTWHO
|
|
134265561U, // EVSTWHOX
|
|
67146941U, // EVSTWWE
|
|
134265218U, // EVSTWWEX
|
|
67149987U, // EVSTWWO
|
|
134265571U, // EVSTWWOX
|
|
46069U, // EVSUBFSMIAAW
|
|
46201U, // EVSUBFSSIAAW
|
|
46135U, // EVSUBFUMIAAW
|
|
46267U, // EVSUBFUSIAAW
|
|
2147530040U, // EVSUBFW
|
|
2583737665U, // EVSUBIFW
|
|
2147527857U, // EVXOR
|
|
36663U, // EXTSB
|
|
36663U, // EXTSB8
|
|
36663U, // EXTSB8_32_64
|
|
33043U, // EXTSB8_rec
|
|
33043U, // EXTSB_rec
|
|
38565U, // EXTSH
|
|
38565U, // EXTSH8
|
|
38565U, // EXTSH8_32_64
|
|
33618U, // EXTSH8_rec
|
|
33618U, // EXTSH_rec
|
|
46885U, // EXTSW
|
|
2147522624U, // EXTSWSLI
|
|
2147522624U, // EXTSWSLI_32_64
|
|
2147517427U, // EXTSWSLI_32_64_rec
|
|
2147517427U, // EXTSWSLI_rec
|
|
46885U, // EXTSW_32
|
|
46885U, // EXTSW_32_64
|
|
35097U, // EXTSW_32_64_rec
|
|
35097U, // EXTSW_rec
|
|
19767U, // EnforceIEIO
|
|
44323U, // FABSD
|
|
34719U, // FABSD_rec
|
|
44323U, // FABSS
|
|
34719U, // FABSS_rec
|
|
2147520871U, // FADD
|
|
2147528135U, // FADDS
|
|
2147518426U, // FADDS_rec
|
|
2147516926U, // FADD_rec
|
|
0U, // FADDrtz
|
|
37410U, // FCFID
|
|
44569U, // FCFIDS
|
|
34805U, // FCFIDS_rec
|
|
45665U, // FCFIDU
|
|
44981U, // FCFIDUS
|
|
34881U, // FCFIDUS_rec
|
|
34934U, // FCFIDU_rec
|
|
33331U, // FCFID_rec
|
|
2147524612U, // FCMPOD
|
|
2147524612U, // FCMPOS
|
|
2147529404U, // FCMPUD
|
|
2147529404U, // FCMPUS
|
|
2147524216U, // FCPSGND
|
|
2147517668U, // FCPSGND_rec
|
|
2147524216U, // FCPSGNS
|
|
2147517668U, // FCPSGNS_rec
|
|
37429U, // FCTID
|
|
45675U, // FCTIDU
|
|
48941U, // FCTIDUZ
|
|
35286U, // FCTIDUZ_rec
|
|
34943U, // FCTIDU_rec
|
|
48766U, // FCTIDZ
|
|
35252U, // FCTIDZ_rec
|
|
33339U, // FCTID_rec
|
|
46453U, // FCTIW
|
|
45815U, // FCTIWU
|
|
48952U, // FCTIWUZ
|
|
35296U, // FCTIWUZ_rec
|
|
34987U, // FCTIWU_rec
|
|
48963U, // FCTIWZ
|
|
35306U, // FCTIWZ_rec
|
|
35058U, // FCTIW_rec
|
|
2147529542U, // FDIV
|
|
2147528700U, // FDIVS
|
|
2147518548U, // FDIVS_rec
|
|
2147518668U, // FDIV_rec
|
|
18877U, // FENCE
|
|
2147520888U, // FMADD
|
|
2147528144U, // FMADDS
|
|
2147518434U, // FMADDS_rec
|
|
2147516943U, // FMADD_rec
|
|
44094U, // FMR
|
|
34678U, // FMR_rec
|
|
2147520460U, // FMSUB
|
|
2147528114U, // FMSUBS
|
|
2147518400U, // FMSUBS_rec
|
|
2147516745U, // FMSUB_rec
|
|
2147523469U, // FMUL
|
|
2147528529U, // FMULS
|
|
2147518504U, // FMULS_rec
|
|
2147517606U, // FMUL_rec
|
|
44349U, // FNABSD
|
|
34736U, // FNABSD_rec
|
|
44349U, // FNABSS
|
|
34736U, // FNABSS_rec
|
|
38371U, // FNEGD
|
|
33590U, // FNEGD_rec
|
|
38371U, // FNEGS
|
|
33590U, // FNEGS_rec
|
|
2147520907U, // FNMADD
|
|
2147528154U, // FNMADDS
|
|
2147518443U, // FNMADDS_rec
|
|
2147516962U, // FNMADD_rec
|
|
2147520479U, // FNMSUB
|
|
2147528124U, // FNMSUBS
|
|
2147518409U, // FNMSUBS_rec
|
|
2147516764U, // FNMSUB_rec
|
|
38028U, // FRE
|
|
44677U, // FRES
|
|
34823U, // FRES_rec
|
|
33505U, // FRE_rec
|
|
40203U, // FRIMD
|
|
33976U, // FRIMD_rec
|
|
40203U, // FRIMS
|
|
33976U, // FRIMS_rec
|
|
40585U, // FRIND
|
|
34050U, // FRIND_rec
|
|
40585U, // FRINS
|
|
34050U, // FRINS_rec
|
|
42191U, // FRIPD
|
|
34346U, // FRIPD_rec
|
|
42191U, // FRIPS
|
|
34346U, // FRIPS_rec
|
|
48849U, // FRIZD
|
|
35270U, // FRIZD_rec
|
|
48849U, // FRIZS
|
|
35270U, // FRIZS_rec
|
|
43173U, // FRSP
|
|
34384U, // FRSP_rec
|
|
38054U, // FRSQRTE
|
|
44685U, // FRSQRTES
|
|
34830U, // FRSQRTES_rec
|
|
33523U, // FRSQRTE_rec
|
|
2147523299U, // FSELD
|
|
2147517573U, // FSELD_rec
|
|
2147523299U, // FSELS
|
|
2147517573U, // FSELS_rec
|
|
45506U, // FSQRT
|
|
44971U, // FSQRTS
|
|
34864U, // FSQRTS_rec
|
|
34917U, // FSQRT_rec
|
|
2147520443U, // FSUB
|
|
2147528105U, // FSUBS
|
|
2147518392U, // FSUBS_rec
|
|
2147516728U, // FSUB_rec
|
|
2147529565U, // FTDIV
|
|
45513U, // FTSQRT
|
|
19228U, // GETtlsADDR
|
|
16834U, // GETtlsADDR32
|
|
19482U, // GETtlsADDR32AIX
|
|
19518U, // GETtlsADDR64AIX
|
|
18997U, // GETtlsADDRPCREL
|
|
19498U, // GETtlsTpointer32AIX
|
|
19214U, // GETtlsldADDR
|
|
16819U, // GETtlsldADDR32
|
|
18978U, // GETtlsldADDRPCREL
|
|
469801608U, // HASHCHK
|
|
469801608U, // HASHCHK8
|
|
469804245U, // HASHCHKP
|
|
469804245U, // HASHCHKP8
|
|
469807616U, // HASHST
|
|
469807616U, // HASHST8
|
|
469805371U, // HASHSTP
|
|
469805371U, // HASHSTP8
|
|
19666U, // HRFID
|
|
1120089U, // ICBI
|
|
1123300U, // ICBIEP
|
|
561344U, // ICBLC
|
|
558771U, // ICBLQ
|
|
569613U, // ICBT
|
|
569159U, // ICBTLS
|
|
38781U, // ICCCI
|
|
2147523305U, // ISEL
|
|
2147523305U, // ISEL8
|
|
19630U, // ISYNC
|
|
503352668U, // LA
|
|
503352668U, // LA8
|
|
134265700U, // LBARX
|
|
134265700U, // LBARXL
|
|
134265581U, // LBEPX
|
|
67157601U, // LBZ
|
|
67157601U, // LBZ8
|
|
2147531257U, // LBZCIX
|
|
536916758U, // LBZU
|
|
536916758U, // LBZU8
|
|
570473894U, // LBZUX
|
|
570473894U, // LBZUX8
|
|
134266406U, // LBZX
|
|
134266406U, // LBZX8
|
|
2147532326U, // LBZXTLS
|
|
2147532326U, // LBZXTLS_
|
|
2147532326U, // LBZXTLS_32
|
|
67146313U, // LD
|
|
134265707U, // LDARX
|
|
134265707U, // LDARXL
|
|
2147528876U, // LDAT
|
|
134265735U, // LDBRX
|
|
2147531226U, // LDCIX
|
|
536916595U, // LDU
|
|
570473791U, // LDUX
|
|
134265125U, // LDX
|
|
2147531045U, // LDXTLS
|
|
2147531045U, // LDXTLS_
|
|
19065U, // LDgotTprelL
|
|
16716U, // LDgotTprelL32
|
|
19642U, // LDtoc
|
|
19404U, // LDtocBA
|
|
19404U, // LDtocCPT
|
|
18958U, // LDtocJTI
|
|
19014U, // LDtocL
|
|
67146238U, // LFD
|
|
134265596U, // LFDEPX
|
|
536916545U, // LFDU
|
|
570473774U, // LFDUX
|
|
134265105U, // LFDX
|
|
2147531025U, // LFDXTLS
|
|
2147531025U, // LFDXTLS_
|
|
134264984U, // LFIWAX
|
|
134266429U, // LFIWZX
|
|
67153574U, // LFS
|
|
536916675U, // LFSU
|
|
570473860U, // LFSUX
|
|
134265974U, // LFSX
|
|
2147531894U, // LFSXTLS
|
|
2147531894U, // LFSXTLS_
|
|
67144853U, // LHA
|
|
67144853U, // LHA8
|
|
134265714U, // LHARX
|
|
134265714U, // LHARXL
|
|
536916533U, // LHAU
|
|
536916533U, // LHAU8
|
|
570473730U, // LHAUX
|
|
570473730U, // LHAUX8
|
|
134264967U, // LHAX
|
|
134264967U, // LHAX8
|
|
2147530887U, // LHAXTLS
|
|
2147530887U, // LHAXTLS_
|
|
2147530887U, // LHAXTLS_32
|
|
134265750U, // LHBRX
|
|
134265750U, // LHBRX8
|
|
134265613U, // LHEPX
|
|
67157672U, // LHZ
|
|
67157672U, // LHZ8
|
|
2147531265U, // LHZCIX
|
|
536916764U, // LHZU
|
|
536916764U, // LHZU8
|
|
570473901U, // LHZUX
|
|
570473901U, // LHZUX8
|
|
134266421U, // LHZX
|
|
134266421U, // LHZX8
|
|
2147532341U, // LHZXTLS
|
|
2147532341U, // LHZXTLS_
|
|
2147532341U, // LHZXTLS_32
|
|
67155379U, // LMW
|
|
67152444U, // LQ
|
|
134265721U, // LQARX
|
|
134265721U, // LQARXL
|
|
19099U, // LQX_PSEUDO
|
|
2147523094U, // LSWI
|
|
134265007U, // LVEBX
|
|
134265251U, // LVEHX
|
|
134266340U, // LVEWX
|
|
134257525U, // LVSL
|
|
134261984U, // LVSR
|
|
134266299U, // LVX
|
|
134257594U, // LVXL
|
|
67145081U, // LWA
|
|
134265728U, // LWARX
|
|
134265728U, // LWARXL
|
|
2147528954U, // LWAT
|
|
570473737U, // LWAUX
|
|
134265001U, // LWAX
|
|
2147530921U, // LWAXTLS
|
|
2147530921U, // LWAXTLS_
|
|
2147530921U, // LWAXTLS_32
|
|
134265001U, // LWAX_32
|
|
67145081U, // LWA_32
|
|
134265784U, // LWBRX
|
|
134265784U, // LWBRX8
|
|
134265628U, // LWEPX
|
|
67157836U, // LWZ
|
|
67157836U, // LWZ8
|
|
2147531273U, // LWZCIX
|
|
536916770U, // LWZU
|
|
536916770U, // LWZU8
|
|
570473908U, // LWZUX
|
|
570473908U, // LWZUX8
|
|
134266446U, // LWZX
|
|
134266446U, // LWZX8
|
|
2147532366U, // LWZXTLS
|
|
2147532366U, // LWZXTLS_
|
|
2147532366U, // LWZXTLS_32
|
|
19658U, // LWZtoc
|
|
19032U, // LWZtocL
|
|
67146572U, // LXSD
|
|
134265157U, // LXSDX
|
|
134266397U, // LXSIBZX
|
|
134266412U, // LXSIHZX
|
|
134264992U, // LXSIWAX
|
|
134266437U, // LXSIWZX
|
|
67152070U, // LXSSP
|
|
134265668U, // LXSSPX
|
|
67154823U, // LXV
|
|
134264931U, // LXVB16X
|
|
134264897U, // LXVD2X
|
|
134265957U, // LXVDSX
|
|
134264950U, // LXVH8X
|
|
436251187U, // LXVKQ
|
|
2147523501U, // LXVL
|
|
2147523376U, // LXVLL
|
|
67152197U, // LXVP
|
|
2147523398U, // LXVPRL
|
|
2147523340U, // LXVPRLL
|
|
134265685U, // LXVPX
|
|
134265031U, // LXVRBX
|
|
134265140U, // LXVRDX
|
|
134265275U, // LXVRHX
|
|
2147523423U, // LXVRL
|
|
2147523359U, // LXVRLL
|
|
134266374U, // LXVRWX
|
|
134264914U, // LXVW4X
|
|
134266019U, // LXVWSX
|
|
134266310U, // LXVX
|
|
2147521041U, // MADDHD
|
|
2147529294U, // MADDHDU
|
|
2147521101U, // MADDLD
|
|
2147521101U, // MADDLD8
|
|
1584028U, // MBAR
|
|
38152U, // MCRF
|
|
44715U, // MCRFS
|
|
1096771U, // MCRXRX
|
|
604017696U, // MFBHRBE
|
|
1092561U, // MFCR
|
|
1092561U, // MFCR8
|
|
1092845U, // MFCTR
|
|
1092845U, // MFCTR8
|
|
43964U, // MFDCR
|
|
1093279U, // MFFS
|
|
40775U, // MFFSCDRN
|
|
637573352U, // MFFSCDRNI
|
|
1086505U, // MFFSCE
|
|
40766U, // MFFSCRN
|
|
268474590U, // MFFSCRNI
|
|
1088366U, // MFFSL
|
|
1083417U, // MFFS_rec
|
|
1092649U, // MFLR
|
|
1092649U, // MFLR8
|
|
1092812U, // MFMSR
|
|
671126798U, // MFOCRF
|
|
671126798U, // MFOCRF8
|
|
44105U, // MFPMR
|
|
44216U, // MFSPR
|
|
44216U, // MFSPR8
|
|
704687302U, // MFSR
|
|
40591U, // MFSRIN
|
|
36684U, // MFTB
|
|
17870008U, // MFTB8
|
|
18918584U, // MFUDSCR
|
|
37606U, // MFVRD
|
|
19967160U, // MFVRSAVE
|
|
19967160U, // MFVRSAVEv
|
|
48977U, // MFVRWZ
|
|
1092575U, // MFVSCR
|
|
37606U, // MFVSRD
|
|
37476U, // MFVSRLD
|
|
48977U, // MFVSRWZ
|
|
2147521271U, // MODSD
|
|
2147530419U, // MODSW
|
|
2147521434U, // MODUD
|
|
2147530629U, // MODUW
|
|
19622U, // MSGSYNC
|
|
19636U, // MSYNC
|
|
38174U, // MTCRF
|
|
38174U, // MTCRF8
|
|
1092852U, // MTCTR
|
|
1092852U, // MTCTR8
|
|
1092852U, // MTCTR8loop
|
|
1092852U, // MTCTRloop
|
|
235318218U, // MTDCR
|
|
1575435U, // MTFSB0
|
|
1575517U, // MTFSB1
|
|
2147521857U, // MTFSF
|
|
2907248626U, // MTFSFI
|
|
759759842U, // MTFSFI_rec
|
|
793319410U, // MTFSFIb
|
|
2147517221U, // MTFSF_rec
|
|
38209U, // MTFSFb
|
|
1092655U, // MTLR
|
|
1092655U, // MTLR8
|
|
201370835U, // MTMSR
|
|
201364190U, // MTMSRD
|
|
627990U, // MTOCRF
|
|
627990U, // MTOCRF8
|
|
44112U, // MTPMR
|
|
44223U, // MTSPR
|
|
44223U, // MTSPR8
|
|
666842U, // MTSR
|
|
40599U, // MTSRIN
|
|
1081451U, // MTUDSCR
|
|
37614U, // MTVRD
|
|
1081461U, // MTVRSAVE
|
|
1474677U, // MTVRSAVEv
|
|
36222U, // MTVRWA
|
|
48986U, // MTVRWZ
|
|
1092583U, // MTVSCR
|
|
39907U, // MTVSRBM
|
|
805345354U, // MTVSRBMI
|
|
37614U, // MTVSRD
|
|
2147520987U, // MTVSRDD
|
|
39979U, // MTVSRDM
|
|
40085U, // MTVSRHM
|
|
40252U, // MTVSRQM
|
|
36222U, // MTVSRWA
|
|
40373U, // MTVSRWM
|
|
45067U, // MTVSRWS
|
|
48986U, // MTVSRWZ
|
|
2147521049U, // MULHD
|
|
2147529303U, // MULHDU
|
|
2147518573U, // MULHDU_rec
|
|
2147516971U, // MULHD_rec
|
|
2147530083U, // MULHW
|
|
2147529453U, // MULHWU
|
|
2147518626U, // MULHWU_rec
|
|
2147518698U, // MULHW_rec
|
|
2147521110U, // MULLD
|
|
2147524462U, // MULLDO
|
|
2147517747U, // MULLDO_rec
|
|
2147516995U, // MULLD_rec
|
|
2147522612U, // MULLI
|
|
2147522612U, // MULLI8
|
|
2147530135U, // MULLW
|
|
2147524756U, // MULLWO
|
|
2147517890U, // MULLWO_rec
|
|
2147518714U, // MULLW_rec
|
|
19263U, // MoveGOTtoLR
|
|
19251U, // MovePCtoLR
|
|
18283U, // MovePCtoLR8
|
|
2147521174U, // NAND
|
|
2147521174U, // NAND8
|
|
2147517009U, // NAND8_rec
|
|
2147517009U, // NAND_rec
|
|
19773U, // NAP
|
|
38356U, // NEG
|
|
38356U, // NEG8
|
|
40901U, // NEG8O
|
|
34197U, // NEG8O_rec
|
|
33584U, // NEG8_rec
|
|
40901U, // NEGO
|
|
34197U, // NEGO_rec
|
|
33584U, // NEG_rec
|
|
19782U, // NOP
|
|
16418U, // NOP_GT_PWR6
|
|
16430U, // NOP_GT_PWR7
|
|
2147527794U, // NOR
|
|
2147527794U, // NOR8
|
|
2147518332U, // NOR8_rec
|
|
2147518332U, // NOR_rec
|
|
2147527787U, // OR
|
|
2147527787U, // OR8
|
|
2147518333U, // OR8_rec
|
|
2147520727U, // ORC
|
|
2147520727U, // ORC8
|
|
2147516875U, // ORC8_rec
|
|
2147516875U, // ORC_rec
|
|
2147522851U, // ORI
|
|
2147522851U, // ORI8
|
|
2147528504U, // ORIS
|
|
2147528504U, // ORIS8
|
|
2147518333U, // OR_rec
|
|
2147522451U, // PADDI
|
|
2147522451U, // PADDI8
|
|
838899603U, // PADDI8pc
|
|
19717U, // PADDIdtprel
|
|
838899603U, // PADDIpc
|
|
2147521226U, // PDEPD
|
|
2147521416U, // PEXTD
|
|
872451430U, // PLA
|
|
872451430U, // PLA8
|
|
906005862U, // PLA8pc
|
|
906005862U, // PLApc
|
|
3087056480U, // PLBZ
|
|
3087056480U, // PLBZ8
|
|
939572832U, // PLBZ8nopc
|
|
906018400U, // PLBZ8onlypc
|
|
973127264U, // PLBZ8pc
|
|
939572832U, // PLBZnopc
|
|
906018400U, // PLBZonlypc
|
|
973127264U, // PLBZpc
|
|
3087045215U, // PLD
|
|
939561567U, // PLDnopc
|
|
906007135U, // PLDonlypc
|
|
973115999U, // PLDpc
|
|
3087045117U, // PLFD
|
|
939561469U, // PLFDnopc
|
|
906007037U, // PLFDonlypc
|
|
973115901U, // PLFDpc
|
|
3087052453U, // PLFS
|
|
939568805U, // PLFSnopc
|
|
906014373U, // PLFSonlypc
|
|
973123237U, // PLFSpc
|
|
3087043732U, // PLHA
|
|
3087043732U, // PLHA8
|
|
939560084U, // PLHA8nopc
|
|
906005652U, // PLHA8onlypc
|
|
973114516U, // PLHA8pc
|
|
939560084U, // PLHAnopc
|
|
906005652U, // PLHAonlypc
|
|
973114516U, // PLHApc
|
|
3087056551U, // PLHZ
|
|
3087056551U, // PLHZ8
|
|
939572903U, // PLHZ8nopc
|
|
906018471U, // PLHZ8onlypc
|
|
973127335U, // PLHZ8pc
|
|
939572903U, // PLHZnopc
|
|
906018471U, // PLHZonlypc
|
|
973127335U, // PLHZpc
|
|
906008635U, // PLI
|
|
906008635U, // PLI8
|
|
3087043960U, // PLWA
|
|
3087043960U, // PLWA8
|
|
939560312U, // PLWA8nopc
|
|
906005880U, // PLWA8onlypc
|
|
973114744U, // PLWA8pc
|
|
939560312U, // PLWAnopc
|
|
906005880U, // PLWAonlypc
|
|
973114744U, // PLWApc
|
|
3087056715U, // PLWZ
|
|
3087056715U, // PLWZ8
|
|
939573067U, // PLWZ8nopc
|
|
906018635U, // PLWZ8onlypc
|
|
973127499U, // PLWZ8pc
|
|
939573067U, // PLWZnopc
|
|
906018635U, // PLWZonlypc
|
|
973127499U, // PLWZpc
|
|
3087045451U, // PLXSD
|
|
939561803U, // PLXSDnopc
|
|
906007371U, // PLXSDonlypc
|
|
973116235U, // PLXSDpc
|
|
3087050949U, // PLXSSP
|
|
939567301U, // PLXSSPnopc
|
|
906012869U, // PLXSSPonlypc
|
|
973121733U, // PLXSSPpc
|
|
3087053702U, // PLXV
|
|
3087051076U, // PLXVP
|
|
939567428U, // PLXVPnopc
|
|
906012996U, // PLXVPonlypc
|
|
973121860U, // PLXVPpc
|
|
939570054U, // PLXVnopc
|
|
906015622U, // PLXVonlypc
|
|
973124486U, // PLXVpc
|
|
2147519182U, // PMXVBF16GER2
|
|
2449514143U, // PMXVBF16GER2NN
|
|
2449515751U, // PMXVBF16GER2NP
|
|
2449514202U, // PMXVBF16GER2PN
|
|
2449515810U, // PMXVBF16GER2PP
|
|
2147519182U, // PMXVBF16GER2W
|
|
2449514143U, // PMXVBF16GER2WNN
|
|
2449515751U, // PMXVBF16GER2WNP
|
|
2449514202U, // PMXVBF16GER2WPN
|
|
2449515810U, // PMXVBF16GER2WPP
|
|
2147519196U, // PMXVF16GER2
|
|
2449514159U, // PMXVF16GER2NN
|
|
2449515767U, // PMXVF16GER2NP
|
|
2449514218U, // PMXVF16GER2PN
|
|
2449515826U, // PMXVF16GER2PP
|
|
2147519196U, // PMXVF16GER2W
|
|
2449514159U, // PMXVF16GER2WNN
|
|
2449515767U, // PMXVF16GER2WNP
|
|
2449514218U, // PMXVF16GER2WPN
|
|
2449515826U, // PMXVF16GER2WPP
|
|
2147527663U, // PMXVF32GER
|
|
2449514174U, // PMXVF32GERNN
|
|
2449515782U, // PMXVF32GERNP
|
|
2449514244U, // PMXVF32GERPN
|
|
2449515884U, // PMXVF32GERPP
|
|
2147527663U, // PMXVF32GERW
|
|
2449514174U, // PMXVF32GERWNN
|
|
2449515782U, // PMXVF32GERWNP
|
|
2449514244U, // PMXVF32GERWPN
|
|
2449515884U, // PMXVF32GERWPP
|
|
2147527675U, // PMXVF64GER
|
|
2449514188U, // PMXVF64GERNN
|
|
2449515796U, // PMXVF64GERNP
|
|
2449514258U, // PMXVF64GERPN
|
|
2449515898U, // PMXVF64GERPP
|
|
2147527675U, // PMXVF64GERW
|
|
2449514188U, // PMXVF64GERWNN
|
|
2449515796U, // PMXVF64GERWNP
|
|
2449514258U, // PMXVF64GERWPN
|
|
2449515898U, // PMXVF64GERWPP
|
|
2147519209U, // PMXVI16GER2
|
|
2449515841U, // PMXVI16GER2PP
|
|
2147527931U, // PMXVI16GER2S
|
|
2449515912U, // PMXVI16GER2SPP
|
|
2147527931U, // PMXVI16GER2SW
|
|
2449515912U, // PMXVI16GER2SWPP
|
|
2147519209U, // PMXVI16GER2W
|
|
2449515841U, // PMXVI16GER2WPP
|
|
2147519343U, // PMXVI4GER8
|
|
2449515870U, // PMXVI4GER8PP
|
|
2147519343U, // PMXVI4GER8W
|
|
2449515870U, // PMXVI4GER8WPP
|
|
2147519222U, // PMXVI8GER4
|
|
2449515856U, // PMXVI8GER4PP
|
|
2449515928U, // PMXVI8GER4SPP
|
|
2147519222U, // PMXVI8GER4W
|
|
2449515856U, // PMXVI8GER4WPP
|
|
2449515928U, // PMXVI8GER4WSPP
|
|
36699U, // POPCNTB
|
|
36699U, // POPCNTB8
|
|
37742U, // POPCNTD
|
|
46926U, // POPCNTW
|
|
19381U, // PPC32GOT
|
|
19391U, // PPC32PICGOT
|
|
16865U, // PREPARE_PROBED_ALLOCA_32
|
|
17286U, // PREPARE_PROBED_ALLOCA_64
|
|
16913U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32
|
|
17334U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
|
|
16847U, // PROBED_ALLOCA_32
|
|
17268U, // PROBED_ALLOCA_64
|
|
16891U, // PROBED_STACKALLOC_32
|
|
17312U, // PROBED_STACKALLOC_64
|
|
39576U, // PSC_DCBZL
|
|
1006672529U, // PSQ_L
|
|
1006678692U, // PSQ_LU
|
|
2147532122U, // PSQ_LUX
|
|
2147531306U, // PSQ_LX
|
|
1006678481U, // PSQ_ST
|
|
1006678756U, // PSQ_STU
|
|
2147532181U, // PSQ_STUX
|
|
2147532025U, // PSQ_STX
|
|
3087044462U, // PSTB
|
|
3087044462U, // PSTB8
|
|
939560814U, // PSTB8nopc
|
|
906006382U, // PSTB8onlypc
|
|
973115246U, // PSTB8pc
|
|
939560814U, // PSTBnopc
|
|
906006382U, // PSTBonlypc
|
|
973115246U, // PSTBpc
|
|
3087045505U, // PSTD
|
|
939561857U, // PSTDnopc
|
|
906007425U, // PSTDonlypc
|
|
973116289U, // PSTDpc
|
|
3087045123U, // PSTFD
|
|
939561475U, // PSTFDnopc
|
|
906007043U, // PSTFDonlypc
|
|
973115907U, // PSTFDpc
|
|
3087052466U, // PSTFS
|
|
939568818U, // PSTFSnopc
|
|
906014386U, // PSTFSonlypc
|
|
973123250U, // PSTFSpc
|
|
3087046352U, // PSTH
|
|
3087046352U, // PSTH8
|
|
939562704U, // PSTH8nopc
|
|
906008272U, // PSTH8onlypc
|
|
973117136U, // PSTH8pc
|
|
939562704U, // PSTHnopc
|
|
906008272U, // PSTHonlypc
|
|
973117136U, // PSTHpc
|
|
3087054700U, // PSTW
|
|
3087054700U, // PSTW8
|
|
939571052U, // PSTW8nopc
|
|
906016620U, // PSTW8onlypc
|
|
973125484U, // PSTW8pc
|
|
939571052U, // PSTWnopc
|
|
906016620U, // PSTWonlypc
|
|
973125484U, // PSTWpc
|
|
3087045458U, // PSTXSD
|
|
939561810U, // PSTXSDnopc
|
|
906007378U, // PSTXSDonlypc
|
|
973116242U, // PSTXSDpc
|
|
3087050957U, // PSTXSSP
|
|
939567309U, // PSTXSSPnopc
|
|
906012877U, // PSTXSSPonlypc
|
|
973121741U, // PSTXSSPpc
|
|
3087053708U, // PSTXV
|
|
3087051083U, // PSTXVP
|
|
939567435U, // PSTXVPnopc
|
|
906013003U, // PSTXVPonlypc
|
|
973121867U, // PSTXVPpc
|
|
939570060U, // PSTXVnopc
|
|
906015628U, // PSTXVonlypc
|
|
973124492U, // PSTXVpc
|
|
44305U, // PS_ABS
|
|
34710U, // PS_ABSo
|
|
2147520853U, // PS_ADD
|
|
2147516908U, // PS_ADDo
|
|
2147519004U, // PS_CMPO0
|
|
2147519086U, // PS_CMPO1
|
|
2147519035U, // PS_CMPU0
|
|
2147519117U, // PS_CMPU1
|
|
2147529526U, // PS_DIV
|
|
2147518652U, // PS_DIVo
|
|
2147520877U, // PS_MADD
|
|
2147519014U, // PS_MADDS0
|
|
2147516581U, // PS_MADDS0o
|
|
2147519096U, // PS_MADDS1
|
|
2147516640U, // PS_MADDS1o
|
|
2147516933U, // PS_MADDo
|
|
2147518963U, // PS_MERGE00
|
|
2147516545U, // PS_MERGE00o
|
|
2147519045U, // PS_MERGE01
|
|
2147516604U, // PS_MERGE01o
|
|
2147518975U, // PS_MERGE10
|
|
2147516558U, // PS_MERGE10o
|
|
2147519057U, // PS_MERGE11
|
|
2147516617U, // PS_MERGE11o
|
|
44085U, // PS_MR
|
|
34670U, // PS_MRo
|
|
2147520449U, // PS_MSUB
|
|
2147516735U, // PS_MSUBo
|
|
2147523451U, // PS_MUL
|
|
2147519025U, // PS_MULS0
|
|
2147516593U, // PS_MULS0o
|
|
2147519107U, // PS_MULS1
|
|
2147516652U, // PS_MULS1o
|
|
2147517590U, // PS_MULo
|
|
44329U, // PS_NABS
|
|
34726U, // PS_NABSo
|
|
38353U, // PS_NEG
|
|
33581U, // PS_NEGo
|
|
2147520895U, // PS_NMADD
|
|
2147516951U, // PS_NMADDo
|
|
2147520467U, // PS_NMSUB
|
|
2147516753U, // PS_NMSUBo
|
|
44667U, // PS_RES
|
|
34814U, // PS_RESo
|
|
38041U, // PS_RSQRTE
|
|
33511U, // PS_RSQRTEo
|
|
2147523289U, // PS_SEL
|
|
2147517564U, // PS_SELo
|
|
2147520425U, // PS_SUB
|
|
2147516710U, // PS_SUBo
|
|
2147518995U, // PS_SUM0
|
|
2147516571U, // PS_SUM0o
|
|
2147519077U, // PS_SUM1
|
|
2147516630U, // PS_SUM1o
|
|
19124U, // PseudoEIEIO
|
|
2147522772U, // QVALIGNI
|
|
2147522772U, // QVALIGNIb
|
|
2147522772U, // QVALIGNIs
|
|
2147522912U, // QVESPLATI
|
|
2147522912U, // QVESPLATIb
|
|
2147522912U, // QVESPLATIs
|
|
44321U, // QVFABS
|
|
44321U, // QVFABSs
|
|
2147520869U, // QVFADD
|
|
2147528133U, // QVFADDS
|
|
2147528133U, // QVFADDSs
|
|
37408U, // QVFCFID
|
|
44567U, // QVFCFIDS
|
|
45663U, // QVFCFIDU
|
|
44979U, // QVFCFIDUS
|
|
37408U, // QVFCFIDb
|
|
2147527096U, // QVFCMPEQ
|
|
2147527096U, // QVFCMPEQb
|
|
2147527096U, // QVFCMPEQbs
|
|
2147529007U, // QVFCMPGT
|
|
2147529007U, // QVFCMPGTb
|
|
2147529007U, // QVFCMPGTbs
|
|
2147529085U, // QVFCMPLT
|
|
2147529085U, // QVFCMPLTb
|
|
2147529085U, // QVFCMPLTbs
|
|
2147524214U, // QVFCPSGN
|
|
2147524214U, // QVFCPSGNs
|
|
37427U, // QVFCTID
|
|
45673U, // QVFCTIDU
|
|
48939U, // QVFCTIDUZ
|
|
48764U, // QVFCTIDZ
|
|
37427U, // QVFCTIDb
|
|
46451U, // QVFCTIW
|
|
45813U, // QVFCTIWU
|
|
48950U, // QVFCTIWUZ
|
|
48961U, // QVFCTIWZ
|
|
2147523232U, // QVFLOGICAL
|
|
2147523232U, // QVFLOGICALb
|
|
2147523232U, // QVFLOGICALs
|
|
2147520886U, // QVFMADD
|
|
2147528142U, // QVFMADDS
|
|
2147528142U, // QVFMADDSs
|
|
44092U, // QVFMR
|
|
44092U, // QVFMRb
|
|
44092U, // QVFMRs
|
|
2147520458U, // QVFMSUB
|
|
2147528112U, // QVFMSUBS
|
|
2147528112U, // QVFMSUBSs
|
|
2147523467U, // QVFMUL
|
|
2147528527U, // QVFMULS
|
|
2147528527U, // QVFMULSs
|
|
44347U, // QVFNABS
|
|
44347U, // QVFNABSs
|
|
38369U, // QVFNEG
|
|
38369U, // QVFNEGs
|
|
2147520905U, // QVFNMADD
|
|
2147528152U, // QVFNMADDS
|
|
2147528152U, // QVFNMADDSs
|
|
2147520477U, // QVFNMSUB
|
|
2147528122U, // QVFNMSUBS
|
|
2147528122U, // QVFNMSUBSs
|
|
2147523959U, // QVFPERM
|
|
2147523959U, // QVFPERMs
|
|
38026U, // QVFRE
|
|
44675U, // QVFRES
|
|
44675U, // QVFRESs
|
|
40201U, // QVFRIM
|
|
40201U, // QVFRIMs
|
|
40583U, // QVFRIN
|
|
40583U, // QVFRINs
|
|
42189U, // QVFRIP
|
|
42189U, // QVFRIPs
|
|
48847U, // QVFRIZ
|
|
48847U, // QVFRIZs
|
|
43171U, // QVFRSP
|
|
43171U, // QVFRSPs
|
|
38052U, // QVFRSQRTE
|
|
44683U, // QVFRSQRTES
|
|
44683U, // QVFRSQRTESs
|
|
2147523297U, // QVFSEL
|
|
2147523297U, // QVFSELb
|
|
2147523297U, // QVFSELbb
|
|
2147523297U, // QVFSELbs
|
|
2147520441U, // QVFSUB
|
|
2147528103U, // QVFSUBS
|
|
2147528103U, // QVFSUBSs
|
|
2147524203U, // QVFTSTNAN
|
|
2147524203U, // QVFTSTNANb
|
|
2147524203U, // QVFTSTNANbs
|
|
2147520942U, // QVFXMADD
|
|
2147528192U, // QVFXMADDS
|
|
2147523492U, // QVFXMUL
|
|
2147528536U, // QVFXMULS
|
|
2147520915U, // QVFXXCPNMADD
|
|
2147528163U, // QVFXXCPNMADDS
|
|
2147520952U, // QVFXXMADD
|
|
2147528203U, // QVFXXMADDS
|
|
2147520929U, // QVFXXNPMADD
|
|
2147528178U, // QVFXXNPMADDS
|
|
1040226180U, // QVGPCI
|
|
134266135U, // QVLFCDUX
|
|
134254050U, // QVLFCDUXA
|
|
134265067U, // QVLFCDX
|
|
134253970U, // QVLFCDXA
|
|
134266221U, // QVLFCSUX
|
|
134254094U, // QVLFCSUXA
|
|
134265938U, // QVLFCSX
|
|
134254010U, // QVLFCSXA
|
|
134265938U, // QVLFCSXs
|
|
570473772U, // QVLFDUX
|
|
134254073U, // QVLFDUXA
|
|
134265103U, // QVLFDX
|
|
134253991U, // QVLFDXA
|
|
134265103U, // QVLFDXb
|
|
134264982U, // QVLFIWAX
|
|
134253959U, // QVLFIWAXA
|
|
134266427U, // QVLFIWZX
|
|
134254149U, // QVLFIWZXA
|
|
570473858U, // QVLFSUX
|
|
134254117U, // QVLFSUXA
|
|
134265972U, // QVLFSX
|
|
134254031U, // QVLFSXA
|
|
134265972U, // QVLFSXb
|
|
134265972U, // QVLFSXs
|
|
134265120U, // QVLPCLDX
|
|
134265989U, // QVLPCLSX
|
|
22068357U, // QVLPCLSXint
|
|
134265130U, // QVLPCRDX
|
|
134266009U, // QVLPCRSX
|
|
134266145U, // QVSTFCDUX
|
|
134254061U, // QVSTFCDUXA
|
|
134257234U, // QVSTFCDUXI
|
|
134253865U, // QVSTFCDUXIA
|
|
134265076U, // QVSTFCDX
|
|
134253980U, // QVSTFCDXA
|
|
134257192U, // QVSTFCDXI
|
|
134253819U, // QVSTFCDXIA
|
|
134266231U, // QVSTFCSUX
|
|
134254105U, // QVSTFCSUXA
|
|
134257257U, // QVSTFCSUXI
|
|
134253890U, // QVSTFCSUXIA
|
|
134265947U, // QVSTFCSX
|
|
134254020U, // QVSTFCSXA
|
|
134257213U, // QVSTFCSXI
|
|
134253842U, // QVSTFCSXIA
|
|
134265947U, // QVSTFCSXs
|
|
570866997U, // QVSTFDUX
|
|
134254083U, // QVSTFDUXA
|
|
134257246U, // QVSTFDUXI
|
|
134253878U, // QVSTFDUXIA
|
|
134265111U, // QVSTFDX
|
|
134254000U, // QVSTFDXA
|
|
134257203U, // QVSTFDXI
|
|
134253831U, // QVSTFDXIA
|
|
134265111U, // QVSTFDXb
|
|
134266355U, // QVSTFIWX
|
|
134254138U, // QVSTFIWXA
|
|
570867083U, // QVSTFSUX
|
|
134254127U, // QVSTFSUXA
|
|
134257269U, // QVSTFSUXI
|
|
134253903U, // QVSTFSUXIA
|
|
570867083U, // QVSTFSUXs
|
|
134265980U, // QVSTFSX
|
|
134254040U, // QVSTFSXA
|
|
134257224U, // QVSTFSXI
|
|
134253854U, // QVSTFSXIA
|
|
134265980U, // QVSTFSXs
|
|
18521U, // RESTORE_ACC
|
|
19160U, // RESTORE_CR
|
|
19315U, // RESTORE_CRBIT
|
|
18814U, // RESTORE_QUADWORD
|
|
18469U, // RESTORE_UACC
|
|
18495U, // RESTORE_WACC
|
|
19693U, // RFCI
|
|
19704U, // RFDI
|
|
691799U, // RFEBB
|
|
19709U, // RFI
|
|
19667U, // RFID
|
|
19698U, // RFMCI
|
|
2147523266U, // RLDCL
|
|
2147517547U, // RLDCL_rec
|
|
2147527619U, // RLDCR
|
|
2147518291U, // RLDCR_rec
|
|
2147520662U, // RLDIC
|
|
2147523273U, // RLDICL
|
|
2147523273U, // RLDICL_32
|
|
2147523273U, // RLDICL_32_64
|
|
2147517555U, // RLDICL_32_rec
|
|
2147517555U, // RLDICL_rec
|
|
2147527639U, // RLDICR
|
|
2147527639U, // RLDICR_32
|
|
2147518299U, // RLDICR_rec
|
|
2147516844U, // RLDIC_rec
|
|
2449512540U, // RLDIMI
|
|
2449507326U, // RLDIMI_rec
|
|
2449512548U, // RLWIMI
|
|
2449512548U, // RLWIMI8
|
|
2449507335U, // RLWIMI8_rec
|
|
2449507335U, // RLWIMI_rec
|
|
2147523865U, // RLWINM
|
|
2147523865U, // RLWINM8
|
|
2147517631U, // RLWINM8_rec
|
|
2147517631U, // RLWINM_rec
|
|
2147523882U, // RLWNM
|
|
2147523882U, // RLWNM8
|
|
2147517640U, // RLWNM8_rec
|
|
2147517640U, // RLWNM_rec
|
|
18461U, // ReadTB
|
|
1085674U, // SC
|
|
1094440U, // SCV
|
|
17551U, // SELECT_CC_F16
|
|
17473U, // SELECT_CC_F4
|
|
18012U, // SELECT_CC_F8
|
|
17498U, // SELECT_CC_I4
|
|
18057U, // SELECT_CC_I8
|
|
18555U, // SELECT_CC_QBRC
|
|
18584U, // SELECT_CC_QFRC
|
|
18673U, // SELECT_CC_QSRC
|
|
18899U, // SELECT_CC_SPE
|
|
17444U, // SELECT_CC_SPE4
|
|
18644U, // SELECT_CC_VRRC
|
|
18613U, // SELECT_CC_VSFRC
|
|
18733U, // SELECT_CC_VSRC
|
|
18702U, // SELECT_CC_VSSRC
|
|
17566U, // SELECT_F16
|
|
17487U, // SELECT_F4
|
|
18026U, // SELECT_F8
|
|
17512U, // SELECT_I4
|
|
18231U, // SELECT_I8
|
|
18571U, // SELECT_QBRC
|
|
18600U, // SELECT_QFRC
|
|
18689U, // SELECT_QSRC
|
|
18914U, // SELECT_SPE
|
|
17460U, // SELECT_SPE4
|
|
18660U, // SELECT_VRRC
|
|
18630U, // SELECT_VSFRC
|
|
18749U, // SELECT_VSRC
|
|
18719U, // SELECT_VSSRC
|
|
36678U, // SETB
|
|
36678U, // SETB8
|
|
36929U, // SETBC
|
|
36929U, // SETBC8
|
|
43956U, // SETBCR
|
|
43956U, // SETBCR8
|
|
19091U, // SETFLM
|
|
36921U, // SETNBC
|
|
36921U, // SETNBC8
|
|
43947U, // SETNBCR
|
|
43947U, // SETNBCR8
|
|
18790U, // SETRND
|
|
19684U, // SETRNDi
|
|
33471U, // SLBFEE_rec
|
|
19578U, // SLBIA
|
|
1086566U, // SLBIE
|
|
38345U, // SLBIEG
|
|
37950U, // SLBMFEE
|
|
45869U, // SLBMFEV
|
|
38033U, // SLBMTE
|
|
19606U, // SLBSYNC
|
|
2147521140U, // SLD
|
|
2147517003U, // SLD_rec
|
|
2147530158U, // SLW
|
|
2147530158U, // SLW8
|
|
2147518722U, // SLW8_rec
|
|
2147518722U, // SLW_rec
|
|
67157836U, // SPELWZ
|
|
134266446U, // SPELWZX
|
|
67155821U, // SPESTW
|
|
134266391U, // SPESTWX
|
|
18534U, // SPILL_ACC
|
|
19172U, // SPILL_CR
|
|
19330U, // SPILL_CRBIT
|
|
18832U, // SPILL_QUADWORD
|
|
18483U, // SPILL_UACC
|
|
18509U, // SPILL_WACC
|
|
18848U, // SPLIT_QUADWORD
|
|
2147520806U, // SRAD
|
|
2147522444U, // SRADI
|
|
2147522444U, // SRADI_32
|
|
2147517339U, // SRADI_rec
|
|
2147516892U, // SRAD_rec
|
|
2147529968U, // SRAW
|
|
2147522989U, // SRAWI
|
|
2147517464U, // SRAWI_rec
|
|
2147518681U, // SRAW_rec
|
|
2147521249U, // SRD
|
|
2147517040U, // SRD_rec
|
|
2147530413U, // SRW
|
|
2147530413U, // SRW8
|
|
2147518728U, // SRW8_rec
|
|
2147518728U, // SRW_rec
|
|
67145583U, // STB
|
|
67145583U, // STB8
|
|
2147531218U, // STBCIX
|
|
134252891U, // STBCX
|
|
134265588U, // STBEPX
|
|
537309755U, // STBU
|
|
537309755U, // STBU8
|
|
570866960U, // STBUX
|
|
570866960U, // STBUX8
|
|
134265048U, // STBX
|
|
134265048U, // STBX8
|
|
2147530968U, // STBXTLS
|
|
2147530968U, // STBXTLS_
|
|
2147530968U, // STBXTLS_32
|
|
67146626U, // STD
|
|
2147528882U, // STDAT
|
|
134265742U, // STDBRX
|
|
2147531233U, // STDCIX
|
|
134252899U, // STDCX
|
|
537309816U, // STDU
|
|
570867013U, // STDUX
|
|
134265172U, // STDX
|
|
2147531092U, // STDXTLS
|
|
2147531092U, // STDXTLS_
|
|
67146244U, // STFD
|
|
134265604U, // STFDEPX
|
|
537309767U, // STFDU
|
|
570866999U, // STFDUX
|
|
134265113U, // STFDX
|
|
2147531033U, // STFDXTLS
|
|
2147531033U, // STFDXTLS_
|
|
134266357U, // STFIWX
|
|
67153587U, // STFS
|
|
537309897U, // STFSU
|
|
570867085U, // STFSUX
|
|
134265982U, // STFSX
|
|
2147531902U, // STFSXTLS
|
|
2147531902U, // STFSXTLS_
|
|
67147473U, // STH
|
|
67147473U, // STH8
|
|
134265757U, // STHBRX
|
|
2147531241U, // STHCIX
|
|
134252907U, // STHCX
|
|
134265620U, // STHEPX
|
|
537309845U, // STHU
|
|
537309845U, // STHU8
|
|
570867027U, // STHUX
|
|
570867027U, // STHUX8
|
|
134265292U, // STHX
|
|
134265292U, // STHX8
|
|
2147531212U, // STHXTLS
|
|
2147531212U, // STHXTLS_
|
|
2147531212U, // STHXTLS_32
|
|
67155384U, // STMW
|
|
19821U, // STOP
|
|
67152578U, // STQ
|
|
134252915U, // STQCX
|
|
19111U, // STQX_PSEUDO
|
|
2147523100U, // STSWI
|
|
134265014U, // STVEBX
|
|
134265258U, // STVEHX
|
|
134266347U, // STVEWX
|
|
134266304U, // STVX
|
|
134257600U, // STVXL
|
|
67155821U, // STW
|
|
67155821U, // STW8
|
|
2147528960U, // STWAT
|
|
134265791U, // STWBRX
|
|
2147531249U, // STWCIX
|
|
134252923U, // STWCX
|
|
134265635U, // STWEPX
|
|
537309959U, // STWU
|
|
537309959U, // STWU8
|
|
570867103U, // STWUX
|
|
570867103U, // STWUX8
|
|
134266391U, // STWX
|
|
134266391U, // STWX8
|
|
2147532311U, // STWXTLS
|
|
2147532311U, // STWXTLS_
|
|
2147532311U, // STWXTLS_32
|
|
67146579U, // STXSD
|
|
134265164U, // STXSDX
|
|
134265022U, // STXSIBX
|
|
134265022U, // STXSIBXv
|
|
134265266U, // STXSIHX
|
|
134265266U, // STXSIHXv
|
|
134266365U, // STXSIWX
|
|
67152078U, // STXSSP
|
|
134265676U, // STXSSPX
|
|
67154829U, // STXV
|
|
134264940U, // STXVB16X
|
|
134264905U, // STXVD2X
|
|
134264958U, // STXVH8X
|
|
2147523507U, // STXVL
|
|
2147523383U, // STXVLL
|
|
67152204U, // STXVP
|
|
2147523406U, // STXVPRL
|
|
2147523349U, // STXVPRLL
|
|
134265692U, // STXVPX
|
|
134265039U, // STXVRBX
|
|
134265148U, // STXVRDX
|
|
134265283U, // STXVRHX
|
|
2147523430U, // STXVRL
|
|
2147523367U, // STXVRLL
|
|
134266382U, // STXVRWX
|
|
134264922U, // STXVW4X
|
|
134266316U, // STXVX
|
|
2147521755U, // SUBF
|
|
2147521755U, // SUBF8
|
|
2147524542U, // SUBF8O
|
|
2147517837U, // SUBF8O_rec
|
|
2147517214U, // SUBF8_rec
|
|
2147520641U, // SUBFC
|
|
2147520641U, // SUBFC8
|
|
2147524448U, // SUBFC8O
|
|
2147517731U, // SUBFC8O_rec
|
|
2147516820U, // SUBFC8_rec
|
|
2147524448U, // SUBFCO
|
|
2147517731U, // SUBFCO_rec
|
|
2147516820U, // SUBFC_rec
|
|
2147521614U, // SUBFE
|
|
2147521614U, // SUBFE8
|
|
2147524492U, // SUBFE8O
|
|
2147517781U, // SUBFE8O_rec
|
|
2147517128U, // SUBFE8_rec
|
|
2147524492U, // SUBFEO
|
|
2147517781U, // SUBFEO_rec
|
|
2147517128U, // SUBFE_rec
|
|
2147520669U, // SUBFIC
|
|
2147520669U, // SUBFIC8
|
|
38011U, // SUBFME
|
|
38011U, // SUBFME8
|
|
40860U, // SUBFME8O
|
|
34151U, // SUBFME8O_rec
|
|
33496U, // SUBFME8_rec
|
|
40860U, // SUBFMEO
|
|
34151U, // SUBFMEO_rec
|
|
33496U, // SUBFME_rec
|
|
2147524542U, // SUBFO
|
|
2147517837U, // SUBFO_rec
|
|
1073786832U, // SUBFUS
|
|
1073776715U, // SUBFUS_rec
|
|
38093U, // SUBFZE
|
|
38093U, // SUBFZE8
|
|
40885U, // SUBFZE8O
|
|
34179U, // SUBFZE8O_rec
|
|
33557U, // SUBFZE8_rec
|
|
40885U, // SUBFZEO
|
|
34179U, // SUBFZEO_rec
|
|
33557U, // SUBFZE_rec
|
|
2147517214U, // SUBF_rec
|
|
1773774U, // SYNC
|
|
23662798U, // SYNCP10
|
|
1083484U, // TABORT
|
|
2148008329U, // TABORTDC
|
|
2148008835U, // TABORTDCI
|
|
2148008401U, // TABORTWC
|
|
2148008847U, // TABORTWCI
|
|
1183316U, // TAILB
|
|
1183316U, // TAILB8
|
|
1215541U, // TAILBA
|
|
1215541U, // TAILBA8
|
|
19830U, // TAILBCTR
|
|
19830U, // TAILBCTR8
|
|
689401U, // TBEGIN
|
|
19288U, // TBEGIN_RET
|
|
1088128U, // TCHECK
|
|
19276U, // TCHECK_RET
|
|
2263980U, // TCRETURNai
|
|
2263877U, // TCRETURNai8
|
|
2232588U, // TCRETURNdi
|
|
2231123U, // TCRETURNdi8
|
|
2141071U, // TCRETURNri
|
|
2132833U, // TCRETURNri8
|
|
2148012897U, // TD
|
|
2148014053U, // TDI
|
|
688728U, // TEND
|
|
19584U, // TLBIA
|
|
252089453U, // TLBIE
|
|
1088209U, // TLBIEL
|
|
2148219489U, // TLBILX
|
|
47245U, // TLBIVAX
|
|
1086022U, // TLBLD
|
|
1087526U, // TLBLI
|
|
19672U, // TLBRE
|
|
2147521667U, // TLBRE2
|
|
48203U, // TLBSX
|
|
2147531851U, // TLBSX2
|
|
2147518883U, // TLBSX2D
|
|
19614U, // TLBSYNC
|
|
19678U, // TLBWE
|
|
2147521711U, // TLBWE2
|
|
19534U, // TLSGDAIX
|
|
18352U, // TLSGDAIX8
|
|
19777U, // TRAP
|
|
16408U, // TRECHKPT
|
|
1082541U, // TRECLAIM
|
|
690064U, // TSR
|
|
2148022080U, // TW
|
|
2148014627U, // TWI
|
|
19134U, // UNENCODED_NOP
|
|
19149U, // UpdateGBR
|
|
2147520372U, // VABSDUB
|
|
2147522262U, // VABSDUH
|
|
2147530636U, // VABSDUW
|
|
2147527397U, // VADDCUQ
|
|
2147530619U, // VADDCUW
|
|
2147527428U, // VADDECUQ
|
|
2147523949U, // VADDEUQM
|
|
2147525692U, // VADDFP
|
|
2147528066U, // VADDSBS
|
|
2147528419U, // VADDSHS
|
|
2147528743U, // VADDSWS
|
|
2147523585U, // VADDUBM
|
|
2147528094U, // VADDUBS
|
|
2147523657U, // VADDUDM
|
|
2147523784U, // VADDUHM
|
|
2147528447U, // VADDUHS
|
|
2147523930U, // VADDUQM
|
|
2147524051U, // VADDUWM
|
|
2147528770U, // VADDUWS
|
|
2147521204U, // VAND
|
|
2147520626U, // VANDC
|
|
2147520246U, // VAVGSB
|
|
2147522148U, // VAVGSH
|
|
2147530444U, // VAVGSW
|
|
2147520390U, // VAVGUB
|
|
2147522280U, // VAVGUH
|
|
2147530663U, // VAVGUW
|
|
2147521145U, // VBPERMD
|
|
2147527245U, // VBPERMQ
|
|
2449521773U, // VCFSX
|
|
2147531885U, // VCFSX_0
|
|
2147521004U, // VCFUGED
|
|
2449521996U, // VCFUX
|
|
2147532108U, // VCFUX_0
|
|
2147527697U, // VCIPHER
|
|
2147529191U, // VCIPHERLAST
|
|
2147520167U, // VCLRLB
|
|
2147520223U, // VCLRRB
|
|
36907U, // VCLZB
|
|
37890U, // VCLZD
|
|
2147523688U, // VCLZDM
|
|
38718U, // VCLZH
|
|
36464U, // VCLZLSBB
|
|
47137U, // VCLZW
|
|
2147525656U, // VCMPBFP
|
|
2147517951U, // VCMPBFP_rec
|
|
2147525755U, // VCMPEQFP
|
|
2147517972U, // VCMPEQFP_rec
|
|
2147520415U, // VCMPEQUB
|
|
2147516699U, // VCMPEQUB_rec
|
|
2147521485U, // VCMPEQUD
|
|
2147517057U, // VCMPEQUD_rec
|
|
2147522305U, // VCMPEQUH
|
|
2147517274U, // VCMPEQUH_rec
|
|
2147527482U, // VCMPEQUQ
|
|
2147518205U, // VCMPEQUQ_rec
|
|
2147530697U, // VCMPEQUW
|
|
2147518753U, // VCMPEQUW_rec
|
|
2147525709U, // VCMPGEFP
|
|
2147517961U, // VCMPGEFP_rec
|
|
2147525765U, // VCMPGTFP
|
|
2147517983U, // VCMPGTFP_rec
|
|
2147520299U, // VCMPGTSB
|
|
2147516680U, // VCMPGTSB_rec
|
|
2147521329U, // VCMPGTSD
|
|
2147517046U, // VCMPGTSD_rec
|
|
2147522201U, // VCMPGTSH
|
|
2147517255U, // VCMPGTSH_rec
|
|
2147527344U, // VCMPGTSQ
|
|
2147518194U, // VCMPGTSQ_rec
|
|
2147530523U, // VCMPGTSW
|
|
2147518734U, // VCMPGTSW_rec
|
|
2147520516U, // VCMPGTUB
|
|
2147516773U, // VCMPGTUB_rec
|
|
2147521495U, // VCMPGTUD
|
|
2147517068U, // VCMPGTUD_rec
|
|
2147522327U, // VCMPGTUH
|
|
2147517285U, // VCMPGTUH_rec
|
|
2147527492U, // VCMPGTUQ
|
|
2147518216U, // VCMPGTUQ_rec
|
|
2147530732U, // VCMPGTUW
|
|
2147518764U, // VCMPGTUW_rec
|
|
2147520132U, // VCMPNEB
|
|
2147516670U, // VCMPNEB_rec
|
|
2147522080U, // VCMPNEH
|
|
2147517245U, // VCMPNEH_rec
|
|
2147530031U, // VCMPNEW
|
|
2147518688U, // VCMPNEW_rec
|
|
2147520545U, // VCMPNEZB
|
|
2147516784U, // VCMPNEZB_rec
|
|
2147522356U, // VCMPNEZH
|
|
2147517296U, // VCMPNEZH_rec
|
|
2147530775U, // VCMPNEZW
|
|
2147518782U, // VCMPNEZW_rec
|
|
2147527336U, // VCMPSQ
|
|
2147527474U, // VCMPUQ
|
|
2147520094U, // VCNTMBB
|
|
2147520819U, // VCNTMBD
|
|
2147522056U, // VCNTMBH
|
|
2147529974U, // VCNTMBW
|
|
2449518748U, // VCTSXS
|
|
2147528860U, // VCTSXS_0
|
|
2449518756U, // VCTUXS
|
|
2147528868U, // VCTUXS_0
|
|
36914U, // VCTZB
|
|
37905U, // VCTZD
|
|
2147523705U, // VCTZDM
|
|
38725U, // VCTZH
|
|
36474U, // VCTZLSBB
|
|
47154U, // VCTZW
|
|
2147521287U, // VDIVESD
|
|
2147527327U, // VDIVESQ
|
|
2147530435U, // VDIVESW
|
|
2147521450U, // VDIVEUD
|
|
2147527457U, // VDIVEUQ
|
|
2147530654U, // VDIVEUW
|
|
2147521339U, // VDIVSD
|
|
2147527354U, // VDIVSQ
|
|
2147530540U, // VDIVSW
|
|
2147521505U, // VDIVUD
|
|
2147527502U, // VDIVUQ
|
|
2147530742U, // VDIVUW
|
|
2147529594U, // VEQV
|
|
39886U, // VEXPANDBM
|
|
39968U, // VEXPANDDM
|
|
40074U, // VEXPANDHM
|
|
40241U, // VEXPANDQM
|
|
40362U, // VEXPANDWM
|
|
42078U, // VEXPTEFP
|
|
2147531391U, // VEXTDDVLX
|
|
2147531769U, // VEXTDDVRX
|
|
2147531379U, // VEXTDUBVLX
|
|
2147531757U, // VEXTDUBVRX
|
|
2147531412U, // VEXTDUHVLX
|
|
2147531790U, // VEXTDUHVRX
|
|
2147531434U, // VEXTDUWVLX
|
|
2147531812U, // VEXTDUWVRX
|
|
39916U, // VEXTRACTBM
|
|
2449511258U, // VEXTRACTD
|
|
39988U, // VEXTRACTDM
|
|
40104U, // VEXTRACTHM
|
|
40261U, // VEXTRACTQM
|
|
2449510392U, // VEXTRACTUB
|
|
2449512203U, // VEXTRACTUH
|
|
2449520595U, // VEXTRACTUW
|
|
40382U, // VEXTRACTWM
|
|
37102U, // VEXTSB2D
|
|
37102U, // VEXTSB2Ds
|
|
45971U, // VEXTSB2W
|
|
45971U, // VEXTSB2Ws
|
|
43356U, // VEXTSD2Q
|
|
37112U, // VEXTSH2D
|
|
37112U, // VEXTSH2Ds
|
|
45981U, // VEXTSH2W
|
|
45981U, // VEXTSH2Ws
|
|
37122U, // VEXTSW2D
|
|
37122U, // VEXTSW2Ds
|
|
2147531323U, // VEXTUBLX
|
|
2147531694U, // VEXTUBRX
|
|
2147531351U, // VEXTUHLX
|
|
2147531737U, // VEXTUHRX
|
|
2147531455U, // VEXTUWLX
|
|
2147531833U, // VEXTUWRX
|
|
37164U, // VGBBD
|
|
2147520196U, // VGNB
|
|
2449521202U, // VINSBLX
|
|
2449521573U, // VINSBRX
|
|
2449521257U, // VINSBVLX
|
|
2449521635U, // VINSBVRX
|
|
1107333921U, // VINSD
|
|
2449521221U, // VINSDLX
|
|
2449521607U, // VINSDRX
|
|
1107332964U, // VINSERTB
|
|
2449511287U, // VINSERTD
|
|
1107334854U, // VINSERTH
|
|
2449520471U, // VINSERTW
|
|
2449521230U, // VINSHLX
|
|
2449521616U, // VINSHRX
|
|
2449521290U, // VINSHVLX
|
|
2449521668U, // VINSHVRX
|
|
1107343115U, // VINSW
|
|
2449521334U, // VINSWLX
|
|
2449521712U, // VINSWRX
|
|
2449521312U, // VINSWVLX
|
|
2449521690U, // VINSWVRX
|
|
42052U, // VLOGEFP
|
|
2147525683U, // VMADDFP
|
|
2147525775U, // VMAXFP
|
|
2147520318U, // VMAXSB
|
|
2147521347U, // VMAXSD
|
|
2147522220U, // VMAXSH
|
|
2147530548U, // VMAXSW
|
|
2147520526U, // VMAXUB
|
|
2147521513U, // VMAXUD
|
|
2147522337U, // VMAXUH
|
|
2147530750U, // VMAXUW
|
|
2147528396U, // VMHADDSHS
|
|
2147528407U, // VMHRADDSHS
|
|
2147525747U, // VMINFP
|
|
2147520282U, // VMINSB
|
|
2147521305U, // VMINSD
|
|
2147522184U, // VMINSH
|
|
2147530499U, // VMINSW
|
|
2147520398U, // VMINUB
|
|
2147521468U, // VMINUD
|
|
2147522288U, // VMINUH
|
|
2147530680U, // VMINUW
|
|
2147523773U, // VMLADDUHM
|
|
2147521270U, // VMODSD
|
|
2147527319U, // VMODSQ
|
|
2147530418U, // VMODSW
|
|
2147521433U, // VMODUD
|
|
2147527438U, // VMODUQ
|
|
2147530628U, // VMODUW
|
|
2147530023U, // VMRGEW
|
|
2147520141U, // VMRGHB
|
|
2147522089U, // VMRGHH
|
|
2147530066U, // VMRGHW
|
|
2147520159U, // VMRGLB
|
|
2147522097U, // VMRGLH
|
|
2147530118U, // VMRGLW
|
|
2147530391U, // VMRGOW
|
|
2147521423U, // VMSUMCUD
|
|
2147523545U, // VMSUMMBM
|
|
2147523742U, // VMSUMSHM
|
|
2147528428U, // VMSUMSHS
|
|
2147523594U, // VMSUMUBM
|
|
2147523666U, // VMSUMUDM
|
|
2147523793U, // VMSUMUHM
|
|
2147528456U, // VMSUMUHS
|
|
43729U, // VMUL10CUQ
|
|
2147527406U, // VMUL10ECUQ
|
|
2147527446U, // VMUL10EUQ
|
|
43719U, // VMUL10UQ
|
|
2147520237U, // VMULESB
|
|
2147521278U, // VMULESD
|
|
2147522139U, // VMULESH
|
|
2147530426U, // VMULESW
|
|
2147520381U, // VMULEUB
|
|
2147521441U, // VMULEUD
|
|
2147522271U, // VMULEUH
|
|
2147530645U, // VMULEUW
|
|
2147521296U, // VMULHSD
|
|
2147530461U, // VMULHSW
|
|
2147521459U, // VMULHUD
|
|
2147530671U, // VMULHUW
|
|
2147521109U, // VMULLD
|
|
2147520290U, // VMULOSB
|
|
2147521320U, // VMULOSD
|
|
2147522192U, // VMULOSH
|
|
2147530514U, // VMULOSW
|
|
2147520406U, // VMULOUB
|
|
2147521476U, // VMULOUD
|
|
2147522296U, // VMULOUH
|
|
2147530688U, // VMULOUW
|
|
2147524060U, // VMULUWM
|
|
2147521189U, // VNAND
|
|
2147527687U, // VNCIPHER
|
|
2147529177U, // VNCIPHERLAST
|
|
37386U, // VNEGD
|
|
46411U, // VNEGW
|
|
2147525665U, // VNMSUBFP
|
|
2147527807U, // VNOR
|
|
2147527820U, // VOR
|
|
2147520740U, // VORC
|
|
2147521225U, // VPDEPD
|
|
2147523968U, // VPERM
|
|
2147527767U, // VPERMR
|
|
2147527840U, // VPERMXOR
|
|
2147521415U, // VPEXTD
|
|
2147531572U, // VPKPX
|
|
2147528572U, // VPKSDSS
|
|
2147528638U, // VPKSDUS
|
|
2147528581U, // VPKSHSS
|
|
2147528664U, // VPKSHUS
|
|
2147528590U, // VPKSWSS
|
|
2147528682U, // VPKSWUS
|
|
2147523983U, // VPKUDUM
|
|
2147528647U, // VPKUDUS
|
|
2147523992U, // VPKUHUM
|
|
2147528673U, // VPKUHUS
|
|
2147524001U, // VPKUWUM
|
|
2147528691U, // VPKUWUS
|
|
2147520187U, // VPMSUMB
|
|
2147521154U, // VPMSUMD
|
|
2147522117U, // VPMSUMH
|
|
2147530174U, // VPMSUMW
|
|
36698U, // VPOPCNTB
|
|
37741U, // VPOPCNTD
|
|
38588U, // VPOPCNTH
|
|
46925U, // VPOPCNTW
|
|
37180U, // VPRTYBD
|
|
43387U, // VPRTYBQ
|
|
46335U, // VPRTYBW
|
|
42071U, // VREFP
|
|
40167U, // VRFIM
|
|
40576U, // VRFIN
|
|
42155U, // VRFIP
|
|
48813U, // VRFIZ
|
|
2147520175U, // VRLB
|
|
2147521133U, // VRLD
|
|
2147522644U, // VRLDMI
|
|
2147523857U, // VRLDNM
|
|
2147522105U, // VRLH
|
|
2147527226U, // VRLQ
|
|
2147522668U, // VRLQMI
|
|
2147523873U, // VRLQNM
|
|
2147530150U, // VRLW
|
|
2147522764U, // VRLWMI
|
|
2147523881U, // VRLWNM
|
|
42088U, // VRSQRTEFP
|
|
47826U, // VSBOX
|
|
2147523311U, // VSEL
|
|
2147520793U, // VSHASIGMAD
|
|
2147529955U, // VSHASIGMAW
|
|
2147523446U, // VSL
|
|
2147520181U, // VSLB
|
|
2147521139U, // VSLD
|
|
2147522399U, // VSLDBI
|
|
2147522803U, // VSLDOI
|
|
2147522111U, // VSLH
|
|
2147524588U, // VSLO
|
|
2147527232U, // VSLQ
|
|
2147529572U, // VSLV
|
|
2147530157U, // VSLW
|
|
2449510226U, // VSPLTB
|
|
2449510226U, // VSPLTBs
|
|
2449512116U, // VSPLTH
|
|
2449512116U, // VSPLTHs
|
|
402689799U, // VSPLTISB
|
|
402691701U, // VSPLTISH
|
|
402700006U, // VSPLTISW
|
|
2449520444U, // VSPLTW
|
|
2147527905U, // VSR
|
|
2147520080U, // VSRAB
|
|
2147520805U, // VSRAD
|
|
2147522049U, // VSRAH
|
|
2147527014U, // VSRAQ
|
|
2147529967U, // VSRAW
|
|
2147520231U, // VSRB
|
|
2147521256U, // VSRD
|
|
2147522407U, // VSRDBI
|
|
2147522133U, // VSRH
|
|
2147524716U, // VSRO
|
|
2147527313U, // VSRQ
|
|
2147529600U, // VSRV
|
|
2147530412U, // VSRW
|
|
39604U, // VSTRIBL
|
|
33889U, // VSTRIBL_rec
|
|
43938U, // VSTRIBR
|
|
34633U, // VSTRIBR_rec
|
|
39683U, // VSTRIHL
|
|
33932U, // VSTRIHL_rec
|
|
44058U, // VSTRIHR
|
|
34660U, // VSTRIHR_rec
|
|
2147527388U, // VSUBCUQ
|
|
2147530610U, // VSUBCUW
|
|
2147527418U, // VSUBECUQ
|
|
2147523939U, // VSUBEUQM
|
|
2147525675U, // VSUBFP
|
|
2147528057U, // VSUBSBS
|
|
2147528387U, // VSUBSHS
|
|
2147528734U, // VSUBSWS
|
|
2147523576U, // VSUBUBM
|
|
2147528085U, // VSUBUBS
|
|
2147523648U, // VSUBUDM
|
|
2147523764U, // VSUBUHM
|
|
2147528438U, // VSUBUHS
|
|
2147523921U, // VSUBUQM
|
|
2147524042U, // VSUBUWM
|
|
2147528761U, // VSUBUWS
|
|
2147528724U, // VSUM2SWS
|
|
2147528047U, // VSUM4SBS
|
|
2147528377U, // VSUM4SHS
|
|
2147528075U, // VSUM4UBS
|
|
2147528752U, // VSUMSWS
|
|
47915U, // VUPKHPX
|
|
36606U, // VUPKHSB
|
|
38508U, // VUPKHSH
|
|
46804U, // VUPKHSW
|
|
47931U, // VUPKLPX
|
|
36625U, // VUPKLSB
|
|
38527U, // VUPKLSH
|
|
46832U, // VUPKLSW
|
|
2147527858U, // VXOR
|
|
2382408882U, // V_SET0
|
|
2382408882U, // V_SET0B
|
|
2382408882U, // V_SET0H
|
|
24164070U, // V_SETALLONES
|
|
24164070U, // V_SETALLONESB
|
|
24164070U, // V_SETALLONESH
|
|
1782125U, // WAIT
|
|
271266157U, // WAITP10
|
|
1086535U, // WRTEE
|
|
1087466U, // WRTEEI
|
|
2147527828U, // XOR
|
|
2147527828U, // XOR8
|
|
2147518338U, // XOR8_rec
|
|
2147522850U, // XORI
|
|
2147522850U, // XORI8
|
|
2147528503U, // XORIS
|
|
2147528503U, // XORIS8
|
|
2147518338U, // XOR_rec
|
|
41771U, // XSABSDP
|
|
42661U, // XSABSQP
|
|
2147524932U, // XSADDDP
|
|
2147526137U, // XSADDQP
|
|
2147524675U, // XSADDQPO
|
|
2147526490U, // XSADDSP
|
|
2147525377U, // XSCMPEQDP
|
|
2147526268U, // XSCMPEQQP
|
|
2147525345U, // XSCMPEXPDP
|
|
2147526246U, // XSCMPEXPQP
|
|
2147524994U, // XSCMPGEDP
|
|
2147526166U, // XSCMPGEQP
|
|
2147525444U, // XSCMPGTDP
|
|
2147526318U, // XSCMPGTQP
|
|
2147525275U, // XSCMPODP
|
|
2147526216U, // XSCMPOQP
|
|
2147525508U, // XSCMPUDP
|
|
2147526339U, // XSCMPUQP
|
|
2147525235U, // XSCPSGNDP
|
|
2147526205U, // XSCPSGNQP
|
|
42135U, // XSCVDPHP
|
|
42578U, // XSCVDPQP
|
|
43104U, // XSCVDPSP
|
|
40749U, // XSCVDPSPN
|
|
44595U, // XSCVDPSXDS
|
|
44595U, // XSCVDPSXDSs
|
|
45140U, // XSCVDPSXWS
|
|
45140U, // XSCVDPSXWSs
|
|
44631U, // XSCVDPUXDS
|
|
44631U, // XSCVDPUXDSs
|
|
45176U, // XSCVDPUXWS
|
|
45176U, // XSCVDPUXWSs
|
|
41637U, // XSCVHPDP
|
|
41647U, // XSCVQPDP
|
|
40946U, // XSCVQPDPO
|
|
48785U, // XSCVQPSDZ
|
|
48906U, // XSCVQPSQZ
|
|
48995U, // XSCVQPSWZ
|
|
48796U, // XSCVQPUDZ
|
|
48917U, // XSCVQPUQZ
|
|
49006U, // XSCVQPUWZ
|
|
42498U, // XSCVSDQP
|
|
41657U, // XSCVSPDP
|
|
40697U, // XSCVSPDPN
|
|
42631U, // XSCVSQQP
|
|
41302U, // XSCVSXDDP
|
|
42860U, // XSCVSXDSP
|
|
42508U, // XSCVUDQP
|
|
42641U, // XSCVUQQP
|
|
41324U, // XSCVUXDDP
|
|
42882U, // XSCVUXDSP
|
|
2147525518U, // XSDIVDP
|
|
2147526349U, // XSDIVQP
|
|
2147524706U, // XSDIVQPO
|
|
2147526912U, // XSDIVSP
|
|
2147525325U, // XSIEXPDP
|
|
2147526236U, // XSIEXPQP
|
|
2449514738U, // XSMADDADP
|
|
2449516316U, // XSMADDASP
|
|
2449515101U, // XSMADDMDP
|
|
2449516598U, // XSMADDMSP
|
|
2449516015U, // XSMADDQP
|
|
2449514552U, // XSMADDQPO
|
|
2147524922U, // XSMAXCDP
|
|
2147526106U, // XSMAXCQP
|
|
2147525578U, // XSMAXDP
|
|
2147525115U, // XSMAXJDP
|
|
2147524912U, // XSMINCDP
|
|
2147526096U, // XSMINCQP
|
|
2147525257U, // XSMINDP
|
|
2147525105U, // XSMINJDP
|
|
2449514692U, // XSMSUBADP
|
|
2449516270U, // XSMSUBASP
|
|
2449515055U, // XSMSUBMDP
|
|
2449516552U, // XSMSUBMSP
|
|
2449515954U, // XSMSUBQP
|
|
2449514519U, // XSMSUBQPO
|
|
2147525125U, // XSMULDP
|
|
2147526196U, // XSMULQP
|
|
2147524685U, // XSMULQPO
|
|
2147526622U, // XSMULSP
|
|
41751U, // XSNABSDP
|
|
41751U, // XSNABSDPs
|
|
42651U, // XSNABSQP
|
|
41408U, // XSNEGDP
|
|
42529U, // XSNEGQP
|
|
2449514714U, // XSNMADDADP
|
|
2449516292U, // XSNMADDASP
|
|
2449515077U, // XSNMADDMDP
|
|
2449516574U, // XSNMADDMSP
|
|
2449516004U, // XSNMADDQP
|
|
2449514540U, // XSNMADDQPO
|
|
2449514668U, // XSNMSUBADP
|
|
2449516246U, // XSNMSUBASP
|
|
2449515031U, // XSNMSUBMDP
|
|
2449516528U, // XSNMSUBMSP
|
|
2449515943U, // XSNMSUBQP
|
|
2449514507U, // XSNMSUBQPO
|
|
39163U, // XSRDPI
|
|
37029U, // XSRDPIC
|
|
40174U, // XSRDPIM
|
|
42162U, // XSRDPIP
|
|
48820U, // XSRDPIZ
|
|
41368U, // XSREDP
|
|
42915U, // XSRESP
|
|
335943947U, // XSRQPI
|
|
335952417U, // XSRQPIX
|
|
335948115U, // XSRQPXP
|
|
43179U, // XSRSP
|
|
41384U, // XSRSQRTEDP
|
|
42931U, // XSRSQRTESP
|
|
41818U, // XSSQRTDP
|
|
42681U, // XSSQRTQP
|
|
41047U, // XSSQRTQPO
|
|
43233U, // XSSQRTSP
|
|
2147524872U, // XSSUBDP
|
|
2147526076U, // XSSUBQP
|
|
2147524642U, // XSSUBQPO
|
|
2147526450U, // XSSUBSP
|
|
2147525527U, // XSTDIVDP
|
|
41828U, // XSTSQRTDP
|
|
2449514778U, // XSTSTDCDP
|
|
2449515973U, // XSTSTDCQP
|
|
2449516356U, // XSTSTDCSP
|
|
41709U, // XSXEXPDP
|
|
42610U, // XSXEXPQP
|
|
41426U, // XSXSIGDP
|
|
42538U, // XSXSIGQP
|
|
41780U, // XVABSDP
|
|
43196U, // XVABSSP
|
|
2147524941U, // XVADDDP
|
|
2147526499U, // XVADDSP
|
|
2147519184U, // XVBF16GER2
|
|
2449514145U, // XVBF16GER2NN
|
|
2449515753U, // XVBF16GER2NP
|
|
2449514204U, // XVBF16GER2PN
|
|
2449515812U, // XVBF16GER2PP
|
|
2147519184U, // XVBF16GER2W
|
|
2449514145U, // XVBF16GER2WNN
|
|
2449515753U, // XVBF16GER2WNP
|
|
2449514204U, // XVBF16GER2WPN
|
|
2449515812U, // XVBF16GER2WPP
|
|
2147525388U, // XVCMPEQDP
|
|
2147517919U, // XVCMPEQDP_rec
|
|
2147526802U, // XVCMPEQSP
|
|
2147518013U, // XVCMPEQSP_rec
|
|
2147525005U, // XVCMPGEDP
|
|
2147517907U, // XVCMPGEDP_rec
|
|
2147526552U, // XVCMPGESP
|
|
2147518001U, // XVCMPGESP_rec
|
|
2147525455U, // XVCMPGTDP
|
|
2147517939U, // XVCMPGTDP_rec
|
|
2147526870U, // XVCMPGTSP
|
|
2147518039U, // XVCMPGTSP_rec
|
|
2147525246U, // XVCPSGNDP
|
|
2147526732U, // XVCPSGNSP
|
|
40736U, // XVCVBF16SPN
|
|
43114U, // XVCVDPSP
|
|
44607U, // XVCVDPSXDS
|
|
45152U, // XVCVDPSXWS
|
|
44643U, // XVCVDPUXDS
|
|
45188U, // XVCVDPUXWS
|
|
43124U, // XVCVHPSP
|
|
35608U, // XVCVSPBF16
|
|
41667U, // XVCVSPDP
|
|
42145U, // XVCVSPHP
|
|
44619U, // XVCVSPSXDS
|
|
45164U, // XVCVSPSXWS
|
|
44655U, // XVCVSPUXDS
|
|
45200U, // XVCVSPUXWS
|
|
41313U, // XVCVSXDDP
|
|
42871U, // XVCVSXDSP
|
|
41908U, // XVCVSXWDP
|
|
43292U, // XVCVSXWSP
|
|
41335U, // XVCVUXDDP
|
|
42893U, // XVCVUXDSP
|
|
41919U, // XVCVUXWDP
|
|
43303U, // XVCVUXWSP
|
|
2147525547U, // XVDIVDP
|
|
2147526931U, // XVDIVSP
|
|
2147519198U, // XVF16GER2
|
|
2449514161U, // XVF16GER2NN
|
|
2449515769U, // XVF16GER2NP
|
|
2449514220U, // XVF16GER2PN
|
|
2449515828U, // XVF16GER2PP
|
|
2147519198U, // XVF16GER2W
|
|
2449514161U, // XVF16GER2WNN
|
|
2449515769U, // XVF16GER2WNP
|
|
2449514220U, // XVF16GER2WPN
|
|
2449515828U, // XVF16GER2WPP
|
|
2147527665U, // XVF32GER
|
|
2449514176U, // XVF32GERNN
|
|
2449515784U, // XVF32GERNP
|
|
2449514246U, // XVF32GERPN
|
|
2449515886U, // XVF32GERPP
|
|
2147527665U, // XVF32GERW
|
|
2449514176U, // XVF32GERWNN
|
|
2449515784U, // XVF32GERWNP
|
|
2449514246U, // XVF32GERWPN
|
|
2449515886U, // XVF32GERWPP
|
|
2147527677U, // XVF64GER
|
|
2449514190U, // XVF64GERNN
|
|
2449515798U, // XVF64GERNP
|
|
2449514260U, // XVF64GERPN
|
|
2449515900U, // XVF64GERPP
|
|
2147527677U, // XVF64GERW
|
|
2449514190U, // XVF64GERWNN
|
|
2449515798U, // XVF64GERWNP
|
|
2449514260U, // XVF64GERWPN
|
|
2449515900U, // XVF64GERWPP
|
|
2147519211U, // XVI16GER2
|
|
2449515843U, // XVI16GER2PP
|
|
2147527933U, // XVI16GER2S
|
|
2449515914U, // XVI16GER2SPP
|
|
2147527933U, // XVI16GER2SW
|
|
2449515914U, // XVI16GER2SWPP
|
|
2147519211U, // XVI16GER2W
|
|
2449515843U, // XVI16GER2WPP
|
|
2147519345U, // XVI4GER8
|
|
2449515872U, // XVI4GER8PP
|
|
2147519345U, // XVI4GER8W
|
|
2449515872U, // XVI4GER8WPP
|
|
2147519224U, // XVI8GER4
|
|
2449515858U, // XVI8GER4PP
|
|
2449515930U, // XVI8GER4SPP
|
|
2147519224U, // XVI8GER4W
|
|
2449515858U, // XVI8GER4WPP
|
|
2449515930U, // XVI8GER4WSPP
|
|
2147525335U, // XVIEXPDP
|
|
2147526782U, // XVIEXPSP
|
|
2449514749U, // XVMADDADP
|
|
2449516327U, // XVMADDASP
|
|
2449515112U, // XVMADDMDP
|
|
2449516609U, // XVMADDMSP
|
|
2147525587U, // XVMAXDP
|
|
2147526962U, // XVMAXSP
|
|
2147525266U, // XVMINDP
|
|
2147526743U, // XVMINSP
|
|
2449514703U, // XVMSUBADP
|
|
2449516281U, // XVMSUBASP
|
|
2449515066U, // XVMSUBMDP
|
|
2449516563U, // XVMSUBMSP
|
|
2147525134U, // XVMULDP
|
|
2147526631U, // XVMULSP
|
|
41761U, // XVNABSDP
|
|
43186U, // XVNABSSP
|
|
41417U, // XVNEGDP
|
|
42955U, // XVNEGSP
|
|
2449514726U, // XVNMADDADP
|
|
2449516304U, // XVNMADDASP
|
|
2449515089U, // XVNMADDMDP
|
|
2449516586U, // XVNMADDMSP
|
|
2449514680U, // XVNMSUBADP
|
|
2449516258U, // XVNMSUBASP
|
|
2449515043U, // XVNMSUBMDP
|
|
2449516540U, // XVNMSUBMSP
|
|
39171U, // XVRDPI
|
|
37038U, // XVRDPIC
|
|
40183U, // XVRDPIM
|
|
42171U, // XVRDPIP
|
|
48829U, // XVRDPIZ
|
|
41376U, // XVREDP
|
|
42923U, // XVRESP
|
|
39187U, // XVRSPI
|
|
37047U, // XVRSPIC
|
|
40192U, // XVRSPIM
|
|
42180U, // XVRSPIP
|
|
48838U, // XVRSPIZ
|
|
41396U, // XVRSQRTEDP
|
|
42943U, // XVRSQRTESP
|
|
41850U, // XVSQRTDP
|
|
43254U, // XVSQRTSP
|
|
2147524881U, // XVSUBDP
|
|
2147526459U, // XVSUBSP
|
|
2147525537U, // XVTDIVDP
|
|
2147526921U, // XVTDIVSP
|
|
36455U, // XVTLSBB
|
|
41839U, // XVTSQRTDP
|
|
43243U, // XVTSQRTSP
|
|
2449514789U, // XVTSTDCDP
|
|
2449516367U, // XVTSTDCSP
|
|
41719U, // XVXEXPDP
|
|
43144U, // XVXEXPSP
|
|
41436U, // XVXSIGDP
|
|
42964U, // XVXSIGSP
|
|
2147520534U, // XXBLENDVB
|
|
2147521521U, // XXBLENDVD
|
|
2147522345U, // XXBLENDVH
|
|
2147530758U, // XXBLENDVW
|
|
37591U, // XXBRD
|
|
38478U, // XXBRH
|
|
43658U, // XXBRQ
|
|
46757U, // XXBRW
|
|
2147523244U, // XXEVAL
|
|
2147530719U, // XXEXTRACTUW
|
|
2147523604U, // XXGENPCVBM
|
|
2147523676U, // XXGENPCVDM
|
|
2147523803U, // XXGENPCVHM
|
|
2147524069U, // XXGENPCVWM
|
|
2449520481U, // XXINSERTW
|
|
2147521163U, // XXLAND
|
|
2147520608U, // XXLANDC
|
|
2147529578U, // XXLEQV
|
|
2382410602U, // XXLEQVOnes
|
|
2147521171U, // XXLNAND
|
|
2147527791U, // XXLNOR
|
|
2147527784U, // XXLOR
|
|
2147520724U, // XXLORC
|
|
2147527784U, // XXLORf
|
|
2147527825U, // XXLXOR
|
|
2382408849U, // XXLXORdpz
|
|
2382408849U, // XXLXORspz
|
|
2382408849U, // XXLXORz
|
|
1478728U, // XXMFACC
|
|
1478728U, // XXMFACCW
|
|
2147530074U, // XXMRGHW
|
|
2147530126U, // XXMRGLW
|
|
1085521U, // XXMTACC
|
|
1085521U, // XXMTACCW
|
|
2147523975U, // XXPERM
|
|
2147522484U, // XXPERMDI
|
|
2147522484U, // XXPERMDIs
|
|
2147527775U, // XXPERMR
|
|
2147531465U, // XXPERMX
|
|
2147523317U, // XXSEL
|
|
1097318U, // XXSETACCZ
|
|
1097318U, // XXSETACCZW
|
|
2147522996U, // XXSLDWI
|
|
2147522996U, // XXSLDWIs
|
|
1140898014U, // XXSPLTI32DX
|
|
1174441621U, // XXSPLTIB
|
|
41446U, // XXSPLTIDP
|
|
46460U, // XXSPLTIW
|
|
2147530564U, // XXSPLTW
|
|
2147530564U, // XXSPLTWs
|
|
2148012093U, // gBC
|
|
2148011065U, // gBCA
|
|
25939062U, // gBCAat
|
|
2148019430U, // gBCCTR
|
|
2148014935U, // gBCCTRL
|
|
2148014781U, // gBCL
|
|
2148011360U, // gBCLA
|
|
25939078U, // gBCLAat
|
|
2148019235U, // gBCLR
|
|
2148014911U, // gBCLRL
|
|
26987777U, // gBCLat
|
|
26987667U, // gBCat
|
|
};
|
|
|
|
static const uint16_t OpInfo1[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_VALUE_LIST
|
|
0U, // DBG_INSTR_REF
|
|
0U, // DBG_PHI
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ATOMIC_CMP_SWAP_I128
|
|
0U, // ATOMIC_LOAD_ADD_I128
|
|
0U, // ATOMIC_LOAD_AND_I128
|
|
0U, // ATOMIC_LOAD_NAND_I128
|
|
0U, // ATOMIC_LOAD_OR_I128
|
|
0U, // ATOMIC_LOAD_SUB_I128
|
|
0U, // ATOMIC_LOAD_XOR_I128
|
|
0U, // ATOMIC_SWAP_I128
|
|
0U, // BUILD_QUADWORD
|
|
0U, // BUILD_UACC
|
|
0U, // CFENCE
|
|
0U, // CFENCE8
|
|
0U, // CLRLSLDI
|
|
0U, // CLRLSLDI_rec
|
|
516U, // CLRLSLWI
|
|
516U, // CLRLSLWI_rec
|
|
128U, // CLRRDI
|
|
128U, // CLRRDI_rec
|
|
132U, // CLRRWI
|
|
132U, // CLRRWI_rec
|
|
0U, // DCBFL
|
|
0U, // DCBFLP
|
|
0U, // DCBFPS
|
|
0U, // DCBFx
|
|
0U, // DCBSTPS
|
|
0U, // DCBTCT
|
|
0U, // DCBTDS
|
|
0U, // DCBTSTCT
|
|
0U, // DCBTSTDS
|
|
0U, // DCBTSTT
|
|
0U, // DCBTSTx
|
|
0U, // DCBTT
|
|
0U, // DCBTx
|
|
0U, // DFLOADf32
|
|
0U, // DFLOADf64
|
|
0U, // DFSTOREf32
|
|
0U, // DFSTOREf64
|
|
0U, // EXTLDI
|
|
0U, // EXTLDI_rec
|
|
516U, // EXTLWI
|
|
516U, // EXTLWI_rec
|
|
0U, // EXTRDI
|
|
0U, // EXTRDI_rec
|
|
516U, // EXTRWI
|
|
516U, // EXTRWI_rec
|
|
516U, // INSLWI
|
|
516U, // INSLWI_rec
|
|
0U, // INSRDI
|
|
0U, // INSRDI_rec
|
|
516U, // INSRWI
|
|
516U, // INSRWI_rec
|
|
0U, // KILL_PAIR
|
|
0U, // LAx
|
|
0U, // LI
|
|
0U, // LI8
|
|
0U, // LIS
|
|
0U, // LIS8
|
|
0U, // LIWAX
|
|
0U, // LIWZX
|
|
136U, // PSUBI
|
|
1028U, // RLWIMIbm
|
|
1028U, // RLWIMIbm_rec
|
|
1028U, // RLWINMbm
|
|
1028U, // RLWINMbm_rec
|
|
1028U, // RLWNMbm
|
|
1028U, // RLWNMbm_rec
|
|
128U, // ROTRDI
|
|
128U, // ROTRDI_rec
|
|
132U, // ROTRWI
|
|
132U, // ROTRWI_rec
|
|
128U, // SLDI
|
|
128U, // SLDI_rec
|
|
132U, // SLWI
|
|
132U, // SLWI_rec
|
|
0U, // SPILLTOVSR_LD
|
|
0U, // SPILLTOVSR_LDX
|
|
0U, // SPILLTOVSR_ST
|
|
0U, // SPILLTOVSR_STX
|
|
128U, // SRDI
|
|
128U, // SRDI_rec
|
|
132U, // SRWI
|
|
132U, // SRWI_rec
|
|
0U, // STIWX
|
|
12U, // SUBI
|
|
12U, // SUBIC
|
|
12U, // SUBIC_rec
|
|
12U, // SUBIS
|
|
0U, // SUBPCIS
|
|
0U, // XFLOADf32
|
|
0U, // XFLOADf64
|
|
0U, // XFSTOREf32
|
|
0U, // XFSTOREf64
|
|
144U, // ADD4
|
|
144U, // ADD4O
|
|
144U, // ADD4O_rec
|
|
144U, // ADD4TLS
|
|
144U, // ADD4_rec
|
|
144U, // ADD8
|
|
144U, // ADD8O
|
|
144U, // ADD8O_rec
|
|
144U, // ADD8TLS
|
|
144U, // ADD8TLS_
|
|
144U, // ADD8_rec
|
|
144U, // ADDC
|
|
144U, // ADDC8
|
|
144U, // ADDC8O
|
|
144U, // ADDC8O_rec
|
|
144U, // ADDC8_rec
|
|
144U, // ADDCO
|
|
144U, // ADDCO_rec
|
|
144U, // ADDC_rec
|
|
144U, // ADDE
|
|
144U, // ADDE8
|
|
144U, // ADDE8O
|
|
144U, // ADDE8O_rec
|
|
144U, // ADDE8_rec
|
|
144U, // ADDEO
|
|
144U, // ADDEO_rec
|
|
1552U, // ADDEX
|
|
1552U, // ADDEX8
|
|
144U, // ADDE_rec
|
|
144U, // ADDG6S
|
|
144U, // ADDG6S8
|
|
12U, // ADDI
|
|
12U, // ADDI8
|
|
12U, // ADDIC
|
|
12U, // ADDIC8
|
|
12U, // ADDIC_rec
|
|
12U, // ADDIS
|
|
12U, // ADDIS8
|
|
0U, // ADDISdtprelHA
|
|
0U, // ADDISdtprelHA32
|
|
0U, // ADDISgotTprelHA
|
|
0U, // ADDIStlsgdHA
|
|
0U, // ADDIStlsldHA
|
|
0U, // ADDIStocHA
|
|
0U, // ADDIStocHA8
|
|
0U, // ADDIdtprelL
|
|
0U, // ADDIdtprelL32
|
|
0U, // ADDItlsgdL
|
|
0U, // ADDItlsgdL32
|
|
0U, // ADDItlsgdLADDR
|
|
0U, // ADDItlsgdLADDR32
|
|
0U, // ADDItlsldL
|
|
0U, // ADDItlsldL32
|
|
0U, // ADDItlsldLADDR
|
|
0U, // ADDItlsldLADDR32
|
|
0U, // ADDItoc
|
|
0U, // ADDItoc8
|
|
0U, // ADDItocL
|
|
0U, // ADDME
|
|
0U, // ADDME8
|
|
0U, // ADDME8O
|
|
0U, // ADDME8O_rec
|
|
0U, // ADDME8_rec
|
|
0U, // ADDMEO
|
|
0U, // ADDMEO_rec
|
|
0U, // ADDME_rec
|
|
0U, // ADDPCIS
|
|
0U, // ADDZE
|
|
0U, // ADDZE8
|
|
0U, // ADDZE8O
|
|
0U, // ADDZE8O_rec
|
|
0U, // ADDZE8_rec
|
|
0U, // ADDZEO
|
|
0U, // ADDZEO_rec
|
|
0U, // ADDZE_rec
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
144U, // AND
|
|
144U, // AND8
|
|
144U, // AND8_rec
|
|
144U, // ANDC
|
|
144U, // ANDC8
|
|
144U, // ANDC8_rec
|
|
144U, // ANDC_rec
|
|
20U, // ANDI8_rec
|
|
20U, // ANDIS8_rec
|
|
20U, // ANDIS_rec
|
|
20U, // ANDI_rec
|
|
0U, // ANDI_rec_1_EQ_BIT
|
|
0U, // ANDI_rec_1_EQ_BIT8
|
|
0U, // ANDI_rec_1_GT_BIT
|
|
0U, // ANDI_rec_1_GT_BIT8
|
|
144U, // AND_rec
|
|
1U, // ATOMIC_CMP_SWAP_I16
|
|
1U, // ATOMIC_CMP_SWAP_I32
|
|
0U, // ATOMIC_CMP_SWAP_I64
|
|
0U, // ATOMIC_CMP_SWAP_I8
|
|
0U, // ATOMIC_LOAD_ADD_I16
|
|
0U, // ATOMIC_LOAD_ADD_I32
|
|
0U, // ATOMIC_LOAD_ADD_I64
|
|
0U, // ATOMIC_LOAD_ADD_I8
|
|
0U, // ATOMIC_LOAD_AND_I16
|
|
0U, // ATOMIC_LOAD_AND_I32
|
|
0U, // ATOMIC_LOAD_AND_I64
|
|
0U, // ATOMIC_LOAD_AND_I8
|
|
0U, // ATOMIC_LOAD_MAX_I16
|
|
0U, // ATOMIC_LOAD_MAX_I32
|
|
0U, // ATOMIC_LOAD_MAX_I64
|
|
0U, // ATOMIC_LOAD_MAX_I8
|
|
0U, // ATOMIC_LOAD_MIN_I16
|
|
0U, // ATOMIC_LOAD_MIN_I32
|
|
0U, // ATOMIC_LOAD_MIN_I64
|
|
0U, // ATOMIC_LOAD_MIN_I8
|
|
0U, // ATOMIC_LOAD_NAND_I16
|
|
0U, // ATOMIC_LOAD_NAND_I32
|
|
0U, // ATOMIC_LOAD_NAND_I64
|
|
0U, // ATOMIC_LOAD_NAND_I8
|
|
0U, // ATOMIC_LOAD_OR_I16
|
|
0U, // ATOMIC_LOAD_OR_I32
|
|
0U, // ATOMIC_LOAD_OR_I64
|
|
0U, // ATOMIC_LOAD_OR_I8
|
|
0U, // ATOMIC_LOAD_SUB_I16
|
|
0U, // ATOMIC_LOAD_SUB_I32
|
|
0U, // ATOMIC_LOAD_SUB_I64
|
|
0U, // ATOMIC_LOAD_SUB_I8
|
|
0U, // ATOMIC_LOAD_UMAX_I16
|
|
0U, // ATOMIC_LOAD_UMAX_I32
|
|
0U, // ATOMIC_LOAD_UMAX_I64
|
|
0U, // ATOMIC_LOAD_UMAX_I8
|
|
0U, // ATOMIC_LOAD_UMIN_I16
|
|
0U, // ATOMIC_LOAD_UMIN_I32
|
|
0U, // ATOMIC_LOAD_UMIN_I64
|
|
0U, // ATOMIC_LOAD_UMIN_I8
|
|
0U, // ATOMIC_LOAD_XOR_I16
|
|
0U, // ATOMIC_LOAD_XOR_I32
|
|
0U, // ATOMIC_LOAD_XOR_I64
|
|
0U, // ATOMIC_LOAD_XOR_I8
|
|
0U, // ATOMIC_SWAP_I16
|
|
0U, // ATOMIC_SWAP_I32
|
|
0U, // ATOMIC_SWAP_I64
|
|
0U, // ATOMIC_SWAP_I8
|
|
0U, // ATTN
|
|
0U, // B
|
|
0U, // BA
|
|
0U, // BC
|
|
0U, // BCC
|
|
0U, // BCCA
|
|
0U, // BCCCTR
|
|
0U, // BCCCTR8
|
|
0U, // BCCCTRL
|
|
0U, // BCCCTRL8
|
|
0U, // BCCL
|
|
0U, // BCCLA
|
|
0U, // BCCLR
|
|
0U, // BCCLRL
|
|
0U, // BCCTR
|
|
0U, // BCCTR8
|
|
0U, // BCCTRL
|
|
0U, // BCCTRL8
|
|
2064U, // BCDADD_rec
|
|
152U, // BCDCFN_rec
|
|
152U, // BCDCFSQ_rec
|
|
152U, // BCDCFZ_rec
|
|
144U, // BCDCPSGN_rec
|
|
0U, // BCDCTN_rec
|
|
0U, // BCDCTSQ_rec
|
|
152U, // BCDCTZ_rec
|
|
152U, // BCDSETSGN_rec
|
|
2064U, // BCDSR_rec
|
|
2064U, // BCDSUB_rec
|
|
2064U, // BCDS_rec
|
|
2064U, // BCDTRUNC_rec
|
|
144U, // BCDUS_rec
|
|
144U, // BCDUTRUNC_rec
|
|
0U, // BCL
|
|
0U, // BCLR
|
|
0U, // BCLRL
|
|
0U, // BCTR
|
|
0U, // BCTR8
|
|
0U, // BCTRL
|
|
0U, // BCTRL8
|
|
0U, // BCTRL8_LDinto_toc
|
|
0U, // BCTRL8_LDinto_toc_RM
|
|
0U, // BCTRL8_RM
|
|
0U, // BCTRL_LWZinto_toc
|
|
0U, // BCTRL_LWZinto_toc_RM
|
|
0U, // BCTRL_RM
|
|
0U, // BL
|
|
0U, // BL8
|
|
0U, // BL8_NOP
|
|
0U, // BL8_NOP_RM
|
|
0U, // BL8_NOP_TLS
|
|
0U, // BL8_NOTOC
|
|
0U, // BL8_NOTOC_RM
|
|
0U, // BL8_NOTOC_TLS
|
|
0U, // BL8_RM
|
|
0U, // BL8_TLS
|
|
0U, // BL8_TLS_
|
|
0U, // BLA
|
|
0U, // BLA8
|
|
0U, // BLA8_NOP
|
|
0U, // BLA8_NOP_RM
|
|
0U, // BLA8_RM
|
|
0U, // BLA_RM
|
|
0U, // BLR
|
|
0U, // BLR8
|
|
0U, // BLRL
|
|
0U, // BL_NOP
|
|
0U, // BL_NOP_RM
|
|
0U, // BL_RM
|
|
0U, // BL_TLS
|
|
144U, // BPERMD
|
|
0U, // BRD
|
|
0U, // BRH
|
|
0U, // BRH8
|
|
144U, // BRINC
|
|
0U, // BRW
|
|
0U, // BRW8
|
|
0U, // CBCDTD
|
|
0U, // CBCDTD8
|
|
0U, // CDTBCD
|
|
0U, // CDTBCD8
|
|
144U, // CFUGED
|
|
0U, // CLRBHRB
|
|
144U, // CMPB
|
|
144U, // CMPB8
|
|
144U, // CMPD
|
|
12U, // CMPDI
|
|
144U, // CMPEQB
|
|
144U, // CMPLD
|
|
20U, // CMPLDI
|
|
144U, // CMPLW
|
|
20U, // CMPLWI
|
|
1040U, // CMPRB
|
|
1040U, // CMPRB8
|
|
144U, // CMPW
|
|
12U, // CMPWI
|
|
0U, // CNTLZD
|
|
144U, // CNTLZDM
|
|
0U, // CNTLZD_rec
|
|
0U, // CNTLZW
|
|
0U, // CNTLZW8
|
|
0U, // CNTLZW8_rec
|
|
0U, // CNTLZW_rec
|
|
0U, // CNTTZD
|
|
144U, // CNTTZDM
|
|
0U, // CNTTZD_rec
|
|
0U, // CNTTZW
|
|
0U, // CNTTZW8
|
|
0U, // CNTTZW8_rec
|
|
0U, // CNTTZW_rec
|
|
0U, // CP_ABORT
|
|
0U, // CP_COPY
|
|
0U, // CP_COPY8
|
|
152U, // CP_PASTE8_rec
|
|
152U, // CP_PASTE_rec
|
|
0U, // CR6SET
|
|
0U, // CR6UNSET
|
|
144U, // CRAND
|
|
144U, // CRANDC
|
|
144U, // CREQV
|
|
144U, // CRNAND
|
|
144U, // CRNOR
|
|
0U, // CRNOT
|
|
144U, // CROR
|
|
144U, // CRORC
|
|
28U, // CRSET
|
|
28U, // CRUNSET
|
|
144U, // CRXOR
|
|
0U, // CTRL_DEP
|
|
144U, // DADD
|
|
144U, // DADDQ
|
|
144U, // DADDQ_rec
|
|
144U, // DADD_rec
|
|
0U, // DARN
|
|
0U, // DCBA
|
|
0U, // DCBF
|
|
0U, // DCBFEP
|
|
0U, // DCBI
|
|
0U, // DCBST
|
|
0U, // DCBSTEP
|
|
0U, // DCBT
|
|
0U, // DCBTEP
|
|
0U, // DCBTST
|
|
0U, // DCBTSTEP
|
|
0U, // DCBZ
|
|
0U, // DCBZEP
|
|
0U, // DCBZL
|
|
0U, // DCBZLEP
|
|
0U, // DCCCI
|
|
0U, // DCFFIX
|
|
0U, // DCFFIXQ
|
|
0U, // DCFFIXQQ
|
|
0U, // DCFFIXQ_rec
|
|
0U, // DCFFIX_rec
|
|
144U, // DCMPO
|
|
144U, // DCMPOQ
|
|
144U, // DCMPU
|
|
144U, // DCMPUQ
|
|
0U, // DCTDP
|
|
0U, // DCTDP_rec
|
|
0U, // DCTFIX
|
|
0U, // DCTFIXQ
|
|
0U, // DCTFIXQQ
|
|
0U, // DCTFIXQ_rec
|
|
0U, // DCTFIX_rec
|
|
0U, // DCTQPQ
|
|
0U, // DCTQPQ_rec
|
|
0U, // DDEDPD
|
|
0U, // DDEDPDQ
|
|
0U, // DDEDPDQ_rec
|
|
0U, // DDEDPD_rec
|
|
144U, // DDIV
|
|
144U, // DDIVQ
|
|
144U, // DDIVQ_rec
|
|
144U, // DDIV_rec
|
|
0U, // DENBCD
|
|
0U, // DENBCDQ
|
|
0U, // DENBCDQ_rec
|
|
0U, // DENBCD_rec
|
|
144U, // DIEX
|
|
144U, // DIEXQ
|
|
144U, // DIEXQ_rec
|
|
144U, // DIEX_rec
|
|
144U, // DIVD
|
|
144U, // DIVDE
|
|
144U, // DIVDEO
|
|
144U, // DIVDEO_rec
|
|
144U, // DIVDEU
|
|
144U, // DIVDEUO
|
|
144U, // DIVDEUO_rec
|
|
144U, // DIVDEU_rec
|
|
144U, // DIVDE_rec
|
|
144U, // DIVDO
|
|
144U, // DIVDO_rec
|
|
144U, // DIVDU
|
|
144U, // DIVDUO
|
|
144U, // DIVDUO_rec
|
|
144U, // DIVDU_rec
|
|
144U, // DIVD_rec
|
|
144U, // DIVW
|
|
144U, // DIVWE
|
|
144U, // DIVWEO
|
|
144U, // DIVWEO_rec
|
|
144U, // DIVWEU
|
|
144U, // DIVWEUO
|
|
144U, // DIVWEUO_rec
|
|
144U, // DIVWEU_rec
|
|
144U, // DIVWE_rec
|
|
144U, // DIVWO
|
|
144U, // DIVWO_rec
|
|
144U, // DIVWU
|
|
144U, // DIVWUO
|
|
144U, // DIVWUO_rec
|
|
144U, // DIVWU_rec
|
|
144U, // DIVW_rec
|
|
0U, // DMMR
|
|
0U, // DMSETDMRZ
|
|
144U, // DMUL
|
|
144U, // DMULQ
|
|
144U, // DMULQ_rec
|
|
144U, // DMUL_rec
|
|
0U, // DMXOR
|
|
32U, // DMXXEXTFDMR256
|
|
0U, // DMXXEXTFDMR512
|
|
0U, // DMXXEXTFDMR512_HI
|
|
32U, // DMXXINSTFDMR256
|
|
272U, // DMXXINSTFDMR512
|
|
400U, // DMXXINSTFDMR512_HI
|
|
1552U, // DQUA
|
|
0U, // DQUAI
|
|
0U, // DQUAIQ
|
|
0U, // DQUAIQ_rec
|
|
0U, // DQUAI_rec
|
|
1552U, // DQUAQ
|
|
1552U, // DQUAQ_rec
|
|
1552U, // DQUA_rec
|
|
0U, // DRDPQ
|
|
0U, // DRDPQ_rec
|
|
0U, // DRINTN
|
|
0U, // DRINTNQ
|
|
0U, // DRINTNQ_rec
|
|
0U, // DRINTN_rec
|
|
0U, // DRINTX
|
|
0U, // DRINTXQ
|
|
0U, // DRINTXQ_rec
|
|
0U, // DRINTX_rec
|
|
1552U, // DRRND
|
|
1552U, // DRRNDQ
|
|
1552U, // DRRNDQ_rec
|
|
1552U, // DRRND_rec
|
|
0U, // DRSP
|
|
0U, // DRSP_rec
|
|
128U, // DSCLI
|
|
128U, // DSCLIQ
|
|
128U, // DSCLIQ_rec
|
|
128U, // DSCLI_rec
|
|
128U, // DSCRI
|
|
128U, // DSCRIQ
|
|
128U, // DSCRIQ_rec
|
|
128U, // DSCRI_rec
|
|
0U, // DSS
|
|
0U, // DSSALL
|
|
36U, // DST
|
|
36U, // DST64
|
|
36U, // DSTST
|
|
36U, // DSTST64
|
|
36U, // DSTSTT
|
|
36U, // DSTSTT64
|
|
36U, // DSTT
|
|
36U, // DSTT64
|
|
144U, // DSUB
|
|
144U, // DSUBQ
|
|
144U, // DSUBQ_rec
|
|
144U, // DSUB_rec
|
|
128U, // DTSTDC
|
|
128U, // DTSTDCQ
|
|
128U, // DTSTDG
|
|
128U, // DTSTDGQ
|
|
144U, // DTSTEX
|
|
144U, // DTSTEXQ
|
|
144U, // DTSTSF
|
|
0U, // DTSTSFI
|
|
0U, // DTSTSFIQ
|
|
144U, // DTSTSFQ
|
|
0U, // DXEX
|
|
0U, // DXEXQ
|
|
0U, // DXEXQ_rec
|
|
0U, // DXEX_rec
|
|
0U, // DYNALLOC
|
|
0U, // DYNALLOC8
|
|
0U, // DYNAREAOFFSET
|
|
0U, // DYNAREAOFFSET8
|
|
0U, // DecreaseCTR8loop
|
|
0U, // DecreaseCTRloop
|
|
0U, // EFDABS
|
|
144U, // EFDADD
|
|
0U, // EFDCFS
|
|
0U, // EFDCFSF
|
|
0U, // EFDCFSI
|
|
0U, // EFDCFSID
|
|
0U, // EFDCFUF
|
|
0U, // EFDCFUI
|
|
0U, // EFDCFUID
|
|
144U, // EFDCMPEQ
|
|
144U, // EFDCMPGT
|
|
144U, // EFDCMPLT
|
|
0U, // EFDCTSF
|
|
0U, // EFDCTSI
|
|
0U, // EFDCTSIDZ
|
|
0U, // EFDCTSIZ
|
|
0U, // EFDCTUF
|
|
0U, // EFDCTUI
|
|
0U, // EFDCTUIDZ
|
|
0U, // EFDCTUIZ
|
|
144U, // EFDDIV
|
|
144U, // EFDMUL
|
|
0U, // EFDNABS
|
|
0U, // EFDNEG
|
|
144U, // EFDSUB
|
|
144U, // EFDTSTEQ
|
|
144U, // EFDTSTGT
|
|
144U, // EFDTSTLT
|
|
0U, // EFSABS
|
|
144U, // EFSADD
|
|
0U, // EFSCFD
|
|
0U, // EFSCFSF
|
|
0U, // EFSCFSI
|
|
0U, // EFSCFUF
|
|
0U, // EFSCFUI
|
|
144U, // EFSCMPEQ
|
|
144U, // EFSCMPGT
|
|
144U, // EFSCMPLT
|
|
0U, // EFSCTSF
|
|
0U, // EFSCTSI
|
|
0U, // EFSCTSIZ
|
|
0U, // EFSCTUF
|
|
0U, // EFSCTUI
|
|
0U, // EFSCTUIZ
|
|
144U, // EFSDIV
|
|
144U, // EFSMUL
|
|
0U, // EFSNABS
|
|
0U, // EFSNEG
|
|
144U, // EFSSUB
|
|
144U, // EFSTSTEQ
|
|
144U, // EFSTSTGT
|
|
144U, // EFSTSTLT
|
|
0U, // EH_SjLj_LongJmp32
|
|
0U, // EH_SjLj_LongJmp64
|
|
0U, // EH_SjLj_SetJmp32
|
|
0U, // EH_SjLj_SetJmp64
|
|
0U, // EH_SjLj_Setup
|
|
144U, // EQV
|
|
144U, // EQV8
|
|
144U, // EQV8_rec
|
|
144U, // EQV_rec
|
|
0U, // EVABS
|
|
168U, // EVADDIW
|
|
0U, // EVADDSMIAAW
|
|
0U, // EVADDSSIAAW
|
|
0U, // EVADDUMIAAW
|
|
0U, // EVADDUSIAAW
|
|
144U, // EVADDW
|
|
144U, // EVAND
|
|
144U, // EVANDC
|
|
144U, // EVCMPEQ
|
|
144U, // EVCMPGTS
|
|
144U, // EVCMPGTU
|
|
144U, // EVCMPLTS
|
|
144U, // EVCMPLTU
|
|
0U, // EVCNTLSW
|
|
0U, // EVCNTLZW
|
|
144U, // EVDIVWS
|
|
144U, // EVDIVWU
|
|
144U, // EVEQV
|
|
0U, // EVEXTSB
|
|
0U, // EVEXTSH
|
|
0U, // EVFSABS
|
|
144U, // EVFSADD
|
|
0U, // EVFSCFSF
|
|
0U, // EVFSCFSI
|
|
0U, // EVFSCFUF
|
|
0U, // EVFSCFUI
|
|
144U, // EVFSCMPEQ
|
|
144U, // EVFSCMPGT
|
|
144U, // EVFSCMPLT
|
|
0U, // EVFSCTSF
|
|
0U, // EVFSCTSI
|
|
0U, // EVFSCTSIZ
|
|
0U, // EVFSCTUF
|
|
0U, // EVFSCTUI
|
|
0U, // EVFSCTUIZ
|
|
144U, // EVFSDIV
|
|
144U, // EVFSMUL
|
|
0U, // EVFSNABS
|
|
0U, // EVFSNEG
|
|
144U, // EVFSSUB
|
|
144U, // EVFSTSTEQ
|
|
144U, // EVFSTSTGT
|
|
144U, // EVFSTSTLT
|
|
0U, // EVLDD
|
|
0U, // EVLDDX
|
|
0U, // EVLDH
|
|
0U, // EVLDHX
|
|
0U, // EVLDW
|
|
0U, // EVLDWX
|
|
0U, // EVLHHESPLAT
|
|
0U, // EVLHHESPLATX
|
|
0U, // EVLHHOSSPLAT
|
|
0U, // EVLHHOSSPLATX
|
|
0U, // EVLHHOUSPLAT
|
|
0U, // EVLHHOUSPLATX
|
|
0U, // EVLWHE
|
|
0U, // EVLWHEX
|
|
0U, // EVLWHOS
|
|
0U, // EVLWHOSX
|
|
0U, // EVLWHOU
|
|
0U, // EVLWHOUX
|
|
0U, // EVLWHSPLAT
|
|
0U, // EVLWHSPLATX
|
|
0U, // EVLWWSPLAT
|
|
0U, // EVLWWSPLATX
|
|
144U, // EVMERGEHI
|
|
144U, // EVMERGEHILO
|
|
144U, // EVMERGELO
|
|
144U, // EVMERGELOHI
|
|
144U, // EVMHEGSMFAA
|
|
144U, // EVMHEGSMFAN
|
|
144U, // EVMHEGSMIAA
|
|
144U, // EVMHEGSMIAN
|
|
144U, // EVMHEGUMIAA
|
|
144U, // EVMHEGUMIAN
|
|
144U, // EVMHESMF
|
|
144U, // EVMHESMFA
|
|
144U, // EVMHESMFAAW
|
|
144U, // EVMHESMFANW
|
|
144U, // EVMHESMI
|
|
144U, // EVMHESMIA
|
|
144U, // EVMHESMIAAW
|
|
144U, // EVMHESMIANW
|
|
144U, // EVMHESSF
|
|
144U, // EVMHESSFA
|
|
144U, // EVMHESSFAAW
|
|
144U, // EVMHESSFANW
|
|
144U, // EVMHESSIAAW
|
|
144U, // EVMHESSIANW
|
|
144U, // EVMHEUMI
|
|
144U, // EVMHEUMIA
|
|
144U, // EVMHEUMIAAW
|
|
144U, // EVMHEUMIANW
|
|
144U, // EVMHEUSIAAW
|
|
144U, // EVMHEUSIANW
|
|
144U, // EVMHOGSMFAA
|
|
144U, // EVMHOGSMFAN
|
|
144U, // EVMHOGSMIAA
|
|
144U, // EVMHOGSMIAN
|
|
144U, // EVMHOGUMIAA
|
|
144U, // EVMHOGUMIAN
|
|
144U, // EVMHOSMF
|
|
144U, // EVMHOSMFA
|
|
144U, // EVMHOSMFAAW
|
|
144U, // EVMHOSMFANW
|
|
144U, // EVMHOSMI
|
|
144U, // EVMHOSMIA
|
|
144U, // EVMHOSMIAAW
|
|
144U, // EVMHOSMIANW
|
|
144U, // EVMHOSSF
|
|
144U, // EVMHOSSFA
|
|
144U, // EVMHOSSFAAW
|
|
144U, // EVMHOSSFANW
|
|
144U, // EVMHOSSIAAW
|
|
144U, // EVMHOSSIANW
|
|
144U, // EVMHOUMI
|
|
144U, // EVMHOUMIA
|
|
144U, // EVMHOUMIAAW
|
|
144U, // EVMHOUMIANW
|
|
144U, // EVMHOUSIAAW
|
|
144U, // EVMHOUSIANW
|
|
0U, // EVMRA
|
|
144U, // EVMWHSMF
|
|
144U, // EVMWHSMFA
|
|
144U, // EVMWHSMI
|
|
144U, // EVMWHSMIA
|
|
144U, // EVMWHSSF
|
|
144U, // EVMWHSSFA
|
|
144U, // EVMWHUMI
|
|
144U, // EVMWHUMIA
|
|
144U, // EVMWLSMIAAW
|
|
144U, // EVMWLSMIANW
|
|
144U, // EVMWLSSIAAW
|
|
144U, // EVMWLSSIANW
|
|
144U, // EVMWLUMI
|
|
144U, // EVMWLUMIA
|
|
144U, // EVMWLUMIAAW
|
|
144U, // EVMWLUMIANW
|
|
144U, // EVMWLUSIAAW
|
|
144U, // EVMWLUSIANW
|
|
144U, // EVMWSMF
|
|
144U, // EVMWSMFA
|
|
144U, // EVMWSMFAA
|
|
144U, // EVMWSMFAN
|
|
144U, // EVMWSMI
|
|
144U, // EVMWSMIA
|
|
144U, // EVMWSMIAA
|
|
144U, // EVMWSMIAN
|
|
144U, // EVMWSSF
|
|
144U, // EVMWSSFA
|
|
144U, // EVMWSSFAA
|
|
144U, // EVMWSSFAN
|
|
144U, // EVMWUMI
|
|
144U, // EVMWUMIA
|
|
144U, // EVMWUMIAA
|
|
144U, // EVMWUMIAN
|
|
144U, // EVNAND
|
|
0U, // EVNEG
|
|
144U, // EVNOR
|
|
144U, // EVOR
|
|
144U, // EVORC
|
|
144U, // EVRLW
|
|
132U, // EVRLWI
|
|
0U, // EVRNDW
|
|
1U, // EVSEL
|
|
144U, // EVSLW
|
|
132U, // EVSLWI
|
|
0U, // EVSPLATFI
|
|
0U, // EVSPLATI
|
|
132U, // EVSRWIS
|
|
132U, // EVSRWIU
|
|
144U, // EVSRWS
|
|
144U, // EVSRWU
|
|
0U, // EVSTDD
|
|
0U, // EVSTDDX
|
|
0U, // EVSTDH
|
|
0U, // EVSTDHX
|
|
0U, // EVSTDW
|
|
0U, // EVSTDWX
|
|
0U, // EVSTWHE
|
|
0U, // EVSTWHEX
|
|
0U, // EVSTWHO
|
|
0U, // EVSTWHOX
|
|
0U, // EVSTWWE
|
|
0U, // EVSTWWEX
|
|
0U, // EVSTWWO
|
|
0U, // EVSTWWOX
|
|
0U, // EVSUBFSMIAAW
|
|
0U, // EVSUBFSSIAAW
|
|
0U, // EVSUBFUMIAAW
|
|
0U, // EVSUBFUSIAAW
|
|
144U, // EVSUBFW
|
|
144U, // EVSUBIFW
|
|
144U, // EVXOR
|
|
0U, // EXTSB
|
|
0U, // EXTSB8
|
|
0U, // EXTSB8_32_64
|
|
0U, // EXTSB8_rec
|
|
0U, // EXTSB_rec
|
|
0U, // EXTSH
|
|
0U, // EXTSH8
|
|
0U, // EXTSH8_32_64
|
|
0U, // EXTSH8_rec
|
|
0U, // EXTSH_rec
|
|
0U, // EXTSW
|
|
128U, // EXTSWSLI
|
|
128U, // EXTSWSLI_32_64
|
|
128U, // EXTSWSLI_32_64_rec
|
|
128U, // EXTSWSLI_rec
|
|
0U, // EXTSW_32
|
|
0U, // EXTSW_32_64
|
|
0U, // EXTSW_32_64_rec
|
|
0U, // EXTSW_rec
|
|
0U, // EnforceIEIO
|
|
0U, // FABSD
|
|
0U, // FABSD_rec
|
|
0U, // FABSS
|
|
0U, // FABSS_rec
|
|
144U, // FADD
|
|
144U, // FADDS
|
|
144U, // FADDS_rec
|
|
144U, // FADD_rec
|
|
0U, // FADDrtz
|
|
0U, // FCFID
|
|
0U, // FCFIDS
|
|
0U, // FCFIDS_rec
|
|
0U, // FCFIDU
|
|
0U, // FCFIDUS
|
|
0U, // FCFIDUS_rec
|
|
0U, // FCFIDU_rec
|
|
0U, // FCFID_rec
|
|
144U, // FCMPOD
|
|
144U, // FCMPOS
|
|
144U, // FCMPUD
|
|
144U, // FCMPUS
|
|
144U, // FCPSGND
|
|
144U, // FCPSGND_rec
|
|
144U, // FCPSGNS
|
|
144U, // FCPSGNS_rec
|
|
0U, // FCTID
|
|
0U, // FCTIDU
|
|
0U, // FCTIDUZ
|
|
0U, // FCTIDUZ_rec
|
|
0U, // FCTIDU_rec
|
|
0U, // FCTIDZ
|
|
0U, // FCTIDZ_rec
|
|
0U, // FCTID_rec
|
|
0U, // FCTIW
|
|
0U, // FCTIWU
|
|
0U, // FCTIWUZ
|
|
0U, // FCTIWUZ_rec
|
|
0U, // FCTIWU_rec
|
|
0U, // FCTIWZ
|
|
0U, // FCTIWZ_rec
|
|
0U, // FCTIW_rec
|
|
144U, // FDIV
|
|
144U, // FDIVS
|
|
144U, // FDIVS_rec
|
|
144U, // FDIV_rec
|
|
0U, // FENCE
|
|
1040U, // FMADD
|
|
1040U, // FMADDS
|
|
1040U, // FMADDS_rec
|
|
1040U, // FMADD_rec
|
|
0U, // FMR
|
|
0U, // FMR_rec
|
|
1040U, // FMSUB
|
|
1040U, // FMSUBS
|
|
1040U, // FMSUBS_rec
|
|
1040U, // FMSUB_rec
|
|
144U, // FMUL
|
|
144U, // FMULS
|
|
144U, // FMULS_rec
|
|
144U, // FMUL_rec
|
|
0U, // FNABSD
|
|
0U, // FNABSD_rec
|
|
0U, // FNABSS
|
|
0U, // FNABSS_rec
|
|
0U, // FNEGD
|
|
0U, // FNEGD_rec
|
|
0U, // FNEGS
|
|
0U, // FNEGS_rec
|
|
1040U, // FNMADD
|
|
1040U, // FNMADDS
|
|
1040U, // FNMADDS_rec
|
|
1040U, // FNMADD_rec
|
|
1040U, // FNMSUB
|
|
1040U, // FNMSUBS
|
|
1040U, // FNMSUBS_rec
|
|
1040U, // FNMSUB_rec
|
|
0U, // FRE
|
|
0U, // FRES
|
|
0U, // FRES_rec
|
|
0U, // FRE_rec
|
|
0U, // FRIMD
|
|
0U, // FRIMD_rec
|
|
0U, // FRIMS
|
|
0U, // FRIMS_rec
|
|
0U, // FRIND
|
|
0U, // FRIND_rec
|
|
0U, // FRINS
|
|
0U, // FRINS_rec
|
|
0U, // FRIPD
|
|
0U, // FRIPD_rec
|
|
0U, // FRIPS
|
|
0U, // FRIPS_rec
|
|
0U, // FRIZD
|
|
0U, // FRIZD_rec
|
|
0U, // FRIZS
|
|
0U, // FRIZS_rec
|
|
0U, // FRSP
|
|
0U, // FRSP_rec
|
|
0U, // FRSQRTE
|
|
0U, // FRSQRTES
|
|
0U, // FRSQRTES_rec
|
|
0U, // FRSQRTE_rec
|
|
1040U, // FSELD
|
|
1040U, // FSELD_rec
|
|
1040U, // FSELS
|
|
1040U, // FSELS_rec
|
|
0U, // FSQRT
|
|
0U, // FSQRTS
|
|
0U, // FSQRTS_rec
|
|
0U, // FSQRT_rec
|
|
144U, // FSUB
|
|
144U, // FSUBS
|
|
144U, // FSUBS_rec
|
|
144U, // FSUB_rec
|
|
144U, // FTDIV
|
|
0U, // FTSQRT
|
|
0U, // GETtlsADDR
|
|
0U, // GETtlsADDR32
|
|
0U, // GETtlsADDR32AIX
|
|
0U, // GETtlsADDR64AIX
|
|
0U, // GETtlsADDRPCREL
|
|
0U, // GETtlsTpointer32AIX
|
|
0U, // GETtlsldADDR
|
|
0U, // GETtlsldADDR32
|
|
0U, // GETtlsldADDRPCREL
|
|
0U, // HASHCHK
|
|
0U, // HASHCHK8
|
|
0U, // HASHCHKP
|
|
0U, // HASHCHKP8
|
|
0U, // HASHST
|
|
0U, // HASHST8
|
|
0U, // HASHSTP
|
|
0U, // HASHSTP8
|
|
0U, // HRFID
|
|
0U, // ICBI
|
|
0U, // ICBIEP
|
|
0U, // ICBLC
|
|
0U, // ICBLQ
|
|
0U, // ICBT
|
|
0U, // ICBTLS
|
|
0U, // ICCCI
|
|
1040U, // ISEL
|
|
1040U, // ISEL8
|
|
0U, // ISYNC
|
|
0U, // LA
|
|
0U, // LA8
|
|
0U, // LBARX
|
|
2U, // LBARXL
|
|
0U, // LBEPX
|
|
0U, // LBZ
|
|
0U, // LBZ8
|
|
144U, // LBZCIX
|
|
0U, // LBZU
|
|
0U, // LBZU8
|
|
0U, // LBZUX
|
|
0U, // LBZUX8
|
|
0U, // LBZX
|
|
0U, // LBZX8
|
|
144U, // LBZXTLS
|
|
144U, // LBZXTLS_
|
|
144U, // LBZXTLS_32
|
|
0U, // LD
|
|
0U, // LDARX
|
|
2U, // LDARXL
|
|
132U, // LDAT
|
|
0U, // LDBRX
|
|
144U, // LDCIX
|
|
0U, // LDU
|
|
0U, // LDUX
|
|
0U, // LDX
|
|
144U, // LDXTLS
|
|
144U, // LDXTLS_
|
|
0U, // LDgotTprelL
|
|
0U, // LDgotTprelL32
|
|
0U, // LDtoc
|
|
0U, // LDtocBA
|
|
0U, // LDtocCPT
|
|
0U, // LDtocJTI
|
|
0U, // LDtocL
|
|
0U, // LFD
|
|
0U, // LFDEPX
|
|
0U, // LFDU
|
|
0U, // LFDUX
|
|
0U, // LFDX
|
|
144U, // LFDXTLS
|
|
144U, // LFDXTLS_
|
|
0U, // LFIWAX
|
|
0U, // LFIWZX
|
|
0U, // LFS
|
|
0U, // LFSU
|
|
0U, // LFSUX
|
|
0U, // LFSX
|
|
144U, // LFSXTLS
|
|
144U, // LFSXTLS_
|
|
0U, // LHA
|
|
0U, // LHA8
|
|
0U, // LHARX
|
|
2U, // LHARXL
|
|
0U, // LHAU
|
|
0U, // LHAU8
|
|
0U, // LHAUX
|
|
0U, // LHAUX8
|
|
0U, // LHAX
|
|
0U, // LHAX8
|
|
144U, // LHAXTLS
|
|
144U, // LHAXTLS_
|
|
144U, // LHAXTLS_32
|
|
0U, // LHBRX
|
|
0U, // LHBRX8
|
|
0U, // LHEPX
|
|
0U, // LHZ
|
|
0U, // LHZ8
|
|
144U, // LHZCIX
|
|
0U, // LHZU
|
|
0U, // LHZU8
|
|
0U, // LHZUX
|
|
0U, // LHZUX8
|
|
0U, // LHZX
|
|
0U, // LHZX8
|
|
144U, // LHZXTLS
|
|
144U, // LHZXTLS_
|
|
144U, // LHZXTLS_32
|
|
0U, // LMW
|
|
0U, // LQ
|
|
0U, // LQARX
|
|
2U, // LQARXL
|
|
0U, // LQX_PSEUDO
|
|
132U, // LSWI
|
|
0U, // LVEBX
|
|
0U, // LVEHX
|
|
0U, // LVEWX
|
|
0U, // LVSL
|
|
0U, // LVSR
|
|
0U, // LVX
|
|
0U, // LVXL
|
|
0U, // LWA
|
|
0U, // LWARX
|
|
2U, // LWARXL
|
|
132U, // LWAT
|
|
0U, // LWAUX
|
|
0U, // LWAX
|
|
144U, // LWAXTLS
|
|
144U, // LWAXTLS_
|
|
144U, // LWAXTLS_32
|
|
0U, // LWAX_32
|
|
0U, // LWA_32
|
|
0U, // LWBRX
|
|
0U, // LWBRX8
|
|
0U, // LWEPX
|
|
0U, // LWZ
|
|
0U, // LWZ8
|
|
144U, // LWZCIX
|
|
0U, // LWZU
|
|
0U, // LWZU8
|
|
0U, // LWZUX
|
|
0U, // LWZUX8
|
|
0U, // LWZX
|
|
0U, // LWZX8
|
|
144U, // LWZXTLS
|
|
144U, // LWZXTLS_
|
|
144U, // LWZXTLS_32
|
|
0U, // LWZtoc
|
|
0U, // LWZtocL
|
|
0U, // LXSD
|
|
0U, // LXSDX
|
|
0U, // LXSIBZX
|
|
0U, // LXSIHZX
|
|
0U, // LXSIWAX
|
|
0U, // LXSIWZX
|
|
0U, // LXSSP
|
|
0U, // LXSSPX
|
|
0U, // LXV
|
|
0U, // LXVB16X
|
|
0U, // LXVD2X
|
|
0U, // LXVDSX
|
|
0U, // LXVH8X
|
|
0U, // LXVKQ
|
|
144U, // LXVL
|
|
144U, // LXVLL
|
|
0U, // LXVP
|
|
144U, // LXVPRL
|
|
144U, // LXVPRLL
|
|
0U, // LXVPX
|
|
0U, // LXVRBX
|
|
0U, // LXVRDX
|
|
0U, // LXVRHX
|
|
144U, // LXVRL
|
|
144U, // LXVRLL
|
|
0U, // LXVRWX
|
|
0U, // LXVW4X
|
|
0U, // LXVWSX
|
|
0U, // LXVX
|
|
1040U, // MADDHD
|
|
1040U, // MADDHDU
|
|
1040U, // MADDLD
|
|
1040U, // MADDLD8
|
|
0U, // MBAR
|
|
0U, // MCRF
|
|
0U, // MCRFS
|
|
0U, // MCRXRX
|
|
0U, // MFBHRBE
|
|
0U, // MFCR
|
|
0U, // MFCR8
|
|
0U, // MFCTR
|
|
0U, // MFCTR8
|
|
0U, // MFDCR
|
|
0U, // MFFS
|
|
0U, // MFFSCDRN
|
|
0U, // MFFSCDRNI
|
|
0U, // MFFSCE
|
|
0U, // MFFSCRN
|
|
0U, // MFFSCRNI
|
|
0U, // MFFSL
|
|
0U, // MFFS_rec
|
|
0U, // MFLR
|
|
0U, // MFLR8
|
|
0U, // MFMSR
|
|
0U, // MFOCRF
|
|
0U, // MFOCRF8
|
|
0U, // MFPMR
|
|
0U, // MFSPR
|
|
0U, // MFSPR8
|
|
0U, // MFSR
|
|
0U, // MFSRIN
|
|
0U, // MFTB
|
|
0U, // MFTB8
|
|
0U, // MFUDSCR
|
|
0U, // MFVRD
|
|
0U, // MFVRSAVE
|
|
0U, // MFVRSAVEv
|
|
0U, // MFVRWZ
|
|
0U, // MFVSCR
|
|
0U, // MFVSRD
|
|
0U, // MFVSRLD
|
|
0U, // MFVSRWZ
|
|
144U, // MODSD
|
|
144U, // MODSW
|
|
144U, // MODUD
|
|
144U, // MODUW
|
|
0U, // MSGSYNC
|
|
0U, // MSYNC
|
|
0U, // MTCRF
|
|
0U, // MTCRF8
|
|
0U, // MTCTR
|
|
0U, // MTCTR8
|
|
0U, // MTCTR8loop
|
|
0U, // MTCTRloop
|
|
0U, // MTDCR
|
|
0U, // MTFSB0
|
|
0U, // MTFSB1
|
|
1048U, // MTFSF
|
|
2U, // MTFSFI
|
|
3U, // MTFSFI_rec
|
|
0U, // MTFSFIb
|
|
1048U, // MTFSF_rec
|
|
0U, // MTFSFb
|
|
0U, // MTLR
|
|
0U, // MTLR8
|
|
0U, // MTMSR
|
|
0U, // MTMSRD
|
|
0U, // MTOCRF
|
|
0U, // MTOCRF8
|
|
0U, // MTPMR
|
|
0U, // MTSPR
|
|
0U, // MTSPR8
|
|
0U, // MTSR
|
|
0U, // MTSRIN
|
|
0U, // MTUDSCR
|
|
0U, // MTVRD
|
|
0U, // MTVRSAVE
|
|
0U, // MTVRSAVEv
|
|
0U, // MTVRWA
|
|
0U, // MTVRWZ
|
|
0U, // MTVSCR
|
|
0U, // MTVSRBM
|
|
0U, // MTVSRBMI
|
|
0U, // MTVSRD
|
|
144U, // MTVSRDD
|
|
0U, // MTVSRDM
|
|
0U, // MTVSRHM
|
|
0U, // MTVSRQM
|
|
0U, // MTVSRWA
|
|
0U, // MTVSRWM
|
|
0U, // MTVSRWS
|
|
0U, // MTVSRWZ
|
|
144U, // MULHD
|
|
144U, // MULHDU
|
|
144U, // MULHDU_rec
|
|
144U, // MULHD_rec
|
|
144U, // MULHW
|
|
144U, // MULHWU
|
|
144U, // MULHWU_rec
|
|
144U, // MULHW_rec
|
|
144U, // MULLD
|
|
144U, // MULLDO
|
|
144U, // MULLDO_rec
|
|
144U, // MULLD_rec
|
|
12U, // MULLI
|
|
12U, // MULLI8
|
|
144U, // MULLW
|
|
144U, // MULLWO
|
|
144U, // MULLWO_rec
|
|
144U, // MULLW_rec
|
|
0U, // MoveGOTtoLR
|
|
0U, // MovePCtoLR
|
|
0U, // MovePCtoLR8
|
|
144U, // NAND
|
|
144U, // NAND8
|
|
144U, // NAND8_rec
|
|
144U, // NAND_rec
|
|
0U, // NAP
|
|
0U, // NEG
|
|
0U, // NEG8
|
|
0U, // NEG8O
|
|
0U, // NEG8O_rec
|
|
0U, // NEG8_rec
|
|
0U, // NEGO
|
|
0U, // NEGO_rec
|
|
0U, // NEG_rec
|
|
0U, // NOP
|
|
0U, // NOP_GT_PWR6
|
|
0U, // NOP_GT_PWR7
|
|
144U, // NOR
|
|
144U, // NOR8
|
|
144U, // NOR8_rec
|
|
144U, // NOR_rec
|
|
144U, // OR
|
|
144U, // OR8
|
|
144U, // OR8_rec
|
|
144U, // ORC
|
|
144U, // ORC8
|
|
144U, // ORC8_rec
|
|
144U, // ORC_rec
|
|
20U, // ORI
|
|
20U, // ORI8
|
|
20U, // ORIS
|
|
20U, // ORIS8
|
|
144U, // OR_rec
|
|
264U, // PADDI
|
|
264U, // PADDI8
|
|
0U, // PADDI8pc
|
|
0U, // PADDIdtprel
|
|
0U, // PADDIpc
|
|
144U, // PDEPD
|
|
144U, // PEXTD
|
|
0U, // PLA
|
|
0U, // PLA8
|
|
0U, // PLA8pc
|
|
0U, // PLApc
|
|
3U, // PLBZ
|
|
3U, // PLBZ8
|
|
0U, // PLBZ8nopc
|
|
0U, // PLBZ8onlypc
|
|
0U, // PLBZ8pc
|
|
0U, // PLBZnopc
|
|
0U, // PLBZonlypc
|
|
0U, // PLBZpc
|
|
3U, // PLD
|
|
0U, // PLDnopc
|
|
0U, // PLDonlypc
|
|
0U, // PLDpc
|
|
3U, // PLFD
|
|
0U, // PLFDnopc
|
|
0U, // PLFDonlypc
|
|
0U, // PLFDpc
|
|
3U, // PLFS
|
|
0U, // PLFSnopc
|
|
0U, // PLFSonlypc
|
|
0U, // PLFSpc
|
|
3U, // PLHA
|
|
3U, // PLHA8
|
|
0U, // PLHA8nopc
|
|
0U, // PLHA8onlypc
|
|
0U, // PLHA8pc
|
|
0U, // PLHAnopc
|
|
0U, // PLHAonlypc
|
|
0U, // PLHApc
|
|
3U, // PLHZ
|
|
3U, // PLHZ8
|
|
0U, // PLHZ8nopc
|
|
0U, // PLHZ8onlypc
|
|
0U, // PLHZ8pc
|
|
0U, // PLHZnopc
|
|
0U, // PLHZonlypc
|
|
0U, // PLHZpc
|
|
0U, // PLI
|
|
0U, // PLI8
|
|
3U, // PLWA
|
|
3U, // PLWA8
|
|
0U, // PLWA8nopc
|
|
0U, // PLWA8onlypc
|
|
0U, // PLWA8pc
|
|
0U, // PLWAnopc
|
|
0U, // PLWAonlypc
|
|
0U, // PLWApc
|
|
3U, // PLWZ
|
|
3U, // PLWZ8
|
|
0U, // PLWZ8nopc
|
|
0U, // PLWZ8onlypc
|
|
0U, // PLWZ8pc
|
|
0U, // PLWZnopc
|
|
0U, // PLWZonlypc
|
|
0U, // PLWZpc
|
|
3U, // PLXSD
|
|
0U, // PLXSDnopc
|
|
0U, // PLXSDonlypc
|
|
0U, // PLXSDpc
|
|
3U, // PLXSSP
|
|
0U, // PLXSSPnopc
|
|
0U, // PLXSSPonlypc
|
|
0U, // PLXSSPpc
|
|
3U, // PLXV
|
|
3U, // PLXVP
|
|
0U, // PLXVPnopc
|
|
0U, // PLXVPonlypc
|
|
0U, // PLXVPpc
|
|
0U, // PLXVnopc
|
|
0U, // PLXVonlypc
|
|
0U, // PLXVpc
|
|
10768U, // PMXVBF16GER2
|
|
52268U, // PMXVBF16GER2NN
|
|
52268U, // PMXVBF16GER2NP
|
|
52268U, // PMXVBF16GER2PN
|
|
52268U, // PMXVBF16GER2PP
|
|
10768U, // PMXVBF16GER2W
|
|
52268U, // PMXVBF16GER2WNN
|
|
52268U, // PMXVBF16GER2WNP
|
|
52268U, // PMXVBF16GER2WPN
|
|
52268U, // PMXVBF16GER2WPP
|
|
10768U, // PMXVF16GER2
|
|
52268U, // PMXVF16GER2NN
|
|
52268U, // PMXVF16GER2NP
|
|
52268U, // PMXVF16GER2PN
|
|
52268U, // PMXVF16GER2PP
|
|
10768U, // PMXVF16GER2W
|
|
52268U, // PMXVF16GER2WNN
|
|
52268U, // PMXVF16GER2WNP
|
|
52268U, // PMXVF16GER2WPN
|
|
52268U, // PMXVF16GER2WPP
|
|
10768U, // PMXVF32GER
|
|
19500U, // PMXVF32GERNN
|
|
19500U, // PMXVF32GERNP
|
|
19500U, // PMXVF32GERPN
|
|
19500U, // PMXVF32GERPP
|
|
10768U, // PMXVF32GERW
|
|
19500U, // PMXVF32GERWNN
|
|
19500U, // PMXVF32GERWNP
|
|
19500U, // PMXVF32GERWPN
|
|
19500U, // PMXVF32GERWPP
|
|
43536U, // PMXVF64GER
|
|
27692U, // PMXVF64GERNN
|
|
27692U, // PMXVF64GERNP
|
|
27692U, // PMXVF64GERPN
|
|
27692U, // PMXVF64GERPP
|
|
43536U, // PMXVF64GERW
|
|
27692U, // PMXVF64GERWNN
|
|
27692U, // PMXVF64GERWNP
|
|
27692U, // PMXVF64GERWPN
|
|
27692U, // PMXVF64GERWPP
|
|
10768U, // PMXVI16GER2
|
|
52268U, // PMXVI16GER2PP
|
|
10768U, // PMXVI16GER2S
|
|
52268U, // PMXVI16GER2SPP
|
|
10768U, // PMXVI16GER2SW
|
|
52268U, // PMXVI16GER2SWPP
|
|
10768U, // PMXVI16GER2W
|
|
52268U, // PMXVI16GER2WPP
|
|
10768U, // PMXVI4GER8
|
|
52268U, // PMXVI4GER8PP
|
|
10768U, // PMXVI4GER8W
|
|
52268U, // PMXVI4GER8WPP
|
|
10768U, // PMXVI8GER4
|
|
52268U, // PMXVI8GER4PP
|
|
52268U, // PMXVI8GER4SPP
|
|
10768U, // PMXVI8GER4W
|
|
52268U, // PMXVI8GER4WPP
|
|
52268U, // PMXVI8GER4WSPP
|
|
0U, // POPCNTB
|
|
0U, // POPCNTB8
|
|
0U, // POPCNTD
|
|
0U, // POPCNTW
|
|
0U, // PPC32GOT
|
|
0U, // PPC32PICGOT
|
|
0U, // PREPARE_PROBED_ALLOCA_32
|
|
0U, // PREPARE_PROBED_ALLOCA_64
|
|
0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32
|
|
0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
|
|
0U, // PROBED_ALLOCA_32
|
|
0U, // PROBED_ALLOCA_64
|
|
0U, // PROBED_STACKALLOC_32
|
|
0U, // PROBED_STACKALLOC_64
|
|
0U, // PSC_DCBZL
|
|
0U, // PSQ_L
|
|
0U, // PSQ_LU
|
|
10256U, // PSQ_LUX
|
|
10256U, // PSQ_LX
|
|
0U, // PSQ_ST
|
|
0U, // PSQ_STU
|
|
10256U, // PSQ_STUX
|
|
10256U, // PSQ_STX
|
|
3U, // PSTB
|
|
3U, // PSTB8
|
|
0U, // PSTB8nopc
|
|
0U, // PSTB8onlypc
|
|
0U, // PSTB8pc
|
|
0U, // PSTBnopc
|
|
0U, // PSTBonlypc
|
|
0U, // PSTBpc
|
|
3U, // PSTD
|
|
0U, // PSTDnopc
|
|
0U, // PSTDonlypc
|
|
0U, // PSTDpc
|
|
3U, // PSTFD
|
|
0U, // PSTFDnopc
|
|
0U, // PSTFDonlypc
|
|
0U, // PSTFDpc
|
|
3U, // PSTFS
|
|
0U, // PSTFSnopc
|
|
0U, // PSTFSonlypc
|
|
0U, // PSTFSpc
|
|
3U, // PSTH
|
|
3U, // PSTH8
|
|
0U, // PSTH8nopc
|
|
0U, // PSTH8onlypc
|
|
0U, // PSTH8pc
|
|
0U, // PSTHnopc
|
|
0U, // PSTHonlypc
|
|
0U, // PSTHpc
|
|
3U, // PSTW
|
|
3U, // PSTW8
|
|
0U, // PSTW8nopc
|
|
0U, // PSTW8onlypc
|
|
0U, // PSTW8pc
|
|
0U, // PSTWnopc
|
|
0U, // PSTWonlypc
|
|
0U, // PSTWpc
|
|
3U, // PSTXSD
|
|
0U, // PSTXSDnopc
|
|
0U, // PSTXSDonlypc
|
|
0U, // PSTXSDpc
|
|
3U, // PSTXSSP
|
|
0U, // PSTXSSPnopc
|
|
0U, // PSTXSSPonlypc
|
|
0U, // PSTXSSPpc
|
|
3U, // PSTXV
|
|
3U, // PSTXVP
|
|
0U, // PSTXVPnopc
|
|
0U, // PSTXVPonlypc
|
|
0U, // PSTXVPpc
|
|
0U, // PSTXVnopc
|
|
0U, // PSTXVonlypc
|
|
0U, // PSTXVpc
|
|
0U, // PS_ABS
|
|
0U, // PS_ABSo
|
|
144U, // PS_ADD
|
|
144U, // PS_ADDo
|
|
144U, // PS_CMPO0
|
|
144U, // PS_CMPO1
|
|
144U, // PS_CMPU0
|
|
144U, // PS_CMPU1
|
|
144U, // PS_DIV
|
|
144U, // PS_DIVo
|
|
1040U, // PS_MADD
|
|
1040U, // PS_MADDS0
|
|
1040U, // PS_MADDS0o
|
|
1040U, // PS_MADDS1
|
|
1040U, // PS_MADDS1o
|
|
1040U, // PS_MADDo
|
|
144U, // PS_MERGE00
|
|
144U, // PS_MERGE00o
|
|
144U, // PS_MERGE01
|
|
144U, // PS_MERGE01o
|
|
144U, // PS_MERGE10
|
|
144U, // PS_MERGE10o
|
|
144U, // PS_MERGE11
|
|
144U, // PS_MERGE11o
|
|
0U, // PS_MR
|
|
0U, // PS_MRo
|
|
1040U, // PS_MSUB
|
|
1040U, // PS_MSUBo
|
|
144U, // PS_MUL
|
|
144U, // PS_MULS0
|
|
144U, // PS_MULS0o
|
|
144U, // PS_MULS1
|
|
144U, // PS_MULS1o
|
|
144U, // PS_MULo
|
|
0U, // PS_NABS
|
|
0U, // PS_NABSo
|
|
0U, // PS_NEG
|
|
0U, // PS_NEGo
|
|
1040U, // PS_NMADD
|
|
1040U, // PS_NMADDo
|
|
1040U, // PS_NMSUB
|
|
1040U, // PS_NMSUBo
|
|
0U, // PS_RES
|
|
0U, // PS_RESo
|
|
0U, // PS_RSQRTE
|
|
0U, // PS_RSQRTEo
|
|
1040U, // PS_SEL
|
|
1040U, // PS_SELo
|
|
144U, // PS_SUB
|
|
144U, // PS_SUBo
|
|
1040U, // PS_SUM0
|
|
1040U, // PS_SUM0o
|
|
1040U, // PS_SUM1
|
|
1040U, // PS_SUM1o
|
|
0U, // PseudoEIEIO
|
|
1552U, // QVALIGNI
|
|
1552U, // QVALIGNIb
|
|
1552U, // QVALIGNIs
|
|
32U, // QVESPLATI
|
|
32U, // QVESPLATIb
|
|
32U, // QVESPLATIs
|
|
0U, // QVFABS
|
|
0U, // QVFABSs
|
|
144U, // QVFADD
|
|
144U, // QVFADDS
|
|
144U, // QVFADDSs
|
|
0U, // QVFCFID
|
|
0U, // QVFCFIDS
|
|
0U, // QVFCFIDU
|
|
0U, // QVFCFIDUS
|
|
0U, // QVFCFIDb
|
|
144U, // QVFCMPEQ
|
|
144U, // QVFCMPEQb
|
|
144U, // QVFCMPEQbs
|
|
144U, // QVFCMPGT
|
|
144U, // QVFCMPGTb
|
|
144U, // QVFCMPGTbs
|
|
144U, // QVFCMPLT
|
|
144U, // QVFCMPLTb
|
|
144U, // QVFCMPLTbs
|
|
144U, // QVFCPSGN
|
|
144U, // QVFCPSGNs
|
|
0U, // QVFCTID
|
|
0U, // QVFCTIDU
|
|
0U, // QVFCTIDUZ
|
|
0U, // QVFCTIDZ
|
|
0U, // QVFCTIDb
|
|
0U, // QVFCTIW
|
|
0U, // QVFCTIWU
|
|
0U, // QVFCTIWUZ
|
|
0U, // QVFCTIWZ
|
|
3600U, // QVFLOGICAL
|
|
3600U, // QVFLOGICALb
|
|
3600U, // QVFLOGICALs
|
|
1040U, // QVFMADD
|
|
4140U, // QVFMADDS
|
|
1040U, // QVFMADDSs
|
|
0U, // QVFMR
|
|
0U, // QVFMRb
|
|
0U, // QVFMRs
|
|
1040U, // QVFMSUB
|
|
4140U, // QVFMSUBS
|
|
1040U, // QVFMSUBSs
|
|
144U, // QVFMUL
|
|
144U, // QVFMULS
|
|
144U, // QVFMULSs
|
|
0U, // QVFNABS
|
|
0U, // QVFNABSs
|
|
0U, // QVFNEG
|
|
0U, // QVFNEGs
|
|
1040U, // QVFNMADD
|
|
4140U, // QVFNMADDS
|
|
1040U, // QVFNMADDSs
|
|
1040U, // QVFNMSUB
|
|
4140U, // QVFNMSUBS
|
|
1040U, // QVFNMSUBSs
|
|
1040U, // QVFPERM
|
|
1040U, // QVFPERMs
|
|
0U, // QVFRE
|
|
0U, // QVFRES
|
|
0U, // QVFRESs
|
|
0U, // QVFRIM
|
|
0U, // QVFRIMs
|
|
0U, // QVFRIN
|
|
0U, // QVFRINs
|
|
0U, // QVFRIP
|
|
0U, // QVFRIPs
|
|
0U, // QVFRIZ
|
|
0U, // QVFRIZs
|
|
0U, // QVFRSP
|
|
0U, // QVFRSPs
|
|
0U, // QVFRSQRTE
|
|
0U, // QVFRSQRTES
|
|
0U, // QVFRSQRTESs
|
|
4140U, // QVFSEL
|
|
4140U, // QVFSELb
|
|
4140U, // QVFSELbb
|
|
4140U, // QVFSELbs
|
|
144U, // QVFSUB
|
|
144U, // QVFSUBS
|
|
144U, // QVFSUBSs
|
|
144U, // QVFTSTNAN
|
|
144U, // QVFTSTNANb
|
|
144U, // QVFTSTNANbs
|
|
4140U, // QVFXMADD
|
|
4140U, // QVFXMADDS
|
|
144U, // QVFXMUL
|
|
144U, // QVFXMULS
|
|
4140U, // QVFXXCPNMADD
|
|
4140U, // QVFXXCPNMADDS
|
|
4140U, // QVFXXMADD
|
|
4140U, // QVFXXMADDS
|
|
4140U, // QVFXXNPMADD
|
|
4140U, // QVFXXNPMADDS
|
|
0U, // QVGPCI
|
|
0U, // QVLFCDUX
|
|
0U, // QVLFCDUXA
|
|
0U, // QVLFCDX
|
|
0U, // QVLFCDXA
|
|
0U, // QVLFCSUX
|
|
0U, // QVLFCSUXA
|
|
0U, // QVLFCSX
|
|
0U, // QVLFCSXA
|
|
0U, // QVLFCSXs
|
|
0U, // QVLFDUX
|
|
0U, // QVLFDUXA
|
|
0U, // QVLFDX
|
|
0U, // QVLFDXA
|
|
0U, // QVLFDXb
|
|
0U, // QVLFIWAX
|
|
0U, // QVLFIWAXA
|
|
0U, // QVLFIWZX
|
|
0U, // QVLFIWZXA
|
|
0U, // QVLFSUX
|
|
0U, // QVLFSUXA
|
|
0U, // QVLFSX
|
|
0U, // QVLFSXA
|
|
0U, // QVLFSXb
|
|
0U, // QVLFSXs
|
|
0U, // QVLPCLDX
|
|
0U, // QVLPCLSX
|
|
0U, // QVLPCLSXint
|
|
0U, // QVLPCRDX
|
|
0U, // QVLPCRSX
|
|
0U, // QVSTFCDUX
|
|
0U, // QVSTFCDUXA
|
|
0U, // QVSTFCDUXI
|
|
0U, // QVSTFCDUXIA
|
|
0U, // QVSTFCDX
|
|
0U, // QVSTFCDXA
|
|
0U, // QVSTFCDXI
|
|
0U, // QVSTFCDXIA
|
|
0U, // QVSTFCSUX
|
|
0U, // QVSTFCSUXA
|
|
0U, // QVSTFCSUXI
|
|
0U, // QVSTFCSUXIA
|
|
0U, // QVSTFCSX
|
|
0U, // QVSTFCSXA
|
|
0U, // QVSTFCSXI
|
|
0U, // QVSTFCSXIA
|
|
0U, // QVSTFCSXs
|
|
0U, // QVSTFDUX
|
|
0U, // QVSTFDUXA
|
|
0U, // QVSTFDUXI
|
|
0U, // QVSTFDUXIA
|
|
0U, // QVSTFDX
|
|
0U, // QVSTFDXA
|
|
0U, // QVSTFDXI
|
|
0U, // QVSTFDXIA
|
|
0U, // QVSTFDXb
|
|
0U, // QVSTFIWX
|
|
0U, // QVSTFIWXA
|
|
0U, // QVSTFSUX
|
|
0U, // QVSTFSUXA
|
|
0U, // QVSTFSUXI
|
|
0U, // QVSTFSUXIA
|
|
0U, // QVSTFSUXs
|
|
0U, // QVSTFSX
|
|
0U, // QVSTFSXA
|
|
0U, // QVSTFSXI
|
|
0U, // QVSTFSXIA
|
|
0U, // QVSTFSXs
|
|
0U, // RESTORE_ACC
|
|
0U, // RESTORE_CR
|
|
0U, // RESTORE_CRBIT
|
|
0U, // RESTORE_QUADWORD
|
|
0U, // RESTORE_UACC
|
|
0U, // RESTORE_WACC
|
|
0U, // RFCI
|
|
0U, // RFDI
|
|
0U, // RFEBB
|
|
0U, // RFI
|
|
0U, // RFID
|
|
0U, // RFMCI
|
|
16U, // RLDCL
|
|
16U, // RLDCL_rec
|
|
16U, // RLDCR
|
|
16U, // RLDCR_rec
|
|
0U, // RLDIC
|
|
0U, // RLDICL
|
|
0U, // RLDICL_32
|
|
0U, // RLDICL_32_64
|
|
0U, // RLDICL_32_rec
|
|
0U, // RLDICL_rec
|
|
0U, // RLDICR
|
|
0U, // RLDICR_32
|
|
0U, // RLDICR_rec
|
|
0U, // RLDIC_rec
|
|
48U, // RLDIMI
|
|
48U, // RLDIMI_rec
|
|
52U, // RLWIMI
|
|
52U, // RLWIMI8
|
|
52U, // RLWIMI8_rec
|
|
52U, // RLWIMI_rec
|
|
41476U, // RLWINM
|
|
41476U, // RLWINM8
|
|
41476U, // RLWINM8_rec
|
|
41476U, // RLWINM_rec
|
|
41488U, // RLWNM
|
|
41488U, // RLWNM8
|
|
41488U, // RLWNM8_rec
|
|
41488U, // RLWNM_rec
|
|
0U, // ReadTB
|
|
0U, // SC
|
|
0U, // SCV
|
|
0U, // SELECT_CC_F16
|
|
0U, // SELECT_CC_F4
|
|
0U, // SELECT_CC_F8
|
|
0U, // SELECT_CC_I4
|
|
0U, // SELECT_CC_I8
|
|
0U, // SELECT_CC_QBRC
|
|
0U, // SELECT_CC_QFRC
|
|
0U, // SELECT_CC_QSRC
|
|
0U, // SELECT_CC_SPE
|
|
0U, // SELECT_CC_SPE4
|
|
0U, // SELECT_CC_VRRC
|
|
0U, // SELECT_CC_VSFRC
|
|
0U, // SELECT_CC_VSRC
|
|
0U, // SELECT_CC_VSSRC
|
|
0U, // SELECT_F16
|
|
0U, // SELECT_F4
|
|
0U, // SELECT_F8
|
|
0U, // SELECT_I4
|
|
0U, // SELECT_I8
|
|
0U, // SELECT_QBRC
|
|
0U, // SELECT_QFRC
|
|
0U, // SELECT_QSRC
|
|
0U, // SELECT_SPE
|
|
0U, // SELECT_SPE4
|
|
0U, // SELECT_VRRC
|
|
0U, // SELECT_VSFRC
|
|
0U, // SELECT_VSRC
|
|
0U, // SELECT_VSSRC
|
|
0U, // SETB
|
|
0U, // SETB8
|
|
0U, // SETBC
|
|
0U, // SETBC8
|
|
0U, // SETBCR
|
|
0U, // SETBCR8
|
|
0U, // SETFLM
|
|
0U, // SETNBC
|
|
0U, // SETNBC8
|
|
0U, // SETNBCR
|
|
0U, // SETNBCR8
|
|
0U, // SETRND
|
|
0U, // SETRNDi
|
|
0U, // SLBFEE_rec
|
|
0U, // SLBIA
|
|
0U, // SLBIE
|
|
0U, // SLBIEG
|
|
0U, // SLBMFEE
|
|
0U, // SLBMFEV
|
|
0U, // SLBMTE
|
|
0U, // SLBSYNC
|
|
144U, // SLD
|
|
144U, // SLD_rec
|
|
144U, // SLW
|
|
144U, // SLW8
|
|
144U, // SLW8_rec
|
|
144U, // SLW_rec
|
|
0U, // SPELWZ
|
|
0U, // SPELWZX
|
|
0U, // SPESTW
|
|
0U, // SPESTWX
|
|
0U, // SPILL_ACC
|
|
0U, // SPILL_CR
|
|
0U, // SPILL_CRBIT
|
|
0U, // SPILL_QUADWORD
|
|
0U, // SPILL_UACC
|
|
0U, // SPILL_WACC
|
|
0U, // SPLIT_QUADWORD
|
|
144U, // SRAD
|
|
128U, // SRADI
|
|
128U, // SRADI_32
|
|
128U, // SRADI_rec
|
|
144U, // SRAD_rec
|
|
144U, // SRAW
|
|
132U, // SRAWI
|
|
132U, // SRAWI_rec
|
|
144U, // SRAW_rec
|
|
144U, // SRD
|
|
144U, // SRD_rec
|
|
144U, // SRW
|
|
144U, // SRW8
|
|
144U, // SRW8_rec
|
|
144U, // SRW_rec
|
|
0U, // STB
|
|
0U, // STB8
|
|
144U, // STBCIX
|
|
0U, // STBCX
|
|
0U, // STBEPX
|
|
0U, // STBU
|
|
0U, // STBU8
|
|
0U, // STBUX
|
|
0U, // STBUX8
|
|
0U, // STBX
|
|
0U, // STBX8
|
|
144U, // STBXTLS
|
|
144U, // STBXTLS_
|
|
144U, // STBXTLS_32
|
|
0U, // STD
|
|
132U, // STDAT
|
|
0U, // STDBRX
|
|
144U, // STDCIX
|
|
0U, // STDCX
|
|
0U, // STDU
|
|
0U, // STDUX
|
|
0U, // STDX
|
|
144U, // STDXTLS
|
|
144U, // STDXTLS_
|
|
0U, // STFD
|
|
0U, // STFDEPX
|
|
0U, // STFDU
|
|
0U, // STFDUX
|
|
0U, // STFDX
|
|
144U, // STFDXTLS
|
|
144U, // STFDXTLS_
|
|
0U, // STFIWX
|
|
0U, // STFS
|
|
0U, // STFSU
|
|
0U, // STFSUX
|
|
0U, // STFSX
|
|
144U, // STFSXTLS
|
|
144U, // STFSXTLS_
|
|
0U, // STH
|
|
0U, // STH8
|
|
0U, // STHBRX
|
|
144U, // STHCIX
|
|
0U, // STHCX
|
|
0U, // STHEPX
|
|
0U, // STHU
|
|
0U, // STHU8
|
|
0U, // STHUX
|
|
0U, // STHUX8
|
|
0U, // STHX
|
|
0U, // STHX8
|
|
144U, // STHXTLS
|
|
144U, // STHXTLS_
|
|
144U, // STHXTLS_32
|
|
0U, // STMW
|
|
0U, // STOP
|
|
0U, // STQ
|
|
0U, // STQCX
|
|
0U, // STQX_PSEUDO
|
|
132U, // STSWI
|
|
0U, // STVEBX
|
|
0U, // STVEHX
|
|
0U, // STVEWX
|
|
0U, // STVX
|
|
0U, // STVXL
|
|
0U, // STW
|
|
0U, // STW8
|
|
132U, // STWAT
|
|
0U, // STWBRX
|
|
144U, // STWCIX
|
|
0U, // STWCX
|
|
0U, // STWEPX
|
|
0U, // STWU
|
|
0U, // STWU8
|
|
0U, // STWUX
|
|
0U, // STWUX8
|
|
0U, // STWX
|
|
0U, // STWX8
|
|
144U, // STWXTLS
|
|
144U, // STWXTLS_
|
|
144U, // STWXTLS_32
|
|
0U, // STXSD
|
|
0U, // STXSDX
|
|
0U, // STXSIBX
|
|
0U, // STXSIBXv
|
|
0U, // STXSIHX
|
|
0U, // STXSIHXv
|
|
0U, // STXSIWX
|
|
0U, // STXSSP
|
|
0U, // STXSSPX
|
|
0U, // STXV
|
|
0U, // STXVB16X
|
|
0U, // STXVD2X
|
|
0U, // STXVH8X
|
|
144U, // STXVL
|
|
144U, // STXVLL
|
|
0U, // STXVP
|
|
144U, // STXVPRL
|
|
144U, // STXVPRLL
|
|
0U, // STXVPX
|
|
0U, // STXVRBX
|
|
0U, // STXVRDX
|
|
0U, // STXVRHX
|
|
144U, // STXVRL
|
|
144U, // STXVRLL
|
|
0U, // STXVRWX
|
|
0U, // STXVW4X
|
|
0U, // STXVX
|
|
144U, // SUBF
|
|
144U, // SUBF8
|
|
144U, // SUBF8O
|
|
144U, // SUBF8O_rec
|
|
144U, // SUBF8_rec
|
|
144U, // SUBFC
|
|
144U, // SUBFC8
|
|
144U, // SUBFC8O
|
|
144U, // SUBFC8O_rec
|
|
144U, // SUBFC8_rec
|
|
144U, // SUBFCO
|
|
144U, // SUBFCO_rec
|
|
144U, // SUBFC_rec
|
|
144U, // SUBFE
|
|
144U, // SUBFE8
|
|
144U, // SUBFE8O
|
|
144U, // SUBFE8O_rec
|
|
144U, // SUBFE8_rec
|
|
144U, // SUBFEO
|
|
144U, // SUBFEO_rec
|
|
144U, // SUBFE_rec
|
|
12U, // SUBFIC
|
|
12U, // SUBFIC8
|
|
0U, // SUBFME
|
|
0U, // SUBFME8
|
|
0U, // SUBFME8O
|
|
0U, // SUBFME8O_rec
|
|
0U, // SUBFME8_rec
|
|
0U, // SUBFMEO
|
|
0U, // SUBFMEO_rec
|
|
0U, // SUBFME_rec
|
|
144U, // SUBFO
|
|
144U, // SUBFO_rec
|
|
0U, // SUBFUS
|
|
0U, // SUBFUS_rec
|
|
0U, // SUBFZE
|
|
0U, // SUBFZE8
|
|
0U, // SUBFZE8O
|
|
0U, // SUBFZE8O_rec
|
|
0U, // SUBFZE8_rec
|
|
0U, // SUBFZEO
|
|
0U, // SUBFZEO_rec
|
|
0U, // SUBFZE_rec
|
|
144U, // SUBF_rec
|
|
0U, // SYNC
|
|
0U, // SYNCP10
|
|
0U, // TABORT
|
|
144U, // TABORTDC
|
|
132U, // TABORTDCI
|
|
144U, // TABORTWC
|
|
132U, // TABORTWCI
|
|
0U, // TAILB
|
|
0U, // TAILB8
|
|
0U, // TAILBA
|
|
0U, // TAILBA8
|
|
0U, // TAILBCTR
|
|
0U, // TAILBCTR8
|
|
0U, // TBEGIN
|
|
0U, // TBEGIN_RET
|
|
0U, // TCHECK
|
|
0U, // TCHECK_RET
|
|
0U, // TCRETURNai
|
|
0U, // TCRETURNai8
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNdi8
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNri8
|
|
144U, // TD
|
|
12U, // TDI
|
|
0U, // TEND
|
|
0U, // TLBIA
|
|
0U, // TLBIE
|
|
0U, // TLBIEL
|
|
144U, // TLBILX
|
|
0U, // TLBIVAX
|
|
0U, // TLBLD
|
|
0U, // TLBLI
|
|
0U, // TLBRE
|
|
144U, // TLBRE2
|
|
0U, // TLBSX
|
|
144U, // TLBSX2
|
|
144U, // TLBSX2D
|
|
0U, // TLBSYNC
|
|
0U, // TLBWE
|
|
144U, // TLBWE2
|
|
0U, // TLSGDAIX
|
|
0U, // TLSGDAIX8
|
|
0U, // TRAP
|
|
0U, // TRECHKPT
|
|
0U, // TRECLAIM
|
|
0U, // TSR
|
|
144U, // TW
|
|
12U, // TWI
|
|
0U, // UNENCODED_NOP
|
|
0U, // UpdateGBR
|
|
144U, // VABSDUB
|
|
144U, // VABSDUH
|
|
144U, // VABSDUW
|
|
144U, // VADDCUQ
|
|
144U, // VADDCUW
|
|
1040U, // VADDECUQ
|
|
1040U, // VADDEUQM
|
|
144U, // VADDFP
|
|
144U, // VADDSBS
|
|
144U, // VADDSHS
|
|
144U, // VADDSWS
|
|
144U, // VADDUBM
|
|
144U, // VADDUBS
|
|
144U, // VADDUDM
|
|
144U, // VADDUHM
|
|
144U, // VADDUHS
|
|
144U, // VADDUQM
|
|
144U, // VADDUWM
|
|
144U, // VADDUWS
|
|
144U, // VAND
|
|
144U, // VANDC
|
|
144U, // VAVGSB
|
|
144U, // VAVGSH
|
|
144U, // VAVGSW
|
|
144U, // VAVGUB
|
|
144U, // VAVGUH
|
|
144U, // VAVGUW
|
|
144U, // VBPERMD
|
|
144U, // VBPERMQ
|
|
56U, // VCFSX
|
|
3U, // VCFSX_0
|
|
144U, // VCFUGED
|
|
56U, // VCFUX
|
|
3U, // VCFUX_0
|
|
144U, // VCIPHER
|
|
144U, // VCIPHERLAST
|
|
144U, // VCLRLB
|
|
144U, // VCLRRB
|
|
0U, // VCLZB
|
|
0U, // VCLZD
|
|
144U, // VCLZDM
|
|
0U, // VCLZH
|
|
0U, // VCLZLSBB
|
|
0U, // VCLZW
|
|
144U, // VCMPBFP
|
|
144U, // VCMPBFP_rec
|
|
144U, // VCMPEQFP
|
|
144U, // VCMPEQFP_rec
|
|
144U, // VCMPEQUB
|
|
144U, // VCMPEQUB_rec
|
|
144U, // VCMPEQUD
|
|
144U, // VCMPEQUD_rec
|
|
144U, // VCMPEQUH
|
|
144U, // VCMPEQUH_rec
|
|
144U, // VCMPEQUQ
|
|
144U, // VCMPEQUQ_rec
|
|
144U, // VCMPEQUW
|
|
144U, // VCMPEQUW_rec
|
|
144U, // VCMPGEFP
|
|
144U, // VCMPGEFP_rec
|
|
144U, // VCMPGTFP
|
|
144U, // VCMPGTFP_rec
|
|
144U, // VCMPGTSB
|
|
144U, // VCMPGTSB_rec
|
|
144U, // VCMPGTSD
|
|
144U, // VCMPGTSD_rec
|
|
144U, // VCMPGTSH
|
|
144U, // VCMPGTSH_rec
|
|
144U, // VCMPGTSQ
|
|
144U, // VCMPGTSQ_rec
|
|
144U, // VCMPGTSW
|
|
144U, // VCMPGTSW_rec
|
|
144U, // VCMPGTUB
|
|
144U, // VCMPGTUB_rec
|
|
144U, // VCMPGTUD
|
|
144U, // VCMPGTUD_rec
|
|
144U, // VCMPGTUH
|
|
144U, // VCMPGTUH_rec
|
|
144U, // VCMPGTUQ
|
|
144U, // VCMPGTUQ_rec
|
|
144U, // VCMPGTUW
|
|
144U, // VCMPGTUW_rec
|
|
144U, // VCMPNEB
|
|
144U, // VCMPNEB_rec
|
|
144U, // VCMPNEH
|
|
144U, // VCMPNEH_rec
|
|
144U, // VCMPNEW
|
|
144U, // VCMPNEW_rec
|
|
144U, // VCMPNEZB
|
|
144U, // VCMPNEZB_rec
|
|
144U, // VCMPNEZH
|
|
144U, // VCMPNEZH_rec
|
|
144U, // VCMPNEZW
|
|
144U, // VCMPNEZW_rec
|
|
144U, // VCMPSQ
|
|
144U, // VCMPUQ
|
|
152U, // VCNTMBB
|
|
152U, // VCNTMBD
|
|
152U, // VCNTMBH
|
|
152U, // VCNTMBW
|
|
56U, // VCTSXS
|
|
3U, // VCTSXS_0
|
|
56U, // VCTUXS
|
|
3U, // VCTUXS_0
|
|
0U, // VCTZB
|
|
0U, // VCTZD
|
|
144U, // VCTZDM
|
|
0U, // VCTZH
|
|
0U, // VCTZLSBB
|
|
0U, // VCTZW
|
|
144U, // VDIVESD
|
|
144U, // VDIVESQ
|
|
144U, // VDIVESW
|
|
144U, // VDIVEUD
|
|
144U, // VDIVEUQ
|
|
144U, // VDIVEUW
|
|
144U, // VDIVSD
|
|
144U, // VDIVSQ
|
|
144U, // VDIVSW
|
|
144U, // VDIVUD
|
|
144U, // VDIVUQ
|
|
144U, // VDIVUW
|
|
144U, // VEQV
|
|
0U, // VEXPANDBM
|
|
0U, // VEXPANDDM
|
|
0U, // VEXPANDHM
|
|
0U, // VEXPANDQM
|
|
0U, // VEXPANDWM
|
|
0U, // VEXPTEFP
|
|
1040U, // VEXTDDVLX
|
|
1040U, // VEXTDDVRX
|
|
1040U, // VEXTDUBVLX
|
|
1040U, // VEXTDUBVRX
|
|
1040U, // VEXTDUHVLX
|
|
1040U, // VEXTDUHVRX
|
|
1040U, // VEXTDUWVLX
|
|
1040U, // VEXTDUWVRX
|
|
0U, // VEXTRACTBM
|
|
60U, // VEXTRACTD
|
|
0U, // VEXTRACTDM
|
|
0U, // VEXTRACTHM
|
|
0U, // VEXTRACTQM
|
|
60U, // VEXTRACTUB
|
|
60U, // VEXTRACTUH
|
|
60U, // VEXTRACTUW
|
|
0U, // VEXTRACTWM
|
|
0U, // VEXTSB2D
|
|
0U, // VEXTSB2Ds
|
|
0U, // VEXTSB2W
|
|
0U, // VEXTSB2Ws
|
|
0U, // VEXTSD2Q
|
|
0U, // VEXTSH2D
|
|
0U, // VEXTSH2Ds
|
|
0U, // VEXTSH2W
|
|
0U, // VEXTSH2Ws
|
|
0U, // VEXTSW2D
|
|
0U, // VEXTSW2Ds
|
|
144U, // VEXTUBLX
|
|
144U, // VEXTUBRX
|
|
144U, // VEXTUHLX
|
|
144U, // VEXTUHRX
|
|
144U, // VEXTUWLX
|
|
144U, // VEXTUWRX
|
|
0U, // VGBBD
|
|
64U, // VGNB
|
|
172U, // VINSBLX
|
|
172U, // VINSBRX
|
|
172U, // VINSBVLX
|
|
172U, // VINSBVRX
|
|
0U, // VINSD
|
|
172U, // VINSDLX
|
|
172U, // VINSDRX
|
|
0U, // VINSERTB
|
|
60U, // VINSERTD
|
|
0U, // VINSERTH
|
|
60U, // VINSERTW
|
|
172U, // VINSHLX
|
|
172U, // VINSHRX
|
|
172U, // VINSHVLX
|
|
172U, // VINSHVRX
|
|
0U, // VINSW
|
|
172U, // VINSWLX
|
|
172U, // VINSWRX
|
|
172U, // VINSWVLX
|
|
172U, // VINSWVRX
|
|
0U, // VLOGEFP
|
|
1040U, // VMADDFP
|
|
144U, // VMAXFP
|
|
144U, // VMAXSB
|
|
144U, // VMAXSD
|
|
144U, // VMAXSH
|
|
144U, // VMAXSW
|
|
144U, // VMAXUB
|
|
144U, // VMAXUD
|
|
144U, // VMAXUH
|
|
144U, // VMAXUW
|
|
1040U, // VMHADDSHS
|
|
1040U, // VMHRADDSHS
|
|
144U, // VMINFP
|
|
144U, // VMINSB
|
|
144U, // VMINSD
|
|
144U, // VMINSH
|
|
144U, // VMINSW
|
|
144U, // VMINUB
|
|
144U, // VMINUD
|
|
144U, // VMINUH
|
|
144U, // VMINUW
|
|
1040U, // VMLADDUHM
|
|
144U, // VMODSD
|
|
144U, // VMODSQ
|
|
144U, // VMODSW
|
|
144U, // VMODUD
|
|
144U, // VMODUQ
|
|
144U, // VMODUW
|
|
144U, // VMRGEW
|
|
144U, // VMRGHB
|
|
144U, // VMRGHH
|
|
144U, // VMRGHW
|
|
144U, // VMRGLB
|
|
144U, // VMRGLH
|
|
144U, // VMRGLW
|
|
144U, // VMRGOW
|
|
1040U, // VMSUMCUD
|
|
1040U, // VMSUMMBM
|
|
1040U, // VMSUMSHM
|
|
1040U, // VMSUMSHS
|
|
1040U, // VMSUMUBM
|
|
1040U, // VMSUMUDM
|
|
1040U, // VMSUMUHM
|
|
1040U, // VMSUMUHS
|
|
0U, // VMUL10CUQ
|
|
144U, // VMUL10ECUQ
|
|
144U, // VMUL10EUQ
|
|
0U, // VMUL10UQ
|
|
144U, // VMULESB
|
|
144U, // VMULESD
|
|
144U, // VMULESH
|
|
144U, // VMULESW
|
|
144U, // VMULEUB
|
|
144U, // VMULEUD
|
|
144U, // VMULEUH
|
|
144U, // VMULEUW
|
|
144U, // VMULHSD
|
|
144U, // VMULHSW
|
|
144U, // VMULHUD
|
|
144U, // VMULHUW
|
|
144U, // VMULLD
|
|
144U, // VMULOSB
|
|
144U, // VMULOSD
|
|
144U, // VMULOSH
|
|
144U, // VMULOSW
|
|
144U, // VMULOUB
|
|
144U, // VMULOUD
|
|
144U, // VMULOUH
|
|
144U, // VMULOUW
|
|
144U, // VMULUWM
|
|
144U, // VNAND
|
|
144U, // VNCIPHER
|
|
144U, // VNCIPHERLAST
|
|
0U, // VNEGD
|
|
0U, // VNEGW
|
|
1040U, // VNMSUBFP
|
|
144U, // VNOR
|
|
144U, // VOR
|
|
144U, // VORC
|
|
144U, // VPDEPD
|
|
1040U, // VPERM
|
|
1040U, // VPERMR
|
|
1040U, // VPERMXOR
|
|
144U, // VPEXTD
|
|
144U, // VPKPX
|
|
144U, // VPKSDSS
|
|
144U, // VPKSDUS
|
|
144U, // VPKSHSS
|
|
144U, // VPKSHUS
|
|
144U, // VPKSWSS
|
|
144U, // VPKSWUS
|
|
144U, // VPKUDUM
|
|
144U, // VPKUDUS
|
|
144U, // VPKUHUM
|
|
144U, // VPKUHUS
|
|
144U, // VPKUWUM
|
|
144U, // VPKUWUS
|
|
144U, // VPMSUMB
|
|
144U, // VPMSUMD
|
|
144U, // VPMSUMH
|
|
144U, // VPMSUMW
|
|
0U, // VPOPCNTB
|
|
0U, // VPOPCNTD
|
|
0U, // VPOPCNTH
|
|
0U, // VPOPCNTW
|
|
0U, // VPRTYBD
|
|
0U, // VPRTYBQ
|
|
0U, // VPRTYBW
|
|
0U, // VREFP
|
|
0U, // VRFIM
|
|
0U, // VRFIN
|
|
0U, // VRFIP
|
|
0U, // VRFIZ
|
|
144U, // VRLB
|
|
144U, // VRLD
|
|
144U, // VRLDMI
|
|
144U, // VRLDNM
|
|
144U, // VRLH
|
|
144U, // VRLQ
|
|
144U, // VRLQMI
|
|
144U, // VRLQNM
|
|
144U, // VRLW
|
|
144U, // VRLWMI
|
|
144U, // VRLWNM
|
|
0U, // VRSQRTEFP
|
|
0U, // VSBOX
|
|
1040U, // VSEL
|
|
2584U, // VSHASIGMAD
|
|
2584U, // VSHASIGMAW
|
|
144U, // VSL
|
|
144U, // VSLB
|
|
144U, // VSLD
|
|
4624U, // VSLDBI
|
|
2576U, // VSLDOI
|
|
144U, // VSLH
|
|
144U, // VSLO
|
|
144U, // VSLQ
|
|
144U, // VSLV
|
|
144U, // VSLW
|
|
56U, // VSPLTB
|
|
56U, // VSPLTBs
|
|
56U, // VSPLTH
|
|
56U, // VSPLTHs
|
|
0U, // VSPLTISB
|
|
0U, // VSPLTISH
|
|
0U, // VSPLTISW
|
|
56U, // VSPLTW
|
|
144U, // VSR
|
|
144U, // VSRAB
|
|
144U, // VSRAD
|
|
144U, // VSRAH
|
|
144U, // VSRAQ
|
|
144U, // VSRAW
|
|
144U, // VSRB
|
|
144U, // VSRD
|
|
4624U, // VSRDBI
|
|
144U, // VSRH
|
|
144U, // VSRO
|
|
144U, // VSRQ
|
|
144U, // VSRV
|
|
144U, // VSRW
|
|
0U, // VSTRIBL
|
|
0U, // VSTRIBL_rec
|
|
0U, // VSTRIBR
|
|
0U, // VSTRIBR_rec
|
|
0U, // VSTRIHL
|
|
0U, // VSTRIHL_rec
|
|
0U, // VSTRIHR
|
|
0U, // VSTRIHR_rec
|
|
144U, // VSUBCUQ
|
|
144U, // VSUBCUW
|
|
1040U, // VSUBECUQ
|
|
1040U, // VSUBEUQM
|
|
144U, // VSUBFP
|
|
144U, // VSUBSBS
|
|
144U, // VSUBSHS
|
|
144U, // VSUBSWS
|
|
144U, // VSUBUBM
|
|
144U, // VSUBUBS
|
|
144U, // VSUBUDM
|
|
144U, // VSUBUHM
|
|
144U, // VSUBUHS
|
|
144U, // VSUBUQM
|
|
144U, // VSUBUWM
|
|
144U, // VSUBUWS
|
|
144U, // VSUM2SWS
|
|
144U, // VSUM4SBS
|
|
144U, // VSUM4SHS
|
|
144U, // VSUM4UBS
|
|
144U, // VSUMSWS
|
|
0U, // VUPKHPX
|
|
0U, // VUPKHSB
|
|
0U, // VUPKHSH
|
|
0U, // VUPKHSW
|
|
0U, // VUPKLPX
|
|
0U, // VUPKLSB
|
|
0U, // VUPKLSH
|
|
0U, // VUPKLSW
|
|
144U, // VXOR
|
|
28U, // V_SET0
|
|
28U, // V_SET0B
|
|
28U, // V_SET0H
|
|
0U, // V_SETALLONES
|
|
0U, // V_SETALLONESB
|
|
0U, // V_SETALLONESH
|
|
0U, // WAIT
|
|
0U, // WAITP10
|
|
0U, // WRTEE
|
|
0U, // WRTEEI
|
|
144U, // XOR
|
|
144U, // XOR8
|
|
144U, // XOR8_rec
|
|
20U, // XORI
|
|
20U, // XORI8
|
|
20U, // XORIS
|
|
20U, // XORIS8
|
|
144U, // XOR_rec
|
|
0U, // XSABSDP
|
|
0U, // XSABSQP
|
|
144U, // XSADDDP
|
|
144U, // XSADDQP
|
|
144U, // XSADDQPO
|
|
144U, // XSADDSP
|
|
144U, // XSCMPEQDP
|
|
144U, // XSCMPEQQP
|
|
144U, // XSCMPEXPDP
|
|
144U, // XSCMPEXPQP
|
|
144U, // XSCMPGEDP
|
|
144U, // XSCMPGEQP
|
|
144U, // XSCMPGTDP
|
|
144U, // XSCMPGTQP
|
|
144U, // XSCMPODP
|
|
144U, // XSCMPOQP
|
|
144U, // XSCMPUDP
|
|
144U, // XSCMPUQP
|
|
144U, // XSCPSGNDP
|
|
144U, // XSCPSGNQP
|
|
0U, // XSCVDPHP
|
|
0U, // XSCVDPQP
|
|
0U, // XSCVDPSP
|
|
0U, // XSCVDPSPN
|
|
0U, // XSCVDPSXDS
|
|
0U, // XSCVDPSXDSs
|
|
0U, // XSCVDPSXWS
|
|
0U, // XSCVDPSXWSs
|
|
0U, // XSCVDPUXDS
|
|
0U, // XSCVDPUXDSs
|
|
0U, // XSCVDPUXWS
|
|
0U, // XSCVDPUXWSs
|
|
0U, // XSCVHPDP
|
|
0U, // XSCVQPDP
|
|
0U, // XSCVQPDPO
|
|
0U, // XSCVQPSDZ
|
|
0U, // XSCVQPSQZ
|
|
0U, // XSCVQPSWZ
|
|
0U, // XSCVQPUDZ
|
|
0U, // XSCVQPUQZ
|
|
0U, // XSCVQPUWZ
|
|
0U, // XSCVSDQP
|
|
0U, // XSCVSPDP
|
|
0U, // XSCVSPDPN
|
|
0U, // XSCVSQQP
|
|
0U, // XSCVSXDDP
|
|
0U, // XSCVSXDSP
|
|
0U, // XSCVUDQP
|
|
0U, // XSCVUQQP
|
|
0U, // XSCVUXDDP
|
|
0U, // XSCVUXDSP
|
|
144U, // XSDIVDP
|
|
144U, // XSDIVQP
|
|
144U, // XSDIVQPO
|
|
144U, // XSDIVSP
|
|
144U, // XSIEXPDP
|
|
144U, // XSIEXPQP
|
|
172U, // XSMADDADP
|
|
172U, // XSMADDASP
|
|
172U, // XSMADDMDP
|
|
172U, // XSMADDMSP
|
|
172U, // XSMADDQP
|
|
172U, // XSMADDQPO
|
|
144U, // XSMAXCDP
|
|
144U, // XSMAXCQP
|
|
144U, // XSMAXDP
|
|
144U, // XSMAXJDP
|
|
144U, // XSMINCDP
|
|
144U, // XSMINCQP
|
|
144U, // XSMINDP
|
|
144U, // XSMINJDP
|
|
172U, // XSMSUBADP
|
|
172U, // XSMSUBASP
|
|
172U, // XSMSUBMDP
|
|
172U, // XSMSUBMSP
|
|
172U, // XSMSUBQP
|
|
172U, // XSMSUBQPO
|
|
144U, // XSMULDP
|
|
144U, // XSMULQP
|
|
144U, // XSMULQPO
|
|
144U, // XSMULSP
|
|
0U, // XSNABSDP
|
|
0U, // XSNABSDPs
|
|
0U, // XSNABSQP
|
|
0U, // XSNEGDP
|
|
0U, // XSNEGQP
|
|
172U, // XSNMADDADP
|
|
172U, // XSNMADDASP
|
|
172U, // XSNMADDMDP
|
|
172U, // XSNMADDMSP
|
|
172U, // XSNMADDQP
|
|
172U, // XSNMADDQPO
|
|
172U, // XSNMSUBADP
|
|
172U, // XSNMSUBASP
|
|
172U, // XSNMSUBMDP
|
|
172U, // XSNMSUBMSP
|
|
172U, // XSNMSUBQP
|
|
172U, // XSNMSUBQPO
|
|
0U, // XSRDPI
|
|
0U, // XSRDPIC
|
|
0U, // XSRDPIM
|
|
0U, // XSRDPIP
|
|
0U, // XSRDPIZ
|
|
0U, // XSREDP
|
|
0U, // XSRESP
|
|
0U, // XSRQPI
|
|
0U, // XSRQPIX
|
|
0U, // XSRQPXP
|
|
0U, // XSRSP
|
|
0U, // XSRSQRTEDP
|
|
0U, // XSRSQRTESP
|
|
0U, // XSSQRTDP
|
|
0U, // XSSQRTQP
|
|
0U, // XSSQRTQPO
|
|
0U, // XSSQRTSP
|
|
144U, // XSSUBDP
|
|
144U, // XSSUBQP
|
|
144U, // XSSUBQPO
|
|
144U, // XSSUBSP
|
|
144U, // XSTDIVDP
|
|
0U, // XSTSQRTDP
|
|
68U, // XSTSTDCDP
|
|
68U, // XSTSTDCQP
|
|
68U, // XSTSTDCSP
|
|
0U, // XSXEXPDP
|
|
0U, // XSXEXPQP
|
|
0U, // XSXSIGDP
|
|
0U, // XSXSIGQP
|
|
0U, // XVABSDP
|
|
0U, // XVABSSP
|
|
144U, // XVADDDP
|
|
144U, // XVADDSP
|
|
144U, // XVBF16GER2
|
|
172U, // XVBF16GER2NN
|
|
172U, // XVBF16GER2NP
|
|
172U, // XVBF16GER2PN
|
|
172U, // XVBF16GER2PP
|
|
144U, // XVBF16GER2W
|
|
172U, // XVBF16GER2WNN
|
|
172U, // XVBF16GER2WNP
|
|
172U, // XVBF16GER2WPN
|
|
172U, // XVBF16GER2WPP
|
|
144U, // XVCMPEQDP
|
|
144U, // XVCMPEQDP_rec
|
|
144U, // XVCMPEQSP
|
|
144U, // XVCMPEQSP_rec
|
|
144U, // XVCMPGEDP
|
|
144U, // XVCMPGEDP_rec
|
|
144U, // XVCMPGESP
|
|
144U, // XVCMPGESP_rec
|
|
144U, // XVCMPGTDP
|
|
144U, // XVCMPGTDP_rec
|
|
144U, // XVCMPGTSP
|
|
144U, // XVCMPGTSP_rec
|
|
144U, // XVCPSGNDP
|
|
144U, // XVCPSGNSP
|
|
0U, // XVCVBF16SPN
|
|
0U, // XVCVDPSP
|
|
0U, // XVCVDPSXDS
|
|
0U, // XVCVDPSXWS
|
|
0U, // XVCVDPUXDS
|
|
0U, // XVCVDPUXWS
|
|
0U, // XVCVHPSP
|
|
0U, // XVCVSPBF16
|
|
0U, // XVCVSPDP
|
|
0U, // XVCVSPHP
|
|
0U, // XVCVSPSXDS
|
|
0U, // XVCVSPSXWS
|
|
0U, // XVCVSPUXDS
|
|
0U, // XVCVSPUXWS
|
|
0U, // XVCVSXDDP
|
|
0U, // XVCVSXDSP
|
|
0U, // XVCVSXWDP
|
|
0U, // XVCVSXWSP
|
|
0U, // XVCVUXDDP
|
|
0U, // XVCVUXDSP
|
|
0U, // XVCVUXWDP
|
|
0U, // XVCVUXWSP
|
|
144U, // XVDIVDP
|
|
144U, // XVDIVSP
|
|
144U, // XVF16GER2
|
|
172U, // XVF16GER2NN
|
|
172U, // XVF16GER2NP
|
|
172U, // XVF16GER2PN
|
|
172U, // XVF16GER2PP
|
|
144U, // XVF16GER2W
|
|
172U, // XVF16GER2WNN
|
|
172U, // XVF16GER2WNP
|
|
172U, // XVF16GER2WPN
|
|
172U, // XVF16GER2WPP
|
|
144U, // XVF32GER
|
|
172U, // XVF32GERNN
|
|
172U, // XVF32GERNP
|
|
172U, // XVF32GERPN
|
|
172U, // XVF32GERPP
|
|
144U, // XVF32GERW
|
|
172U, // XVF32GERWNN
|
|
172U, // XVF32GERWNP
|
|
172U, // XVF32GERWPN
|
|
172U, // XVF32GERWPP
|
|
144U, // XVF64GER
|
|
172U, // XVF64GERNN
|
|
172U, // XVF64GERNP
|
|
172U, // XVF64GERPN
|
|
172U, // XVF64GERPP
|
|
144U, // XVF64GERW
|
|
172U, // XVF64GERWNN
|
|
172U, // XVF64GERWNP
|
|
172U, // XVF64GERWPN
|
|
172U, // XVF64GERWPP
|
|
144U, // XVI16GER2
|
|
172U, // XVI16GER2PP
|
|
144U, // XVI16GER2S
|
|
172U, // XVI16GER2SPP
|
|
144U, // XVI16GER2SW
|
|
172U, // XVI16GER2SWPP
|
|
144U, // XVI16GER2W
|
|
172U, // XVI16GER2WPP
|
|
144U, // XVI4GER8
|
|
172U, // XVI4GER8PP
|
|
144U, // XVI4GER8W
|
|
172U, // XVI4GER8WPP
|
|
144U, // XVI8GER4
|
|
172U, // XVI8GER4PP
|
|
172U, // XVI8GER4SPP
|
|
144U, // XVI8GER4W
|
|
172U, // XVI8GER4WPP
|
|
172U, // XVI8GER4WSPP
|
|
144U, // XVIEXPDP
|
|
144U, // XVIEXPSP
|
|
172U, // XVMADDADP
|
|
172U, // XVMADDASP
|
|
172U, // XVMADDMDP
|
|
172U, // XVMADDMSP
|
|
144U, // XVMAXDP
|
|
144U, // XVMAXSP
|
|
144U, // XVMINDP
|
|
144U, // XVMINSP
|
|
172U, // XVMSUBADP
|
|
172U, // XVMSUBASP
|
|
172U, // XVMSUBMDP
|
|
172U, // XVMSUBMSP
|
|
144U, // XVMULDP
|
|
144U, // XVMULSP
|
|
0U, // XVNABSDP
|
|
0U, // XVNABSSP
|
|
0U, // XVNEGDP
|
|
0U, // XVNEGSP
|
|
172U, // XVNMADDADP
|
|
172U, // XVNMADDASP
|
|
172U, // XVNMADDMDP
|
|
172U, // XVNMADDMSP
|
|
172U, // XVNMSUBADP
|
|
172U, // XVNMSUBASP
|
|
172U, // XVNMSUBMDP
|
|
172U, // XVNMSUBMSP
|
|
0U, // XVRDPI
|
|
0U, // XVRDPIC
|
|
0U, // XVRDPIM
|
|
0U, // XVRDPIP
|
|
0U, // XVRDPIZ
|
|
0U, // XVREDP
|
|
0U, // XVRESP
|
|
0U, // XVRSPI
|
|
0U, // XVRSPIC
|
|
0U, // XVRSPIM
|
|
0U, // XVRSPIP
|
|
0U, // XVRSPIZ
|
|
0U, // XVRSQRTEDP
|
|
0U, // XVRSQRTESP
|
|
0U, // XVSQRTDP
|
|
0U, // XVSQRTSP
|
|
144U, // XVSUBDP
|
|
144U, // XVSUBSP
|
|
144U, // XVTDIVDP
|
|
144U, // XVTDIVSP
|
|
0U, // XVTLSBB
|
|
0U, // XVTSQRTDP
|
|
0U, // XVTSQRTSP
|
|
68U, // XVTSTDCDP
|
|
68U, // XVTSTDCSP
|
|
0U, // XVXEXPDP
|
|
0U, // XVXEXPSP
|
|
0U, // XVXSIGDP
|
|
0U, // XVXSIGSP
|
|
1040U, // XXBLENDVB
|
|
1040U, // XXBLENDVD
|
|
1040U, // XXBLENDVH
|
|
1040U, // XXBLENDVW
|
|
0U, // XXBRD
|
|
0U, // XXBRH
|
|
0U, // XXBRQ
|
|
0U, // XXBRW
|
|
9232U, // XXEVAL
|
|
72U, // XXEXTRACTUW
|
|
76U, // XXGENPCVBM
|
|
76U, // XXGENPCVDM
|
|
76U, // XXGENPCVHM
|
|
76U, // XXGENPCVWM
|
|
80U, // XXINSERTW
|
|
144U, // XXLAND
|
|
144U, // XXLANDC
|
|
144U, // XXLEQV
|
|
28U, // XXLEQVOnes
|
|
144U, // XXLNAND
|
|
144U, // XXLNOR
|
|
144U, // XXLOR
|
|
144U, // XXLORC
|
|
144U, // XXLORf
|
|
144U, // XXLXOR
|
|
28U, // XXLXORdpz
|
|
28U, // XXLXORspz
|
|
28U, // XXLXORz
|
|
0U, // XXMFACC
|
|
0U, // XXMFACCW
|
|
144U, // XXMRGHW
|
|
144U, // XXMRGLW
|
|
0U, // XXMTACC
|
|
0U, // XXMTACCW
|
|
172U, // XXPERM
|
|
1552U, // XXPERMDI
|
|
5160U, // XXPERMDIs
|
|
172U, // XXPERMR
|
|
9232U, // XXPERMX
|
|
1040U, // XXSEL
|
|
0U, // XXSETACCZ
|
|
0U, // XXSETACCZW
|
|
1552U, // XXSLDWI
|
|
5160U, // XXSLDWIs
|
|
0U, // XXSPLTI32DX
|
|
0U, // XXSPLTIB
|
|
0U, // XXSPLTIDP
|
|
0U, // XXSPLTIW
|
|
32U, // XXSPLTW
|
|
32U, // XXSPLTWs
|
|
84U, // gBC
|
|
88U, // gBCA
|
|
0U, // gBCAat
|
|
144U, // gBCCTR
|
|
144U, // gBCCTRL
|
|
84U, // gBCL
|
|
88U, // gBCLA
|
|
0U, // gBCLAat
|
|
144U, // gBCLR
|
|
144U, // gBCLRL
|
|
0U, // gBCLat
|
|
0U, // gBCat
|
|
};
|
|
|
|
static const uint8_t OpInfo2[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_VALUE_LIST
|
|
0U, // DBG_INSTR_REF
|
|
0U, // DBG_PHI
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ATOMIC_CMP_SWAP_I128
|
|
0U, // ATOMIC_LOAD_ADD_I128
|
|
0U, // ATOMIC_LOAD_AND_I128
|
|
0U, // ATOMIC_LOAD_NAND_I128
|
|
0U, // ATOMIC_LOAD_OR_I128
|
|
0U, // ATOMIC_LOAD_SUB_I128
|
|
0U, // ATOMIC_LOAD_XOR_I128
|
|
0U, // ATOMIC_SWAP_I128
|
|
0U, // BUILD_QUADWORD
|
|
0U, // BUILD_UACC
|
|
0U, // CFENCE
|
|
0U, // CFENCE8
|
|
0U, // CLRLSLDI
|
|
0U, // CLRLSLDI_rec
|
|
0U, // CLRLSLWI
|
|
0U, // CLRLSLWI_rec
|
|
0U, // CLRRDI
|
|
0U, // CLRRDI_rec
|
|
0U, // CLRRWI
|
|
0U, // CLRRWI_rec
|
|
0U, // DCBFL
|
|
0U, // DCBFLP
|
|
0U, // DCBFPS
|
|
0U, // DCBFx
|
|
0U, // DCBSTPS
|
|
0U, // DCBTCT
|
|
0U, // DCBTDS
|
|
0U, // DCBTSTCT
|
|
0U, // DCBTSTDS
|
|
0U, // DCBTSTT
|
|
0U, // DCBTSTx
|
|
0U, // DCBTT
|
|
0U, // DCBTx
|
|
0U, // DFLOADf32
|
|
0U, // DFLOADf64
|
|
0U, // DFSTOREf32
|
|
0U, // DFSTOREf64
|
|
0U, // EXTLDI
|
|
0U, // EXTLDI_rec
|
|
0U, // EXTLWI
|
|
0U, // EXTLWI_rec
|
|
0U, // EXTRDI
|
|
0U, // EXTRDI_rec
|
|
0U, // EXTRWI
|
|
0U, // EXTRWI_rec
|
|
0U, // INSLWI
|
|
0U, // INSLWI_rec
|
|
0U, // INSRDI
|
|
0U, // INSRDI_rec
|
|
0U, // INSRWI
|
|
0U, // INSRWI_rec
|
|
0U, // KILL_PAIR
|
|
0U, // LAx
|
|
0U, // LI
|
|
0U, // LI8
|
|
0U, // LIS
|
|
0U, // LIS8
|
|
0U, // LIWAX
|
|
0U, // LIWZX
|
|
0U, // PSUBI
|
|
0U, // RLWIMIbm
|
|
0U, // RLWIMIbm_rec
|
|
0U, // RLWINMbm
|
|
0U, // RLWINMbm_rec
|
|
0U, // RLWNMbm
|
|
0U, // RLWNMbm_rec
|
|
0U, // ROTRDI
|
|
0U, // ROTRDI_rec
|
|
0U, // ROTRWI
|
|
0U, // ROTRWI_rec
|
|
0U, // SLDI
|
|
0U, // SLDI_rec
|
|
0U, // SLWI
|
|
0U, // SLWI_rec
|
|
0U, // SPILLTOVSR_LD
|
|
0U, // SPILLTOVSR_LDX
|
|
0U, // SPILLTOVSR_ST
|
|
0U, // SPILLTOVSR_STX
|
|
0U, // SRDI
|
|
0U, // SRDI_rec
|
|
0U, // SRWI
|
|
0U, // SRWI_rec
|
|
0U, // STIWX
|
|
0U, // SUBI
|
|
0U, // SUBIC
|
|
0U, // SUBIC_rec
|
|
0U, // SUBIS
|
|
0U, // SUBPCIS
|
|
0U, // XFLOADf32
|
|
0U, // XFLOADf64
|
|
0U, // XFSTOREf32
|
|
0U, // XFSTOREf64
|
|
0U, // ADD4
|
|
0U, // ADD4O
|
|
0U, // ADD4O_rec
|
|
0U, // ADD4TLS
|
|
0U, // ADD4_rec
|
|
0U, // ADD8
|
|
0U, // ADD8O
|
|
0U, // ADD8O_rec
|
|
0U, // ADD8TLS
|
|
0U, // ADD8TLS_
|
|
0U, // ADD8_rec
|
|
0U, // ADDC
|
|
0U, // ADDC8
|
|
0U, // ADDC8O
|
|
0U, // ADDC8O_rec
|
|
0U, // ADDC8_rec
|
|
0U, // ADDCO
|
|
0U, // ADDCO_rec
|
|
0U, // ADDC_rec
|
|
0U, // ADDE
|
|
0U, // ADDE8
|
|
0U, // ADDE8O
|
|
0U, // ADDE8O_rec
|
|
0U, // ADDE8_rec
|
|
0U, // ADDEO
|
|
0U, // ADDEO_rec
|
|
0U, // ADDEX
|
|
0U, // ADDEX8
|
|
0U, // ADDE_rec
|
|
0U, // ADDG6S
|
|
0U, // ADDG6S8
|
|
0U, // ADDI
|
|
0U, // ADDI8
|
|
0U, // ADDIC
|
|
0U, // ADDIC8
|
|
0U, // ADDIC_rec
|
|
0U, // ADDIS
|
|
0U, // ADDIS8
|
|
0U, // ADDISdtprelHA
|
|
0U, // ADDISdtprelHA32
|
|
0U, // ADDISgotTprelHA
|
|
0U, // ADDIStlsgdHA
|
|
0U, // ADDIStlsldHA
|
|
0U, // ADDIStocHA
|
|
0U, // ADDIStocHA8
|
|
0U, // ADDIdtprelL
|
|
0U, // ADDIdtprelL32
|
|
0U, // ADDItlsgdL
|
|
0U, // ADDItlsgdL32
|
|
0U, // ADDItlsgdLADDR
|
|
0U, // ADDItlsgdLADDR32
|
|
0U, // ADDItlsldL
|
|
0U, // ADDItlsldL32
|
|
0U, // ADDItlsldLADDR
|
|
0U, // ADDItlsldLADDR32
|
|
0U, // ADDItoc
|
|
0U, // ADDItoc8
|
|
0U, // ADDItocL
|
|
0U, // ADDME
|
|
0U, // ADDME8
|
|
0U, // ADDME8O
|
|
0U, // ADDME8O_rec
|
|
0U, // ADDME8_rec
|
|
0U, // ADDMEO
|
|
0U, // ADDMEO_rec
|
|
0U, // ADDME_rec
|
|
0U, // ADDPCIS
|
|
0U, // ADDZE
|
|
0U, // ADDZE8
|
|
0U, // ADDZE8O
|
|
0U, // ADDZE8O_rec
|
|
0U, // ADDZE8_rec
|
|
0U, // ADDZEO
|
|
0U, // ADDZEO_rec
|
|
0U, // ADDZE_rec
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // AND
|
|
0U, // AND8
|
|
0U, // AND8_rec
|
|
0U, // ANDC
|
|
0U, // ANDC8
|
|
0U, // ANDC8_rec
|
|
0U, // ANDC_rec
|
|
0U, // ANDI8_rec
|
|
0U, // ANDIS8_rec
|
|
0U, // ANDIS_rec
|
|
0U, // ANDI_rec
|
|
0U, // ANDI_rec_1_EQ_BIT
|
|
0U, // ANDI_rec_1_EQ_BIT8
|
|
0U, // ANDI_rec_1_GT_BIT
|
|
0U, // ANDI_rec_1_GT_BIT8
|
|
0U, // AND_rec
|
|
0U, // ATOMIC_CMP_SWAP_I16
|
|
0U, // ATOMIC_CMP_SWAP_I32
|
|
0U, // ATOMIC_CMP_SWAP_I64
|
|
0U, // ATOMIC_CMP_SWAP_I8
|
|
0U, // ATOMIC_LOAD_ADD_I16
|
|
0U, // ATOMIC_LOAD_ADD_I32
|
|
0U, // ATOMIC_LOAD_ADD_I64
|
|
0U, // ATOMIC_LOAD_ADD_I8
|
|
0U, // ATOMIC_LOAD_AND_I16
|
|
0U, // ATOMIC_LOAD_AND_I32
|
|
0U, // ATOMIC_LOAD_AND_I64
|
|
0U, // ATOMIC_LOAD_AND_I8
|
|
0U, // ATOMIC_LOAD_MAX_I16
|
|
0U, // ATOMIC_LOAD_MAX_I32
|
|
0U, // ATOMIC_LOAD_MAX_I64
|
|
0U, // ATOMIC_LOAD_MAX_I8
|
|
0U, // ATOMIC_LOAD_MIN_I16
|
|
0U, // ATOMIC_LOAD_MIN_I32
|
|
0U, // ATOMIC_LOAD_MIN_I64
|
|
0U, // ATOMIC_LOAD_MIN_I8
|
|
0U, // ATOMIC_LOAD_NAND_I16
|
|
0U, // ATOMIC_LOAD_NAND_I32
|
|
0U, // ATOMIC_LOAD_NAND_I64
|
|
0U, // ATOMIC_LOAD_NAND_I8
|
|
0U, // ATOMIC_LOAD_OR_I16
|
|
0U, // ATOMIC_LOAD_OR_I32
|
|
0U, // ATOMIC_LOAD_OR_I64
|
|
0U, // ATOMIC_LOAD_OR_I8
|
|
0U, // ATOMIC_LOAD_SUB_I16
|
|
0U, // ATOMIC_LOAD_SUB_I32
|
|
0U, // ATOMIC_LOAD_SUB_I64
|
|
0U, // ATOMIC_LOAD_SUB_I8
|
|
0U, // ATOMIC_LOAD_UMAX_I16
|
|
0U, // ATOMIC_LOAD_UMAX_I32
|
|
0U, // ATOMIC_LOAD_UMAX_I64
|
|
0U, // ATOMIC_LOAD_UMAX_I8
|
|
0U, // ATOMIC_LOAD_UMIN_I16
|
|
0U, // ATOMIC_LOAD_UMIN_I32
|
|
0U, // ATOMIC_LOAD_UMIN_I64
|
|
0U, // ATOMIC_LOAD_UMIN_I8
|
|
0U, // ATOMIC_LOAD_XOR_I16
|
|
0U, // ATOMIC_LOAD_XOR_I32
|
|
0U, // ATOMIC_LOAD_XOR_I64
|
|
0U, // ATOMIC_LOAD_XOR_I8
|
|
0U, // ATOMIC_SWAP_I16
|
|
0U, // ATOMIC_SWAP_I32
|
|
0U, // ATOMIC_SWAP_I64
|
|
0U, // ATOMIC_SWAP_I8
|
|
0U, // ATTN
|
|
0U, // B
|
|
0U, // BA
|
|
0U, // BC
|
|
0U, // BCC
|
|
0U, // BCCA
|
|
0U, // BCCCTR
|
|
0U, // BCCCTR8
|
|
0U, // BCCCTRL
|
|
0U, // BCCCTRL8
|
|
0U, // BCCL
|
|
0U, // BCCLA
|
|
0U, // BCCLR
|
|
0U, // BCCLRL
|
|
0U, // BCCTR
|
|
0U, // BCCTR8
|
|
0U, // BCCTRL
|
|
0U, // BCCTRL8
|
|
0U, // BCDADD_rec
|
|
0U, // BCDCFN_rec
|
|
0U, // BCDCFSQ_rec
|
|
0U, // BCDCFZ_rec
|
|
0U, // BCDCPSGN_rec
|
|
0U, // BCDCTN_rec
|
|
0U, // BCDCTSQ_rec
|
|
0U, // BCDCTZ_rec
|
|
0U, // BCDSETSGN_rec
|
|
0U, // BCDSR_rec
|
|
0U, // BCDSUB_rec
|
|
0U, // BCDS_rec
|
|
0U, // BCDTRUNC_rec
|
|
0U, // BCDUS_rec
|
|
0U, // BCDUTRUNC_rec
|
|
0U, // BCL
|
|
0U, // BCLR
|
|
0U, // BCLRL
|
|
0U, // BCTR
|
|
0U, // BCTR8
|
|
0U, // BCTRL
|
|
0U, // BCTRL8
|
|
0U, // BCTRL8_LDinto_toc
|
|
0U, // BCTRL8_LDinto_toc_RM
|
|
0U, // BCTRL8_RM
|
|
0U, // BCTRL_LWZinto_toc
|
|
0U, // BCTRL_LWZinto_toc_RM
|
|
0U, // BCTRL_RM
|
|
0U, // BL
|
|
0U, // BL8
|
|
0U, // BL8_NOP
|
|
0U, // BL8_NOP_RM
|
|
0U, // BL8_NOP_TLS
|
|
0U, // BL8_NOTOC
|
|
0U, // BL8_NOTOC_RM
|
|
0U, // BL8_NOTOC_TLS
|
|
0U, // BL8_RM
|
|
0U, // BL8_TLS
|
|
0U, // BL8_TLS_
|
|
0U, // BLA
|
|
0U, // BLA8
|
|
0U, // BLA8_NOP
|
|
0U, // BLA8_NOP_RM
|
|
0U, // BLA8_RM
|
|
0U, // BLA_RM
|
|
0U, // BLR
|
|
0U, // BLR8
|
|
0U, // BLRL
|
|
0U, // BL_NOP
|
|
0U, // BL_NOP_RM
|
|
0U, // BL_RM
|
|
0U, // BL_TLS
|
|
0U, // BPERMD
|
|
0U, // BRD
|
|
0U, // BRH
|
|
0U, // BRH8
|
|
0U, // BRINC
|
|
0U, // BRW
|
|
0U, // BRW8
|
|
0U, // CBCDTD
|
|
0U, // CBCDTD8
|
|
0U, // CDTBCD
|
|
0U, // CDTBCD8
|
|
0U, // CFUGED
|
|
0U, // CLRBHRB
|
|
0U, // CMPB
|
|
0U, // CMPB8
|
|
0U, // CMPD
|
|
0U, // CMPDI
|
|
0U, // CMPEQB
|
|
0U, // CMPLD
|
|
0U, // CMPLDI
|
|
0U, // CMPLW
|
|
0U, // CMPLWI
|
|
0U, // CMPRB
|
|
0U, // CMPRB8
|
|
0U, // CMPW
|
|
0U, // CMPWI
|
|
0U, // CNTLZD
|
|
0U, // CNTLZDM
|
|
0U, // CNTLZD_rec
|
|
0U, // CNTLZW
|
|
0U, // CNTLZW8
|
|
0U, // CNTLZW8_rec
|
|
0U, // CNTLZW_rec
|
|
0U, // CNTTZD
|
|
0U, // CNTTZDM
|
|
0U, // CNTTZD_rec
|
|
0U, // CNTTZW
|
|
0U, // CNTTZW8
|
|
0U, // CNTTZW8_rec
|
|
0U, // CNTTZW_rec
|
|
0U, // CP_ABORT
|
|
0U, // CP_COPY
|
|
0U, // CP_COPY8
|
|
0U, // CP_PASTE8_rec
|
|
0U, // CP_PASTE_rec
|
|
0U, // CR6SET
|
|
0U, // CR6UNSET
|
|
0U, // CRAND
|
|
0U, // CRANDC
|
|
0U, // CREQV
|
|
0U, // CRNAND
|
|
0U, // CRNOR
|
|
0U, // CRNOT
|
|
0U, // CROR
|
|
0U, // CRORC
|
|
0U, // CRSET
|
|
0U, // CRUNSET
|
|
0U, // CRXOR
|
|
0U, // CTRL_DEP
|
|
0U, // DADD
|
|
0U, // DADDQ
|
|
0U, // DADDQ_rec
|
|
0U, // DADD_rec
|
|
0U, // DARN
|
|
0U, // DCBA
|
|
0U, // DCBF
|
|
0U, // DCBFEP
|
|
0U, // DCBI
|
|
0U, // DCBST
|
|
0U, // DCBSTEP
|
|
0U, // DCBT
|
|
0U, // DCBTEP
|
|
0U, // DCBTST
|
|
0U, // DCBTSTEP
|
|
0U, // DCBZ
|
|
0U, // DCBZEP
|
|
0U, // DCBZL
|
|
0U, // DCBZLEP
|
|
0U, // DCCCI
|
|
0U, // DCFFIX
|
|
0U, // DCFFIXQ
|
|
0U, // DCFFIXQQ
|
|
0U, // DCFFIXQ_rec
|
|
0U, // DCFFIX_rec
|
|
0U, // DCMPO
|
|
0U, // DCMPOQ
|
|
0U, // DCMPU
|
|
0U, // DCMPUQ
|
|
0U, // DCTDP
|
|
0U, // DCTDP_rec
|
|
0U, // DCTFIX
|
|
0U, // DCTFIXQ
|
|
0U, // DCTFIXQQ
|
|
0U, // DCTFIXQ_rec
|
|
0U, // DCTFIX_rec
|
|
0U, // DCTQPQ
|
|
0U, // DCTQPQ_rec
|
|
0U, // DDEDPD
|
|
0U, // DDEDPDQ
|
|
0U, // DDEDPDQ_rec
|
|
0U, // DDEDPD_rec
|
|
0U, // DDIV
|
|
0U, // DDIVQ
|
|
0U, // DDIVQ_rec
|
|
0U, // DDIV_rec
|
|
0U, // DENBCD
|
|
0U, // DENBCDQ
|
|
0U, // DENBCDQ_rec
|
|
0U, // DENBCD_rec
|
|
0U, // DIEX
|
|
0U, // DIEXQ
|
|
0U, // DIEXQ_rec
|
|
0U, // DIEX_rec
|
|
0U, // DIVD
|
|
0U, // DIVDE
|
|
0U, // DIVDEO
|
|
0U, // DIVDEO_rec
|
|
0U, // DIVDEU
|
|
0U, // DIVDEUO
|
|
0U, // DIVDEUO_rec
|
|
0U, // DIVDEU_rec
|
|
0U, // DIVDE_rec
|
|
0U, // DIVDO
|
|
0U, // DIVDO_rec
|
|
0U, // DIVDU
|
|
0U, // DIVDUO
|
|
0U, // DIVDUO_rec
|
|
0U, // DIVDU_rec
|
|
0U, // DIVD_rec
|
|
0U, // DIVW
|
|
0U, // DIVWE
|
|
0U, // DIVWEO
|
|
0U, // DIVWEO_rec
|
|
0U, // DIVWEU
|
|
0U, // DIVWEUO
|
|
0U, // DIVWEUO_rec
|
|
0U, // DIVWEU_rec
|
|
0U, // DIVWE_rec
|
|
0U, // DIVWO
|
|
0U, // DIVWO_rec
|
|
0U, // DIVWU
|
|
0U, // DIVWUO
|
|
0U, // DIVWUO_rec
|
|
0U, // DIVWU_rec
|
|
0U, // DIVW_rec
|
|
0U, // DMMR
|
|
0U, // DMSETDMRZ
|
|
0U, // DMUL
|
|
0U, // DMULQ
|
|
0U, // DMULQ_rec
|
|
0U, // DMUL_rec
|
|
0U, // DMXOR
|
|
0U, // DMXXEXTFDMR256
|
|
0U, // DMXXEXTFDMR512
|
|
0U, // DMXXEXTFDMR512_HI
|
|
0U, // DMXXINSTFDMR256
|
|
0U, // DMXXINSTFDMR512
|
|
0U, // DMXXINSTFDMR512_HI
|
|
0U, // DQUA
|
|
0U, // DQUAI
|
|
0U, // DQUAIQ
|
|
0U, // DQUAIQ_rec
|
|
0U, // DQUAI_rec
|
|
0U, // DQUAQ
|
|
0U, // DQUAQ_rec
|
|
0U, // DQUA_rec
|
|
0U, // DRDPQ
|
|
0U, // DRDPQ_rec
|
|
0U, // DRINTN
|
|
0U, // DRINTNQ
|
|
0U, // DRINTNQ_rec
|
|
0U, // DRINTN_rec
|
|
0U, // DRINTX
|
|
0U, // DRINTXQ
|
|
0U, // DRINTXQ_rec
|
|
0U, // DRINTX_rec
|
|
0U, // DRRND
|
|
0U, // DRRNDQ
|
|
0U, // DRRNDQ_rec
|
|
0U, // DRRND_rec
|
|
0U, // DRSP
|
|
0U, // DRSP_rec
|
|
0U, // DSCLI
|
|
0U, // DSCLIQ
|
|
0U, // DSCLIQ_rec
|
|
0U, // DSCLI_rec
|
|
0U, // DSCRI
|
|
0U, // DSCRIQ
|
|
0U, // DSCRIQ_rec
|
|
0U, // DSCRI_rec
|
|
0U, // DSS
|
|
0U, // DSSALL
|
|
0U, // DST
|
|
0U, // DST64
|
|
0U, // DSTST
|
|
0U, // DSTST64
|
|
0U, // DSTSTT
|
|
0U, // DSTSTT64
|
|
0U, // DSTT
|
|
0U, // DSTT64
|
|
0U, // DSUB
|
|
0U, // DSUBQ
|
|
0U, // DSUBQ_rec
|
|
0U, // DSUB_rec
|
|
0U, // DTSTDC
|
|
0U, // DTSTDCQ
|
|
0U, // DTSTDG
|
|
0U, // DTSTDGQ
|
|
0U, // DTSTEX
|
|
0U, // DTSTEXQ
|
|
0U, // DTSTSF
|
|
0U, // DTSTSFI
|
|
0U, // DTSTSFIQ
|
|
0U, // DTSTSFQ
|
|
0U, // DXEX
|
|
0U, // DXEXQ
|
|
0U, // DXEXQ_rec
|
|
0U, // DXEX_rec
|
|
0U, // DYNALLOC
|
|
0U, // DYNALLOC8
|
|
0U, // DYNAREAOFFSET
|
|
0U, // DYNAREAOFFSET8
|
|
0U, // DecreaseCTR8loop
|
|
0U, // DecreaseCTRloop
|
|
0U, // EFDABS
|
|
0U, // EFDADD
|
|
0U, // EFDCFS
|
|
0U, // EFDCFSF
|
|
0U, // EFDCFSI
|
|
0U, // EFDCFSID
|
|
0U, // EFDCFUF
|
|
0U, // EFDCFUI
|
|
0U, // EFDCFUID
|
|
0U, // EFDCMPEQ
|
|
0U, // EFDCMPGT
|
|
0U, // EFDCMPLT
|
|
0U, // EFDCTSF
|
|
0U, // EFDCTSI
|
|
0U, // EFDCTSIDZ
|
|
0U, // EFDCTSIZ
|
|
0U, // EFDCTUF
|
|
0U, // EFDCTUI
|
|
0U, // EFDCTUIDZ
|
|
0U, // EFDCTUIZ
|
|
0U, // EFDDIV
|
|
0U, // EFDMUL
|
|
0U, // EFDNABS
|
|
0U, // EFDNEG
|
|
0U, // EFDSUB
|
|
0U, // EFDTSTEQ
|
|
0U, // EFDTSTGT
|
|
0U, // EFDTSTLT
|
|
0U, // EFSABS
|
|
0U, // EFSADD
|
|
0U, // EFSCFD
|
|
0U, // EFSCFSF
|
|
0U, // EFSCFSI
|
|
0U, // EFSCFUF
|
|
0U, // EFSCFUI
|
|
0U, // EFSCMPEQ
|
|
0U, // EFSCMPGT
|
|
0U, // EFSCMPLT
|
|
0U, // EFSCTSF
|
|
0U, // EFSCTSI
|
|
0U, // EFSCTSIZ
|
|
0U, // EFSCTUF
|
|
0U, // EFSCTUI
|
|
0U, // EFSCTUIZ
|
|
0U, // EFSDIV
|
|
0U, // EFSMUL
|
|
0U, // EFSNABS
|
|
0U, // EFSNEG
|
|
0U, // EFSSUB
|
|
0U, // EFSTSTEQ
|
|
0U, // EFSTSTGT
|
|
0U, // EFSTSTLT
|
|
0U, // EH_SjLj_LongJmp32
|
|
0U, // EH_SjLj_LongJmp64
|
|
0U, // EH_SjLj_SetJmp32
|
|
0U, // EH_SjLj_SetJmp64
|
|
0U, // EH_SjLj_Setup
|
|
0U, // EQV
|
|
0U, // EQV8
|
|
0U, // EQV8_rec
|
|
0U, // EQV_rec
|
|
0U, // EVABS
|
|
0U, // EVADDIW
|
|
0U, // EVADDSMIAAW
|
|
0U, // EVADDSSIAAW
|
|
0U, // EVADDUMIAAW
|
|
0U, // EVADDUSIAAW
|
|
0U, // EVADDW
|
|
0U, // EVAND
|
|
0U, // EVANDC
|
|
0U, // EVCMPEQ
|
|
0U, // EVCMPGTS
|
|
0U, // EVCMPGTU
|
|
0U, // EVCMPLTS
|
|
0U, // EVCMPLTU
|
|
0U, // EVCNTLSW
|
|
0U, // EVCNTLZW
|
|
0U, // EVDIVWS
|
|
0U, // EVDIVWU
|
|
0U, // EVEQV
|
|
0U, // EVEXTSB
|
|
0U, // EVEXTSH
|
|
0U, // EVFSABS
|
|
0U, // EVFSADD
|
|
0U, // EVFSCFSF
|
|
0U, // EVFSCFSI
|
|
0U, // EVFSCFUF
|
|
0U, // EVFSCFUI
|
|
0U, // EVFSCMPEQ
|
|
0U, // EVFSCMPGT
|
|
0U, // EVFSCMPLT
|
|
0U, // EVFSCTSF
|
|
0U, // EVFSCTSI
|
|
0U, // EVFSCTSIZ
|
|
0U, // EVFSCTUF
|
|
0U, // EVFSCTUI
|
|
0U, // EVFSCTUIZ
|
|
0U, // EVFSDIV
|
|
0U, // EVFSMUL
|
|
0U, // EVFSNABS
|
|
0U, // EVFSNEG
|
|
0U, // EVFSSUB
|
|
0U, // EVFSTSTEQ
|
|
0U, // EVFSTSTGT
|
|
0U, // EVFSTSTLT
|
|
0U, // EVLDD
|
|
0U, // EVLDDX
|
|
0U, // EVLDH
|
|
0U, // EVLDHX
|
|
0U, // EVLDW
|
|
0U, // EVLDWX
|
|
0U, // EVLHHESPLAT
|
|
0U, // EVLHHESPLATX
|
|
0U, // EVLHHOSSPLAT
|
|
0U, // EVLHHOSSPLATX
|
|
0U, // EVLHHOUSPLAT
|
|
0U, // EVLHHOUSPLATX
|
|
0U, // EVLWHE
|
|
0U, // EVLWHEX
|
|
0U, // EVLWHOS
|
|
0U, // EVLWHOSX
|
|
0U, // EVLWHOU
|
|
0U, // EVLWHOUX
|
|
0U, // EVLWHSPLAT
|
|
0U, // EVLWHSPLATX
|
|
0U, // EVLWWSPLAT
|
|
0U, // EVLWWSPLATX
|
|
0U, // EVMERGEHI
|
|
0U, // EVMERGEHILO
|
|
0U, // EVMERGELO
|
|
0U, // EVMERGELOHI
|
|
0U, // EVMHEGSMFAA
|
|
0U, // EVMHEGSMFAN
|
|
0U, // EVMHEGSMIAA
|
|
0U, // EVMHEGSMIAN
|
|
0U, // EVMHEGUMIAA
|
|
0U, // EVMHEGUMIAN
|
|
0U, // EVMHESMF
|
|
0U, // EVMHESMFA
|
|
0U, // EVMHESMFAAW
|
|
0U, // EVMHESMFANW
|
|
0U, // EVMHESMI
|
|
0U, // EVMHESMIA
|
|
0U, // EVMHESMIAAW
|
|
0U, // EVMHESMIANW
|
|
0U, // EVMHESSF
|
|
0U, // EVMHESSFA
|
|
0U, // EVMHESSFAAW
|
|
0U, // EVMHESSFANW
|
|
0U, // EVMHESSIAAW
|
|
0U, // EVMHESSIANW
|
|
0U, // EVMHEUMI
|
|
0U, // EVMHEUMIA
|
|
0U, // EVMHEUMIAAW
|
|
0U, // EVMHEUMIANW
|
|
0U, // EVMHEUSIAAW
|
|
0U, // EVMHEUSIANW
|
|
0U, // EVMHOGSMFAA
|
|
0U, // EVMHOGSMFAN
|
|
0U, // EVMHOGSMIAA
|
|
0U, // EVMHOGSMIAN
|
|
0U, // EVMHOGUMIAA
|
|
0U, // EVMHOGUMIAN
|
|
0U, // EVMHOSMF
|
|
0U, // EVMHOSMFA
|
|
0U, // EVMHOSMFAAW
|
|
0U, // EVMHOSMFANW
|
|
0U, // EVMHOSMI
|
|
0U, // EVMHOSMIA
|
|
0U, // EVMHOSMIAAW
|
|
0U, // EVMHOSMIANW
|
|
0U, // EVMHOSSF
|
|
0U, // EVMHOSSFA
|
|
0U, // EVMHOSSFAAW
|
|
0U, // EVMHOSSFANW
|
|
0U, // EVMHOSSIAAW
|
|
0U, // EVMHOSSIANW
|
|
0U, // EVMHOUMI
|
|
0U, // EVMHOUMIA
|
|
0U, // EVMHOUMIAAW
|
|
0U, // EVMHOUMIANW
|
|
0U, // EVMHOUSIAAW
|
|
0U, // EVMHOUSIANW
|
|
0U, // EVMRA
|
|
0U, // EVMWHSMF
|
|
0U, // EVMWHSMFA
|
|
0U, // EVMWHSMI
|
|
0U, // EVMWHSMIA
|
|
0U, // EVMWHSSF
|
|
0U, // EVMWHSSFA
|
|
0U, // EVMWHUMI
|
|
0U, // EVMWHUMIA
|
|
0U, // EVMWLSMIAAW
|
|
0U, // EVMWLSMIANW
|
|
0U, // EVMWLSSIAAW
|
|
0U, // EVMWLSSIANW
|
|
0U, // EVMWLUMI
|
|
0U, // EVMWLUMIA
|
|
0U, // EVMWLUMIAAW
|
|
0U, // EVMWLUMIANW
|
|
0U, // EVMWLUSIAAW
|
|
0U, // EVMWLUSIANW
|
|
0U, // EVMWSMF
|
|
0U, // EVMWSMFA
|
|
0U, // EVMWSMFAA
|
|
0U, // EVMWSMFAN
|
|
0U, // EVMWSMI
|
|
0U, // EVMWSMIA
|
|
0U, // EVMWSMIAA
|
|
0U, // EVMWSMIAN
|
|
0U, // EVMWSSF
|
|
0U, // EVMWSSFA
|
|
0U, // EVMWSSFAA
|
|
0U, // EVMWSSFAN
|
|
0U, // EVMWUMI
|
|
0U, // EVMWUMIA
|
|
0U, // EVMWUMIAA
|
|
0U, // EVMWUMIAN
|
|
0U, // EVNAND
|
|
0U, // EVNEG
|
|
0U, // EVNOR
|
|
0U, // EVOR
|
|
0U, // EVORC
|
|
0U, // EVRLW
|
|
0U, // EVRLWI
|
|
0U, // EVRNDW
|
|
0U, // EVSEL
|
|
0U, // EVSLW
|
|
0U, // EVSLWI
|
|
0U, // EVSPLATFI
|
|
0U, // EVSPLATI
|
|
0U, // EVSRWIS
|
|
0U, // EVSRWIU
|
|
0U, // EVSRWS
|
|
0U, // EVSRWU
|
|
0U, // EVSTDD
|
|
0U, // EVSTDDX
|
|
0U, // EVSTDH
|
|
0U, // EVSTDHX
|
|
0U, // EVSTDW
|
|
0U, // EVSTDWX
|
|
0U, // EVSTWHE
|
|
0U, // EVSTWHEX
|
|
0U, // EVSTWHO
|
|
0U, // EVSTWHOX
|
|
0U, // EVSTWWE
|
|
0U, // EVSTWWEX
|
|
0U, // EVSTWWO
|
|
0U, // EVSTWWOX
|
|
0U, // EVSUBFSMIAAW
|
|
0U, // EVSUBFSSIAAW
|
|
0U, // EVSUBFUMIAAW
|
|
0U, // EVSUBFUSIAAW
|
|
0U, // EVSUBFW
|
|
0U, // EVSUBIFW
|
|
0U, // EVXOR
|
|
0U, // EXTSB
|
|
0U, // EXTSB8
|
|
0U, // EXTSB8_32_64
|
|
0U, // EXTSB8_rec
|
|
0U, // EXTSB_rec
|
|
0U, // EXTSH
|
|
0U, // EXTSH8
|
|
0U, // EXTSH8_32_64
|
|
0U, // EXTSH8_rec
|
|
0U, // EXTSH_rec
|
|
0U, // EXTSW
|
|
0U, // EXTSWSLI
|
|
0U, // EXTSWSLI_32_64
|
|
0U, // EXTSWSLI_32_64_rec
|
|
0U, // EXTSWSLI_rec
|
|
0U, // EXTSW_32
|
|
0U, // EXTSW_32_64
|
|
0U, // EXTSW_32_64_rec
|
|
0U, // EXTSW_rec
|
|
0U, // EnforceIEIO
|
|
0U, // FABSD
|
|
0U, // FABSD_rec
|
|
0U, // FABSS
|
|
0U, // FABSS_rec
|
|
0U, // FADD
|
|
0U, // FADDS
|
|
0U, // FADDS_rec
|
|
0U, // FADD_rec
|
|
0U, // FADDrtz
|
|
0U, // FCFID
|
|
0U, // FCFIDS
|
|
0U, // FCFIDS_rec
|
|
0U, // FCFIDU
|
|
0U, // FCFIDUS
|
|
0U, // FCFIDUS_rec
|
|
0U, // FCFIDU_rec
|
|
0U, // FCFID_rec
|
|
0U, // FCMPOD
|
|
0U, // FCMPOS
|
|
0U, // FCMPUD
|
|
0U, // FCMPUS
|
|
0U, // FCPSGND
|
|
0U, // FCPSGND_rec
|
|
0U, // FCPSGNS
|
|
0U, // FCPSGNS_rec
|
|
0U, // FCTID
|
|
0U, // FCTIDU
|
|
0U, // FCTIDUZ
|
|
0U, // FCTIDUZ_rec
|
|
0U, // FCTIDU_rec
|
|
0U, // FCTIDZ
|
|
0U, // FCTIDZ_rec
|
|
0U, // FCTID_rec
|
|
0U, // FCTIW
|
|
0U, // FCTIWU
|
|
0U, // FCTIWUZ
|
|
0U, // FCTIWUZ_rec
|
|
0U, // FCTIWU_rec
|
|
0U, // FCTIWZ
|
|
0U, // FCTIWZ_rec
|
|
0U, // FCTIW_rec
|
|
0U, // FDIV
|
|
0U, // FDIVS
|
|
0U, // FDIVS_rec
|
|
0U, // FDIV_rec
|
|
0U, // FENCE
|
|
0U, // FMADD
|
|
0U, // FMADDS
|
|
0U, // FMADDS_rec
|
|
0U, // FMADD_rec
|
|
0U, // FMR
|
|
0U, // FMR_rec
|
|
0U, // FMSUB
|
|
0U, // FMSUBS
|
|
0U, // FMSUBS_rec
|
|
0U, // FMSUB_rec
|
|
0U, // FMUL
|
|
0U, // FMULS
|
|
0U, // FMULS_rec
|
|
0U, // FMUL_rec
|
|
0U, // FNABSD
|
|
0U, // FNABSD_rec
|
|
0U, // FNABSS
|
|
0U, // FNABSS_rec
|
|
0U, // FNEGD
|
|
0U, // FNEGD_rec
|
|
0U, // FNEGS
|
|
0U, // FNEGS_rec
|
|
0U, // FNMADD
|
|
0U, // FNMADDS
|
|
0U, // FNMADDS_rec
|
|
0U, // FNMADD_rec
|
|
0U, // FNMSUB
|
|
0U, // FNMSUBS
|
|
0U, // FNMSUBS_rec
|
|
0U, // FNMSUB_rec
|
|
0U, // FRE
|
|
0U, // FRES
|
|
0U, // FRES_rec
|
|
0U, // FRE_rec
|
|
0U, // FRIMD
|
|
0U, // FRIMD_rec
|
|
0U, // FRIMS
|
|
0U, // FRIMS_rec
|
|
0U, // FRIND
|
|
0U, // FRIND_rec
|
|
0U, // FRINS
|
|
0U, // FRINS_rec
|
|
0U, // FRIPD
|
|
0U, // FRIPD_rec
|
|
0U, // FRIPS
|
|
0U, // FRIPS_rec
|
|
0U, // FRIZD
|
|
0U, // FRIZD_rec
|
|
0U, // FRIZS
|
|
0U, // FRIZS_rec
|
|
0U, // FRSP
|
|
0U, // FRSP_rec
|
|
0U, // FRSQRTE
|
|
0U, // FRSQRTES
|
|
0U, // FRSQRTES_rec
|
|
0U, // FRSQRTE_rec
|
|
0U, // FSELD
|
|
0U, // FSELD_rec
|
|
0U, // FSELS
|
|
0U, // FSELS_rec
|
|
0U, // FSQRT
|
|
0U, // FSQRTS
|
|
0U, // FSQRTS_rec
|
|
0U, // FSQRT_rec
|
|
0U, // FSUB
|
|
0U, // FSUBS
|
|
0U, // FSUBS_rec
|
|
0U, // FSUB_rec
|
|
0U, // FTDIV
|
|
0U, // FTSQRT
|
|
0U, // GETtlsADDR
|
|
0U, // GETtlsADDR32
|
|
0U, // GETtlsADDR32AIX
|
|
0U, // GETtlsADDR64AIX
|
|
0U, // GETtlsADDRPCREL
|
|
0U, // GETtlsTpointer32AIX
|
|
0U, // GETtlsldADDR
|
|
0U, // GETtlsldADDR32
|
|
0U, // GETtlsldADDRPCREL
|
|
0U, // HASHCHK
|
|
0U, // HASHCHK8
|
|
0U, // HASHCHKP
|
|
0U, // HASHCHKP8
|
|
0U, // HASHST
|
|
0U, // HASHST8
|
|
0U, // HASHSTP
|
|
0U, // HASHSTP8
|
|
0U, // HRFID
|
|
0U, // ICBI
|
|
0U, // ICBIEP
|
|
0U, // ICBLC
|
|
0U, // ICBLQ
|
|
0U, // ICBT
|
|
0U, // ICBTLS
|
|
0U, // ICCCI
|
|
0U, // ISEL
|
|
0U, // ISEL8
|
|
0U, // ISYNC
|
|
0U, // LA
|
|
0U, // LA8
|
|
0U, // LBARX
|
|
0U, // LBARXL
|
|
0U, // LBEPX
|
|
0U, // LBZ
|
|
0U, // LBZ8
|
|
0U, // LBZCIX
|
|
0U, // LBZU
|
|
0U, // LBZU8
|
|
0U, // LBZUX
|
|
0U, // LBZUX8
|
|
0U, // LBZX
|
|
0U, // LBZX8
|
|
0U, // LBZXTLS
|
|
0U, // LBZXTLS_
|
|
0U, // LBZXTLS_32
|
|
0U, // LD
|
|
0U, // LDARX
|
|
0U, // LDARXL
|
|
0U, // LDAT
|
|
0U, // LDBRX
|
|
0U, // LDCIX
|
|
0U, // LDU
|
|
0U, // LDUX
|
|
0U, // LDX
|
|
0U, // LDXTLS
|
|
0U, // LDXTLS_
|
|
0U, // LDgotTprelL
|
|
0U, // LDgotTprelL32
|
|
0U, // LDtoc
|
|
0U, // LDtocBA
|
|
0U, // LDtocCPT
|
|
0U, // LDtocJTI
|
|
0U, // LDtocL
|
|
0U, // LFD
|
|
0U, // LFDEPX
|
|
0U, // LFDU
|
|
0U, // LFDUX
|
|
0U, // LFDX
|
|
0U, // LFDXTLS
|
|
0U, // LFDXTLS_
|
|
0U, // LFIWAX
|
|
0U, // LFIWZX
|
|
0U, // LFS
|
|
0U, // LFSU
|
|
0U, // LFSUX
|
|
0U, // LFSX
|
|
0U, // LFSXTLS
|
|
0U, // LFSXTLS_
|
|
0U, // LHA
|
|
0U, // LHA8
|
|
0U, // LHARX
|
|
0U, // LHARXL
|
|
0U, // LHAU
|
|
0U, // LHAU8
|
|
0U, // LHAUX
|
|
0U, // LHAUX8
|
|
0U, // LHAX
|
|
0U, // LHAX8
|
|
0U, // LHAXTLS
|
|
0U, // LHAXTLS_
|
|
0U, // LHAXTLS_32
|
|
0U, // LHBRX
|
|
0U, // LHBRX8
|
|
0U, // LHEPX
|
|
0U, // LHZ
|
|
0U, // LHZ8
|
|
0U, // LHZCIX
|
|
0U, // LHZU
|
|
0U, // LHZU8
|
|
0U, // LHZUX
|
|
0U, // LHZUX8
|
|
0U, // LHZX
|
|
0U, // LHZX8
|
|
0U, // LHZXTLS
|
|
0U, // LHZXTLS_
|
|
0U, // LHZXTLS_32
|
|
0U, // LMW
|
|
0U, // LQ
|
|
0U, // LQARX
|
|
0U, // LQARXL
|
|
0U, // LQX_PSEUDO
|
|
0U, // LSWI
|
|
0U, // LVEBX
|
|
0U, // LVEHX
|
|
0U, // LVEWX
|
|
0U, // LVSL
|
|
0U, // LVSR
|
|
0U, // LVX
|
|
0U, // LVXL
|
|
0U, // LWA
|
|
0U, // LWARX
|
|
0U, // LWARXL
|
|
0U, // LWAT
|
|
0U, // LWAUX
|
|
0U, // LWAX
|
|
0U, // LWAXTLS
|
|
0U, // LWAXTLS_
|
|
0U, // LWAXTLS_32
|
|
0U, // LWAX_32
|
|
0U, // LWA_32
|
|
0U, // LWBRX
|
|
0U, // LWBRX8
|
|
0U, // LWEPX
|
|
0U, // LWZ
|
|
0U, // LWZ8
|
|
0U, // LWZCIX
|
|
0U, // LWZU
|
|
0U, // LWZU8
|
|
0U, // LWZUX
|
|
0U, // LWZUX8
|
|
0U, // LWZX
|
|
0U, // LWZX8
|
|
0U, // LWZXTLS
|
|
0U, // LWZXTLS_
|
|
0U, // LWZXTLS_32
|
|
0U, // LWZtoc
|
|
0U, // LWZtocL
|
|
0U, // LXSD
|
|
0U, // LXSDX
|
|
0U, // LXSIBZX
|
|
0U, // LXSIHZX
|
|
0U, // LXSIWAX
|
|
0U, // LXSIWZX
|
|
0U, // LXSSP
|
|
0U, // LXSSPX
|
|
0U, // LXV
|
|
0U, // LXVB16X
|
|
0U, // LXVD2X
|
|
0U, // LXVDSX
|
|
0U, // LXVH8X
|
|
0U, // LXVKQ
|
|
0U, // LXVL
|
|
0U, // LXVLL
|
|
0U, // LXVP
|
|
0U, // LXVPRL
|
|
0U, // LXVPRLL
|
|
0U, // LXVPX
|
|
0U, // LXVRBX
|
|
0U, // LXVRDX
|
|
0U, // LXVRHX
|
|
0U, // LXVRL
|
|
0U, // LXVRLL
|
|
0U, // LXVRWX
|
|
0U, // LXVW4X
|
|
0U, // LXVWSX
|
|
0U, // LXVX
|
|
0U, // MADDHD
|
|
0U, // MADDHDU
|
|
0U, // MADDLD
|
|
0U, // MADDLD8
|
|
0U, // MBAR
|
|
0U, // MCRF
|
|
0U, // MCRFS
|
|
0U, // MCRXRX
|
|
0U, // MFBHRBE
|
|
0U, // MFCR
|
|
0U, // MFCR8
|
|
0U, // MFCTR
|
|
0U, // MFCTR8
|
|
0U, // MFDCR
|
|
0U, // MFFS
|
|
0U, // MFFSCDRN
|
|
0U, // MFFSCDRNI
|
|
0U, // MFFSCE
|
|
0U, // MFFSCRN
|
|
0U, // MFFSCRNI
|
|
0U, // MFFSL
|
|
0U, // MFFS_rec
|
|
0U, // MFLR
|
|
0U, // MFLR8
|
|
0U, // MFMSR
|
|
0U, // MFOCRF
|
|
0U, // MFOCRF8
|
|
0U, // MFPMR
|
|
0U, // MFSPR
|
|
0U, // MFSPR8
|
|
0U, // MFSR
|
|
0U, // MFSRIN
|
|
0U, // MFTB
|
|
0U, // MFTB8
|
|
0U, // MFUDSCR
|
|
0U, // MFVRD
|
|
0U, // MFVRSAVE
|
|
0U, // MFVRSAVEv
|
|
0U, // MFVRWZ
|
|
0U, // MFVSCR
|
|
0U, // MFVSRD
|
|
0U, // MFVSRLD
|
|
0U, // MFVSRWZ
|
|
0U, // MODSD
|
|
0U, // MODSW
|
|
0U, // MODUD
|
|
0U, // MODUW
|
|
0U, // MSGSYNC
|
|
0U, // MSYNC
|
|
0U, // MTCRF
|
|
0U, // MTCRF8
|
|
0U, // MTCTR
|
|
0U, // MTCTR8
|
|
0U, // MTCTR8loop
|
|
0U, // MTCTRloop
|
|
0U, // MTDCR
|
|
0U, // MTFSB0
|
|
0U, // MTFSB1
|
|
0U, // MTFSF
|
|
0U, // MTFSFI
|
|
0U, // MTFSFI_rec
|
|
0U, // MTFSFIb
|
|
0U, // MTFSF_rec
|
|
0U, // MTFSFb
|
|
0U, // MTLR
|
|
0U, // MTLR8
|
|
0U, // MTMSR
|
|
0U, // MTMSRD
|
|
0U, // MTOCRF
|
|
0U, // MTOCRF8
|
|
0U, // MTPMR
|
|
0U, // MTSPR
|
|
0U, // MTSPR8
|
|
0U, // MTSR
|
|
0U, // MTSRIN
|
|
0U, // MTUDSCR
|
|
0U, // MTVRD
|
|
0U, // MTVRSAVE
|
|
0U, // MTVRSAVEv
|
|
0U, // MTVRWA
|
|
0U, // MTVRWZ
|
|
0U, // MTVSCR
|
|
0U, // MTVSRBM
|
|
0U, // MTVSRBMI
|
|
0U, // MTVSRD
|
|
0U, // MTVSRDD
|
|
0U, // MTVSRDM
|
|
0U, // MTVSRHM
|
|
0U, // MTVSRQM
|
|
0U, // MTVSRWA
|
|
0U, // MTVSRWM
|
|
0U, // MTVSRWS
|
|
0U, // MTVSRWZ
|
|
0U, // MULHD
|
|
0U, // MULHDU
|
|
0U, // MULHDU_rec
|
|
0U, // MULHD_rec
|
|
0U, // MULHW
|
|
0U, // MULHWU
|
|
0U, // MULHWU_rec
|
|
0U, // MULHW_rec
|
|
0U, // MULLD
|
|
0U, // MULLDO
|
|
0U, // MULLDO_rec
|
|
0U, // MULLD_rec
|
|
0U, // MULLI
|
|
0U, // MULLI8
|
|
0U, // MULLW
|
|
0U, // MULLWO
|
|
0U, // MULLWO_rec
|
|
0U, // MULLW_rec
|
|
0U, // MoveGOTtoLR
|
|
0U, // MovePCtoLR
|
|
0U, // MovePCtoLR8
|
|
0U, // NAND
|
|
0U, // NAND8
|
|
0U, // NAND8_rec
|
|
0U, // NAND_rec
|
|
0U, // NAP
|
|
0U, // NEG
|
|
0U, // NEG8
|
|
0U, // NEG8O
|
|
0U, // NEG8O_rec
|
|
0U, // NEG8_rec
|
|
0U, // NEGO
|
|
0U, // NEGO_rec
|
|
0U, // NEG_rec
|
|
0U, // NOP
|
|
0U, // NOP_GT_PWR6
|
|
0U, // NOP_GT_PWR7
|
|
0U, // NOR
|
|
0U, // NOR8
|
|
0U, // NOR8_rec
|
|
0U, // NOR_rec
|
|
0U, // OR
|
|
0U, // OR8
|
|
0U, // OR8_rec
|
|
0U, // ORC
|
|
0U, // ORC8
|
|
0U, // ORC8_rec
|
|
0U, // ORC_rec
|
|
0U, // ORI
|
|
0U, // ORI8
|
|
0U, // ORIS
|
|
0U, // ORIS8
|
|
0U, // OR_rec
|
|
0U, // PADDI
|
|
0U, // PADDI8
|
|
0U, // PADDI8pc
|
|
0U, // PADDIdtprel
|
|
0U, // PADDIpc
|
|
0U, // PDEPD
|
|
0U, // PEXTD
|
|
0U, // PLA
|
|
0U, // PLA8
|
|
0U, // PLA8pc
|
|
0U, // PLApc
|
|
0U, // PLBZ
|
|
0U, // PLBZ8
|
|
0U, // PLBZ8nopc
|
|
0U, // PLBZ8onlypc
|
|
0U, // PLBZ8pc
|
|
0U, // PLBZnopc
|
|
0U, // PLBZonlypc
|
|
0U, // PLBZpc
|
|
0U, // PLD
|
|
0U, // PLDnopc
|
|
0U, // PLDonlypc
|
|
0U, // PLDpc
|
|
0U, // PLFD
|
|
0U, // PLFDnopc
|
|
0U, // PLFDonlypc
|
|
0U, // PLFDpc
|
|
0U, // PLFS
|
|
0U, // PLFSnopc
|
|
0U, // PLFSonlypc
|
|
0U, // PLFSpc
|
|
0U, // PLHA
|
|
0U, // PLHA8
|
|
0U, // PLHA8nopc
|
|
0U, // PLHA8onlypc
|
|
0U, // PLHA8pc
|
|
0U, // PLHAnopc
|
|
0U, // PLHAonlypc
|
|
0U, // PLHApc
|
|
0U, // PLHZ
|
|
0U, // PLHZ8
|
|
0U, // PLHZ8nopc
|
|
0U, // PLHZ8onlypc
|
|
0U, // PLHZ8pc
|
|
0U, // PLHZnopc
|
|
0U, // PLHZonlypc
|
|
0U, // PLHZpc
|
|
0U, // PLI
|
|
0U, // PLI8
|
|
0U, // PLWA
|
|
0U, // PLWA8
|
|
0U, // PLWA8nopc
|
|
0U, // PLWA8onlypc
|
|
0U, // PLWA8pc
|
|
0U, // PLWAnopc
|
|
0U, // PLWAonlypc
|
|
0U, // PLWApc
|
|
0U, // PLWZ
|
|
0U, // PLWZ8
|
|
0U, // PLWZ8nopc
|
|
0U, // PLWZ8onlypc
|
|
0U, // PLWZ8pc
|
|
0U, // PLWZnopc
|
|
0U, // PLWZonlypc
|
|
0U, // PLWZpc
|
|
0U, // PLXSD
|
|
0U, // PLXSDnopc
|
|
0U, // PLXSDonlypc
|
|
0U, // PLXSDpc
|
|
0U, // PLXSSP
|
|
0U, // PLXSSPnopc
|
|
0U, // PLXSSPonlypc
|
|
0U, // PLXSSPpc
|
|
0U, // PLXV
|
|
0U, // PLXVP
|
|
0U, // PLXVPnopc
|
|
0U, // PLXVPonlypc
|
|
0U, // PLXVPpc
|
|
0U, // PLXVnopc
|
|
0U, // PLXVonlypc
|
|
0U, // PLXVpc
|
|
0U, // PMXVBF16GER2
|
|
4U, // PMXVBF16GER2NN
|
|
4U, // PMXVBF16GER2NP
|
|
4U, // PMXVBF16GER2PN
|
|
4U, // PMXVBF16GER2PP
|
|
0U, // PMXVBF16GER2W
|
|
4U, // PMXVBF16GER2WNN
|
|
4U, // PMXVBF16GER2WNP
|
|
4U, // PMXVBF16GER2WPN
|
|
4U, // PMXVBF16GER2WPP
|
|
0U, // PMXVF16GER2
|
|
4U, // PMXVF16GER2NN
|
|
4U, // PMXVF16GER2NP
|
|
4U, // PMXVF16GER2PN
|
|
4U, // PMXVF16GER2PP
|
|
0U, // PMXVF16GER2W
|
|
4U, // PMXVF16GER2WNN
|
|
4U, // PMXVF16GER2WNP
|
|
4U, // PMXVF16GER2WPN
|
|
4U, // PMXVF16GER2WPP
|
|
8U, // PMXVF32GER
|
|
1U, // PMXVF32GERNN
|
|
1U, // PMXVF32GERNP
|
|
1U, // PMXVF32GERPN
|
|
1U, // PMXVF32GERPP
|
|
8U, // PMXVF32GERW
|
|
1U, // PMXVF32GERWNN
|
|
1U, // PMXVF32GERWNP
|
|
1U, // PMXVF32GERWPN
|
|
1U, // PMXVF32GERWPP
|
|
1U, // PMXVF64GER
|
|
0U, // PMXVF64GERNN
|
|
0U, // PMXVF64GERNP
|
|
0U, // PMXVF64GERPN
|
|
0U, // PMXVF64GERPP
|
|
1U, // PMXVF64GERW
|
|
0U, // PMXVF64GERWNN
|
|
0U, // PMXVF64GERWNP
|
|
0U, // PMXVF64GERWPN
|
|
0U, // PMXVF64GERWPP
|
|
0U, // PMXVI16GER2
|
|
4U, // PMXVI16GER2PP
|
|
0U, // PMXVI16GER2S
|
|
4U, // PMXVI16GER2SPP
|
|
0U, // PMXVI16GER2SW
|
|
4U, // PMXVI16GER2SWPP
|
|
0U, // PMXVI16GER2W
|
|
4U, // PMXVI16GER2WPP
|
|
32U, // PMXVI4GER8
|
|
12U, // PMXVI4GER8PP
|
|
32U, // PMXVI4GER8W
|
|
12U, // PMXVI4GER8WPP
|
|
64U, // PMXVI8GER4
|
|
16U, // PMXVI8GER4PP
|
|
16U, // PMXVI8GER4SPP
|
|
64U, // PMXVI8GER4W
|
|
16U, // PMXVI8GER4WPP
|
|
16U, // PMXVI8GER4WSPP
|
|
0U, // POPCNTB
|
|
0U, // POPCNTB8
|
|
0U, // POPCNTD
|
|
0U, // POPCNTW
|
|
0U, // PPC32GOT
|
|
0U, // PPC32PICGOT
|
|
0U, // PREPARE_PROBED_ALLOCA_32
|
|
0U, // PREPARE_PROBED_ALLOCA_64
|
|
0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32
|
|
0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
|
|
0U, // PROBED_ALLOCA_32
|
|
0U, // PROBED_ALLOCA_64
|
|
0U, // PROBED_STACKALLOC_32
|
|
0U, // PROBED_STACKALLOC_64
|
|
0U, // PSC_DCBZL
|
|
0U, // PSQ_L
|
|
0U, // PSQ_LU
|
|
2U, // PSQ_LUX
|
|
2U, // PSQ_LX
|
|
0U, // PSQ_ST
|
|
0U, // PSQ_STU
|
|
2U, // PSQ_STUX
|
|
2U, // PSQ_STX
|
|
0U, // PSTB
|
|
0U, // PSTB8
|
|
0U, // PSTB8nopc
|
|
0U, // PSTB8onlypc
|
|
0U, // PSTB8pc
|
|
0U, // PSTBnopc
|
|
0U, // PSTBonlypc
|
|
0U, // PSTBpc
|
|
0U, // PSTD
|
|
0U, // PSTDnopc
|
|
0U, // PSTDonlypc
|
|
0U, // PSTDpc
|
|
0U, // PSTFD
|
|
0U, // PSTFDnopc
|
|
0U, // PSTFDonlypc
|
|
0U, // PSTFDpc
|
|
0U, // PSTFS
|
|
0U, // PSTFSnopc
|
|
0U, // PSTFSonlypc
|
|
0U, // PSTFSpc
|
|
0U, // PSTH
|
|
0U, // PSTH8
|
|
0U, // PSTH8nopc
|
|
0U, // PSTH8onlypc
|
|
0U, // PSTH8pc
|
|
0U, // PSTHnopc
|
|
0U, // PSTHonlypc
|
|
0U, // PSTHpc
|
|
0U, // PSTW
|
|
0U, // PSTW8
|
|
0U, // PSTW8nopc
|
|
0U, // PSTW8onlypc
|
|
0U, // PSTW8pc
|
|
0U, // PSTWnopc
|
|
0U, // PSTWonlypc
|
|
0U, // PSTWpc
|
|
0U, // PSTXSD
|
|
0U, // PSTXSDnopc
|
|
0U, // PSTXSDonlypc
|
|
0U, // PSTXSDpc
|
|
0U, // PSTXSSP
|
|
0U, // PSTXSSPnopc
|
|
0U, // PSTXSSPonlypc
|
|
0U, // PSTXSSPpc
|
|
0U, // PSTXV
|
|
0U, // PSTXVP
|
|
0U, // PSTXVPnopc
|
|
0U, // PSTXVPonlypc
|
|
0U, // PSTXVPpc
|
|
0U, // PSTXVnopc
|
|
0U, // PSTXVonlypc
|
|
0U, // PSTXVpc
|
|
0U, // PS_ABS
|
|
0U, // PS_ABSo
|
|
0U, // PS_ADD
|
|
0U, // PS_ADDo
|
|
0U, // PS_CMPO0
|
|
0U, // PS_CMPO1
|
|
0U, // PS_CMPU0
|
|
0U, // PS_CMPU1
|
|
0U, // PS_DIV
|
|
0U, // PS_DIVo
|
|
0U, // PS_MADD
|
|
0U, // PS_MADDS0
|
|
0U, // PS_MADDS0o
|
|
0U, // PS_MADDS1
|
|
0U, // PS_MADDS1o
|
|
0U, // PS_MADDo
|
|
0U, // PS_MERGE00
|
|
0U, // PS_MERGE00o
|
|
0U, // PS_MERGE01
|
|
0U, // PS_MERGE01o
|
|
0U, // PS_MERGE10
|
|
0U, // PS_MERGE10o
|
|
0U, // PS_MERGE11
|
|
0U, // PS_MERGE11o
|
|
0U, // PS_MR
|
|
0U, // PS_MRo
|
|
0U, // PS_MSUB
|
|
0U, // PS_MSUBo
|
|
0U, // PS_MUL
|
|
0U, // PS_MULS0
|
|
0U, // PS_MULS0o
|
|
0U, // PS_MULS1
|
|
0U, // PS_MULS1o
|
|
0U, // PS_MULo
|
|
0U, // PS_NABS
|
|
0U, // PS_NABSo
|
|
0U, // PS_NEG
|
|
0U, // PS_NEGo
|
|
0U, // PS_NMADD
|
|
0U, // PS_NMADDo
|
|
0U, // PS_NMSUB
|
|
0U, // PS_NMSUBo
|
|
0U, // PS_RES
|
|
0U, // PS_RESo
|
|
0U, // PS_RSQRTE
|
|
0U, // PS_RSQRTEo
|
|
0U, // PS_SEL
|
|
0U, // PS_SELo
|
|
0U, // PS_SUB
|
|
0U, // PS_SUBo
|
|
0U, // PS_SUM0
|
|
0U, // PS_SUM0o
|
|
0U, // PS_SUM1
|
|
0U, // PS_SUM1o
|
|
0U, // PseudoEIEIO
|
|
0U, // QVALIGNI
|
|
0U, // QVALIGNIb
|
|
0U, // QVALIGNIs
|
|
0U, // QVESPLATI
|
|
0U, // QVESPLATIb
|
|
0U, // QVESPLATIs
|
|
0U, // QVFABS
|
|
0U, // QVFABSs
|
|
0U, // QVFADD
|
|
0U, // QVFADDS
|
|
0U, // QVFADDSs
|
|
0U, // QVFCFID
|
|
0U, // QVFCFIDS
|
|
0U, // QVFCFIDU
|
|
0U, // QVFCFIDUS
|
|
0U, // QVFCFIDb
|
|
0U, // QVFCMPEQ
|
|
0U, // QVFCMPEQb
|
|
0U, // QVFCMPEQbs
|
|
0U, // QVFCMPGT
|
|
0U, // QVFCMPGTb
|
|
0U, // QVFCMPGTbs
|
|
0U, // QVFCMPLT
|
|
0U, // QVFCMPLTb
|
|
0U, // QVFCMPLTbs
|
|
0U, // QVFCPSGN
|
|
0U, // QVFCPSGNs
|
|
0U, // QVFCTID
|
|
0U, // QVFCTIDU
|
|
0U, // QVFCTIDUZ
|
|
0U, // QVFCTIDZ
|
|
0U, // QVFCTIDb
|
|
0U, // QVFCTIW
|
|
0U, // QVFCTIWU
|
|
0U, // QVFCTIWUZ
|
|
0U, // QVFCTIWZ
|
|
0U, // QVFLOGICAL
|
|
0U, // QVFLOGICALb
|
|
0U, // QVFLOGICALs
|
|
0U, // QVFMADD
|
|
0U, // QVFMADDS
|
|
0U, // QVFMADDSs
|
|
0U, // QVFMR
|
|
0U, // QVFMRb
|
|
0U, // QVFMRs
|
|
0U, // QVFMSUB
|
|
0U, // QVFMSUBS
|
|
0U, // QVFMSUBSs
|
|
0U, // QVFMUL
|
|
0U, // QVFMULS
|
|
0U, // QVFMULSs
|
|
0U, // QVFNABS
|
|
0U, // QVFNABSs
|
|
0U, // QVFNEG
|
|
0U, // QVFNEGs
|
|
0U, // QVFNMADD
|
|
0U, // QVFNMADDS
|
|
0U, // QVFNMADDSs
|
|
0U, // QVFNMSUB
|
|
0U, // QVFNMSUBS
|
|
0U, // QVFNMSUBSs
|
|
0U, // QVFPERM
|
|
0U, // QVFPERMs
|
|
0U, // QVFRE
|
|
0U, // QVFRES
|
|
0U, // QVFRESs
|
|
0U, // QVFRIM
|
|
0U, // QVFRIMs
|
|
0U, // QVFRIN
|
|
0U, // QVFRINs
|
|
0U, // QVFRIP
|
|
0U, // QVFRIPs
|
|
0U, // QVFRIZ
|
|
0U, // QVFRIZs
|
|
0U, // QVFRSP
|
|
0U, // QVFRSPs
|
|
0U, // QVFRSQRTE
|
|
0U, // QVFRSQRTES
|
|
0U, // QVFRSQRTESs
|
|
0U, // QVFSEL
|
|
0U, // QVFSELb
|
|
0U, // QVFSELbb
|
|
0U, // QVFSELbs
|
|
0U, // QVFSUB
|
|
0U, // QVFSUBS
|
|
0U, // QVFSUBSs
|
|
0U, // QVFTSTNAN
|
|
0U, // QVFTSTNANb
|
|
0U, // QVFTSTNANbs
|
|
0U, // QVFXMADD
|
|
0U, // QVFXMADDS
|
|
0U, // QVFXMUL
|
|
0U, // QVFXMULS
|
|
0U, // QVFXXCPNMADD
|
|
0U, // QVFXXCPNMADDS
|
|
0U, // QVFXXMADD
|
|
0U, // QVFXXMADDS
|
|
0U, // QVFXXNPMADD
|
|
0U, // QVFXXNPMADDS
|
|
0U, // QVGPCI
|
|
0U, // QVLFCDUX
|
|
0U, // QVLFCDUXA
|
|
0U, // QVLFCDX
|
|
0U, // QVLFCDXA
|
|
0U, // QVLFCSUX
|
|
0U, // QVLFCSUXA
|
|
0U, // QVLFCSX
|
|
0U, // QVLFCSXA
|
|
0U, // QVLFCSXs
|
|
0U, // QVLFDUX
|
|
0U, // QVLFDUXA
|
|
0U, // QVLFDX
|
|
0U, // QVLFDXA
|
|
0U, // QVLFDXb
|
|
0U, // QVLFIWAX
|
|
0U, // QVLFIWAXA
|
|
0U, // QVLFIWZX
|
|
0U, // QVLFIWZXA
|
|
0U, // QVLFSUX
|
|
0U, // QVLFSUXA
|
|
0U, // QVLFSX
|
|
0U, // QVLFSXA
|
|
0U, // QVLFSXb
|
|
0U, // QVLFSXs
|
|
0U, // QVLPCLDX
|
|
0U, // QVLPCLSX
|
|
0U, // QVLPCLSXint
|
|
0U, // QVLPCRDX
|
|
0U, // QVLPCRSX
|
|
0U, // QVSTFCDUX
|
|
0U, // QVSTFCDUXA
|
|
0U, // QVSTFCDUXI
|
|
0U, // QVSTFCDUXIA
|
|
0U, // QVSTFCDX
|
|
0U, // QVSTFCDXA
|
|
0U, // QVSTFCDXI
|
|
0U, // QVSTFCDXIA
|
|
0U, // QVSTFCSUX
|
|
0U, // QVSTFCSUXA
|
|
0U, // QVSTFCSUXI
|
|
0U, // QVSTFCSUXIA
|
|
0U, // QVSTFCSX
|
|
0U, // QVSTFCSXA
|
|
0U, // QVSTFCSXI
|
|
0U, // QVSTFCSXIA
|
|
0U, // QVSTFCSXs
|
|
0U, // QVSTFDUX
|
|
0U, // QVSTFDUXA
|
|
0U, // QVSTFDUXI
|
|
0U, // QVSTFDUXIA
|
|
0U, // QVSTFDX
|
|
0U, // QVSTFDXA
|
|
0U, // QVSTFDXI
|
|
0U, // QVSTFDXIA
|
|
0U, // QVSTFDXb
|
|
0U, // QVSTFIWX
|
|
0U, // QVSTFIWXA
|
|
0U, // QVSTFSUX
|
|
0U, // QVSTFSUXA
|
|
0U, // QVSTFSUXI
|
|
0U, // QVSTFSUXIA
|
|
0U, // QVSTFSUXs
|
|
0U, // QVSTFSX
|
|
0U, // QVSTFSXA
|
|
0U, // QVSTFSXI
|
|
0U, // QVSTFSXIA
|
|
0U, // QVSTFSXs
|
|
0U, // RESTORE_ACC
|
|
0U, // RESTORE_CR
|
|
0U, // RESTORE_CRBIT
|
|
0U, // RESTORE_QUADWORD
|
|
0U, // RESTORE_UACC
|
|
0U, // RESTORE_WACC
|
|
0U, // RFCI
|
|
0U, // RFDI
|
|
0U, // RFEBB
|
|
0U, // RFI
|
|
0U, // RFID
|
|
0U, // RFMCI
|
|
0U, // RLDCL
|
|
0U, // RLDCL_rec
|
|
0U, // RLDCR
|
|
0U, // RLDCR_rec
|
|
0U, // RLDIC
|
|
0U, // RLDICL
|
|
0U, // RLDICL_32
|
|
0U, // RLDICL_32_64
|
|
0U, // RLDICL_32_rec
|
|
0U, // RLDICL_rec
|
|
0U, // RLDICR
|
|
0U, // RLDICR_32
|
|
0U, // RLDICR_rec
|
|
0U, // RLDIC_rec
|
|
0U, // RLDIMI
|
|
0U, // RLDIMI_rec
|
|
0U, // RLWIMI
|
|
0U, // RLWIMI8
|
|
0U, // RLWIMI8_rec
|
|
0U, // RLWIMI_rec
|
|
2U, // RLWINM
|
|
2U, // RLWINM8
|
|
2U, // RLWINM8_rec
|
|
2U, // RLWINM_rec
|
|
2U, // RLWNM
|
|
2U, // RLWNM8
|
|
2U, // RLWNM8_rec
|
|
2U, // RLWNM_rec
|
|
0U, // ReadTB
|
|
0U, // SC
|
|
0U, // SCV
|
|
0U, // SELECT_CC_F16
|
|
0U, // SELECT_CC_F4
|
|
0U, // SELECT_CC_F8
|
|
0U, // SELECT_CC_I4
|
|
0U, // SELECT_CC_I8
|
|
0U, // SELECT_CC_QBRC
|
|
0U, // SELECT_CC_QFRC
|
|
0U, // SELECT_CC_QSRC
|
|
0U, // SELECT_CC_SPE
|
|
0U, // SELECT_CC_SPE4
|
|
0U, // SELECT_CC_VRRC
|
|
0U, // SELECT_CC_VSFRC
|
|
0U, // SELECT_CC_VSRC
|
|
0U, // SELECT_CC_VSSRC
|
|
0U, // SELECT_F16
|
|
0U, // SELECT_F4
|
|
0U, // SELECT_F8
|
|
0U, // SELECT_I4
|
|
0U, // SELECT_I8
|
|
0U, // SELECT_QBRC
|
|
0U, // SELECT_QFRC
|
|
0U, // SELECT_QSRC
|
|
0U, // SELECT_SPE
|
|
0U, // SELECT_SPE4
|
|
0U, // SELECT_VRRC
|
|
0U, // SELECT_VSFRC
|
|
0U, // SELECT_VSRC
|
|
0U, // SELECT_VSSRC
|
|
0U, // SETB
|
|
0U, // SETB8
|
|
0U, // SETBC
|
|
0U, // SETBC8
|
|
0U, // SETBCR
|
|
0U, // SETBCR8
|
|
0U, // SETFLM
|
|
0U, // SETNBC
|
|
0U, // SETNBC8
|
|
0U, // SETNBCR
|
|
0U, // SETNBCR8
|
|
0U, // SETRND
|
|
0U, // SETRNDi
|
|
0U, // SLBFEE_rec
|
|
0U, // SLBIA
|
|
0U, // SLBIE
|
|
0U, // SLBIEG
|
|
0U, // SLBMFEE
|
|
0U, // SLBMFEV
|
|
0U, // SLBMTE
|
|
0U, // SLBSYNC
|
|
0U, // SLD
|
|
0U, // SLD_rec
|
|
0U, // SLW
|
|
0U, // SLW8
|
|
0U, // SLW8_rec
|
|
0U, // SLW_rec
|
|
0U, // SPELWZ
|
|
0U, // SPELWZX
|
|
0U, // SPESTW
|
|
0U, // SPESTWX
|
|
0U, // SPILL_ACC
|
|
0U, // SPILL_CR
|
|
0U, // SPILL_CRBIT
|
|
0U, // SPILL_QUADWORD
|
|
0U, // SPILL_UACC
|
|
0U, // SPILL_WACC
|
|
0U, // SPLIT_QUADWORD
|
|
0U, // SRAD
|
|
0U, // SRADI
|
|
0U, // SRADI_32
|
|
0U, // SRADI_rec
|
|
0U, // SRAD_rec
|
|
0U, // SRAW
|
|
0U, // SRAWI
|
|
0U, // SRAWI_rec
|
|
0U, // SRAW_rec
|
|
0U, // SRD
|
|
0U, // SRD_rec
|
|
0U, // SRW
|
|
0U, // SRW8
|
|
0U, // SRW8_rec
|
|
0U, // SRW_rec
|
|
0U, // STB
|
|
0U, // STB8
|
|
0U, // STBCIX
|
|
0U, // STBCX
|
|
0U, // STBEPX
|
|
0U, // STBU
|
|
0U, // STBU8
|
|
0U, // STBUX
|
|
0U, // STBUX8
|
|
0U, // STBX
|
|
0U, // STBX8
|
|
0U, // STBXTLS
|
|
0U, // STBXTLS_
|
|
0U, // STBXTLS_32
|
|
0U, // STD
|
|
0U, // STDAT
|
|
0U, // STDBRX
|
|
0U, // STDCIX
|
|
0U, // STDCX
|
|
0U, // STDU
|
|
0U, // STDUX
|
|
0U, // STDX
|
|
0U, // STDXTLS
|
|
0U, // STDXTLS_
|
|
0U, // STFD
|
|
0U, // STFDEPX
|
|
0U, // STFDU
|
|
0U, // STFDUX
|
|
0U, // STFDX
|
|
0U, // STFDXTLS
|
|
0U, // STFDXTLS_
|
|
0U, // STFIWX
|
|
0U, // STFS
|
|
0U, // STFSU
|
|
0U, // STFSUX
|
|
0U, // STFSX
|
|
0U, // STFSXTLS
|
|
0U, // STFSXTLS_
|
|
0U, // STH
|
|
0U, // STH8
|
|
0U, // STHBRX
|
|
0U, // STHCIX
|
|
0U, // STHCX
|
|
0U, // STHEPX
|
|
0U, // STHU
|
|
0U, // STHU8
|
|
0U, // STHUX
|
|
0U, // STHUX8
|
|
0U, // STHX
|
|
0U, // STHX8
|
|
0U, // STHXTLS
|
|
0U, // STHXTLS_
|
|
0U, // STHXTLS_32
|
|
0U, // STMW
|
|
0U, // STOP
|
|
0U, // STQ
|
|
0U, // STQCX
|
|
0U, // STQX_PSEUDO
|
|
0U, // STSWI
|
|
0U, // STVEBX
|
|
0U, // STVEHX
|
|
0U, // STVEWX
|
|
0U, // STVX
|
|
0U, // STVXL
|
|
0U, // STW
|
|
0U, // STW8
|
|
0U, // STWAT
|
|
0U, // STWBRX
|
|
0U, // STWCIX
|
|
0U, // STWCX
|
|
0U, // STWEPX
|
|
0U, // STWU
|
|
0U, // STWU8
|
|
0U, // STWUX
|
|
0U, // STWUX8
|
|
0U, // STWX
|
|
0U, // STWX8
|
|
0U, // STWXTLS
|
|
0U, // STWXTLS_
|
|
0U, // STWXTLS_32
|
|
0U, // STXSD
|
|
0U, // STXSDX
|
|
0U, // STXSIBX
|
|
0U, // STXSIBXv
|
|
0U, // STXSIHX
|
|
0U, // STXSIHXv
|
|
0U, // STXSIWX
|
|
0U, // STXSSP
|
|
0U, // STXSSPX
|
|
0U, // STXV
|
|
0U, // STXVB16X
|
|
0U, // STXVD2X
|
|
0U, // STXVH8X
|
|
0U, // STXVL
|
|
0U, // STXVLL
|
|
0U, // STXVP
|
|
0U, // STXVPRL
|
|
0U, // STXVPRLL
|
|
0U, // STXVPX
|
|
0U, // STXVRBX
|
|
0U, // STXVRDX
|
|
0U, // STXVRHX
|
|
0U, // STXVRL
|
|
0U, // STXVRLL
|
|
0U, // STXVRWX
|
|
0U, // STXVW4X
|
|
0U, // STXVX
|
|
0U, // SUBF
|
|
0U, // SUBF8
|
|
0U, // SUBF8O
|
|
0U, // SUBF8O_rec
|
|
0U, // SUBF8_rec
|
|
0U, // SUBFC
|
|
0U, // SUBFC8
|
|
0U, // SUBFC8O
|
|
0U, // SUBFC8O_rec
|
|
0U, // SUBFC8_rec
|
|
0U, // SUBFCO
|
|
0U, // SUBFCO_rec
|
|
0U, // SUBFC_rec
|
|
0U, // SUBFE
|
|
0U, // SUBFE8
|
|
0U, // SUBFE8O
|
|
0U, // SUBFE8O_rec
|
|
0U, // SUBFE8_rec
|
|
0U, // SUBFEO
|
|
0U, // SUBFEO_rec
|
|
0U, // SUBFE_rec
|
|
0U, // SUBFIC
|
|
0U, // SUBFIC8
|
|
0U, // SUBFME
|
|
0U, // SUBFME8
|
|
0U, // SUBFME8O
|
|
0U, // SUBFME8O_rec
|
|
0U, // SUBFME8_rec
|
|
0U, // SUBFMEO
|
|
0U, // SUBFMEO_rec
|
|
0U, // SUBFME_rec
|
|
0U, // SUBFO
|
|
0U, // SUBFO_rec
|
|
0U, // SUBFUS
|
|
0U, // SUBFUS_rec
|
|
0U, // SUBFZE
|
|
0U, // SUBFZE8
|
|
0U, // SUBFZE8O
|
|
0U, // SUBFZE8O_rec
|
|
0U, // SUBFZE8_rec
|
|
0U, // SUBFZEO
|
|
0U, // SUBFZEO_rec
|
|
0U, // SUBFZE_rec
|
|
0U, // SUBF_rec
|
|
0U, // SYNC
|
|
0U, // SYNCP10
|
|
0U, // TABORT
|
|
0U, // TABORTDC
|
|
0U, // TABORTDCI
|
|
0U, // TABORTWC
|
|
0U, // TABORTWCI
|
|
0U, // TAILB
|
|
0U, // TAILB8
|
|
0U, // TAILBA
|
|
0U, // TAILBA8
|
|
0U, // TAILBCTR
|
|
0U, // TAILBCTR8
|
|
0U, // TBEGIN
|
|
0U, // TBEGIN_RET
|
|
0U, // TCHECK
|
|
0U, // TCHECK_RET
|
|
0U, // TCRETURNai
|
|
0U, // TCRETURNai8
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNdi8
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNri8
|
|
0U, // TD
|
|
0U, // TDI
|
|
0U, // TEND
|
|
0U, // TLBIA
|
|
0U, // TLBIE
|
|
0U, // TLBIEL
|
|
0U, // TLBILX
|
|
0U, // TLBIVAX
|
|
0U, // TLBLD
|
|
0U, // TLBLI
|
|
0U, // TLBRE
|
|
0U, // TLBRE2
|
|
0U, // TLBSX
|
|
0U, // TLBSX2
|
|
0U, // TLBSX2D
|
|
0U, // TLBSYNC
|
|
0U, // TLBWE
|
|
0U, // TLBWE2
|
|
0U, // TLSGDAIX
|
|
0U, // TLSGDAIX8
|
|
0U, // TRAP
|
|
0U, // TRECHKPT
|
|
0U, // TRECLAIM
|
|
0U, // TSR
|
|
0U, // TW
|
|
0U, // TWI
|
|
0U, // UNENCODED_NOP
|
|
0U, // UpdateGBR
|
|
0U, // VABSDUB
|
|
0U, // VABSDUH
|
|
0U, // VABSDUW
|
|
0U, // VADDCUQ
|
|
0U, // VADDCUW
|
|
0U, // VADDECUQ
|
|
0U, // VADDEUQM
|
|
0U, // VADDFP
|
|
0U, // VADDSBS
|
|
0U, // VADDSHS
|
|
0U, // VADDSWS
|
|
0U, // VADDUBM
|
|
0U, // VADDUBS
|
|
0U, // VADDUDM
|
|
0U, // VADDUHM
|
|
0U, // VADDUHS
|
|
0U, // VADDUQM
|
|
0U, // VADDUWM
|
|
0U, // VADDUWS
|
|
0U, // VAND
|
|
0U, // VANDC
|
|
0U, // VAVGSB
|
|
0U, // VAVGSH
|
|
0U, // VAVGSW
|
|
0U, // VAVGUB
|
|
0U, // VAVGUH
|
|
0U, // VAVGUW
|
|
0U, // VBPERMD
|
|
0U, // VBPERMQ
|
|
0U, // VCFSX
|
|
0U, // VCFSX_0
|
|
0U, // VCFUGED
|
|
0U, // VCFUX
|
|
0U, // VCFUX_0
|
|
0U, // VCIPHER
|
|
0U, // VCIPHERLAST
|
|
0U, // VCLRLB
|
|
0U, // VCLRRB
|
|
0U, // VCLZB
|
|
0U, // VCLZD
|
|
0U, // VCLZDM
|
|
0U, // VCLZH
|
|
0U, // VCLZLSBB
|
|
0U, // VCLZW
|
|
0U, // VCMPBFP
|
|
0U, // VCMPBFP_rec
|
|
0U, // VCMPEQFP
|
|
0U, // VCMPEQFP_rec
|
|
0U, // VCMPEQUB
|
|
0U, // VCMPEQUB_rec
|
|
0U, // VCMPEQUD
|
|
0U, // VCMPEQUD_rec
|
|
0U, // VCMPEQUH
|
|
0U, // VCMPEQUH_rec
|
|
0U, // VCMPEQUQ
|
|
0U, // VCMPEQUQ_rec
|
|
0U, // VCMPEQUW
|
|
0U, // VCMPEQUW_rec
|
|
0U, // VCMPGEFP
|
|
0U, // VCMPGEFP_rec
|
|
0U, // VCMPGTFP
|
|
0U, // VCMPGTFP_rec
|
|
0U, // VCMPGTSB
|
|
0U, // VCMPGTSB_rec
|
|
0U, // VCMPGTSD
|
|
0U, // VCMPGTSD_rec
|
|
0U, // VCMPGTSH
|
|
0U, // VCMPGTSH_rec
|
|
0U, // VCMPGTSQ
|
|
0U, // VCMPGTSQ_rec
|
|
0U, // VCMPGTSW
|
|
0U, // VCMPGTSW_rec
|
|
0U, // VCMPGTUB
|
|
0U, // VCMPGTUB_rec
|
|
0U, // VCMPGTUD
|
|
0U, // VCMPGTUD_rec
|
|
0U, // VCMPGTUH
|
|
0U, // VCMPGTUH_rec
|
|
0U, // VCMPGTUQ
|
|
0U, // VCMPGTUQ_rec
|
|
0U, // VCMPGTUW
|
|
0U, // VCMPGTUW_rec
|
|
0U, // VCMPNEB
|
|
0U, // VCMPNEB_rec
|
|
0U, // VCMPNEH
|
|
0U, // VCMPNEH_rec
|
|
0U, // VCMPNEW
|
|
0U, // VCMPNEW_rec
|
|
0U, // VCMPNEZB
|
|
0U, // VCMPNEZB_rec
|
|
0U, // VCMPNEZH
|
|
0U, // VCMPNEZH_rec
|
|
0U, // VCMPNEZW
|
|
0U, // VCMPNEZW_rec
|
|
0U, // VCMPSQ
|
|
0U, // VCMPUQ
|
|
0U, // VCNTMBB
|
|
0U, // VCNTMBD
|
|
0U, // VCNTMBH
|
|
0U, // VCNTMBW
|
|
0U, // VCTSXS
|
|
0U, // VCTSXS_0
|
|
0U, // VCTUXS
|
|
0U, // VCTUXS_0
|
|
0U, // VCTZB
|
|
0U, // VCTZD
|
|
0U, // VCTZDM
|
|
0U, // VCTZH
|
|
0U, // VCTZLSBB
|
|
0U, // VCTZW
|
|
0U, // VDIVESD
|
|
0U, // VDIVESQ
|
|
0U, // VDIVESW
|
|
0U, // VDIVEUD
|
|
0U, // VDIVEUQ
|
|
0U, // VDIVEUW
|
|
0U, // VDIVSD
|
|
0U, // VDIVSQ
|
|
0U, // VDIVSW
|
|
0U, // VDIVUD
|
|
0U, // VDIVUQ
|
|
0U, // VDIVUW
|
|
0U, // VEQV
|
|
0U, // VEXPANDBM
|
|
0U, // VEXPANDDM
|
|
0U, // VEXPANDHM
|
|
0U, // VEXPANDQM
|
|
0U, // VEXPANDWM
|
|
0U, // VEXPTEFP
|
|
0U, // VEXTDDVLX
|
|
0U, // VEXTDDVRX
|
|
0U, // VEXTDUBVLX
|
|
0U, // VEXTDUBVRX
|
|
0U, // VEXTDUHVLX
|
|
0U, // VEXTDUHVRX
|
|
0U, // VEXTDUWVLX
|
|
0U, // VEXTDUWVRX
|
|
0U, // VEXTRACTBM
|
|
0U, // VEXTRACTD
|
|
0U, // VEXTRACTDM
|
|
0U, // VEXTRACTHM
|
|
0U, // VEXTRACTQM
|
|
0U, // VEXTRACTUB
|
|
0U, // VEXTRACTUH
|
|
0U, // VEXTRACTUW
|
|
0U, // VEXTRACTWM
|
|
0U, // VEXTSB2D
|
|
0U, // VEXTSB2Ds
|
|
0U, // VEXTSB2W
|
|
0U, // VEXTSB2Ws
|
|
0U, // VEXTSD2Q
|
|
0U, // VEXTSH2D
|
|
0U, // VEXTSH2Ds
|
|
0U, // VEXTSH2W
|
|
0U, // VEXTSH2Ws
|
|
0U, // VEXTSW2D
|
|
0U, // VEXTSW2Ds
|
|
0U, // VEXTUBLX
|
|
0U, // VEXTUBRX
|
|
0U, // VEXTUHLX
|
|
0U, // VEXTUHRX
|
|
0U, // VEXTUWLX
|
|
0U, // VEXTUWRX
|
|
0U, // VGBBD
|
|
0U, // VGNB
|
|
0U, // VINSBLX
|
|
0U, // VINSBRX
|
|
0U, // VINSBVLX
|
|
0U, // VINSBVRX
|
|
0U, // VINSD
|
|
0U, // VINSDLX
|
|
0U, // VINSDRX
|
|
0U, // VINSERTB
|
|
0U, // VINSERTD
|
|
0U, // VINSERTH
|
|
0U, // VINSERTW
|
|
0U, // VINSHLX
|
|
0U, // VINSHRX
|
|
0U, // VINSHVLX
|
|
0U, // VINSHVRX
|
|
0U, // VINSW
|
|
0U, // VINSWLX
|
|
0U, // VINSWRX
|
|
0U, // VINSWVLX
|
|
0U, // VINSWVRX
|
|
0U, // VLOGEFP
|
|
0U, // VMADDFP
|
|
0U, // VMAXFP
|
|
0U, // VMAXSB
|
|
0U, // VMAXSD
|
|
0U, // VMAXSH
|
|
0U, // VMAXSW
|
|
0U, // VMAXUB
|
|
0U, // VMAXUD
|
|
0U, // VMAXUH
|
|
0U, // VMAXUW
|
|
0U, // VMHADDSHS
|
|
0U, // VMHRADDSHS
|
|
0U, // VMINFP
|
|
0U, // VMINSB
|
|
0U, // VMINSD
|
|
0U, // VMINSH
|
|
0U, // VMINSW
|
|
0U, // VMINUB
|
|
0U, // VMINUD
|
|
0U, // VMINUH
|
|
0U, // VMINUW
|
|
0U, // VMLADDUHM
|
|
0U, // VMODSD
|
|
0U, // VMODSQ
|
|
0U, // VMODSW
|
|
0U, // VMODUD
|
|
0U, // VMODUQ
|
|
0U, // VMODUW
|
|
0U, // VMRGEW
|
|
0U, // VMRGHB
|
|
0U, // VMRGHH
|
|
0U, // VMRGHW
|
|
0U, // VMRGLB
|
|
0U, // VMRGLH
|
|
0U, // VMRGLW
|
|
0U, // VMRGOW
|
|
0U, // VMSUMCUD
|
|
0U, // VMSUMMBM
|
|
0U, // VMSUMSHM
|
|
0U, // VMSUMSHS
|
|
0U, // VMSUMUBM
|
|
0U, // VMSUMUDM
|
|
0U, // VMSUMUHM
|
|
0U, // VMSUMUHS
|
|
0U, // VMUL10CUQ
|
|
0U, // VMUL10ECUQ
|
|
0U, // VMUL10EUQ
|
|
0U, // VMUL10UQ
|
|
0U, // VMULESB
|
|
0U, // VMULESD
|
|
0U, // VMULESH
|
|
0U, // VMULESW
|
|
0U, // VMULEUB
|
|
0U, // VMULEUD
|
|
0U, // VMULEUH
|
|
0U, // VMULEUW
|
|
0U, // VMULHSD
|
|
0U, // VMULHSW
|
|
0U, // VMULHUD
|
|
0U, // VMULHUW
|
|
0U, // VMULLD
|
|
0U, // VMULOSB
|
|
0U, // VMULOSD
|
|
0U, // VMULOSH
|
|
0U, // VMULOSW
|
|
0U, // VMULOUB
|
|
0U, // VMULOUD
|
|
0U, // VMULOUH
|
|
0U, // VMULOUW
|
|
0U, // VMULUWM
|
|
0U, // VNAND
|
|
0U, // VNCIPHER
|
|
0U, // VNCIPHERLAST
|
|
0U, // VNEGD
|
|
0U, // VNEGW
|
|
0U, // VNMSUBFP
|
|
0U, // VNOR
|
|
0U, // VOR
|
|
0U, // VORC
|
|
0U, // VPDEPD
|
|
0U, // VPERM
|
|
0U, // VPERMR
|
|
0U, // VPERMXOR
|
|
0U, // VPEXTD
|
|
0U, // VPKPX
|
|
0U, // VPKSDSS
|
|
0U, // VPKSDUS
|
|
0U, // VPKSHSS
|
|
0U, // VPKSHUS
|
|
0U, // VPKSWSS
|
|
0U, // VPKSWUS
|
|
0U, // VPKUDUM
|
|
0U, // VPKUDUS
|
|
0U, // VPKUHUM
|
|
0U, // VPKUHUS
|
|
0U, // VPKUWUM
|
|
0U, // VPKUWUS
|
|
0U, // VPMSUMB
|
|
0U, // VPMSUMD
|
|
0U, // VPMSUMH
|
|
0U, // VPMSUMW
|
|
0U, // VPOPCNTB
|
|
0U, // VPOPCNTD
|
|
0U, // VPOPCNTH
|
|
0U, // VPOPCNTW
|
|
0U, // VPRTYBD
|
|
0U, // VPRTYBQ
|
|
0U, // VPRTYBW
|
|
0U, // VREFP
|
|
0U, // VRFIM
|
|
0U, // VRFIN
|
|
0U, // VRFIP
|
|
0U, // VRFIZ
|
|
0U, // VRLB
|
|
0U, // VRLD
|
|
0U, // VRLDMI
|
|
0U, // VRLDNM
|
|
0U, // VRLH
|
|
0U, // VRLQ
|
|
0U, // VRLQMI
|
|
0U, // VRLQNM
|
|
0U, // VRLW
|
|
0U, // VRLWMI
|
|
0U, // VRLWNM
|
|
0U, // VRSQRTEFP
|
|
0U, // VSBOX
|
|
0U, // VSEL
|
|
0U, // VSHASIGMAD
|
|
0U, // VSHASIGMAW
|
|
0U, // VSL
|
|
0U, // VSLB
|
|
0U, // VSLD
|
|
0U, // VSLDBI
|
|
0U, // VSLDOI
|
|
0U, // VSLH
|
|
0U, // VSLO
|
|
0U, // VSLQ
|
|
0U, // VSLV
|
|
0U, // VSLW
|
|
0U, // VSPLTB
|
|
0U, // VSPLTBs
|
|
0U, // VSPLTH
|
|
0U, // VSPLTHs
|
|
0U, // VSPLTISB
|
|
0U, // VSPLTISH
|
|
0U, // VSPLTISW
|
|
0U, // VSPLTW
|
|
0U, // VSR
|
|
0U, // VSRAB
|
|
0U, // VSRAD
|
|
0U, // VSRAH
|
|
0U, // VSRAQ
|
|
0U, // VSRAW
|
|
0U, // VSRB
|
|
0U, // VSRD
|
|
0U, // VSRDBI
|
|
0U, // VSRH
|
|
0U, // VSRO
|
|
0U, // VSRQ
|
|
0U, // VSRV
|
|
0U, // VSRW
|
|
0U, // VSTRIBL
|
|
0U, // VSTRIBL_rec
|
|
0U, // VSTRIBR
|
|
0U, // VSTRIBR_rec
|
|
0U, // VSTRIHL
|
|
0U, // VSTRIHL_rec
|
|
0U, // VSTRIHR
|
|
0U, // VSTRIHR_rec
|
|
0U, // VSUBCUQ
|
|
0U, // VSUBCUW
|
|
0U, // VSUBECUQ
|
|
0U, // VSUBEUQM
|
|
0U, // VSUBFP
|
|
0U, // VSUBSBS
|
|
0U, // VSUBSHS
|
|
0U, // VSUBSWS
|
|
0U, // VSUBUBM
|
|
0U, // VSUBUBS
|
|
0U, // VSUBUDM
|
|
0U, // VSUBUHM
|
|
0U, // VSUBUHS
|
|
0U, // VSUBUQM
|
|
0U, // VSUBUWM
|
|
0U, // VSUBUWS
|
|
0U, // VSUM2SWS
|
|
0U, // VSUM4SBS
|
|
0U, // VSUM4SHS
|
|
0U, // VSUM4UBS
|
|
0U, // VSUMSWS
|
|
0U, // VUPKHPX
|
|
0U, // VUPKHSB
|
|
0U, // VUPKHSH
|
|
0U, // VUPKHSW
|
|
0U, // VUPKLPX
|
|
0U, // VUPKLSB
|
|
0U, // VUPKLSH
|
|
0U, // VUPKLSW
|
|
0U, // VXOR
|
|
0U, // V_SET0
|
|
0U, // V_SET0B
|
|
0U, // V_SET0H
|
|
0U, // V_SETALLONES
|
|
0U, // V_SETALLONESB
|
|
0U, // V_SETALLONESH
|
|
0U, // WAIT
|
|
0U, // WAITP10
|
|
0U, // WRTEE
|
|
0U, // WRTEEI
|
|
0U, // XOR
|
|
0U, // XOR8
|
|
0U, // XOR8_rec
|
|
0U, // XORI
|
|
0U, // XORI8
|
|
0U, // XORIS
|
|
0U, // XORIS8
|
|
0U, // XOR_rec
|
|
0U, // XSABSDP
|
|
0U, // XSABSQP
|
|
0U, // XSADDDP
|
|
0U, // XSADDQP
|
|
0U, // XSADDQPO
|
|
0U, // XSADDSP
|
|
0U, // XSCMPEQDP
|
|
0U, // XSCMPEQQP
|
|
0U, // XSCMPEXPDP
|
|
0U, // XSCMPEXPQP
|
|
0U, // XSCMPGEDP
|
|
0U, // XSCMPGEQP
|
|
0U, // XSCMPGTDP
|
|
0U, // XSCMPGTQP
|
|
0U, // XSCMPODP
|
|
0U, // XSCMPOQP
|
|
0U, // XSCMPUDP
|
|
0U, // XSCMPUQP
|
|
0U, // XSCPSGNDP
|
|
0U, // XSCPSGNQP
|
|
0U, // XSCVDPHP
|
|
0U, // XSCVDPQP
|
|
0U, // XSCVDPSP
|
|
0U, // XSCVDPSPN
|
|
0U, // XSCVDPSXDS
|
|
0U, // XSCVDPSXDSs
|
|
0U, // XSCVDPSXWS
|
|
0U, // XSCVDPSXWSs
|
|
0U, // XSCVDPUXDS
|
|
0U, // XSCVDPUXDSs
|
|
0U, // XSCVDPUXWS
|
|
0U, // XSCVDPUXWSs
|
|
0U, // XSCVHPDP
|
|
0U, // XSCVQPDP
|
|
0U, // XSCVQPDPO
|
|
0U, // XSCVQPSDZ
|
|
0U, // XSCVQPSQZ
|
|
0U, // XSCVQPSWZ
|
|
0U, // XSCVQPUDZ
|
|
0U, // XSCVQPUQZ
|
|
0U, // XSCVQPUWZ
|
|
0U, // XSCVSDQP
|
|
0U, // XSCVSPDP
|
|
0U, // XSCVSPDPN
|
|
0U, // XSCVSQQP
|
|
0U, // XSCVSXDDP
|
|
0U, // XSCVSXDSP
|
|
0U, // XSCVUDQP
|
|
0U, // XSCVUQQP
|
|
0U, // XSCVUXDDP
|
|
0U, // XSCVUXDSP
|
|
0U, // XSDIVDP
|
|
0U, // XSDIVQP
|
|
0U, // XSDIVQPO
|
|
0U, // XSDIVSP
|
|
0U, // XSIEXPDP
|
|
0U, // XSIEXPQP
|
|
0U, // XSMADDADP
|
|
0U, // XSMADDASP
|
|
0U, // XSMADDMDP
|
|
0U, // XSMADDMSP
|
|
0U, // XSMADDQP
|
|
0U, // XSMADDQPO
|
|
0U, // XSMAXCDP
|
|
0U, // XSMAXCQP
|
|
0U, // XSMAXDP
|
|
0U, // XSMAXJDP
|
|
0U, // XSMINCDP
|
|
0U, // XSMINCQP
|
|
0U, // XSMINDP
|
|
0U, // XSMINJDP
|
|
0U, // XSMSUBADP
|
|
0U, // XSMSUBASP
|
|
0U, // XSMSUBMDP
|
|
0U, // XSMSUBMSP
|
|
0U, // XSMSUBQP
|
|
0U, // XSMSUBQPO
|
|
0U, // XSMULDP
|
|
0U, // XSMULQP
|
|
0U, // XSMULQPO
|
|
0U, // XSMULSP
|
|
0U, // XSNABSDP
|
|
0U, // XSNABSDPs
|
|
0U, // XSNABSQP
|
|
0U, // XSNEGDP
|
|
0U, // XSNEGQP
|
|
0U, // XSNMADDADP
|
|
0U, // XSNMADDASP
|
|
0U, // XSNMADDMDP
|
|
0U, // XSNMADDMSP
|
|
0U, // XSNMADDQP
|
|
0U, // XSNMADDQPO
|
|
0U, // XSNMSUBADP
|
|
0U, // XSNMSUBASP
|
|
0U, // XSNMSUBMDP
|
|
0U, // XSNMSUBMSP
|
|
0U, // XSNMSUBQP
|
|
0U, // XSNMSUBQPO
|
|
0U, // XSRDPI
|
|
0U, // XSRDPIC
|
|
0U, // XSRDPIM
|
|
0U, // XSRDPIP
|
|
0U, // XSRDPIZ
|
|
0U, // XSREDP
|
|
0U, // XSRESP
|
|
0U, // XSRQPI
|
|
0U, // XSRQPIX
|
|
0U, // XSRQPXP
|
|
0U, // XSRSP
|
|
0U, // XSRSQRTEDP
|
|
0U, // XSRSQRTESP
|
|
0U, // XSSQRTDP
|
|
0U, // XSSQRTQP
|
|
0U, // XSSQRTQPO
|
|
0U, // XSSQRTSP
|
|
0U, // XSSUBDP
|
|
0U, // XSSUBQP
|
|
0U, // XSSUBQPO
|
|
0U, // XSSUBSP
|
|
0U, // XSTDIVDP
|
|
0U, // XSTSQRTDP
|
|
0U, // XSTSTDCDP
|
|
0U, // XSTSTDCQP
|
|
0U, // XSTSTDCSP
|
|
0U, // XSXEXPDP
|
|
0U, // XSXEXPQP
|
|
0U, // XSXSIGDP
|
|
0U, // XSXSIGQP
|
|
0U, // XVABSDP
|
|
0U, // XVABSSP
|
|
0U, // XVADDDP
|
|
0U, // XVADDSP
|
|
0U, // XVBF16GER2
|
|
0U, // XVBF16GER2NN
|
|
0U, // XVBF16GER2NP
|
|
0U, // XVBF16GER2PN
|
|
0U, // XVBF16GER2PP
|
|
0U, // XVBF16GER2W
|
|
0U, // XVBF16GER2WNN
|
|
0U, // XVBF16GER2WNP
|
|
0U, // XVBF16GER2WPN
|
|
0U, // XVBF16GER2WPP
|
|
0U, // XVCMPEQDP
|
|
0U, // XVCMPEQDP_rec
|
|
0U, // XVCMPEQSP
|
|
0U, // XVCMPEQSP_rec
|
|
0U, // XVCMPGEDP
|
|
0U, // XVCMPGEDP_rec
|
|
0U, // XVCMPGESP
|
|
0U, // XVCMPGESP_rec
|
|
0U, // XVCMPGTDP
|
|
0U, // XVCMPGTDP_rec
|
|
0U, // XVCMPGTSP
|
|
0U, // XVCMPGTSP_rec
|
|
0U, // XVCPSGNDP
|
|
0U, // XVCPSGNSP
|
|
0U, // XVCVBF16SPN
|
|
0U, // XVCVDPSP
|
|
0U, // XVCVDPSXDS
|
|
0U, // XVCVDPSXWS
|
|
0U, // XVCVDPUXDS
|
|
0U, // XVCVDPUXWS
|
|
0U, // XVCVHPSP
|
|
0U, // XVCVSPBF16
|
|
0U, // XVCVSPDP
|
|
0U, // XVCVSPHP
|
|
0U, // XVCVSPSXDS
|
|
0U, // XVCVSPSXWS
|
|
0U, // XVCVSPUXDS
|
|
0U, // XVCVSPUXWS
|
|
0U, // XVCVSXDDP
|
|
0U, // XVCVSXDSP
|
|
0U, // XVCVSXWDP
|
|
0U, // XVCVSXWSP
|
|
0U, // XVCVUXDDP
|
|
0U, // XVCVUXDSP
|
|
0U, // XVCVUXWDP
|
|
0U, // XVCVUXWSP
|
|
0U, // XVDIVDP
|
|
0U, // XVDIVSP
|
|
0U, // XVF16GER2
|
|
0U, // XVF16GER2NN
|
|
0U, // XVF16GER2NP
|
|
0U, // XVF16GER2PN
|
|
0U, // XVF16GER2PP
|
|
0U, // XVF16GER2W
|
|
0U, // XVF16GER2WNN
|
|
0U, // XVF16GER2WNP
|
|
0U, // XVF16GER2WPN
|
|
0U, // XVF16GER2WPP
|
|
0U, // XVF32GER
|
|
0U, // XVF32GERNN
|
|
0U, // XVF32GERNP
|
|
0U, // XVF32GERPN
|
|
0U, // XVF32GERPP
|
|
0U, // XVF32GERW
|
|
0U, // XVF32GERWNN
|
|
0U, // XVF32GERWNP
|
|
0U, // XVF32GERWPN
|
|
0U, // XVF32GERWPP
|
|
0U, // XVF64GER
|
|
0U, // XVF64GERNN
|
|
0U, // XVF64GERNP
|
|
0U, // XVF64GERPN
|
|
0U, // XVF64GERPP
|
|
0U, // XVF64GERW
|
|
0U, // XVF64GERWNN
|
|
0U, // XVF64GERWNP
|
|
0U, // XVF64GERWPN
|
|
0U, // XVF64GERWPP
|
|
0U, // XVI16GER2
|
|
0U, // XVI16GER2PP
|
|
0U, // XVI16GER2S
|
|
0U, // XVI16GER2SPP
|
|
0U, // XVI16GER2SW
|
|
0U, // XVI16GER2SWPP
|
|
0U, // XVI16GER2W
|
|
0U, // XVI16GER2WPP
|
|
0U, // XVI4GER8
|
|
0U, // XVI4GER8PP
|
|
0U, // XVI4GER8W
|
|
0U, // XVI4GER8WPP
|
|
0U, // XVI8GER4
|
|
0U, // XVI8GER4PP
|
|
0U, // XVI8GER4SPP
|
|
0U, // XVI8GER4W
|
|
0U, // XVI8GER4WPP
|
|
0U, // XVI8GER4WSPP
|
|
0U, // XVIEXPDP
|
|
0U, // XVIEXPSP
|
|
0U, // XVMADDADP
|
|
0U, // XVMADDASP
|
|
0U, // XVMADDMDP
|
|
0U, // XVMADDMSP
|
|
0U, // XVMAXDP
|
|
0U, // XVMAXSP
|
|
0U, // XVMINDP
|
|
0U, // XVMINSP
|
|
0U, // XVMSUBADP
|
|
0U, // XVMSUBASP
|
|
0U, // XVMSUBMDP
|
|
0U, // XVMSUBMSP
|
|
0U, // XVMULDP
|
|
0U, // XVMULSP
|
|
0U, // XVNABSDP
|
|
0U, // XVNABSSP
|
|
0U, // XVNEGDP
|
|
0U, // XVNEGSP
|
|
0U, // XVNMADDADP
|
|
0U, // XVNMADDASP
|
|
0U, // XVNMADDMDP
|
|
0U, // XVNMADDMSP
|
|
0U, // XVNMSUBADP
|
|
0U, // XVNMSUBASP
|
|
0U, // XVNMSUBMDP
|
|
0U, // XVNMSUBMSP
|
|
0U, // XVRDPI
|
|
0U, // XVRDPIC
|
|
0U, // XVRDPIM
|
|
0U, // XVRDPIP
|
|
0U, // XVRDPIZ
|
|
0U, // XVREDP
|
|
0U, // XVRESP
|
|
0U, // XVRSPI
|
|
0U, // XVRSPIC
|
|
0U, // XVRSPIM
|
|
0U, // XVRSPIP
|
|
0U, // XVRSPIZ
|
|
0U, // XVRSQRTEDP
|
|
0U, // XVRSQRTESP
|
|
0U, // XVSQRTDP
|
|
0U, // XVSQRTSP
|
|
0U, // XVSUBDP
|
|
0U, // XVSUBSP
|
|
0U, // XVTDIVDP
|
|
0U, // XVTDIVSP
|
|
0U, // XVTLSBB
|
|
0U, // XVTSQRTDP
|
|
0U, // XVTSQRTSP
|
|
0U, // XVTSTDCDP
|
|
0U, // XVTSTDCSP
|
|
0U, // XVXEXPDP
|
|
0U, // XVXEXPSP
|
|
0U, // XVXSIGDP
|
|
0U, // XVXSIGSP
|
|
0U, // XXBLENDVB
|
|
0U, // XXBLENDVD
|
|
0U, // XXBLENDVH
|
|
0U, // XXBLENDVW
|
|
0U, // XXBRD
|
|
0U, // XXBRH
|
|
0U, // XXBRQ
|
|
0U, // XXBRW
|
|
3U, // XXEVAL
|
|
0U, // XXEXTRACTUW
|
|
0U, // XXGENPCVBM
|
|
0U, // XXGENPCVDM
|
|
0U, // XXGENPCVHM
|
|
0U, // XXGENPCVWM
|
|
0U, // XXINSERTW
|
|
0U, // XXLAND
|
|
0U, // XXLANDC
|
|
0U, // XXLEQV
|
|
0U, // XXLEQVOnes
|
|
0U, // XXLNAND
|
|
0U, // XXLNOR
|
|
0U, // XXLOR
|
|
0U, // XXLORC
|
|
0U, // XXLORf
|
|
0U, // XXLXOR
|
|
0U, // XXLXORdpz
|
|
0U, // XXLXORspz
|
|
0U, // XXLXORz
|
|
0U, // XXMFACC
|
|
0U, // XXMFACCW
|
|
0U, // XXMRGHW
|
|
0U, // XXMRGLW
|
|
0U, // XXMTACC
|
|
0U, // XXMTACCW
|
|
0U, // XXPERM
|
|
0U, // XXPERMDI
|
|
0U, // XXPERMDIs
|
|
0U, // XXPERMR
|
|
2U, // XXPERMX
|
|
0U, // XXSEL
|
|
0U, // XXSETACCZ
|
|
0U, // XXSETACCZW
|
|
0U, // XXSLDWI
|
|
0U, // XXSLDWIs
|
|
0U, // XXSPLTI32DX
|
|
0U, // XXSPLTIB
|
|
0U, // XXSPLTIDP
|
|
0U, // XXSPLTIW
|
|
0U, // XXSPLTW
|
|
0U, // XXSPLTWs
|
|
0U, // gBC
|
|
0U, // gBCA
|
|
0U, // gBCAat
|
|
0U, // gBCCTR
|
|
0U, // gBCCTRL
|
|
0U, // gBCL
|
|
0U, // gBCLA
|
|
0U, // gBCLAat
|
|
0U, // gBCLR
|
|
0U, // gBCLRL
|
|
0U, // gBCLat
|
|
0U, // gBCat
|
|
};
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint64_t Bits = 0;
|
|
Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0;
|
|
Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32;
|
|
Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48;
|
|
MnemonicBitsInfo MBI = {
|
|
#ifndef CAPSTONE_DIET
|
|
AsmStrs+(Bits & 32767)-1,
|
|
#else
|
|
NULL,
|
|
#endif // CAPSTONE_DIET
|
|
Bits
|
|
};
|
|
return MBI;
|
|
}
|
|
|
|
/// printInstruction - This method is automatically generated by tablegen
|
|
/// from the instruction set description.
|
|
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
|
|
SStream_concat0(O, "");
|
|
MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
|
|
|
|
SStream_concat0(O, MnemonicInfo.first);
|
|
|
|
uint64_t Bits = MnemonicInfo.second;
|
|
CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
|
|
|
|
// Fragment 0 encoded into 5 bits for 24 unique commands.
|
|
switch ((Bits >> 15) & 31) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// DCBFL, DCBFLP, DCBFPS, DCBFx, DCBSTPS, DCBTCT, DCBTDS, DCBTSTCT, DCBTS...
|
|
printMemRegReg(MI, 0, O);
|
|
break;
|
|
case 3:
|
|
// ADJCALLSTACKDOWN, ADJCALLSTACKUP
|
|
printU16ImmOperand(MI, 0, O);
|
|
SStream_concat1(O, ' ');
|
|
printU16ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// B, BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOTOC, BL8_NOTOC_RM, BL8_RM, BL_N...
|
|
printBranchOperand(MI, Address, 0, O);
|
|
break;
|
|
case 5:
|
|
// BA, BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM, TAILBA, TAILBA8...
|
|
printAbsBranchOperand(MI, 0, O);
|
|
break;
|
|
case 6:
|
|
// BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCC...
|
|
printPredicateOperand(MI, 0, O, "cc");
|
|
break;
|
|
case 7:
|
|
// BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL_LWZinto_toc, BCTRL_LWZi...
|
|
printMemRegImm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// BL8_NOP_TLS, BL8_NOTOC_TLS, BL8_TLS, BL8_TLS_, BL_TLS
|
|
printTLSCall(MI, 0, O);
|
|
break;
|
|
case 9:
|
|
// DCBF, DCBT, DCBTST
|
|
printMemRegReg(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 10:
|
|
// DCBTEP, DCBTSTEP
|
|
printU5ImmOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printMemRegReg(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// DDEDPD, DDEDPDQ, DDEDPDQ_rec, DDEDPD_rec
|
|
printU2ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// DENBCD, DENBCDQ, DENBCDQ_rec, DENBCD_rec, DRINTN, DRINTNQ, DRINTNQ_rec...
|
|
printU1ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 13:
|
|
// DMXXEXTFDMR256, DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DS...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 14:
|
|
// DMXXEXTFDMR512, DMXXEXTFDMR512_HI
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 15:
|
|
// DQUAI, DQUAIQ, DQUAIQ_rec, DQUAI_rec
|
|
printS5ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printU2ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// DSS, MBAR, MTFSB0, MTFSB1, TABORTDC, TABORTDCI, TABORTWC, TABORTWCI, T...
|
|
printU5ImmOperand(MI, 0, O);
|
|
break;
|
|
case 17:
|
|
// ICBLC, ICBLQ, ICBT, ICBTLS
|
|
printU4ImmOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printMemRegReg(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// MTFSFI, MTFSFI_rec, MTFSFIb, SYNCP10
|
|
printU3ImmOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 19:
|
|
// MTOCRF, MTOCRF8
|
|
printcrbitm(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// MTSR
|
|
printU4ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// RFEBB, TBEGIN, TEND, TSR
|
|
printU1ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// SYNC, TLBILX, WAIT, WAITP10
|
|
printU2ImmOperand(MI, 0, O);
|
|
break;
|
|
case 23:
|
|
// gBCAat, gBCLAat, gBCLat, gBCat
|
|
printATBitsAsHint(MI, 1, O);
|
|
SStream_concat1(O, ' ');
|
|
printU5ImmOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 5 bits for 26 unique commands.
|
|
switch ((Bits >> 20) & 31) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// DCBFL, DCBFLP, DCBFPS, DCBFx, DCBSTPS, DCBTSTT, DCBTSTx, DCBTT, DCBTx,...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, TCRETURNai8, TCR...
|
|
SStream_concat1(O, ' ');
|
|
break;
|
|
case 3:
|
|
// BCC, CTRL_DEP
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printBranchOperand(MI, Address, 2, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// BCCA
|
|
SStream_concat1(O, 'a');
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printAbsBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// BCCCTR, BCCCTR8
|
|
SStream_concat0(O, "ctr");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 6:
|
|
// BCCCTRL, BCCCTRL8
|
|
SStream_concat0(O, "ctrl");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BCCL
|
|
SStream_concat1(O, 'l');
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printBranchOperand(MI, Address, 2, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// BCCLA
|
|
SStream_concat0(O, "la");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printAbsBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// BCCLR
|
|
SStream_concat0(O, "lr");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 10:
|
|
// BCCLRL
|
|
SStream_concat0(O, "lrl");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat1(O, ' ');
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 11:
|
|
// BCCTR, BCCTR8, BCCTRL, BCCTRL8, BCLR, BCLRL, DMXXEXTFDMR512
|
|
SStream_concat0(O, ", 0");
|
|
return;
|
|
break;
|
|
case 12:
|
|
// BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BLA8_NOP, BLA8_NOP_RM, BL_NOP, BL_NO...
|
|
SStream_concat0(O, "\n\tnop");
|
|
return;
|
|
break;
|
|
case 13:
|
|
// DCBF
|
|
printU3ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// DCBT, DCBTST
|
|
printU5ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// DMXXEXTFDMR512_HI
|
|
SStream_concat0(O, ", 1");
|
|
return;
|
|
break;
|
|
case 16:
|
|
// EVSEL, TLBIE
|
|
SStream_concat1(O, ',');
|
|
break;
|
|
case 17:
|
|
// MFTB8
|
|
SStream_concat0(O, ", 268");
|
|
return;
|
|
break;
|
|
case 18:
|
|
// MFUDSCR
|
|
SStream_concat0(O, ", 3");
|
|
return;
|
|
break;
|
|
case 19:
|
|
// MFVRSAVE, MFVRSAVEv
|
|
SStream_concat0(O, ", 256");
|
|
return;
|
|
break;
|
|
case 20:
|
|
// MTFSFI, MTFSFI_rec, MTFSFIb
|
|
printU4ImmOperand(MI, 1, O);
|
|
break;
|
|
case 21:
|
|
// QVLPCLSXint
|
|
SStream_concat0(O, ", 0, ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// SYNCP10
|
|
printU2ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// V_SETALLONES, V_SETALLONESB, V_SETALLONESH
|
|
SStream_concat0(O, ", -1");
|
|
return;
|
|
break;
|
|
case 24:
|
|
// gBCAat, gBCLAat
|
|
printAbsBranchOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// gBCLat, gBCat
|
|
printBranchOperand(MI, Address, 3, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 6 bits for 36 unique commands.
|
|
switch ((Bits >> 25) & 63) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 1:
|
|
// DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, EVADDIW
|
|
printU5ImmOperand(MI, 2, O);
|
|
break;
|
|
case 2:
|
|
// LAx, EVLDD, EVLDH, EVLDW, EVLHHESPLAT, EVLHHOSSPLAT, EVLHHOUSPLAT, EVL...
|
|
printMemRegImm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// LI, LI8, LIS, LIS8, SUBPCIS
|
|
printS16ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, EVLDDX, EVLDHX, EVLDWX, EVLH...
|
|
printMemRegReg(MI, 1, O);
|
|
break;
|
|
case 5:
|
|
// BC, BCL
|
|
printBranchOperand(MI, Address, 1, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// CMPRB, CMPRB8, MTMSR, MTMSRD
|
|
printU1ImmOperand(MI, 1, O);
|
|
break;
|
|
case 7:
|
|
// CRSET, CRUNSET, DMXXEXTFDMR256, MTDCR, TLBIE, V_SET0, V_SET0B, V_SET0H...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 8:
|
|
// DARN, MFFSCRNI, WAITP10
|
|
printU2ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// DMXOR, DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, PMX...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 10:
|
|
// DRINTN, DRINTNQ, DRINTNQ_rec, DRINTN_rec, DRINTX, DRINTXQ, DRINTXQ_rec...
|
|
printU2ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// DTSTSFI, DTSTSFIQ
|
|
printU6ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// EVSPLATFI, EVSPLATI, VSPLTISB, VSPLTISH, VSPLTISW
|
|
printS5ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// EVSUBIFW, LXVKQ
|
|
printU5ImmOperand(MI, 1, O);
|
|
break;
|
|
case 14:
|
|
// HASHCHK, HASHCHK8, HASHCHKP, HASHCHKP8, HASHST, HASHST8, HASHSTP, HASH...
|
|
printMemRegImmHash(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// LA, LA8
|
|
printS16ImmOperand(MI, 2, O);
|
|
SStream_concat1(O, '(');
|
|
printOperand(MI, 1, O);
|
|
SStream_concat1(O, ')');
|
|
return;
|
|
break;
|
|
case 16:
|
|
// LBZU, LBZU8, LDU, LFDU, LFSU, LHAU, LHAU8, LHZU, LHZU8, LWZU, LWZU8, S...
|
|
printMemRegImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// LBZUX, LBZUX8, LDUX, LFDUX, LFSUX, LHAUX, LHAUX8, LHZUX, LHZUX8, LWAUX...
|
|
printMemRegReg(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// MFBHRBE
|
|
printU10ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// MFFSCDRNI
|
|
printU3ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// MFOCRF, MFOCRF8
|
|
printcrbitm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// MFSR
|
|
printU4ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// MTFSFI, MTFSFI_rec
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 23:
|
|
// MTFSFIb
|
|
return;
|
|
break;
|
|
case 24:
|
|
// MTVSRBMI
|
|
printU16ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// PADDI8pc, PADDIpc
|
|
printImmZeroOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printS34ImmOperand(MI, 2, O);
|
|
SStream_concat0(O, ", 1");
|
|
return;
|
|
break;
|
|
case 26:
|
|
// PLA, PLA8
|
|
printS34ImmOperand(MI, 2, O);
|
|
SStream_concat1(O, ' ');
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// PLA8pc, PLApc, PLBZ8onlypc, PLBZonlypc, PLDonlypc, PLFDonlypc, PLFSonl...
|
|
printS34ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// PLBZ, PLBZ8, PLBZ8nopc, PLBZnopc, PLD, PLDnopc, PLFD, PLFDnopc, PLFS, ...
|
|
printMemRegImm34(MI, 1, O);
|
|
break;
|
|
case 29:
|
|
// PLBZ8pc, PLBZpc, PLDpc, PLFDpc, PLFSpc, PLHA8pc, PLHApc, PLHZ8pc, PLHZ...
|
|
printMemRegImm34PCRel(MI, 1, O);
|
|
SStream_concat0(O, ", 1");
|
|
return;
|
|
break;
|
|
case 30:
|
|
// PSQ_L, PSQ_LU, PSQ_ST, PSQ_STU
|
|
printMemRegImmPS(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printU1ImmOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU3ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// QVGPCI
|
|
printU12ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// SUBFUS, SUBFUS_rec
|
|
printU1ImmOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// VINSD, VINSERTB, VINSERTH, VINSW
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU4ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// XXSPLTI32DX
|
|
printU1ImmOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// XXSPLTIB
|
|
printU8ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 3 bits for 8 unique commands.
|
|
switch ((Bits >> 31) & 7) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// BUILD_UACC, DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, ADDME, ADDME8, ADDME8O...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CLRRDI_rec, CL...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32
|
|
SStream_concat1(O, ' ');
|
|
printOperand(MI, 3, O);
|
|
SStream_concat1(O, ' ');
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// EVSEL
|
|
SStream_concat1(O, ',');
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// LBARXL, LDARXL, LHARXL, LQARXL, LWARXL
|
|
SStream_concat0(O, ", 1");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// MTFSFI
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// MTFSFI_rec
|
|
printU1ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// PLBZ, PLBZ8, PLD, PLFD, PLFS, PLHA, PLHA8, PLHZ, PLHZ8, PLWA, PLWA8, P...
|
|
SStream_concat0(O, ", 0");
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 5 bits for 23 unique commands.
|
|
switch ((Bits >> 34) & 31) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDI_rec, CLRRDI, CLRRDI_rec, EXTLDI, EXTLDI_rec, EXTRDI...
|
|
printU6ImmOperand(MI, 2, O);
|
|
break;
|
|
case 1:
|
|
// CLRLSLWI, CLRLSLWI_rec, CLRRWI, CLRRWI_rec, EXTLWI, EXTLWI_rec, EXTRWI...
|
|
printU5ImmOperand(MI, 2, O);
|
|
break;
|
|
case 2:
|
|
// PSUBI, PADDI, PADDI8
|
|
printS34ImmOperand(MI, 2, O);
|
|
break;
|
|
case 3:
|
|
// SUBI, SUBIC, SUBIC_rec, SUBIS, ADDI, ADDI8, ADDIC, ADDIC8, ADDIC_rec, ...
|
|
printS16ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADD4, ADD4O, ADD4O_rec, ADD4TLS, ADD4_rec, ADD8, ADD8O, ADD8O_rec, ADD...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 5:
|
|
// ANDI8_rec, ANDIS8_rec, ANDIS_rec, ANDI_rec, CMPLDI, CMPLWI, ORI, ORI8,...
|
|
printU16ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// BCDCFN_rec, BCDCFSQ_rec, BCDCFZ_rec, BCDCTZ_rec, BCDSETSGN_rec, CP_PAS...
|
|
printU1ImmOperand(MI, 2, O);
|
|
break;
|
|
case 7:
|
|
// CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H, XXLEQVOnes, XXLXORdpz, XXLXO...
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// DMXXEXTFDMR256, DMXXINSTFDMR256, QVESPLATI, QVESPLATIb, QVESPLATIs, XX...
|
|
printU2ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
|
|
printU5ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// EVADDIW, XXPERMDIs, XXSLDWIs
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 11:
|
|
// PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 12:
|
|
// RLDIMI, RLDIMI_rec
|
|
printU6ImmOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU6ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// RLWIMI, RLWIMI8, RLWIMI8_rec, RLWIMI_rec
|
|
printU5ImmOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU5ImmOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printU5ImmOperand(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTW
|
|
printU5ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// VEXTRACTD, VEXTRACTUB, VEXTRACTUH, VEXTRACTUW, VINSERTD, VINSERTW
|
|
printU4ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// VGNB
|
|
printU3ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// XSTSTDCDP, XSTSTDCQP, XSTSTDCSP, XVTSTDCDP, XVTSTDCSP
|
|
printU7ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// XXEXTRACTUW
|
|
printU4ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// XXGENPCVBM, XXGENPCVDM, XXGENPCVHM, XXGENPCVWM
|
|
printS5ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// XXINSERTW
|
|
printU4ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// gBC, gBCL
|
|
printBranchOperand(MI, Address, 2, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// gBCA, gBCLA
|
|
printAbsBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 2 bits for 4 unique commands.
|
|
switch ((Bits >> 39) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, EXTLDI, EXTLDI_rec, EX...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// CLRRDI, CLRRDI_rec, CLRRWI, CLRRWI_rec, PSUBI, ROTRDI, ROTRDI_rec, ROT...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// DMXXINSTFDMR512, PADDI, PADDI8
|
|
SStream_concat0(O, ", 0");
|
|
return;
|
|
break;
|
|
case 3:
|
|
// DMXXINSTFDMR512_HI
|
|
SStream_concat0(O, ", 1");
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 6 encoded into 4 bits for 11 unique commands.
|
|
switch ((Bits >> 41) & 15) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDI_rec, EXTLDI, EXTLDI_rec, EXTRDI, EXTRDI_rec, INSRDI...
|
|
printU6ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI...
|
|
printU5ImmOperand(MI, 3, O);
|
|
break;
|
|
case 2:
|
|
// RLWIMIbm, RLWIMIbm_rec, RLWINMbm, RLWINMbm_rec, RLWNMbm, RLWNMbm_rec, ...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 3:
|
|
// ADDEX, ADDEX8, DQUA, DQUAQ, DQUAQ_rec, DQUA_rec, DRRND, DRRNDQ, DRRNDQ...
|
|
printU2ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// BCDADD_rec, BCDSR_rec, BCDSUB_rec, BCDS_rec, BCDTRUNC_rec, PSQ_LUX, PS...
|
|
printU1ImmOperand(MI, 3, O);
|
|
break;
|
|
case 5:
|
|
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM...
|
|
printU4ImmOperand(MI, 3, O);
|
|
break;
|
|
case 6:
|
|
// PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF...
|
|
printU4ImmOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 7:
|
|
// QVFLOGICAL, QVFLOGICALb, QVFLOGICALs
|
|
printU12ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// QVFMADDS, QVFMSUBS, QVFNMADDS, QVFNMSUBS, QVFSEL, QVFSELb, QVFSELbb, Q...
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// VSLDBI, VSRDBI
|
|
printU3ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// XXPERMDIs, XXSLDWIs
|
|
printU2ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 7 encoded into 2 bits for 4 unique commands.
|
|
switch ((Bits >> 45) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF...
|
|
printU4ImmOperand(MI, 5, O);
|
|
break;
|
|
case 3:
|
|
// PMXVF64GERNN, PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVF64GERWNN,...
|
|
printU2ImmOperand(MI, 5, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 8 encoded into 3 bits for 7 unique commands.
|
|
switch ((Bits >> 47) & 7) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM...
|
|
printU4ImmOperand(MI, 4, O);
|
|
break;
|
|
case 1:
|
|
// PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// PMXVF32GERNN, PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF32GERWNN,...
|
|
return;
|
|
break;
|
|
case 3:
|
|
// PMXVF64GER, PMXVF64GERW
|
|
printU2ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// PSQ_LUX, PSQ_LX, PSQ_STUX, PSQ_STX, XXPERMX
|
|
printU3ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// RLWINM, RLWINM8, RLWINM8_rec, RLWINM_rec, RLWNM, RLWNM8, RLWNM8_rec, R...
|
|
printU5ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// XXEVAL
|
|
printU8ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 9 encoded into 3 bits for 5 unique commands.
|
|
switch ((Bits >> 50) & 7) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVI16GER2, P...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF...
|
|
printU2ImmOperand(MI, 6, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// PMXVF32GER, PMXVF32GERW
|
|
return;
|
|
break;
|
|
case 3:
|
|
// PMXVI4GER8PP, PMXVI4GER8WPP
|
|
printU8ImmOperand(MI, 6, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// PMXVI8GER4PP, PMXVI8GER4SPP, PMXVI8GER4WPP, PMXVI8GER4WSPP
|
|
printU4ImmOperand(MI, 6, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 10 encoded into 2 bits for 3 unique commands.
|
|
switch ((Bits >> 53) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVI16GER2, P...
|
|
printU2ImmOperand(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// PMXVI4GER8, PMXVI4GER8W
|
|
printU8ImmOperand(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// PMXVI8GER4, PMXVI8GER4W
|
|
printU4ImmOperand(MI, 5, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
static const char *getRegisterName(unsigned RegNo) {
|
|
#ifndef CAPSTONE_DIET
|
|
CS_ASSERT_RET_VAL(RegNo && RegNo < 580 && "Invalid register number!", NULL);
|
|
|
|
static const char AsmStrs[] = {
|
|
/* 0 */ "**ROUNDING MODE**\0"
|
|
/* 18 */ "**FRAME POINTER**\0"
|
|
/* 36 */ "**BASE POINTER**\0"
|
|
/* 53 */ "H10\0"
|
|
/* 57 */ "f10\0"
|
|
/* 61 */ "fp10\0"
|
|
/* 66 */ "vsp10\0"
|
|
/* 72 */ "dmrrowp10\0"
|
|
/* 82 */ "q10\0"
|
|
/* 86 */ "r10\0"
|
|
/* 90 */ "vs10\0"
|
|
/* 95 */ "v10\0"
|
|
/* 99 */ "dmrrow10\0"
|
|
/* 108 */ "H20\0"
|
|
/* 112 */ "f20\0"
|
|
/* 116 */ "fp20\0"
|
|
/* 121 */ "vsp20\0"
|
|
/* 127 */ "dmrrowp20\0"
|
|
/* 137 */ "q20\0"
|
|
/* 141 */ "r20\0"
|
|
/* 145 */ "vs20\0"
|
|
/* 150 */ "v20\0"
|
|
/* 154 */ "dmrrow20\0"
|
|
/* 163 */ "H30\0"
|
|
/* 167 */ "f30\0"
|
|
/* 171 */ "fp30\0"
|
|
/* 176 */ "vsp30\0"
|
|
/* 182 */ "dmrrowp30\0"
|
|
/* 192 */ "q30\0"
|
|
/* 196 */ "r30\0"
|
|
/* 200 */ "vs30\0"
|
|
/* 205 */ "v30\0"
|
|
/* 209 */ "dmrrow30\0"
|
|
/* 218 */ "vsp40\0"
|
|
/* 224 */ "vs40\0"
|
|
/* 229 */ "dmrrow40\0"
|
|
/* 238 */ "vsp50\0"
|
|
/* 244 */ "vs50\0"
|
|
/* 249 */ "dmrrow50\0"
|
|
/* 258 */ "vsp60\0"
|
|
/* 264 */ "vs60\0"
|
|
/* 269 */ "dmrrow60\0"
|
|
/* 278 */ "H0\0"
|
|
/* 281 */ "wacc0\0"
|
|
/* 287 */ "f0\0"
|
|
/* 290 */ "wacc_hi0\0"
|
|
/* 299 */ "fp0\0"
|
|
/* 303 */ "dmrp0\0"
|
|
/* 309 */ "vsp0\0"
|
|
/* 314 */ "dmrrowp0\0"
|
|
/* 323 */ "q0\0"
|
|
/* 326 */ "cr0\0"
|
|
/* 330 */ "dmr0\0"
|
|
/* 335 */ "vs0\0"
|
|
/* 339 */ "v0\0"
|
|
/* 342 */ "dmrrow0\0"
|
|
/* 350 */ "H11\0"
|
|
/* 354 */ "f11\0"
|
|
/* 358 */ "dmrrowp11\0"
|
|
/* 368 */ "q11\0"
|
|
/* 372 */ "r11\0"
|
|
/* 376 */ "vs11\0"
|
|
/* 381 */ "v11\0"
|
|
/* 385 */ "dmrrow11\0"
|
|
/* 394 */ "H21\0"
|
|
/* 398 */ "f21\0"
|
|
/* 402 */ "dmrrowp21\0"
|
|
/* 412 */ "q21\0"
|
|
/* 416 */ "r21\0"
|
|
/* 420 */ "vs21\0"
|
|
/* 425 */ "v21\0"
|
|
/* 429 */ "dmrrow21\0"
|
|
/* 438 */ "H31\0"
|
|
/* 442 */ "f31\0"
|
|
/* 446 */ "dmrrowp31\0"
|
|
/* 456 */ "q31\0"
|
|
/* 460 */ "r31\0"
|
|
/* 464 */ "vs31\0"
|
|
/* 469 */ "v31\0"
|
|
/* 473 */ "dmrrow31\0"
|
|
/* 482 */ "vs41\0"
|
|
/* 487 */ "dmrrow41\0"
|
|
/* 496 */ "vs51\0"
|
|
/* 501 */ "dmrrow51\0"
|
|
/* 510 */ "vs61\0"
|
|
/* 515 */ "dmrrow61\0"
|
|
/* 524 */ "H1\0"
|
|
/* 527 */ "wacc1\0"
|
|
/* 533 */ "f1\0"
|
|
/* 536 */ "wacc_hi1\0"
|
|
/* 545 */ "dmrp1\0"
|
|
/* 551 */ "dmrrowp1\0"
|
|
/* 560 */ "q1\0"
|
|
/* 563 */ "cr1\0"
|
|
/* 567 */ "dmr1\0"
|
|
/* 572 */ "vs1\0"
|
|
/* 576 */ "v1\0"
|
|
/* 579 */ "dmrrow1\0"
|
|
/* 587 */ "H12\0"
|
|
/* 591 */ "f12\0"
|
|
/* 595 */ "fp12\0"
|
|
/* 600 */ "vsp12\0"
|
|
/* 606 */ "dmrrowp12\0"
|
|
/* 616 */ "q12\0"
|
|
/* 620 */ "r12\0"
|
|
/* 624 */ "vs12\0"
|
|
/* 629 */ "v12\0"
|
|
/* 633 */ "dmrrow12\0"
|
|
/* 642 */ "H22\0"
|
|
/* 646 */ "f22\0"
|
|
/* 650 */ "fp22\0"
|
|
/* 655 */ "vsp22\0"
|
|
/* 661 */ "dmrrowp22\0"
|
|
/* 671 */ "q22\0"
|
|
/* 675 */ "r22\0"
|
|
/* 679 */ "vs22\0"
|
|
/* 684 */ "v22\0"
|
|
/* 688 */ "dmrrow22\0"
|
|
/* 697 */ "vsp32\0"
|
|
/* 703 */ "vs32\0"
|
|
/* 708 */ "dmrrow32\0"
|
|
/* 717 */ "vsp42\0"
|
|
/* 723 */ "vs42\0"
|
|
/* 728 */ "dmrrow42\0"
|
|
/* 737 */ "vsp52\0"
|
|
/* 743 */ "vs52\0"
|
|
/* 748 */ "dmrrow52\0"
|
|
/* 757 */ "vsp62\0"
|
|
/* 763 */ "vs62\0"
|
|
/* 768 */ "dmrrow62\0"
|
|
/* 777 */ "H2\0"
|
|
/* 780 */ "wacc2\0"
|
|
/* 786 */ "f2\0"
|
|
/* 789 */ "wacc_hi2\0"
|
|
/* 798 */ "fp2\0"
|
|
/* 802 */ "dmrp2\0"
|
|
/* 808 */ "vsp2\0"
|
|
/* 813 */ "dmrrowp2\0"
|
|
/* 822 */ "q2\0"
|
|
/* 825 */ "cr2\0"
|
|
/* 829 */ "dmr2\0"
|
|
/* 834 */ "vs2\0"
|
|
/* 838 */ "v2\0"
|
|
/* 841 */ "dmrrow2\0"
|
|
/* 849 */ "H13\0"
|
|
/* 853 */ "f13\0"
|
|
/* 857 */ "dmrrowp13\0"
|
|
/* 867 */ "q13\0"
|
|
/* 871 */ "r13\0"
|
|
/* 875 */ "vs13\0"
|
|
/* 880 */ "v13\0"
|
|
/* 884 */ "dmrrow13\0"
|
|
/* 893 */ "H23\0"
|
|
/* 897 */ "f23\0"
|
|
/* 901 */ "dmrrowp23\0"
|
|
/* 911 */ "q23\0"
|
|
/* 915 */ "r23\0"
|
|
/* 919 */ "vs23\0"
|
|
/* 924 */ "v23\0"
|
|
/* 928 */ "dmrrow23\0"
|
|
/* 937 */ "vs33\0"
|
|
/* 942 */ "dmrrow33\0"
|
|
/* 951 */ "vs43\0"
|
|
/* 956 */ "dmrrow43\0"
|
|
/* 965 */ "vs53\0"
|
|
/* 970 */ "dmrrow53\0"
|
|
/* 979 */ "vs63\0"
|
|
/* 984 */ "dmrrow63\0"
|
|
/* 993 */ "H3\0"
|
|
/* 996 */ "wacc3\0"
|
|
/* 1002 */ "f3\0"
|
|
/* 1005 */ "wacc_hi3\0"
|
|
/* 1014 */ "dmrp3\0"
|
|
/* 1020 */ "dmrrowp3\0"
|
|
/* 1029 */ "q3\0"
|
|
/* 1032 */ "cr3\0"
|
|
/* 1036 */ "dmr3\0"
|
|
/* 1041 */ "vs3\0"
|
|
/* 1045 */ "v3\0"
|
|
/* 1048 */ "dmrrow3\0"
|
|
/* 1056 */ "H14\0"
|
|
/* 1060 */ "f14\0"
|
|
/* 1064 */ "fp14\0"
|
|
/* 1069 */ "vsp14\0"
|
|
/* 1075 */ "dmrrowp14\0"
|
|
/* 1085 */ "q14\0"
|
|
/* 1089 */ "r14\0"
|
|
/* 1093 */ "vs14\0"
|
|
/* 1098 */ "v14\0"
|
|
/* 1102 */ "dmrrow14\0"
|
|
/* 1111 */ "H24\0"
|
|
/* 1115 */ "f24\0"
|
|
/* 1119 */ "fp24\0"
|
|
/* 1124 */ "vsp24\0"
|
|
/* 1130 */ "dmrrowp24\0"
|
|
/* 1140 */ "q24\0"
|
|
/* 1144 */ "r24\0"
|
|
/* 1148 */ "vs24\0"
|
|
/* 1153 */ "v24\0"
|
|
/* 1157 */ "dmrrow24\0"
|
|
/* 1166 */ "vsp34\0"
|
|
/* 1172 */ "vs34\0"
|
|
/* 1177 */ "dmrrow34\0"
|
|
/* 1186 */ "vsp44\0"
|
|
/* 1192 */ "vs44\0"
|
|
/* 1197 */ "dmrrow44\0"
|
|
/* 1206 */ "vsp54\0"
|
|
/* 1212 */ "vs54\0"
|
|
/* 1217 */ "dmrrow54\0"
|
|
/* 1226 */ "H4\0"
|
|
/* 1229 */ "wacc4\0"
|
|
/* 1235 */ "f4\0"
|
|
/* 1238 */ "wacc_hi4\0"
|
|
/* 1247 */ "fp4\0"
|
|
/* 1251 */ "vsp4\0"
|
|
/* 1256 */ "dmrrowp4\0"
|
|
/* 1265 */ "q4\0"
|
|
/* 1268 */ "cr4\0"
|
|
/* 1272 */ "dmr4\0"
|
|
/* 1277 */ "vs4\0"
|
|
/* 1281 */ "v4\0"
|
|
/* 1284 */ "dmrrow4\0"
|
|
/* 1292 */ "H15\0"
|
|
/* 1296 */ "f15\0"
|
|
/* 1300 */ "dmrrowp15\0"
|
|
/* 1310 */ "q15\0"
|
|
/* 1314 */ "r15\0"
|
|
/* 1318 */ "vs15\0"
|
|
/* 1323 */ "v15\0"
|
|
/* 1327 */ "dmrrow15\0"
|
|
/* 1336 */ "H25\0"
|
|
/* 1340 */ "f25\0"
|
|
/* 1344 */ "dmrrowp25\0"
|
|
/* 1354 */ "q25\0"
|
|
/* 1358 */ "r25\0"
|
|
/* 1362 */ "vs25\0"
|
|
/* 1367 */ "v25\0"
|
|
/* 1371 */ "dmrrow25\0"
|
|
/* 1380 */ "vs35\0"
|
|
/* 1385 */ "dmrrow35\0"
|
|
/* 1394 */ "vs45\0"
|
|
/* 1399 */ "dmrrow45\0"
|
|
/* 1408 */ "vs55\0"
|
|
/* 1413 */ "dmrrow55\0"
|
|
/* 1422 */ "H5\0"
|
|
/* 1425 */ "wacc5\0"
|
|
/* 1431 */ "f5\0"
|
|
/* 1434 */ "wacc_hi5\0"
|
|
/* 1443 */ "dmrrowp5\0"
|
|
/* 1452 */ "q5\0"
|
|
/* 1455 */ "cr5\0"
|
|
/* 1459 */ "dmr5\0"
|
|
/* 1464 */ "vs5\0"
|
|
/* 1468 */ "v5\0"
|
|
/* 1471 */ "dmrrow5\0"
|
|
/* 1479 */ "H16\0"
|
|
/* 1483 */ "f16\0"
|
|
/* 1487 */ "fp16\0"
|
|
/* 1492 */ "vsp16\0"
|
|
/* 1498 */ "dmrrowp16\0"
|
|
/* 1508 */ "q16\0"
|
|
/* 1512 */ "r16\0"
|
|
/* 1516 */ "vs16\0"
|
|
/* 1521 */ "v16\0"
|
|
/* 1525 */ "dmrrow16\0"
|
|
/* 1534 */ "H26\0"
|
|
/* 1538 */ "f26\0"
|
|
/* 1542 */ "fp26\0"
|
|
/* 1547 */ "vsp26\0"
|
|
/* 1553 */ "dmrrowp26\0"
|
|
/* 1563 */ "q26\0"
|
|
/* 1567 */ "r26\0"
|
|
/* 1571 */ "vs26\0"
|
|
/* 1576 */ "v26\0"
|
|
/* 1580 */ "dmrrow26\0"
|
|
/* 1589 */ "vsp36\0"
|
|
/* 1595 */ "vs36\0"
|
|
/* 1600 */ "dmrrow36\0"
|
|
/* 1609 */ "vsp46\0"
|
|
/* 1615 */ "vs46\0"
|
|
/* 1620 */ "dmrrow46\0"
|
|
/* 1629 */ "vsp56\0"
|
|
/* 1635 */ "vs56\0"
|
|
/* 1640 */ "dmrrow56\0"
|
|
/* 1649 */ "H6\0"
|
|
/* 1652 */ "wacc6\0"
|
|
/* 1658 */ "f6\0"
|
|
/* 1661 */ "wacc_hi6\0"
|
|
/* 1670 */ "fp6\0"
|
|
/* 1674 */ "vsp6\0"
|
|
/* 1679 */ "dmrrowp6\0"
|
|
/* 1688 */ "q6\0"
|
|
/* 1691 */ "cr6\0"
|
|
/* 1695 */ "dmr6\0"
|
|
/* 1700 */ "vs6\0"
|
|
/* 1704 */ "v6\0"
|
|
/* 1707 */ "dmrrow6\0"
|
|
/* 1715 */ "H17\0"
|
|
/* 1719 */ "f17\0"
|
|
/* 1723 */ "dmrrowp17\0"
|
|
/* 1733 */ "q17\0"
|
|
/* 1737 */ "r17\0"
|
|
/* 1741 */ "vs17\0"
|
|
/* 1746 */ "v17\0"
|
|
/* 1750 */ "dmrrow17\0"
|
|
/* 1759 */ "H27\0"
|
|
/* 1763 */ "f27\0"
|
|
/* 1767 */ "dmrrowp27\0"
|
|
/* 1777 */ "q27\0"
|
|
/* 1781 */ "r27\0"
|
|
/* 1785 */ "vs27\0"
|
|
/* 1790 */ "v27\0"
|
|
/* 1794 */ "dmrrow27\0"
|
|
/* 1803 */ "vs37\0"
|
|
/* 1808 */ "dmrrow37\0"
|
|
/* 1817 */ "vs47\0"
|
|
/* 1822 */ "dmrrow47\0"
|
|
/* 1831 */ "vs57\0"
|
|
/* 1836 */ "dmrrow57\0"
|
|
/* 1845 */ "H7\0"
|
|
/* 1848 */ "wacc7\0"
|
|
/* 1854 */ "f7\0"
|
|
/* 1857 */ "wacc_hi7\0"
|
|
/* 1866 */ "dmrrowp7\0"
|
|
/* 1875 */ "q7\0"
|
|
/* 1878 */ "cr7\0"
|
|
/* 1882 */ "dmr7\0"
|
|
/* 1887 */ "vs7\0"
|
|
/* 1891 */ "v7\0"
|
|
/* 1894 */ "dmrrow7\0"
|
|
/* 1902 */ "H18\0"
|
|
/* 1906 */ "f18\0"
|
|
/* 1910 */ "fp18\0"
|
|
/* 1915 */ "vsp18\0"
|
|
/* 1921 */ "dmrrowp18\0"
|
|
/* 1931 */ "q18\0"
|
|
/* 1935 */ "r18\0"
|
|
/* 1939 */ "vs18\0"
|
|
/* 1944 */ "v18\0"
|
|
/* 1948 */ "dmrrow18\0"
|
|
/* 1957 */ "H28\0"
|
|
/* 1961 */ "f28\0"
|
|
/* 1965 */ "fp28\0"
|
|
/* 1970 */ "vsp28\0"
|
|
/* 1976 */ "dmrrowp28\0"
|
|
/* 1986 */ "q28\0"
|
|
/* 1990 */ "r28\0"
|
|
/* 1994 */ "vs28\0"
|
|
/* 1999 */ "v28\0"
|
|
/* 2003 */ "dmrrow28\0"
|
|
/* 2012 */ "vsp38\0"
|
|
/* 2018 */ "vs38\0"
|
|
/* 2023 */ "dmrrow38\0"
|
|
/* 2032 */ "vsp48\0"
|
|
/* 2038 */ "vs48\0"
|
|
/* 2043 */ "dmrrow48\0"
|
|
/* 2052 */ "vsp58\0"
|
|
/* 2058 */ "vs58\0"
|
|
/* 2063 */ "dmrrow58\0"
|
|
/* 2072 */ "H8\0"
|
|
/* 2075 */ "f8\0"
|
|
/* 2078 */ "fp8\0"
|
|
/* 2082 */ "vsp8\0"
|
|
/* 2087 */ "dmrrowp8\0"
|
|
/* 2096 */ "q8\0"
|
|
/* 2099 */ "r8\0"
|
|
/* 2102 */ "vs8\0"
|
|
/* 2106 */ "v8\0"
|
|
/* 2109 */ "dmrrow8\0"
|
|
/* 2117 */ "H19\0"
|
|
/* 2121 */ "f19\0"
|
|
/* 2125 */ "dmrrowp19\0"
|
|
/* 2135 */ "q19\0"
|
|
/* 2139 */ "r19\0"
|
|
/* 2143 */ "vs19\0"
|
|
/* 2148 */ "v19\0"
|
|
/* 2152 */ "dmrrow19\0"
|
|
/* 2161 */ "H29\0"
|
|
/* 2165 */ "f29\0"
|
|
/* 2169 */ "dmrrowp29\0"
|
|
/* 2179 */ "q29\0"
|
|
/* 2183 */ "r29\0"
|
|
/* 2187 */ "vs29\0"
|
|
/* 2192 */ "v29\0"
|
|
/* 2196 */ "dmrrow29\0"
|
|
/* 2205 */ "vs39\0"
|
|
/* 2210 */ "dmrrow39\0"
|
|
/* 2219 */ "vs49\0"
|
|
/* 2224 */ "dmrrow49\0"
|
|
/* 2233 */ "vs59\0"
|
|
/* 2238 */ "dmrrow59\0"
|
|
/* 2247 */ "H9\0"
|
|
/* 2250 */ "f9\0"
|
|
/* 2253 */ "dmrrowp9\0"
|
|
/* 2262 */ "q9\0"
|
|
/* 2265 */ "r9\0"
|
|
/* 2268 */ "vs9\0"
|
|
/* 2272 */ "v9\0"
|
|
/* 2275 */ "dmrrow9\0"
|
|
/* 2283 */ "vrsave\0"
|
|
/* 2290 */ "spefscr\0"
|
|
/* 2298 */ "xer\0"
|
|
/* 2302 */ "lr\0"
|
|
/* 2305 */ "ctr\0"
|
|
};
|
|
static const uint16_t RegAsmOffset[] = {
|
|
36, 2298, 2305, 18, 2302, 0, 2290, 2283, 2298, 55, 282, 528, 781, 997,
|
|
1230, 1426, 1653, 1849, 36, 326, 563, 825, 1032, 1268, 1455, 1691, 1878, 2305,
|
|
330, 567, 829, 1036, 1272, 1459, 1695, 1882, 342, 579, 841, 1048, 1284, 1471,
|
|
1707, 1894, 2109, 2275, 99, 385, 633, 884, 1102, 1327, 1525, 1750, 1948, 2152,
|
|
154, 429, 688, 928, 1157, 1371, 1580, 1794, 2003, 2196, 209, 473, 708, 942,
|
|
1177, 1385, 1600, 1808, 2023, 2210, 229, 487, 728, 956, 1197, 1399, 1620, 1822,
|
|
2043, 2224, 249, 501, 748, 970, 1217, 1413, 1640, 1836, 2063, 2238, 269, 515,
|
|
768, 984, 314, 551, 813, 1020, 1256, 1443, 1679, 1866, 2087, 2253, 72, 358,
|
|
606, 857, 1075, 1300, 1498, 1723, 1921, 2125, 127, 402, 661, 901, 1130, 1344,
|
|
1553, 1767, 1976, 2169, 182, 446, 303, 545, 802, 1014, 287, 533, 786, 1002,
|
|
1235, 1431, 1658, 1854, 2075, 2250, 57, 354, 591, 853, 1060, 1296, 1483, 1719,
|
|
1906, 2121, 112, 398, 646, 897, 1115, 1340, 1538, 1763, 1961, 2165, 167, 442,
|
|
18, 299, 798, 1247, 1670, 2078, 61, 595, 1064, 1487, 1910, 116, 650, 1119,
|
|
1542, 1965, 171, 278, 524, 777, 993, 1226, 1422, 1649, 1845, 2072, 2247, 53,
|
|
350, 587, 849, 1056, 1292, 1479, 1715, 1902, 2117, 108, 394, 642, 893, 1111,
|
|
1336, 1534, 1759, 1957, 2161, 163, 438, 2302, 323, 560, 822, 1029, 1265, 1452,
|
|
1688, 1875, 2096, 2262, 82, 368, 616, 867, 1085, 1310, 1508, 1733, 1931, 2135,
|
|
137, 412, 671, 911, 1140, 1354, 1563, 1777, 1986, 2179, 192, 456, 327, 564,
|
|
826, 1033, 1269, 1456, 1692, 1879, 2099, 2265, 86, 372, 620, 871, 1089, 1314,
|
|
1512, 1737, 1935, 2139, 141, 416, 675, 915, 1144, 1358, 1567, 1781, 1990, 2183,
|
|
196, 460, 327, 564, 826, 1033, 1269, 1456, 1692, 1879, 2099, 2265, 86, 372,
|
|
620, 871, 1089, 1314, 1512, 1737, 1935, 2139, 141, 416, 675, 915, 1144, 1358,
|
|
1567, 1781, 1990, 2183, 196, 460, 282, 528, 781, 997, 1230, 1426, 1653, 1849,
|
|
339, 576, 838, 1045, 1281, 1468, 1704, 1891, 2106, 2272, 95, 381, 629, 880,
|
|
1098, 1323, 1521, 1746, 1944, 2148, 150, 425, 684, 924, 1153, 1367, 1576, 1790,
|
|
1999, 2192, 205, 469, 339, 576, 838, 1045, 1281, 1468, 1704, 1891, 2106, 2272,
|
|
95, 381, 629, 880, 1098, 1323, 1521, 1746, 1944, 2148, 150, 425, 684, 924,
|
|
1153, 1367, 1576, 1790, 1999, 2192, 205, 469, 335, 572, 834, 1041, 1277, 1464,
|
|
1700, 1887, 2102, 2268, 90, 376, 624, 875, 1093, 1318, 1516, 1741, 1939, 2143,
|
|
145, 420, 679, 919, 1148, 1362, 1571, 1785, 1994, 2187, 200, 464, 309, 808,
|
|
1251, 1674, 2082, 66, 600, 1069, 1492, 1915, 121, 655, 1124, 1547, 1970, 176,
|
|
697, 1166, 1589, 2012, 218, 717, 1186, 1609, 2032, 238, 737, 1206, 1629, 2052,
|
|
258, 757, 703, 937, 1172, 1380, 1595, 1803, 2018, 2205, 224, 482, 723, 951,
|
|
1192, 1394, 1615, 1817, 2038, 2219, 244, 496, 743, 965, 1212, 1408, 1635, 1831,
|
|
2058, 2233, 264, 510, 763, 979, 281, 527, 780, 996, 1229, 1425, 1652, 1848,
|
|
290, 536, 789, 1005, 1238, 1434, 1661, 1857, 327, 564, 826, 1033, 1269, 1456,
|
|
1692, 1879, 2099, 2265, 86, 372, 620, 871, 1089, 1314, 1512, 1737, 1935, 2139,
|
|
141, 416, 675, 915, 1144, 1358, 1567, 1781, 1990, 2183, 196, 460, 55, 589,
|
|
1481, 54, 1057, 1903, 643, 1535, 164, 352, 1294, 2119, 850, 1716, 395, 1337,
|
|
2162, 55, 1058, 1904, 588, 1480, 109, 1112, 1958, 851, 1717, 351, 1293, 2118,
|
|
894, 1760, 439, 327, 826, 1269, 1692, 2099, 86, 620, 1089, 1512, 1935, 141,
|
|
675, 1144, 1567, 1990, 196,
|
|
};
|
|
|
|
CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) &&
|
|
"Invalid alt name index for register!", NULL);
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
#else
|
|
return NULL;
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
|
|
#ifndef CAPSTONE_DIET
|
|
static const PatternsForOpcode OpToPatterns[] = {
|
|
{PPC_ADDI, 0, 1 },
|
|
{PPC_ADDI8, 1, 1 },
|
|
{PPC_ADDIS, 2, 1 },
|
|
{PPC_ADDIS8, 3, 1 },
|
|
{PPC_ADDPCIS, 4, 1 },
|
|
{PPC_BCC, 5, 24 },
|
|
{PPC_BCCA, 29, 24 },
|
|
{PPC_BCCCTR, 53, 24 },
|
|
{PPC_BCCCTRL, 77, 24 },
|
|
{PPC_BCCL, 101, 24 },
|
|
{PPC_BCCLA, 125, 24 },
|
|
{PPC_BCCLR, 149, 24 },
|
|
{PPC_BCCLRL, 173, 24 },
|
|
{PPC_CMPD, 197, 1 },
|
|
{PPC_CMPDI, 198, 1 },
|
|
{PPC_CMPLD, 199, 1 },
|
|
{PPC_CMPLDI, 200, 1 },
|
|
{PPC_CMPLW, 201, 1 },
|
|
{PPC_CMPLWI, 202, 1 },
|
|
{PPC_CMPW, 203, 1 },
|
|
{PPC_CMPWI, 204, 1 },
|
|
{PPC_CNTLZW, 205, 1 },
|
|
{PPC_CNTLZW8, 206, 1 },
|
|
{PPC_CNTLZW8_rec, 207, 1 },
|
|
{PPC_CNTLZW_rec, 208, 1 },
|
|
{PPC_CP_PASTE_rec, 209, 1 },
|
|
{PPC_CREQV, 210, 1 },
|
|
{PPC_CRNOR, 211, 1 },
|
|
{PPC_CROR, 212, 1 },
|
|
{PPC_CRXOR, 213, 1 },
|
|
{PPC_ISEL, 214, 3 },
|
|
{PPC_ISEL8, 217, 3 },
|
|
{PPC_MBAR, 220, 1 },
|
|
{PPC_MFDCR, 221, 8 },
|
|
{PPC_MFSPR, 229, 46 },
|
|
{PPC_MFSPR8, 275, 19 },
|
|
{PPC_MFTB, 294, 1 },
|
|
{PPC_MFUDSCR, 295, 1 },
|
|
{PPC_MFVRSAVE, 296, 1 },
|
|
{PPC_MFVSRD, 297, 1 },
|
|
{PPC_MFVSRWZ, 298, 1 },
|
|
{PPC_MTCRF, 299, 1 },
|
|
{PPC_MTCRF8, 300, 1 },
|
|
{PPC_MTDCR, 301, 8 },
|
|
{PPC_MTFSF, 309, 1 },
|
|
{PPC_MTFSFI, 310, 1 },
|
|
{PPC_MTFSFI_rec, 311, 1 },
|
|
{PPC_MTFSF_rec, 312, 1 },
|
|
{PPC_MTMSR, 313, 1 },
|
|
{PPC_MTMSRD, 314, 1 },
|
|
{PPC_MTSPR, 315, 45 },
|
|
{PPC_MTSPR8, 360, 18 },
|
|
{PPC_MTUDSCR, 378, 1 },
|
|
{PPC_MTVRSAVE, 379, 1 },
|
|
{PPC_MTVSRD, 380, 1 },
|
|
{PPC_MTVSRWA, 381, 1 },
|
|
{PPC_MTVSRWZ, 382, 1 },
|
|
{PPC_NOR, 383, 1 },
|
|
{PPC_NOR8, 384, 1 },
|
|
{PPC_NOR8_rec, 385, 1 },
|
|
{PPC_NOR_rec, 386, 1 },
|
|
{PPC_OR, 387, 1 },
|
|
{PPC_OR8, 388, 1 },
|
|
{PPC_OR8_rec, 389, 1 },
|
|
{PPC_ORI, 390, 1 },
|
|
{PPC_ORI8, 391, 1 },
|
|
{PPC_OR_rec, 392, 1 },
|
|
{PPC_PADDI8, 393, 1 },
|
|
{PPC_QVFLOGICALb, 394, 12 },
|
|
{PPC_RFEBB, 406, 1 },
|
|
{PPC_RLDCL, 407, 1 },
|
|
{PPC_RLDCL_rec, 408, 1 },
|
|
{PPC_RLDICL, 409, 2 },
|
|
{PPC_RLDICL_32_64, 411, 2 },
|
|
{PPC_RLDICL_rec, 413, 2 },
|
|
{PPC_RLWINM, 415, 2 },
|
|
{PPC_RLWINM8, 417, 2 },
|
|
{PPC_RLWINM8_rec, 419, 2 },
|
|
{PPC_RLWINM_rec, 421, 2 },
|
|
{PPC_RLWNM, 423, 1 },
|
|
{PPC_RLWNM8, 424, 1 },
|
|
{PPC_RLWNM8_rec, 425, 1 },
|
|
{PPC_RLWNM_rec, 426, 1 },
|
|
{PPC_SC, 427, 1 },
|
|
{PPC_SUBF, 428, 1 },
|
|
{PPC_SUBF8, 429, 1 },
|
|
{PPC_SUBF8_rec, 430, 1 },
|
|
{PPC_SUBFC, 431, 1 },
|
|
{PPC_SUBFC8, 432, 1 },
|
|
{PPC_SUBFC8_rec, 433, 1 },
|
|
{PPC_SUBFC_rec, 434, 1 },
|
|
{PPC_SUBF_rec, 435, 1 },
|
|
{PPC_SYNC, 436, 3 },
|
|
{PPC_SYNCP10, 439, 8 },
|
|
{PPC_TD, 447, 7 },
|
|
{PPC_TDI, 454, 7 },
|
|
{PPC_TEND, 461, 2 },
|
|
{PPC_TLBIE, 463, 1 },
|
|
{PPC_TLBILX, 464, 4 },
|
|
{PPC_TLBRE2, 468, 2 },
|
|
{PPC_TLBWE2, 470, 2 },
|
|
{PPC_TSR, 472, 2 },
|
|
{PPC_TW, 474, 8 },
|
|
{PPC_TWI, 482, 7 },
|
|
{PPC_VNOR, 489, 1 },
|
|
{PPC_VOR, 490, 1 },
|
|
{PPC_WAIT, 491, 3 },
|
|
{PPC_WAITP10, 494, 2 },
|
|
{PPC_XORI, 496, 1 },
|
|
{PPC_XORI8, 497, 1 },
|
|
{PPC_XVCPSGNDP, 498, 1 },
|
|
{PPC_XVCPSGNSP, 499, 1 },
|
|
{PPC_XXPERMDI, 500, 5 },
|
|
{PPC_XXPERMDIs, 505, 3 },
|
|
{PPC_gBC, 508, 11 },
|
|
{PPC_gBCA, 519, 11 },
|
|
{PPC_gBCAat, 530, 8 },
|
|
{PPC_gBCCTR, 538, 7 },
|
|
{PPC_gBCCTRL, 545, 7 },
|
|
{PPC_gBCL, 552, 11 },
|
|
{PPC_gBCLA, 563, 11 },
|
|
{PPC_gBCLAat, 574, 8 },
|
|
{PPC_gBCLR, 582, 17 },
|
|
{PPC_gBCLRL, 599, 17 },
|
|
{PPC_gBCLat, 616, 8 },
|
|
{PPC_gBCat, 624, 8 },
|
|
{0}, };
|
|
|
|
static const AliasPattern Patterns[] = {
|
|
// PPC_ADDI - 0
|
|
{0, 0, 3, 2 },
|
|
// PPC_ADDI8 - 1
|
|
{0, 2, 3, 2 },
|
|
// PPC_ADDIS - 2
|
|
{12, 4, 3, 2 },
|
|
// PPC_ADDIS8 - 3
|
|
{12, 6, 3, 2 },
|
|
// PPC_ADDPCIS - 4
|
|
{25, 8, 2, 2 },
|
|
// PPC_BCC - 5
|
|
{33, 10, 3, 2 },
|
|
{46, 12, 3, 2 },
|
|
{55, 14, 3, 2 },
|
|
{69, 16, 3, 2 },
|
|
{79, 18, 3, 2 },
|
|
{93, 20, 3, 2 },
|
|
{103, 22, 3, 2 },
|
|
{116, 24, 3, 2 },
|
|
{125, 26, 3, 2 },
|
|
{139, 28, 3, 2 },
|
|
{149, 30, 3, 2 },
|
|
{163, 32, 3, 2 },
|
|
{173, 34, 3, 2 },
|
|
{186, 36, 3, 2 },
|
|
{195, 38, 3, 2 },
|
|
{209, 40, 3, 2 },
|
|
{219, 42, 3, 2 },
|
|
{233, 44, 3, 2 },
|
|
{243, 46, 3, 2 },
|
|
{256, 48, 3, 2 },
|
|
{265, 50, 3, 2 },
|
|
{279, 52, 3, 2 },
|
|
{289, 54, 3, 2 },
|
|
{303, 56, 3, 2 },
|
|
// PPC_BCCA - 29
|
|
{313, 58, 3, 2 },
|
|
{327, 60, 3, 2 },
|
|
{337, 62, 3, 2 },
|
|
{352, 64, 3, 2 },
|
|
{363, 66, 3, 2 },
|
|
{378, 68, 3, 2 },
|
|
{389, 70, 3, 2 },
|
|
{403, 72, 3, 2 },
|
|
{413, 74, 3, 2 },
|
|
{428, 76, 3, 2 },
|
|
{439, 78, 3, 2 },
|
|
{454, 80, 3, 2 },
|
|
{465, 82, 3, 2 },
|
|
{479, 84, 3, 2 },
|
|
{489, 86, 3, 2 },
|
|
{504, 88, 3, 2 },
|
|
{515, 90, 3, 2 },
|
|
{530, 92, 3, 2 },
|
|
{541, 94, 3, 2 },
|
|
{555, 96, 3, 2 },
|
|
{565, 98, 3, 2 },
|
|
{580, 100, 3, 2 },
|
|
{591, 102, 3, 2 },
|
|
{606, 104, 3, 2 },
|
|
// PPC_BCCCTR - 53
|
|
{617, 106, 2, 2 },
|
|
{627, 108, 2, 2 },
|
|
{634, 110, 2, 2 },
|
|
{645, 112, 2, 2 },
|
|
{653, 114, 2, 2 },
|
|
{664, 116, 2, 2 },
|
|
{672, 118, 2, 2 },
|
|
{682, 120, 2, 2 },
|
|
{689, 122, 2, 2 },
|
|
{700, 124, 2, 2 },
|
|
{708, 126, 2, 2 },
|
|
{719, 128, 2, 2 },
|
|
{727, 130, 2, 2 },
|
|
{737, 132, 2, 2 },
|
|
{744, 134, 2, 2 },
|
|
{755, 136, 2, 2 },
|
|
{763, 138, 2, 2 },
|
|
{774, 140, 2, 2 },
|
|
{782, 142, 2, 2 },
|
|
{792, 144, 2, 2 },
|
|
{799, 146, 2, 2 },
|
|
{810, 148, 2, 2 },
|
|
{818, 150, 2, 2 },
|
|
{829, 152, 2, 2 },
|
|
// PPC_BCCCTRL - 77
|
|
{837, 154, 2, 2 },
|
|
{848, 156, 2, 2 },
|
|
{856, 158, 2, 2 },
|
|
{868, 160, 2, 2 },
|
|
{877, 162, 2, 2 },
|
|
{889, 164, 2, 2 },
|
|
{898, 166, 2, 2 },
|
|
{909, 168, 2, 2 },
|
|
{917, 170, 2, 2 },
|
|
{929, 172, 2, 2 },
|
|
{938, 174, 2, 2 },
|
|
{950, 176, 2, 2 },
|
|
{959, 178, 2, 2 },
|
|
{970, 180, 2, 2 },
|
|
{978, 182, 2, 2 },
|
|
{990, 184, 2, 2 },
|
|
{999, 186, 2, 2 },
|
|
{1011, 188, 2, 2 },
|
|
{1020, 190, 2, 2 },
|
|
{1031, 192, 2, 2 },
|
|
{1039, 194, 2, 2 },
|
|
{1051, 196, 2, 2 },
|
|
{1060, 198, 2, 2 },
|
|
{1072, 200, 2, 2 },
|
|
// PPC_BCCL - 101
|
|
{1081, 202, 3, 2 },
|
|
{1095, 204, 3, 2 },
|
|
{1105, 206, 3, 2 },
|
|
{1120, 208, 3, 2 },
|
|
{1131, 210, 3, 2 },
|
|
{1146, 212, 3, 2 },
|
|
{1157, 214, 3, 2 },
|
|
{1171, 216, 3, 2 },
|
|
{1181, 218, 3, 2 },
|
|
{1196, 220, 3, 2 },
|
|
{1207, 222, 3, 2 },
|
|
{1222, 224, 3, 2 },
|
|
{1233, 226, 3, 2 },
|
|
{1247, 228, 3, 2 },
|
|
{1257, 230, 3, 2 },
|
|
{1272, 232, 3, 2 },
|
|
{1283, 234, 3, 2 },
|
|
{1298, 236, 3, 2 },
|
|
{1309, 238, 3, 2 },
|
|
{1323, 240, 3, 2 },
|
|
{1333, 242, 3, 2 },
|
|
{1348, 244, 3, 2 },
|
|
{1359, 246, 3, 2 },
|
|
{1374, 248, 3, 2 },
|
|
// PPC_BCCLA - 125
|
|
{1385, 250, 3, 2 },
|
|
{1400, 252, 3, 2 },
|
|
{1411, 254, 3, 2 },
|
|
{1427, 256, 3, 2 },
|
|
{1439, 258, 3, 2 },
|
|
{1455, 260, 3, 2 },
|
|
{1467, 262, 3, 2 },
|
|
{1482, 264, 3, 2 },
|
|
{1493, 266, 3, 2 },
|
|
{1509, 268, 3, 2 },
|
|
{1521, 270, 3, 2 },
|
|
{1537, 272, 3, 2 },
|
|
{1549, 274, 3, 2 },
|
|
{1564, 276, 3, 2 },
|
|
{1575, 278, 3, 2 },
|
|
{1591, 280, 3, 2 },
|
|
{1603, 282, 3, 2 },
|
|
{1619, 284, 3, 2 },
|
|
{1631, 286, 3, 2 },
|
|
{1646, 288, 3, 2 },
|
|
{1657, 290, 3, 2 },
|
|
{1673, 292, 3, 2 },
|
|
{1685, 294, 3, 2 },
|
|
{1701, 296, 3, 2 },
|
|
// PPC_BCCLR - 149
|
|
{1713, 298, 2, 2 },
|
|
{1722, 300, 2, 2 },
|
|
{1728, 302, 2, 2 },
|
|
{1738, 304, 2, 2 },
|
|
{1745, 306, 2, 2 },
|
|
{1755, 308, 2, 2 },
|
|
{1762, 310, 2, 2 },
|
|
{1771, 312, 2, 2 },
|
|
{1777, 314, 2, 2 },
|
|
{1787, 316, 2, 2 },
|
|
{1794, 318, 2, 2 },
|
|
{1804, 320, 2, 2 },
|
|
{1811, 322, 2, 2 },
|
|
{1820, 324, 2, 2 },
|
|
{1826, 326, 2, 2 },
|
|
{1836, 328, 2, 2 },
|
|
{1843, 330, 2, 2 },
|
|
{1853, 332, 2, 2 },
|
|
{1860, 334, 2, 2 },
|
|
{1869, 336, 2, 2 },
|
|
{1875, 338, 2, 2 },
|
|
{1885, 340, 2, 2 },
|
|
{1892, 342, 2, 2 },
|
|
{1902, 344, 2, 2 },
|
|
// PPC_BCCLRL - 173
|
|
{1909, 346, 2, 2 },
|
|
{1919, 348, 2, 2 },
|
|
{1926, 350, 2, 2 },
|
|
{1937, 352, 2, 2 },
|
|
{1945, 354, 2, 2 },
|
|
{1956, 356, 2, 2 },
|
|
{1964, 358, 2, 2 },
|
|
{1974, 360, 2, 2 },
|
|
{1981, 362, 2, 2 },
|
|
{1992, 364, 2, 2 },
|
|
{2000, 366, 2, 2 },
|
|
{2011, 368, 2, 2 },
|
|
{2019, 370, 2, 2 },
|
|
{2029, 372, 2, 2 },
|
|
{2036, 374, 2, 2 },
|
|
{2047, 376, 2, 2 },
|
|
{2055, 378, 2, 2 },
|
|
{2066, 380, 2, 2 },
|
|
{2074, 382, 2, 2 },
|
|
{2084, 384, 2, 2 },
|
|
{2091, 386, 2, 2 },
|
|
{2102, 388, 2, 2 },
|
|
{2110, 390, 2, 2 },
|
|
{2121, 392, 2, 2 },
|
|
// PPC_CMPD - 197
|
|
{2129, 394, 3, 3 },
|
|
// PPC_CMPDI - 198
|
|
{2141, 397, 3, 2 },
|
|
// PPC_CMPLD - 199
|
|
{2156, 399, 3, 3 },
|
|
// PPC_CMPLDI - 200
|
|
{2169, 402, 3, 2 },
|
|
// PPC_CMPLW - 201
|
|
{2185, 404, 3, 3 },
|
|
// PPC_CMPLWI - 202
|
|
{2198, 407, 3, 2 },
|
|
// PPC_CMPW - 203
|
|
{2214, 409, 3, 3 },
|
|
// PPC_CMPWI - 204
|
|
{2226, 412, 3, 2 },
|
|
// PPC_CNTLZW - 205
|
|
{2241, 414, 2, 2 },
|
|
// PPC_CNTLZW8 - 206
|
|
{2241, 416, 2, 2 },
|
|
// PPC_CNTLZW8_rec - 207
|
|
{2255, 418, 2, 2 },
|
|
// PPC_CNTLZW_rec - 208
|
|
{2255, 420, 2, 2 },
|
|
// PPC_CP_PASTE_rec - 209
|
|
{2270, 422, 3, 4 },
|
|
// PPC_CREQV - 210
|
|
{2284, 426, 3, 3 },
|
|
// PPC_CRNOR - 211
|
|
{2293, 429, 3, 3 },
|
|
// PPC_CROR - 212
|
|
{2306, 432, 3, 3 },
|
|
// PPC_CRXOR - 213
|
|
{2320, 435, 3, 3 },
|
|
// PPC_ISEL - 214
|
|
{2329, 438, 4, 4 },
|
|
{2347, 442, 4, 4 },
|
|
{2365, 446, 4, 4 },
|
|
// PPC_ISEL8 - 217
|
|
{2329, 450, 4, 4 },
|
|
{2347, 454, 4, 4 },
|
|
{2365, 458, 4, 4 },
|
|
// PPC_MBAR - 220
|
|
{2383, 462, 1, 2 },
|
|
// PPC_MFDCR - 221
|
|
{2388, 464, 2, 5 },
|
|
{2397, 469, 2, 5 },
|
|
{2406, 474, 2, 5 },
|
|
{2415, 479, 2, 5 },
|
|
{2424, 484, 2, 5 },
|
|
{2433, 489, 2, 5 },
|
|
{2442, 494, 2, 5 },
|
|
{2451, 499, 2, 5 },
|
|
// PPC_MFSPR - 229
|
|
{2460, 504, 2, 2 },
|
|
{2469, 506, 2, 5 },
|
|
{2480, 511, 2, 5 },
|
|
{2490, 516, 2, 5 },
|
|
{2500, 521, 2, 5 },
|
|
{2508, 526, 2, 5 },
|
|
{2517, 531, 2, 5 },
|
|
{2527, 536, 2, 5 },
|
|
{2537, 541, 2, 5 },
|
|
{2548, 546, 2, 5 },
|
|
{2557, 551, 2, 5 },
|
|
{2566, 556, 2, 5 },
|
|
{2576, 561, 2, 5 },
|
|
{2586, 566, 2, 5 },
|
|
{2596, 571, 2, 5 },
|
|
{2606, 576, 2, 5 },
|
|
{2615, 581, 2, 5 },
|
|
{2624, 586, 2, 5 },
|
|
{2633, 591, 2, 5 },
|
|
{2642, 596, 2, 5 },
|
|
{2655, 601, 2, 5 },
|
|
{2669, 606, 2, 5 },
|
|
{2683, 611, 2, 5 },
|
|
{2697, 616, 2, 5 },
|
|
{2711, 621, 2, 5 },
|
|
{2725, 626, 2, 5 },
|
|
{2739, 631, 2, 5 },
|
|
{2753, 636, 2, 5 },
|
|
{2767, 641, 2, 5 },
|
|
{2781, 646, 2, 5 },
|
|
{2795, 651, 2, 5 },
|
|
{2809, 656, 2, 5 },
|
|
{2823, 661, 2, 5 },
|
|
{2837, 666, 2, 5 },
|
|
{2851, 671, 2, 5 },
|
|
{2865, 676, 2, 5 },
|
|
{2879, 681, 2, 5 },
|
|
{2888, 686, 2, 5 },
|
|
{2897, 691, 2, 5 },
|
|
{2907, 696, 2, 5 },
|
|
{2916, 701, 2, 5 },
|
|
{2926, 706, 2, 5 },
|
|
{2936, 711, 2, 5 },
|
|
{2946, 716, 2, 5 },
|
|
{2956, 721, 2, 5 },
|
|
{2966, 726, 2, 5 },
|
|
// PPC_MFSPR8 - 275
|
|
{2460, 731, 2, 2 },
|
|
{2469, 733, 2, 5 },
|
|
{2480, 738, 2, 5 },
|
|
{2490, 743, 2, 5 },
|
|
{2500, 748, 2, 5 },
|
|
{2508, 753, 2, 5 },
|
|
{2517, 758, 2, 5 },
|
|
{2527, 763, 2, 5 },
|
|
{2537, 768, 2, 5 },
|
|
{2548, 773, 2, 5 },
|
|
{2557, 778, 2, 5 },
|
|
{2566, 783, 2, 5 },
|
|
{2576, 788, 2, 5 },
|
|
{2586, 793, 2, 5 },
|
|
{2596, 798, 2, 5 },
|
|
{2606, 803, 2, 5 },
|
|
{2624, 808, 2, 5 },
|
|
{2633, 813, 2, 5 },
|
|
{2642, 818, 2, 5 },
|
|
// PPC_MFTB - 294
|
|
{2976, 823, 2, 2 },
|
|
// PPC_MFUDSCR - 295
|
|
{2469, 825, 1, 4 },
|
|
// PPC_MFVRSAVE - 296
|
|
{2985, 829, 1, 1 },
|
|
// PPC_MFVSRD - 297
|
|
{2997, 830, 2, 2 },
|
|
// PPC_MFVSRWZ - 298
|
|
{3011, 832, 2, 2 },
|
|
// PPC_MTCRF - 299
|
|
{3026, 834, 2, 2 },
|
|
// PPC_MTCRF8 - 300
|
|
{3026, 836, 2, 2 },
|
|
// PPC_MTDCR - 301
|
|
{3034, 838, 2, 5 },
|
|
{3043, 843, 2, 5 },
|
|
{3052, 848, 2, 5 },
|
|
{3061, 853, 2, 5 },
|
|
{3070, 858, 2, 5 },
|
|
{3079, 863, 2, 5 },
|
|
{3088, 868, 2, 5 },
|
|
{3097, 873, 2, 5 },
|
|
// PPC_MTFSF - 309
|
|
{3106, 878, 4, 5 },
|
|
// PPC_MTFSFI - 310
|
|
{3119, 883, 3, 4 },
|
|
// PPC_MTFSFI_rec - 311
|
|
{3137, 887, 3, 4 },
|
|
// PPC_MTFSF_rec - 312
|
|
{3156, 891, 4, 5 },
|
|
// PPC_MTMSR - 313
|
|
{3170, 896, 2, 5 },
|
|
// PPC_MTMSRD - 314
|
|
{3179, 901, 2, 5 },
|
|
// PPC_MTSPR - 315
|
|
{3189, 906, 2, 2 },
|
|
{3198, 908, 2, 5 },
|
|
{3209, 913, 2, 5 },
|
|
{3217, 918, 2, 5 },
|
|
{3226, 923, 2, 5 },
|
|
{3236, 928, 2, 5 },
|
|
{3246, 933, 2, 5 },
|
|
{3257, 938, 2, 5 },
|
|
{3266, 943, 2, 5 },
|
|
{3275, 948, 2, 5 },
|
|
{3285, 953, 2, 5 },
|
|
{3295, 958, 2, 5 },
|
|
{3305, 963, 2, 5 },
|
|
{3315, 968, 2, 5 },
|
|
{3324, 973, 2, 5 },
|
|
{3333, 978, 2, 5 },
|
|
{3342, 983, 2, 5 },
|
|
{3351, 988, 2, 5 },
|
|
{3360, 993, 2, 5 },
|
|
{3373, 998, 2, 5 },
|
|
{3387, 1003, 2, 5 },
|
|
{3401, 1008, 2, 5 },
|
|
{3415, 1013, 2, 5 },
|
|
{3429, 1018, 2, 5 },
|
|
{3443, 1023, 2, 5 },
|
|
{3457, 1028, 2, 5 },
|
|
{3471, 1033, 2, 5 },
|
|
{3485, 1038, 2, 5 },
|
|
{3499, 1043, 2, 5 },
|
|
{3513, 1048, 2, 5 },
|
|
{3527, 1053, 2, 5 },
|
|
{3541, 1058, 2, 5 },
|
|
{3555, 1063, 2, 5 },
|
|
{3569, 1068, 2, 5 },
|
|
{3583, 1073, 2, 5 },
|
|
{3597, 1078, 2, 5 },
|
|
{3606, 1083, 2, 5 },
|
|
{3615, 1088, 2, 5 },
|
|
{3625, 1093, 2, 5 },
|
|
{3634, 1098, 2, 5 },
|
|
{3644, 1103, 2, 5 },
|
|
{3654, 1108, 2, 5 },
|
|
{3664, 1113, 2, 5 },
|
|
{3674, 1118, 2, 5 },
|
|
{3684, 1123, 2, 5 },
|
|
// PPC_MTSPR8 - 360
|
|
{3189, 1128, 2, 2 },
|
|
{3198, 1130, 2, 5 },
|
|
{3209, 1135, 2, 5 },
|
|
{3217, 1140, 2, 5 },
|
|
{3226, 1145, 2, 5 },
|
|
{3236, 1150, 2, 5 },
|
|
{3246, 1155, 2, 5 },
|
|
{3257, 1160, 2, 5 },
|
|
{3266, 1165, 2, 5 },
|
|
{3275, 1170, 2, 5 },
|
|
{3285, 1175, 2, 5 },
|
|
{3295, 1180, 2, 5 },
|
|
{3305, 1185, 2, 5 },
|
|
{3315, 1190, 2, 5 },
|
|
{3333, 1195, 2, 5 },
|
|
{3342, 1200, 2, 5 },
|
|
{3351, 1205, 2, 5 },
|
|
{3360, 1210, 2, 5 },
|
|
// PPC_MTUDSCR - 378
|
|
{3694, 1215, 1, 4 },
|
|
// PPC_MTVRSAVE - 379
|
|
{3705, 1219, 1, 1 },
|
|
// PPC_MTVSRD - 380
|
|
{3717, 1220, 2, 2 },
|
|
// PPC_MTVSRWA - 381
|
|
{3731, 1222, 2, 2 },
|
|
// PPC_MTVSRWZ - 382
|
|
{3746, 1224, 2, 2 },
|
|
// PPC_NOR - 383
|
|
{3761, 1226, 3, 3 },
|
|
// PPC_NOR8 - 384
|
|
{3761, 1229, 3, 3 },
|
|
// PPC_NOR8_rec - 385
|
|
{3772, 1232, 3, 3 },
|
|
// PPC_NOR_rec - 386
|
|
{3772, 1235, 3, 3 },
|
|
// PPC_OR - 387
|
|
{3784, 1238, 3, 3 },
|
|
// PPC_OR8 - 388
|
|
{3784, 1241, 3, 3 },
|
|
// PPC_OR8_rec - 389
|
|
{3794, 1244, 3, 3 },
|
|
// PPC_ORI - 390
|
|
{3805, 1247, 3, 3 },
|
|
// PPC_ORI8 - 391
|
|
{3805, 1250, 3, 3 },
|
|
// PPC_OR_rec - 392
|
|
{3794, 1253, 3, 3 },
|
|
// PPC_PADDI8 - 393
|
|
{3809, 1256, 3, 2 },
|
|
// PPC_QVFLOGICALb - 394
|
|
{3828, 1258, 4, 5 },
|
|
{3838, 1263, 4, 5 },
|
|
{3856, 1268, 4, 5 },
|
|
{3875, 1273, 4, 5 },
|
|
{3890, 1278, 4, 5 },
|
|
{3908, 1283, 4, 5 },
|
|
{3925, 1288, 4, 5 },
|
|
{3943, 1293, 4, 5 },
|
|
{3961, 1298, 4, 5 },
|
|
{3975, 1303, 4, 5 },
|
|
{3993, 1308, 4, 5 },
|
|
{4012, 1313, 4, 5 },
|
|
// PPC_RFEBB - 406
|
|
{4022, 1318, 1, 1 },
|
|
// PPC_RLDCL - 407
|
|
{4028, 1319, 4, 4 },
|
|
// PPC_RLDCL_rec - 408
|
|
{4045, 1323, 4, 4 },
|
|
// PPC_RLDICL - 409
|
|
{4063, 1327, 4, 4 },
|
|
{4083, 1331, 4, 3 },
|
|
// PPC_RLDICL_32_64 - 411
|
|
{4063, 1334, 4, 4 },
|
|
{4083, 1338, 4, 3 },
|
|
// PPC_RLDICL_rec - 413
|
|
{4103, 1341, 4, 4 },
|
|
{4124, 1345, 4, 3 },
|
|
// PPC_RLWINM - 415
|
|
{4145, 1348, 5, 5 },
|
|
{4165, 1353, 5, 5 },
|
|
// PPC_RLWINM8 - 417
|
|
{4145, 1358, 5, 5 },
|
|
{4165, 1363, 5, 5 },
|
|
// PPC_RLWINM8_rec - 419
|
|
{4185, 1368, 5, 5 },
|
|
{4206, 1373, 5, 5 },
|
|
// PPC_RLWINM_rec - 421
|
|
{4185, 1378, 5, 5 },
|
|
{4206, 1383, 5, 5 },
|
|
// PPC_RLWNM - 423
|
|
{4227, 1388, 5, 5 },
|
|
// PPC_RLWNM8 - 424
|
|
{4227, 1393, 5, 5 },
|
|
// PPC_RLWNM8_rec - 425
|
|
{4244, 1398, 5, 5 },
|
|
// PPC_RLWNM_rec - 426
|
|
{4244, 1403, 5, 5 },
|
|
// PPC_SC - 427
|
|
{4262, 1408, 1, 1 },
|
|
// PPC_SUBF - 428
|
|
{4265, 1409, 3, 3 },
|
|
// PPC_SUBF8 - 429
|
|
{4265, 1412, 3, 3 },
|
|
// PPC_SUBF8_rec - 430
|
|
{4280, 1415, 3, 3 },
|
|
// PPC_SUBFC - 431
|
|
{4296, 1418, 3, 3 },
|
|
// PPC_SUBFC8 - 432
|
|
{4296, 1421, 3, 3 },
|
|
// PPC_SUBFC8_rec - 433
|
|
{4312, 1424, 3, 3 },
|
|
// PPC_SUBFC_rec - 434
|
|
{4312, 1427, 3, 3 },
|
|
// PPC_SUBF_rec - 435
|
|
{4280, 1430, 3, 3 },
|
|
// PPC_SYNC - 436
|
|
{4329, 1433, 1, 2 },
|
|
{4334, 1435, 1, 2 },
|
|
{4341, 1437, 1, 2 },
|
|
// PPC_SYNCP10 - 439
|
|
{4329, 1439, 2, 2 },
|
|
{4341, 1441, 2, 2 },
|
|
{4349, 1443, 2, 2 },
|
|
{4357, 1445, 2, 2 },
|
|
{4365, 1447, 2, 2 },
|
|
{4375, 1449, 2, 2 },
|
|
{4385, 1451, 2, 2 },
|
|
{4394, 1453, 2, 2 },
|
|
// PPC_TD - 447
|
|
{4401, 1455, 3, 3 },
|
|
{4413, 1458, 3, 3 },
|
|
{4425, 1461, 3, 3 },
|
|
{4437, 1464, 3, 3 },
|
|
{4449, 1467, 3, 3 },
|
|
{4462, 1470, 3, 3 },
|
|
{4475, 1473, 3, 3 },
|
|
// PPC_TDI - 454
|
|
{4486, 1476, 3, 2 },
|
|
{4501, 1478, 3, 2 },
|
|
{4516, 1480, 3, 2 },
|
|
{4531, 1482, 3, 2 },
|
|
{4546, 1484, 3, 2 },
|
|
{4562, 1486, 3, 2 },
|
|
{4578, 1488, 3, 2 },
|
|
// PPC_TEND - 461
|
|
{4592, 1490, 1, 1 },
|
|
{4598, 1491, 1, 1 },
|
|
// PPC_TLBIE - 463
|
|
{4607, 1492, 2, 2 },
|
|
// PPC_TLBILX - 464
|
|
{4616, 1494, 3, 4 },
|
|
{4627, 1498, 3, 4 },
|
|
{4637, 1502, 3, 4 },
|
|
{4653, 1506, 3, 4 },
|
|
// PPC_TLBRE2 - 468
|
|
{4665, 1510, 3, 4 },
|
|
{4680, 1514, 3, 4 },
|
|
// PPC_TLBWE2 - 470
|
|
{4695, 1518, 3, 4 },
|
|
{4710, 1522, 3, 4 },
|
|
// PPC_TSR - 472
|
|
{4725, 1526, 1, 1 },
|
|
{4735, 1527, 1, 1 },
|
|
// PPC_TW - 474
|
|
{4744, 1528, 3, 3 },
|
|
{4749, 1531, 3, 3 },
|
|
{4761, 1534, 3, 3 },
|
|
{4773, 1537, 3, 3 },
|
|
{4785, 1540, 3, 3 },
|
|
{4797, 1543, 3, 3 },
|
|
{4810, 1546, 3, 3 },
|
|
{4823, 1549, 3, 3 },
|
|
// PPC_TWI - 482
|
|
{4834, 1552, 3, 2 },
|
|
{4849, 1554, 3, 2 },
|
|
{4864, 1556, 3, 2 },
|
|
{4879, 1558, 3, 2 },
|
|
{4894, 1560, 3, 2 },
|
|
{4910, 1562, 3, 2 },
|
|
{4926, 1564, 3, 2 },
|
|
// PPC_VNOR - 489
|
|
{4940, 1566, 3, 3 },
|
|
// PPC_VOR - 490
|
|
{4952, 1569, 3, 3 },
|
|
// PPC_WAIT - 491
|
|
{4963, 1572, 1, 1 },
|
|
{4968, 1573, 1, 1 },
|
|
{4976, 1574, 1, 1 },
|
|
// PPC_WAITP10 - 494
|
|
{4963, 1575, 2, 2 },
|
|
{4968, 1577, 2, 2 },
|
|
// PPC_XORI - 496
|
|
{4985, 1579, 3, 3 },
|
|
// PPC_XORI8 - 497
|
|
{4985, 1582, 3, 3 },
|
|
// PPC_XVCPSGNDP - 498
|
|
{4990, 1585, 3, 3 },
|
|
// PPC_XVCPSGNSP - 499
|
|
{5005, 1588, 3, 3 },
|
|
// PPC_XXPERMDI - 500
|
|
{5020, 1591, 4, 7 },
|
|
{5038, 1598, 4, 7 },
|
|
{5056, 1605, 4, 4 },
|
|
{5075, 1609, 4, 4 },
|
|
{5094, 1613, 4, 4 },
|
|
// PPC_XXPERMDIs - 505
|
|
{5020, 1617, 3, 6 },
|
|
{5038, 1623, 3, 6 },
|
|
{5094, 1629, 3, 3 },
|
|
// PPC_gBC - 508
|
|
{5109, 1632, 3, 2 },
|
|
{5121, 1634, 3, 2 },
|
|
{5133, 1636, 3, 2 },
|
|
{5146, 1638, 3, 2 },
|
|
{5159, 1640, 3, 2 },
|
|
{5172, 1642, 3, 2 },
|
|
{5185, 1644, 3, 2 },
|
|
{5200, 1646, 3, 2 },
|
|
{5215, 1648, 3, 2 },
|
|
{5229, 1650, 3, 2 },
|
|
{5243, 1652, 3, 2 },
|
|
// PPC_gBCA - 519
|
|
{5250, 1654, 3, 2 },
|
|
{5263, 1656, 3, 2 },
|
|
{5276, 1658, 3, 2 },
|
|
{5290, 1660, 3, 2 },
|
|
{5304, 1662, 3, 2 },
|
|
{5318, 1664, 3, 2 },
|
|
{5332, 1666, 3, 2 },
|
|
{5348, 1668, 3, 2 },
|
|
{5364, 1670, 3, 2 },
|
|
{5379, 1672, 3, 2 },
|
|
{5394, 1674, 3, 2 },
|
|
// PPC_gBCAat - 530
|
|
{5402, 1676, 4, 3 },
|
|
{5422, 1679, 4, 3 },
|
|
{5442, 1682, 4, 3 },
|
|
{5451, 1685, 4, 3 },
|
|
{5461, 1688, 4, 3 },
|
|
{5471, 1691, 4, 3 },
|
|
{5482, 1694, 4, 3 },
|
|
{5492, 1697, 4, 3 },
|
|
// PPC_gBCCTR - 538
|
|
{5503, 1700, 3, 3 },
|
|
{5512, 1703, 3, 3 },
|
|
{5521, 1706, 3, 3 },
|
|
{5531, 1709, 3, 3 },
|
|
{5541, 1712, 3, 3 },
|
|
{5551, 1715, 3, 3 },
|
|
{5561, 1718, 3, 3 },
|
|
// PPC_gBCCTRL - 545
|
|
{5566, 1721, 3, 3 },
|
|
{5576, 1724, 3, 3 },
|
|
{5586, 1727, 3, 3 },
|
|
{5597, 1730, 3, 3 },
|
|
{5608, 1733, 3, 3 },
|
|
{5619, 1736, 3, 3 },
|
|
{5630, 1739, 3, 3 },
|
|
// PPC_gBCL - 552
|
|
{5636, 1742, 3, 2 },
|
|
{5649, 1744, 3, 2 },
|
|
{5662, 1746, 3, 2 },
|
|
{5676, 1748, 3, 2 },
|
|
{5690, 1750, 3, 2 },
|
|
{5704, 1752, 3, 2 },
|
|
{5718, 1754, 3, 2 },
|
|
{5734, 1756, 3, 2 },
|
|
{5750, 1758, 3, 2 },
|
|
{5765, 1760, 3, 2 },
|
|
{5780, 1762, 3, 2 },
|
|
// PPC_gBCLA - 563
|
|
{5788, 1764, 3, 2 },
|
|
{5802, 1766, 3, 2 },
|
|
{5816, 1768, 3, 2 },
|
|
{5831, 1770, 3, 2 },
|
|
{5846, 1772, 3, 2 },
|
|
{5861, 1774, 3, 2 },
|
|
{5876, 1776, 3, 2 },
|
|
{5893, 1778, 3, 2 },
|
|
{5910, 1780, 3, 2 },
|
|
{5926, 1782, 3, 2 },
|
|
{5942, 1784, 3, 2 },
|
|
// PPC_gBCLAat - 574
|
|
{5951, 1786, 4, 3 },
|
|
{5972, 1789, 4, 3 },
|
|
{5993, 1792, 4, 3 },
|
|
{6004, 1795, 4, 3 },
|
|
{6016, 1798, 4, 3 },
|
|
{6028, 1801, 4, 3 },
|
|
{6041, 1804, 4, 3 },
|
|
{6053, 1807, 4, 3 },
|
|
// PPC_gBCLR - 582
|
|
{6066, 1810, 3, 3 },
|
|
{6072, 1813, 3, 3 },
|
|
{6079, 1816, 3, 3 },
|
|
{6086, 1819, 3, 3 },
|
|
{6094, 1822, 3, 3 },
|
|
{6101, 1825, 3, 3 },
|
|
{6109, 1828, 3, 3 },
|
|
{6117, 1831, 3, 3 },
|
|
{6125, 1834, 3, 3 },
|
|
{6134, 1837, 3, 3 },
|
|
{6143, 1840, 3, 3 },
|
|
{6152, 1843, 3, 3 },
|
|
{6161, 1846, 3, 3 },
|
|
{6172, 1849, 3, 3 },
|
|
{6183, 1852, 3, 3 },
|
|
{6193, 1855, 3, 3 },
|
|
{6203, 1858, 3, 3 },
|
|
// PPC_gBCLRL - 599
|
|
{6207, 1861, 3, 3 },
|
|
{6214, 1864, 3, 3 },
|
|
{6222, 1867, 3, 3 },
|
|
{6230, 1870, 3, 3 },
|
|
{6239, 1873, 3, 3 },
|
|
{6247, 1876, 3, 3 },
|
|
{6256, 1879, 3, 3 },
|
|
{6265, 1882, 3, 3 },
|
|
{6274, 1885, 3, 3 },
|
|
{6284, 1888, 3, 3 },
|
|
{6294, 1891, 3, 3 },
|
|
{6304, 1894, 3, 3 },
|
|
{6314, 1897, 3, 3 },
|
|
{6326, 1900, 3, 3 },
|
|
{6338, 1903, 3, 3 },
|
|
{6349, 1906, 3, 3 },
|
|
{6360, 1909, 3, 3 },
|
|
// PPC_gBCLat - 616
|
|
{6365, 1912, 4, 3 },
|
|
{6385, 1915, 4, 3 },
|
|
{6405, 1918, 4, 3 },
|
|
{6415, 1921, 4, 3 },
|
|
{6426, 1924, 4, 3 },
|
|
{6437, 1927, 4, 3 },
|
|
{6449, 1930, 4, 3 },
|
|
{6460, 1933, 4, 3 },
|
|
// PPC_gBCat - 624
|
|
{6472, 1936, 4, 3 },
|
|
{6491, 1939, 4, 3 },
|
|
{6510, 1942, 4, 3 },
|
|
{6519, 1945, 4, 3 },
|
|
{6529, 1948, 4, 3 },
|
|
{6539, 1951, 4, 3 },
|
|
{6550, 1954, 4, 3 },
|
|
{6560, 1957, 4, 3 },
|
|
{0}, };
|
|
|
|
static const AliasPatternCond Conds[] = {
|
|
// (ADDI gprc:$rD, ZERO, s16imm:$imm) - 0
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_ZERO},
|
|
// (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm) - 2
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_ZERO8},
|
|
// (ADDIS gprc:$rD, ZERO, s17imm:$imm) - 4
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_ZERO},
|
|
// (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm) - 6
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_ZERO8},
|
|
// (ADDPCIS g8rc:$RT, 0) - 8
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (BCC 12, crrc:$cc, condbrtarget:$dst) - 10
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 12, CR0, condbrtarget:$dst) - 12
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 14, crrc:$cc, condbrtarget:$dst) - 14
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 14, CR0, condbrtarget:$dst) - 16
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 15, crrc:$cc, condbrtarget:$dst) - 18
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 15, CR0, condbrtarget:$dst) - 20
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 44, crrc:$cc, condbrtarget:$dst) - 22
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 44, CR0, condbrtarget:$dst) - 24
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 46, crrc:$cc, condbrtarget:$dst) - 26
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 46, CR0, condbrtarget:$dst) - 28
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 47, crrc:$cc, condbrtarget:$dst) - 30
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 47, CR0, condbrtarget:$dst) - 32
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 76, crrc:$cc, condbrtarget:$dst) - 34
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 76, CR0, condbrtarget:$dst) - 36
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 78, crrc:$cc, condbrtarget:$dst) - 38
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 78, CR0, condbrtarget:$dst) - 40
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 79, crrc:$cc, condbrtarget:$dst) - 42
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 79, CR0, condbrtarget:$dst) - 44
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 68, crrc:$cc, condbrtarget:$dst) - 46
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 68, CR0, condbrtarget:$dst) - 48
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 70, crrc:$cc, condbrtarget:$dst) - 50
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 70, CR0, condbrtarget:$dst) - 52
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCC 71, crrc:$cc, condbrtarget:$dst) - 54
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCC 71, CR0, condbrtarget:$dst) - 56
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 12, crrc:$cc, abscondbrtarget:$dst) - 58
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 12, CR0, abscondbrtarget:$dst) - 60
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 14, crrc:$cc, abscondbrtarget:$dst) - 62
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 14, CR0, abscondbrtarget:$dst) - 64
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 15, crrc:$cc, abscondbrtarget:$dst) - 66
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 15, CR0, abscondbrtarget:$dst) - 68
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 44, crrc:$cc, abscondbrtarget:$dst) - 70
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 44, CR0, abscondbrtarget:$dst) - 72
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 46, crrc:$cc, abscondbrtarget:$dst) - 74
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 46, CR0, abscondbrtarget:$dst) - 76
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 47, crrc:$cc, abscondbrtarget:$dst) - 78
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 47, CR0, abscondbrtarget:$dst) - 80
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 76, crrc:$cc, abscondbrtarget:$dst) - 82
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 76, CR0, abscondbrtarget:$dst) - 84
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 78, crrc:$cc, abscondbrtarget:$dst) - 86
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 78, CR0, abscondbrtarget:$dst) - 88
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 79, crrc:$cc, abscondbrtarget:$dst) - 90
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 79, CR0, abscondbrtarget:$dst) - 92
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 68, crrc:$cc, abscondbrtarget:$dst) - 94
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 68, CR0, abscondbrtarget:$dst) - 96
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 70, crrc:$cc, abscondbrtarget:$dst) - 98
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 70, CR0, abscondbrtarget:$dst) - 100
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCA 71, crrc:$cc, abscondbrtarget:$dst) - 102
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCA 71, CR0, abscondbrtarget:$dst) - 104
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 12, crrc:$cc) - 106
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 12, CR0) - 108
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 14, crrc:$cc) - 110
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 14, CR0) - 112
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 15, crrc:$cc) - 114
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 15, CR0) - 116
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 44, crrc:$cc) - 118
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 44, CR0) - 120
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 46, crrc:$cc) - 122
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 46, CR0) - 124
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 47, crrc:$cc) - 126
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 47, CR0) - 128
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 76, crrc:$cc) - 130
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 76, CR0) - 132
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 78, crrc:$cc) - 134
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 78, CR0) - 136
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 79, crrc:$cc) - 138
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 79, CR0) - 140
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 68, crrc:$cc) - 142
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 68, CR0) - 144
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 70, crrc:$cc) - 146
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 70, CR0) - 148
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTR 71, crrc:$cc) - 150
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTR 71, CR0) - 152
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 12, crrc:$cc) - 154
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 12, CR0) - 156
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 14, crrc:$cc) - 158
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 14, CR0) - 160
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 15, crrc:$cc) - 162
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 15, CR0) - 164
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 44, crrc:$cc) - 166
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 44, CR0) - 168
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 46, crrc:$cc) - 170
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 46, CR0) - 172
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 47, crrc:$cc) - 174
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 47, CR0) - 176
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 76, crrc:$cc) - 178
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 76, CR0) - 180
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 78, crrc:$cc) - 182
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 78, CR0) - 184
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 79, crrc:$cc) - 186
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 79, CR0) - 188
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 68, crrc:$cc) - 190
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 68, CR0) - 192
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 70, crrc:$cc) - 194
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 70, CR0) - 196
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCCTRL 71, crrc:$cc) - 198
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCCTRL 71, CR0) - 200
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 12, crrc:$cc, condbrtarget:$dst) - 202
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 12, CR0, condbrtarget:$dst) - 204
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 14, crrc:$cc, condbrtarget:$dst) - 206
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 14, CR0, condbrtarget:$dst) - 208
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 15, crrc:$cc, condbrtarget:$dst) - 210
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 15, CR0, condbrtarget:$dst) - 212
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 44, crrc:$cc, condbrtarget:$dst) - 214
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 44, CR0, condbrtarget:$dst) - 216
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 46, crrc:$cc, condbrtarget:$dst) - 218
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 46, CR0, condbrtarget:$dst) - 220
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 47, crrc:$cc, condbrtarget:$dst) - 222
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 47, CR0, condbrtarget:$dst) - 224
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 76, crrc:$cc, condbrtarget:$dst) - 226
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 76, CR0, condbrtarget:$dst) - 228
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 78, crrc:$cc, condbrtarget:$dst) - 230
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 78, CR0, condbrtarget:$dst) - 232
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 79, crrc:$cc, condbrtarget:$dst) - 234
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 79, CR0, condbrtarget:$dst) - 236
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 68, crrc:$cc, condbrtarget:$dst) - 238
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 68, CR0, condbrtarget:$dst) - 240
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 70, crrc:$cc, condbrtarget:$dst) - 242
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 70, CR0, condbrtarget:$dst) - 244
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCL 71, crrc:$cc, condbrtarget:$dst) - 246
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCL 71, CR0, condbrtarget:$dst) - 248
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 12, crrc:$cc, abscondbrtarget:$dst) - 250
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 12, CR0, abscondbrtarget:$dst) - 252
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 14, crrc:$cc, abscondbrtarget:$dst) - 254
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 14, CR0, abscondbrtarget:$dst) - 256
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 15, crrc:$cc, abscondbrtarget:$dst) - 258
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 15, CR0, abscondbrtarget:$dst) - 260
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 44, crrc:$cc, abscondbrtarget:$dst) - 262
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 44, CR0, abscondbrtarget:$dst) - 264
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 46, crrc:$cc, abscondbrtarget:$dst) - 266
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 46, CR0, abscondbrtarget:$dst) - 268
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 47, crrc:$cc, abscondbrtarget:$dst) - 270
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 47, CR0, abscondbrtarget:$dst) - 272
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 76, crrc:$cc, abscondbrtarget:$dst) - 274
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 76, CR0, abscondbrtarget:$dst) - 276
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 78, crrc:$cc, abscondbrtarget:$dst) - 278
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 78, CR0, abscondbrtarget:$dst) - 280
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 79, crrc:$cc, abscondbrtarget:$dst) - 282
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 79, CR0, abscondbrtarget:$dst) - 284
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 68, crrc:$cc, abscondbrtarget:$dst) - 286
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 68, CR0, abscondbrtarget:$dst) - 288
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 70, crrc:$cc, abscondbrtarget:$dst) - 290
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 70, CR0, abscondbrtarget:$dst) - 292
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLA 71, crrc:$cc, abscondbrtarget:$dst) - 294
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLA 71, CR0, abscondbrtarget:$dst) - 296
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 12, crrc:$cc) - 298
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 12, CR0) - 300
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 14, crrc:$cc) - 302
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 14, CR0) - 304
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 15, crrc:$cc) - 306
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 15, CR0) - 308
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 44, crrc:$cc) - 310
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 44, CR0) - 312
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 46, crrc:$cc) - 314
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 46, CR0) - 316
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 47, crrc:$cc) - 318
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 47, CR0) - 320
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 76, crrc:$cc) - 322
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 76, CR0) - 324
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 78, crrc:$cc) - 326
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 78, CR0) - 328
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 79, crrc:$cc) - 330
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 79, CR0) - 332
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 68, crrc:$cc) - 334
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 68, CR0) - 336
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 70, crrc:$cc) - 338
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 70, CR0) - 340
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLR 71, crrc:$cc) - 342
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLR 71, CR0) - 344
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 12, crrc:$cc) - 346
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 12, CR0) - 348
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 14, crrc:$cc) - 350
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 14, CR0) - 352
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 15, crrc:$cc) - 354
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 15, CR0) - 356
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 44, crrc:$cc) - 358
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 44, CR0) - 360
|
|
{AliasPatternCond_K_Imm, (uint32_t)44},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 46, crrc:$cc) - 362
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 46, CR0) - 364
|
|
{AliasPatternCond_K_Imm, (uint32_t)46},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 47, crrc:$cc) - 366
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 47, CR0) - 368
|
|
{AliasPatternCond_K_Imm, (uint32_t)47},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 76, crrc:$cc) - 370
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 76, CR0) - 372
|
|
{AliasPatternCond_K_Imm, (uint32_t)76},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 78, crrc:$cc) - 374
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 78, CR0) - 376
|
|
{AliasPatternCond_K_Imm, (uint32_t)78},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 79, crrc:$cc) - 378
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 79, CR0) - 380
|
|
{AliasPatternCond_K_Imm, (uint32_t)79},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 68, crrc:$cc) - 382
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 68, CR0) - 384
|
|
{AliasPatternCond_K_Imm, (uint32_t)68},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 70, crrc:$cc) - 386
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 70, CR0) - 388
|
|
{AliasPatternCond_K_Imm, (uint32_t)70},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (BCCLRL 71, crrc:$cc) - 390
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_RegClass, PPC_CRRCRegClassID},
|
|
// (BCCLRL 71, CR0) - 392
|
|
{AliasPatternCond_K_Imm, (uint32_t)71},
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
// (CMPD CR0, g8rc:$rA, g8rc:$rB) - 394
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (CMPDI CR0, g8rc:$rA, s16imm64:$imm) - 397
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (CMPLD CR0, g8rc:$rA, g8rc:$rB) - 399
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (CMPLDI CR0, g8rc:$rA, u16imm64:$imm) - 402
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (CMPLW CR0, gprc:$rA, gprc:$rB) - 404
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (CMPLWI CR0, gprc:$rA, u16imm:$imm) - 407
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (CMPW CR0, gprc:$rA, gprc:$rB) - 409
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (CMPWI CR0, gprc:$rA, s16imm:$imm) - 412
|
|
{AliasPatternCond_K_Reg, PPC_CR0},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (CNTLZW gprc:$rA, gprc:$rS) - 414
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (CNTLZW8 g8rc:$rA, g8rc:$rS) - 416
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (CNTLZW8_rec g8rc:$rA, g8rc:$rS) - 418
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (CNTLZW_rec gprc:$rA, gprc:$rS) - 420
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (CP_PASTE_rec gprc:$RA, gprc:$RB, 1) - 422
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureISA2_06},
|
|
// (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) - 426
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
// (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by) - 429
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by) - 432
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) - 435
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
// (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT) - 438
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRC_NOR0RegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT) - 442
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRC_NOR0RegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_CR0GT},
|
|
// (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ) - 446
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRC_NOR0RegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_CR0EQ},
|
|
// (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT) - 450
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT) - 454
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_CR0GT},
|
|
// (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ) - 458
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Reg, PPC_CR0EQ},
|
|
// (MBAR 0) - 462
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureBookE},
|
|
// (MFDCR gprc:$Rx, 128) - 464
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)128},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 129) - 469
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)129},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 130) - 474
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)130},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 131) - 479
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)131},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 132) - 484
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)132},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 133) - 489
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)133},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 134) - 494
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)134},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFDCR gprc:$Rx, 135) - 499
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)135},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 1) - 504
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (MFSPR gprc:$Rx, 3) - 506
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 4) - 511
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 5) - 516
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)5},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 8) - 521
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 9) - 526
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)9},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 13) - 531
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)13},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 17) - 536
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)17},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 18) - 541
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 19) - 546
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)19},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 22) - 551
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)22},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 25) - 556
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 26) - 561
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 27) - 566
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 28) - 571
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)28},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 29) - 576
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)29},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 48) - 581
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)48},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$RT, 280) - 586
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)280},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$RT, 287) - 591
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)287},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 512) - 596
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)512},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 536) - 601
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)536},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 537) - 606
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)537},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 528) - 611
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)528},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 529) - 616
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)529},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 538) - 621
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)538},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 539) - 626
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)539},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 530) - 631
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)530},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 531) - 636
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)531},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 540) - 641
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)540},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 541) - 646
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)541},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 532) - 651
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)532},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 533) - 656
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)533},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 542) - 661
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)542},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 543) - 666
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)543},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 534) - 671
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)534},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 535) - 676
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)535},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$RT, 896) - 681
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)896},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 980) - 686
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)980},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 981) - 691
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)981},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 986) - 696
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)986},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 988) - 701
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)988},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 989) - 706
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)989},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 990) - 711
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)990},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 991) - 716
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)991},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 1018) - 721
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1018},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR gprc:$Rx, 1019) - 726
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1019},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 1) - 731
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (MFSPR8 g8rc:$Rx, 3) - 733
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 4) - 738
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 5) - 743
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)5},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 8) - 748
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 9) - 753
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)9},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 13) - 758
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)13},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 17) - 763
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)17},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 18) - 768
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 19) - 773
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)19},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 22) - 778
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)22},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 25) - 783
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 26) - 788
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 27) - 793
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 28) - 798
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)28},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 29) - 803
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)29},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$RT, 280) - 808
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)280},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$RT, 287) - 813
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)287},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFSPR8 g8rc:$Rx, 512) - 818
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)512},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFTB gprc:$Rx, 269) - 823
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)269},
|
|
// (MFUDSCR gprc:$Rx) - 825
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MFVRSAVE gprc:$rS) - 829
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (MFVSRD g8rc:$rA, f8rc:$src) - 830
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
// (MFVSRWZ gprc:$rA, f8rc:$src) - 832
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
// (MTCRF 255, gprc:$rA) - 834
|
|
{AliasPatternCond_K_Imm, (uint32_t)255},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (MTCRF8 255, g8rc:$rA) - 836
|
|
{AliasPatternCond_K_Imm, (uint32_t)255},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (MTDCR gprc:$Rx, 128) - 838
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)128},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 129) - 843
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)129},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 130) - 848
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)130},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 131) - 853
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)131},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 132) - 858
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)132},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 133) - 863
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)133},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 134) - 868
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)134},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTDCR gprc:$Rx, 135) - 873
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)135},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0) - 878
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureISA2_07},
|
|
// (MTFSFI u3imm:$BF, u4imm:$U, 0) - 883
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureISA2_07},
|
|
// (MTFSFI_rec u3imm:$BF, u4imm:$U, 0) - 887
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureISA2_07},
|
|
// (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0) - 891
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureISA2_07},
|
|
// (MTMSR gprc:$RS, 0) - 896
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTMSRD gprc:$RS, 0) - 901
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 1, gprc:$Rx) - 906
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (MTSPR 3, gprc:$Rx) - 908
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 8, gprc:$Rx) - 913
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 9, gprc:$Rx) - 918
|
|
{AliasPatternCond_K_Imm, (uint32_t)9},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 13, gprc:$Rx) - 923
|
|
{AliasPatternCond_K_Imm, (uint32_t)13},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 17, gprc:$Rx) - 928
|
|
{AliasPatternCond_K_Imm, (uint32_t)17},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 18, gprc:$Rx) - 933
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 19, gprc:$Rx) - 938
|
|
{AliasPatternCond_K_Imm, (uint32_t)19},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 22, gprc:$Rx) - 943
|
|
{AliasPatternCond_K_Imm, (uint32_t)22},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 25, gprc:$Rx) - 948
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 26, gprc:$Rx) - 953
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 27, gprc:$Rx) - 958
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 28, gprc:$Rx) - 963
|
|
{AliasPatternCond_K_Imm, (uint32_t)28},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 29, gprc:$Rx) - 968
|
|
{AliasPatternCond_K_Imm, (uint32_t)29},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 48, gprc:$Rx) - 973
|
|
{AliasPatternCond_K_Imm, (uint32_t)48},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 280, gprc:$RT) - 978
|
|
{AliasPatternCond_K_Imm, (uint32_t)280},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 284, gprc:$Rx) - 983
|
|
{AliasPatternCond_K_Imm, (uint32_t)284},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 285, gprc:$Rx) - 988
|
|
{AliasPatternCond_K_Imm, (uint32_t)285},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 512, gprc:$Rx) - 993
|
|
{AliasPatternCond_K_Imm, (uint32_t)512},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 536, gprc:$Rx) - 998
|
|
{AliasPatternCond_K_Imm, (uint32_t)536},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 537, gprc:$Rx) - 1003
|
|
{AliasPatternCond_K_Imm, (uint32_t)537},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 528, gprc:$Rx) - 1008
|
|
{AliasPatternCond_K_Imm, (uint32_t)528},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 529, gprc:$Rx) - 1013
|
|
{AliasPatternCond_K_Imm, (uint32_t)529},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 538, gprc:$Rx) - 1018
|
|
{AliasPatternCond_K_Imm, (uint32_t)538},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 539, gprc:$Rx) - 1023
|
|
{AliasPatternCond_K_Imm, (uint32_t)539},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 530, gprc:$Rx) - 1028
|
|
{AliasPatternCond_K_Imm, (uint32_t)530},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 531, gprc:$Rx) - 1033
|
|
{AliasPatternCond_K_Imm, (uint32_t)531},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 540, gprc:$Rx) - 1038
|
|
{AliasPatternCond_K_Imm, (uint32_t)540},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 541, gprc:$Rx) - 1043
|
|
{AliasPatternCond_K_Imm, (uint32_t)541},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 532, gprc:$Rx) - 1048
|
|
{AliasPatternCond_K_Imm, (uint32_t)532},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 533, gprc:$Rx) - 1053
|
|
{AliasPatternCond_K_Imm, (uint32_t)533},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 542, gprc:$Rx) - 1058
|
|
{AliasPatternCond_K_Imm, (uint32_t)542},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 543, gprc:$Rx) - 1063
|
|
{AliasPatternCond_K_Imm, (uint32_t)543},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 534, gprc:$Rx) - 1068
|
|
{AliasPatternCond_K_Imm, (uint32_t)534},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 535, gprc:$Rx) - 1073
|
|
{AliasPatternCond_K_Imm, (uint32_t)535},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 896, gprc:$RT) - 1078
|
|
{AliasPatternCond_K_Imm, (uint32_t)896},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 980, gprc:$Rx) - 1083
|
|
{AliasPatternCond_K_Imm, (uint32_t)980},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 981, gprc:$Rx) - 1088
|
|
{AliasPatternCond_K_Imm, (uint32_t)981},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 986, gprc:$Rx) - 1093
|
|
{AliasPatternCond_K_Imm, (uint32_t)986},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 988, gprc:$Rx) - 1098
|
|
{AliasPatternCond_K_Imm, (uint32_t)988},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 989, gprc:$Rx) - 1103
|
|
{AliasPatternCond_K_Imm, (uint32_t)989},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 990, gprc:$Rx) - 1108
|
|
{AliasPatternCond_K_Imm, (uint32_t)990},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 991, gprc:$Rx) - 1113
|
|
{AliasPatternCond_K_Imm, (uint32_t)991},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 1018, gprc:$Rx) - 1118
|
|
{AliasPatternCond_K_Imm, (uint32_t)1018},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR 1019, gprc:$Rx) - 1123
|
|
{AliasPatternCond_K_Imm, (uint32_t)1019},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 1, g8rc:$Rx) - 1128
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (MTSPR8 3, g8rc:$Rx) - 1130
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 8, g8rc:$Rx) - 1135
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 9, g8rc:$Rx) - 1140
|
|
{AliasPatternCond_K_Imm, (uint32_t)9},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 13, g8rc:$Rx) - 1145
|
|
{AliasPatternCond_K_Imm, (uint32_t)13},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 17, g8rc:$Rx) - 1150
|
|
{AliasPatternCond_K_Imm, (uint32_t)17},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 18, g8rc:$Rx) - 1155
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 19, g8rc:$Rx) - 1160
|
|
{AliasPatternCond_K_Imm, (uint32_t)19},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 22, g8rc:$Rx) - 1165
|
|
{AliasPatternCond_K_Imm, (uint32_t)22},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 25, g8rc:$Rx) - 1170
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 26, g8rc:$Rx) - 1175
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 27, g8rc:$Rx) - 1180
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 28, g8rc:$Rx) - 1185
|
|
{AliasPatternCond_K_Imm, (uint32_t)28},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 29, g8rc:$Rx) - 1190
|
|
{AliasPatternCond_K_Imm, (uint32_t)29},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 280, g8rc:$RT) - 1195
|
|
{AliasPatternCond_K_Imm, (uint32_t)280},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 284, g8rc:$Rx) - 1200
|
|
{AliasPatternCond_K_Imm, (uint32_t)284},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 285, g8rc:$Rx) - 1205
|
|
{AliasPatternCond_K_Imm, (uint32_t)285},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTSPR8 512, g8rc:$Rx) - 1210
|
|
{AliasPatternCond_K_Imm, (uint32_t)512},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTUDSCR gprc:$Rx) - 1215
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (MTVRSAVE gprc:$rS) - 1219
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (MTVSRD f8rc:$dst, g8rc:$rA) - 1220
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (MTVSRWA f8rc:$dst, gprc:$rA) - 1222
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (MTVSRWZ f8rc:$dst, gprc:$rA) - 1224
|
|
{AliasPatternCond_K_RegClass, PPC_F8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (NOR gprc:$rA, gprc:$rS, gprc:$rS) - 1226
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1229
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1232
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS) - 1235
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (OR gprc:$rA, gprc:$rB, gprc:$rB) - 1238
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1241
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1244
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (ORI R0, R0, 0) - 1247
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (ORI8 X0, X0, 0) - 1250
|
|
{AliasPatternCond_K_Reg, PPC_X0},
|
|
{AliasPatternCond_K_Reg, PPC_X0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (OR_rec gprc:$rA, gprc:$rB, gprc:$rB) - 1253
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI) - 1256
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 0) - 1258
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 1) - 1263
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 4) - 1268
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 5) - 1273
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)5},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 6) - 1278
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 7) - 1283
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 8) - 1288
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 9) - 1293
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)9},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 10) - 1298
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 13) - 1303
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)13},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 14) - 1308
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 15) - 1313
|
|
{AliasPatternCond_K_RegClass, PPC_QBRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureQPX},
|
|
// (RFEBB 1) - 1318
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0) - 1319
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0) - 1323
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0) - 1327
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n) - 1331
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0) - 1334
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n) - 1338
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0) - 1341
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n) - 1345
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) - 1348
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) - 1353
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31) - 1358
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31) - 1363
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31) - 1368
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31) - 1373
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) - 1378
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) - 1383
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) - 1388
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31) - 1393
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31) - 1398
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) - 1403
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
// (SC 0) - 1408
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SUBF gprc:$rA, gprc:$rC, gprc:$rB) - 1409
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1412
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1415
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (SUBFC gprc:$rA, gprc:$rC, gprc:$rB) - 1418
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1421
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1424
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB) - 1427
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB) - 1430
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (SYNC 0) - 1433
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_NegFeature, PPC_FeatureMSYNC},
|
|
// (SYNC 1) - 1435
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_NegFeature, PPC_FeatureMSYNC},
|
|
// (SYNC 2) - 1437
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_NegFeature, PPC_FeatureMSYNC},
|
|
// (SYNCP10 0, 0) - 1439
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SYNCP10 2, 0) - 1441
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SYNCP10 4, 0) - 1443
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SYNCP10 5, 0) - 1445
|
|
{AliasPatternCond_K_Imm, (uint32_t)5},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SYNCP10 u3imm:$L, 0) - 1447
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (SYNCP10 1, 1) - 1449
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (SYNCP10 0, 2) - 1451
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
// (SYNCP10 0, 3) - 1453
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
// (TD 16, g8rc:$rA, g8rc:$rB) - 1455
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TD 4, g8rc:$rA, g8rc:$rB) - 1458
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TD 8, g8rc:$rA, g8rc:$rB) - 1461
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TD 24, g8rc:$rA, g8rc:$rB) - 1464
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TD 2, g8rc:$rA, g8rc:$rB) - 1467
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TD 1, g8rc:$rA, g8rc:$rB) - 1470
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TD 31, g8rc:$rA, g8rc:$rB) - 1473
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 16, g8rc:$rA, s16imm:$imm) - 1476
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 4, g8rc:$rA, s16imm:$imm) - 1478
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 8, g8rc:$rA, s16imm:$imm) - 1480
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 24, g8rc:$rA, s16imm:$imm) - 1482
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 2, g8rc:$rA, s16imm:$imm) - 1484
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 1, g8rc:$rA, s16imm:$imm) - 1486
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TDI 31, g8rc:$rA, s16imm:$imm) - 1488
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_RegClass, PPC_G8RCRegClassID},
|
|
// (TEND 0) - 1490
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (TEND 1) - 1491
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (TLBIE R0, gprc:$RB) - 1492
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TLBILX 0, R0, R0) - 1494
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureBookE},
|
|
// (TLBILX 1, R0, R0) - 1498
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureBookE},
|
|
// (TLBILX 3, gprc:$RA, gprc:$RB) - 1502
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureBookE},
|
|
// (TLBILX 3, R0, gprc:$RB) - 1506
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Feature, PPC_FeatureBookE},
|
|
// (TLBRE2 gprc:$RS, gprc:$A, 0) - 1510
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeaturePPC4xx},
|
|
// (TLBRE2 gprc:$RS, gprc:$A, 1) - 1514
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Feature, PPC_FeaturePPC4xx},
|
|
// (TLBWE2 gprc:$RS, gprc:$A, 0) - 1518
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Feature, PPC_FeaturePPC4xx},
|
|
// (TLBWE2 gprc:$RS, gprc:$A, 1) - 1522
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Feature, PPC_FeaturePPC4xx},
|
|
// (TSR 0) - 1526
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (TSR 1) - 1527
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (TW 31, R0, R0) - 1528
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
// (TW 16, gprc:$rA, gprc:$rB) - 1531
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TW 4, gprc:$rA, gprc:$rB) - 1534
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TW 8, gprc:$rA, gprc:$rB) - 1537
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TW 24, gprc:$rA, gprc:$rB) - 1540
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TW 2, gprc:$rA, gprc:$rB) - 1543
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TW 1, gprc:$rA, gprc:$rB) - 1546
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TW 31, gprc:$rA, gprc:$rB) - 1549
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 16, gprc:$rA, s16imm:$imm) - 1552
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 4, gprc:$rA, s16imm:$imm) - 1554
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 8, gprc:$rA, s16imm:$imm) - 1556
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 24, gprc:$rA, s16imm:$imm) - 1558
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 2, gprc:$rA, s16imm:$imm) - 1560
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 1, gprc:$rA, s16imm:$imm) - 1562
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (TWI 31, gprc:$rA, s16imm:$imm) - 1564
|
|
{AliasPatternCond_K_Imm, (uint32_t)31},
|
|
{AliasPatternCond_K_RegClass, PPC_GPRCRegClassID},
|
|
// (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA) - 1566
|
|
{AliasPatternCond_K_RegClass, PPC_VRRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VRRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA) - 1569
|
|
{AliasPatternCond_K_RegClass, PPC_VRRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VRRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (WAIT 0) - 1572
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (WAIT 1) - 1573
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
// (WAIT 2) - 1574
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
// (WAITP10 0, 0) - 1575
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (WAITP10 1, 0) - 1577
|
|
{AliasPatternCond_K_Imm, (uint32_t)1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (XORI R0, R0, 0) - 1579
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Reg, PPC_R0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (XORI8 X0, X0, 0) - 1582
|
|
{AliasPatternCond_K_Reg, PPC_X0},
|
|
{AliasPatternCond_K_Reg, PPC_X0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB) - 1585
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB) - 1588
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0) - 1591
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3) - 1598
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0) - 1605
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3) - 1609
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2) - 1613
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
// (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0) - 1617
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSFRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3) - 1623
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSFRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_OrNegFeature, PPC_AIXOS},
|
|
{AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2) - 1629
|
|
{AliasPatternCond_K_RegClass, PPC_VSRCRegClassID},
|
|
{AliasPatternCond_K_RegClass, PPC_VSFRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
// (gBC 12, crbitrc:$bi, condbrtarget:$dst) - 1632
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 4, crbitrc:$bi, condbrtarget:$dst) - 1634
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 14, crbitrc:$bi, condbrtarget:$dst) - 1636
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 6, crbitrc:$bi, condbrtarget:$dst) - 1638
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 15, crbitrc:$bi, condbrtarget:$dst) - 1640
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 7, crbitrc:$bi, condbrtarget:$dst) - 1642
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 8, crbitrc:$bi, condbrtarget:$dst) - 1644
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 0, crbitrc:$bi, condbrtarget:$dst) - 1646
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 10, crbitrc:$bi, condbrtarget:$dst) - 1648
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 2, crbitrc:$bi, condbrtarget:$dst) - 1650
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBC 20, CR0LT, condbrtarget:$dst) - 1652
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCA 12, crbitrc:$bi, abscondbrtarget:$dst) - 1654
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 4, crbitrc:$bi, abscondbrtarget:$dst) - 1656
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 14, crbitrc:$bi, abscondbrtarget:$dst) - 1658
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 6, crbitrc:$bi, abscondbrtarget:$dst) - 1660
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 15, crbitrc:$bi, abscondbrtarget:$dst) - 1662
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 7, crbitrc:$bi, abscondbrtarget:$dst) - 1664
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 8, crbitrc:$bi, abscondbrtarget:$dst) - 1666
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 0, crbitrc:$bi, abscondbrtarget:$dst) - 1668
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 10, crbitrc:$bi, abscondbrtarget:$dst) - 1670
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 2, crbitrc:$bi, abscondbrtarget:$dst) - 1672
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCA 20, CR0LT, abscondbrtarget:$dst) - 1674
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1676
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1679
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCAat 18, 0, CR0LT, abscondbrtarget:$dst) - 1682
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCAat 16, 0, CR0LT, abscondbrtarget:$dst) - 1685
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCAat 27, 3, CR0LT, abscondbrtarget:$dst) - 1688
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCAat 25, 3, CR0LT, abscondbrtarget:$dst) - 1691
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCAat 26, 2, CR0LT, abscondbrtarget:$dst) - 1694
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCAat 24, 2, CR0LT, abscondbrtarget:$dst) - 1697
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCCTR 12, crbitrc:$bi, 0) - 1700
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTR 4, crbitrc:$bi, 0) - 1703
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTR 14, crbitrc:$bi, 0) - 1706
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTR 6, crbitrc:$bi, 0) - 1709
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTR 15, crbitrc:$bi, 0) - 1712
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTR 7, crbitrc:$bi, 0) - 1715
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTR 20, CR0LT, 0) - 1718
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 12, crbitrc:$bi, 0) - 1721
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 4, crbitrc:$bi, 0) - 1724
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 14, crbitrc:$bi, 0) - 1727
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 6, crbitrc:$bi, 0) - 1730
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 15, crbitrc:$bi, 0) - 1733
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 7, crbitrc:$bi, 0) - 1736
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCCTRL 20, CR0LT, 0) - 1739
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCL 12, crbitrc:$bi, condbrtarget:$dst) - 1742
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 4, crbitrc:$bi, condbrtarget:$dst) - 1744
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 14, crbitrc:$bi, condbrtarget:$dst) - 1746
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 6, crbitrc:$bi, condbrtarget:$dst) - 1748
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 15, crbitrc:$bi, condbrtarget:$dst) - 1750
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 7, crbitrc:$bi, condbrtarget:$dst) - 1752
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 8, crbitrc:$bi, condbrtarget:$dst) - 1754
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 0, crbitrc:$bi, condbrtarget:$dst) - 1756
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 10, crbitrc:$bi, condbrtarget:$dst) - 1758
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 2, crbitrc:$bi, condbrtarget:$dst) - 1760
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCL 20, CR0LT, condbrtarget:$dst) - 1762
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLA 12, crbitrc:$bi, abscondbrtarget:$dst) - 1764
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 4, crbitrc:$bi, abscondbrtarget:$dst) - 1766
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 14, crbitrc:$bi, abscondbrtarget:$dst) - 1768
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 6, crbitrc:$bi, abscondbrtarget:$dst) - 1770
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 15, crbitrc:$bi, abscondbrtarget:$dst) - 1772
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 7, crbitrc:$bi, abscondbrtarget:$dst) - 1774
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 8, crbitrc:$bi, abscondbrtarget:$dst) - 1776
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 0, crbitrc:$bi, abscondbrtarget:$dst) - 1778
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 10, crbitrc:$bi, abscondbrtarget:$dst) - 1780
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 2, crbitrc:$bi, abscondbrtarget:$dst) - 1782
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLA 20, CR0LT, abscondbrtarget:$dst) - 1784
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1786
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1789
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLAat 18, 0, CR0LT, abscondbrtarget:$dst) - 1792
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLAat 16, 0, CR0LT, abscondbrtarget:$dst) - 1795
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLAat 27, 3, CR0LT, abscondbrtarget:$dst) - 1798
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLAat 25, 3, CR0LT, abscondbrtarget:$dst) - 1801
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLAat 26, 2, CR0LT, abscondbrtarget:$dst) - 1804
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLAat 24, 2, CR0LT, abscondbrtarget:$dst) - 1807
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLR 18, CR0LT, 0) - 1810
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 16, CR0LT, 0) - 1813
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 27, CR0LT, 0) - 1816
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 25, CR0LT, 0) - 1819
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 26, CR0LT, 0) - 1822
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 24, CR0LT, 0) - 1825
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 12, crbitrc:$bi, 0) - 1828
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 4, crbitrc:$bi, 0) - 1831
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 14, crbitrc:$bi, 0) - 1834
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 6, crbitrc:$bi, 0) - 1837
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 15, crbitrc:$bi, 0) - 1840
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 7, crbitrc:$bi, 0) - 1843
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 8, crbitrc:$bi, 0) - 1846
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 0, crbitrc:$bi, 0) - 1849
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 10, crbitrc:$bi, 0) - 1852
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 2, crbitrc:$bi, 0) - 1855
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLR 20, CR0LT, 0) - 1858
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 18, CR0LT, 0) - 1861
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 16, CR0LT, 0) - 1864
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 27, CR0LT, 0) - 1867
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 25, CR0LT, 0) - 1870
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 26, CR0LT, 0) - 1873
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 24, CR0LT, 0) - 1876
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 12, crbitrc:$bi, 0) - 1879
|
|
{AliasPatternCond_K_Imm, (uint32_t)12},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 4, crbitrc:$bi, 0) - 1882
|
|
{AliasPatternCond_K_Imm, (uint32_t)4},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 14, crbitrc:$bi, 0) - 1885
|
|
{AliasPatternCond_K_Imm, (uint32_t)14},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 6, crbitrc:$bi, 0) - 1888
|
|
{AliasPatternCond_K_Imm, (uint32_t)6},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 15, crbitrc:$bi, 0) - 1891
|
|
{AliasPatternCond_K_Imm, (uint32_t)15},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 7, crbitrc:$bi, 0) - 1894
|
|
{AliasPatternCond_K_Imm, (uint32_t)7},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 8, crbitrc:$bi, 0) - 1897
|
|
{AliasPatternCond_K_Imm, (uint32_t)8},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 0, crbitrc:$bi, 0) - 1900
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 10, crbitrc:$bi, 0) - 1903
|
|
{AliasPatternCond_K_Imm, (uint32_t)10},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 2, crbitrc:$bi, 0) - 1906
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLRL 20, CR0LT, 0) - 1909
|
|
{AliasPatternCond_K_Imm, (uint32_t)20},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (gBCLat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1912
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1915
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCLat 18, 0, CR0LT, condbrtarget:$dst) - 1918
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLat 16, 0, CR0LT, condbrtarget:$dst) - 1921
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLat 27, 3, CR0LT, condbrtarget:$dst) - 1924
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLat 25, 3, CR0LT, condbrtarget:$dst) - 1927
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLat 26, 2, CR0LT, condbrtarget:$dst) - 1930
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCLat 24, 2, CR0LT, condbrtarget:$dst) - 1933
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1936
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1939
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID},
|
|
// (gBCat 18, 0, CR0LT, condbrtarget:$dst) - 1942
|
|
{AliasPatternCond_K_Imm, (uint32_t)18},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCat 16, 0, CR0LT, condbrtarget:$dst) - 1945
|
|
{AliasPatternCond_K_Imm, (uint32_t)16},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCat 27, 3, CR0LT, condbrtarget:$dst) - 1948
|
|
{AliasPatternCond_K_Imm, (uint32_t)27},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCat 25, 3, CR0LT, condbrtarget:$dst) - 1951
|
|
{AliasPatternCond_K_Imm, (uint32_t)25},
|
|
{AliasPatternCond_K_Imm, (uint32_t)3},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCat 26, 2, CR0LT, condbrtarget:$dst) - 1954
|
|
{AliasPatternCond_K_Imm, (uint32_t)26},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
// (gBCat 24, 2, CR0LT, condbrtarget:$dst) - 1957
|
|
{AliasPatternCond_K_Imm, (uint32_t)24},
|
|
{AliasPatternCond_K_Imm, (uint32_t)2},
|
|
{AliasPatternCond_K_Reg, PPC_CR0LT},
|
|
{0}, };
|
|
|
|
static const char AsmStrings[] =
|
|
/* 0 */ "li $\x01, $\xFF\x03\x01\0"
|
|
/* 12 */ "lis $\x01, $\xFF\x03\x01\0"
|
|
/* 25 */ "lnia $\x01\0"
|
|
/* 33 */ "blt $\x02, $\xFF\x03\x02\0"
|
|
/* 46 */ "blt $\xFF\x03\x02\0"
|
|
/* 55 */ "blt- $\x02, $\xFF\x03\x02\0"
|
|
/* 69 */ "blt- $\xFF\x03\x02\0"
|
|
/* 79 */ "blt+ $\x02, $\xFF\x03\x02\0"
|
|
/* 93 */ "blt+ $\xFF\x03\x02\0"
|
|
/* 103 */ "bgt $\x02, $\xFF\x03\x02\0"
|
|
/* 116 */ "bgt $\xFF\x03\x02\0"
|
|
/* 125 */ "bgt- $\x02, $\xFF\x03\x02\0"
|
|
/* 139 */ "bgt- $\xFF\x03\x02\0"
|
|
/* 149 */ "bgt+ $\x02, $\xFF\x03\x02\0"
|
|
/* 163 */ "bgt+ $\xFF\x03\x02\0"
|
|
/* 173 */ "beq $\x02, $\xFF\x03\x02\0"
|
|
/* 186 */ "beq $\xFF\x03\x02\0"
|
|
/* 195 */ "beq- $\x02, $\xFF\x03\x02\0"
|
|
/* 209 */ "beq- $\xFF\x03\x02\0"
|
|
/* 219 */ "beq+ $\x02, $\xFF\x03\x02\0"
|
|
/* 233 */ "beq+ $\xFF\x03\x02\0"
|
|
/* 243 */ "bne $\x02, $\xFF\x03\x02\0"
|
|
/* 256 */ "bne $\xFF\x03\x02\0"
|
|
/* 265 */ "bne- $\x02, $\xFF\x03\x02\0"
|
|
/* 279 */ "bne- $\xFF\x03\x02\0"
|
|
/* 289 */ "bne+ $\x02, $\xFF\x03\x02\0"
|
|
/* 303 */ "bne+ $\xFF\x03\x02\0"
|
|
/* 313 */ "blta $\x02, $\xFF\x03\x03\0"
|
|
/* 327 */ "blta $\xFF\x03\x03\0"
|
|
/* 337 */ "blta- $\x02, $\xFF\x03\x03\0"
|
|
/* 352 */ "blta- $\xFF\x03\x03\0"
|
|
/* 363 */ "blta+ $\x02, $\xFF\x03\x03\0"
|
|
/* 378 */ "blta+ $\xFF\x03\x03\0"
|
|
/* 389 */ "bgta $\x02, $\xFF\x03\x03\0"
|
|
/* 403 */ "bgta $\xFF\x03\x03\0"
|
|
/* 413 */ "bgta- $\x02, $\xFF\x03\x03\0"
|
|
/* 428 */ "bgta- $\xFF\x03\x03\0"
|
|
/* 439 */ "bgta+ $\x02, $\xFF\x03\x03\0"
|
|
/* 454 */ "bgta+ $\xFF\x03\x03\0"
|
|
/* 465 */ "beqa $\x02, $\xFF\x03\x03\0"
|
|
/* 479 */ "beqa $\xFF\x03\x03\0"
|
|
/* 489 */ "beqa- $\x02, $\xFF\x03\x03\0"
|
|
/* 504 */ "beqa- $\xFF\x03\x03\0"
|
|
/* 515 */ "beqa+ $\x02, $\xFF\x03\x03\0"
|
|
/* 530 */ "beqa+ $\xFF\x03\x03\0"
|
|
/* 541 */ "bnea $\x02, $\xFF\x03\x03\0"
|
|
/* 555 */ "bnea $\xFF\x03\x03\0"
|
|
/* 565 */ "bnea- $\x02, $\xFF\x03\x03\0"
|
|
/* 580 */ "bnea- $\xFF\x03\x03\0"
|
|
/* 591 */ "bnea+ $\x02, $\xFF\x03\x03\0"
|
|
/* 606 */ "bnea+ $\xFF\x03\x03\0"
|
|
/* 617 */ "bltctr $\x02\0"
|
|
/* 627 */ "bltctr\0"
|
|
/* 634 */ "bltctr- $\x02\0"
|
|
/* 645 */ "bltctr-\0"
|
|
/* 653 */ "bltctr+ $\x02\0"
|
|
/* 664 */ "bltctr+\0"
|
|
/* 672 */ "bgtctr $\x02\0"
|
|
/* 682 */ "bgtctr\0"
|
|
/* 689 */ "bgtctr- $\x02\0"
|
|
/* 700 */ "bgtctr-\0"
|
|
/* 708 */ "bgtctr+ $\x02\0"
|
|
/* 719 */ "bgtctr+\0"
|
|
/* 727 */ "beqctr $\x02\0"
|
|
/* 737 */ "beqctr\0"
|
|
/* 744 */ "beqctr- $\x02\0"
|
|
/* 755 */ "beqctr-\0"
|
|
/* 763 */ "beqctr+ $\x02\0"
|
|
/* 774 */ "beqctr+\0"
|
|
/* 782 */ "bnectr $\x02\0"
|
|
/* 792 */ "bnectr\0"
|
|
/* 799 */ "bnectr- $\x02\0"
|
|
/* 810 */ "bnectr-\0"
|
|
/* 818 */ "bnectr+ $\x02\0"
|
|
/* 829 */ "bnectr+\0"
|
|
/* 837 */ "bltctrl $\x02\0"
|
|
/* 848 */ "bltctrl\0"
|
|
/* 856 */ "bltctrl- $\x02\0"
|
|
/* 868 */ "bltctrl-\0"
|
|
/* 877 */ "bltctrl+ $\x02\0"
|
|
/* 889 */ "bltctrl+\0"
|
|
/* 898 */ "bgtctrl $\x02\0"
|
|
/* 909 */ "bgtctrl\0"
|
|
/* 917 */ "bgtctrl- $\x02\0"
|
|
/* 929 */ "bgtctrl-\0"
|
|
/* 938 */ "bgtctrl+ $\x02\0"
|
|
/* 950 */ "bgtctrl+\0"
|
|
/* 959 */ "beqctrl $\x02\0"
|
|
/* 970 */ "beqctrl\0"
|
|
/* 978 */ "beqctrl- $\x02\0"
|
|
/* 990 */ "beqctrl-\0"
|
|
/* 999 */ "beqctrl+ $\x02\0"
|
|
/* 1011 */ "beqctrl+\0"
|
|
/* 1020 */ "bnectrl $\x02\0"
|
|
/* 1031 */ "bnectrl\0"
|
|
/* 1039 */ "bnectrl- $\x02\0"
|
|
/* 1051 */ "bnectrl-\0"
|
|
/* 1060 */ "bnectrl+ $\x02\0"
|
|
/* 1072 */ "bnectrl+\0"
|
|
/* 1081 */ "bltl $\x02, $\xFF\x03\x02\0"
|
|
/* 1095 */ "bltl $\xFF\x03\x02\0"
|
|
/* 1105 */ "bltl- $\x02, $\xFF\x03\x02\0"
|
|
/* 1120 */ "bltl- $\xFF\x03\x02\0"
|
|
/* 1131 */ "bltl+ $\x02, $\xFF\x03\x02\0"
|
|
/* 1146 */ "bltl+ $\xFF\x03\x02\0"
|
|
/* 1157 */ "bgtl $\x02, $\xFF\x03\x02\0"
|
|
/* 1171 */ "bgtl $\xFF\x03\x02\0"
|
|
/* 1181 */ "bgtl- $\x02, $\xFF\x03\x02\0"
|
|
/* 1196 */ "bgtl- $\xFF\x03\x02\0"
|
|
/* 1207 */ "bgtl+ $\x02, $\xFF\x03\x02\0"
|
|
/* 1222 */ "bgtl+ $\xFF\x03\x02\0"
|
|
/* 1233 */ "beql $\x02, $\xFF\x03\x02\0"
|
|
/* 1247 */ "beql $\xFF\x03\x02\0"
|
|
/* 1257 */ "beql- $\x02, $\xFF\x03\x02\0"
|
|
/* 1272 */ "beql- $\xFF\x03\x02\0"
|
|
/* 1283 */ "beql+ $\x02, $\xFF\x03\x02\0"
|
|
/* 1298 */ "beql+ $\xFF\x03\x02\0"
|
|
/* 1309 */ "bnel $\x02, $\xFF\x03\x02\0"
|
|
/* 1323 */ "bnel $\xFF\x03\x02\0"
|
|
/* 1333 */ "bnel- $\x02, $\xFF\x03\x02\0"
|
|
/* 1348 */ "bnel- $\xFF\x03\x02\0"
|
|
/* 1359 */ "bnel+ $\x02, $\xFF\x03\x02\0"
|
|
/* 1374 */ "bnel+ $\xFF\x03\x02\0"
|
|
/* 1385 */ "bltla $\x02, $\xFF\x03\x03\0"
|
|
/* 1400 */ "bltla $\xFF\x03\x03\0"
|
|
/* 1411 */ "bltla- $\x02, $\xFF\x03\x03\0"
|
|
/* 1427 */ "bltla- $\xFF\x03\x03\0"
|
|
/* 1439 */ "bltla+ $\x02, $\xFF\x03\x03\0"
|
|
/* 1455 */ "bltla+ $\xFF\x03\x03\0"
|
|
/* 1467 */ "bgtla $\x02, $\xFF\x03\x03\0"
|
|
/* 1482 */ "bgtla $\xFF\x03\x03\0"
|
|
/* 1493 */ "bgtla- $\x02, $\xFF\x03\x03\0"
|
|
/* 1509 */ "bgtla- $\xFF\x03\x03\0"
|
|
/* 1521 */ "bgtla+ $\x02, $\xFF\x03\x03\0"
|
|
/* 1537 */ "bgtla+ $\xFF\x03\x03\0"
|
|
/* 1549 */ "beqla $\x02, $\xFF\x03\x03\0"
|
|
/* 1564 */ "beqla $\xFF\x03\x03\0"
|
|
/* 1575 */ "beqla- $\x02, $\xFF\x03\x03\0"
|
|
/* 1591 */ "beqla- $\xFF\x03\x03\0"
|
|
/* 1603 */ "beqla+ $\x02, $\xFF\x03\x03\0"
|
|
/* 1619 */ "beqla+ $\xFF\x03\x03\0"
|
|
/* 1631 */ "bnela $\x02, $\xFF\x03\x03\0"
|
|
/* 1646 */ "bnela $\xFF\x03\x03\0"
|
|
/* 1657 */ "bnela- $\x02, $\xFF\x03\x03\0"
|
|
/* 1673 */ "bnela- $\xFF\x03\x03\0"
|
|
/* 1685 */ "bnela+ $\x02, $\xFF\x03\x03\0"
|
|
/* 1701 */ "bnela+ $\xFF\x03\x03\0"
|
|
/* 1713 */ "bltlr $\x02\0"
|
|
/* 1722 */ "bltlr\0"
|
|
/* 1728 */ "bltlr- $\x02\0"
|
|
/* 1738 */ "bltlr-\0"
|
|
/* 1745 */ "bltlr+ $\x02\0"
|
|
/* 1755 */ "bltlr+\0"
|
|
/* 1762 */ "bgtlr $\x02\0"
|
|
/* 1771 */ "bgtlr\0"
|
|
/* 1777 */ "bgtlr- $\x02\0"
|
|
/* 1787 */ "bgtlr-\0"
|
|
/* 1794 */ "bgtlr+ $\x02\0"
|
|
/* 1804 */ "bgtlr+\0"
|
|
/* 1811 */ "beqlr $\x02\0"
|
|
/* 1820 */ "beqlr\0"
|
|
/* 1826 */ "beqlr- $\x02\0"
|
|
/* 1836 */ "beqlr-\0"
|
|
/* 1843 */ "beqlr+ $\x02\0"
|
|
/* 1853 */ "beqlr+\0"
|
|
/* 1860 */ "bnelr $\x02\0"
|
|
/* 1869 */ "bnelr\0"
|
|
/* 1875 */ "bnelr- $\x02\0"
|
|
/* 1885 */ "bnelr-\0"
|
|
/* 1892 */ "bnelr+ $\x02\0"
|
|
/* 1902 */ "bnelr+\0"
|
|
/* 1909 */ "bltlrl $\x02\0"
|
|
/* 1919 */ "bltlrl\0"
|
|
/* 1926 */ "bltlrl- $\x02\0"
|
|
/* 1937 */ "bltlrl-\0"
|
|
/* 1945 */ "bltlrl+ $\x02\0"
|
|
/* 1956 */ "bltlrl+\0"
|
|
/* 1964 */ "bgtlrl $\x02\0"
|
|
/* 1974 */ "bgtlrl\0"
|
|
/* 1981 */ "bgtlrl- $\x02\0"
|
|
/* 1992 */ "bgtlrl-\0"
|
|
/* 2000 */ "bgtlrl+ $\x02\0"
|
|
/* 2011 */ "bgtlrl+\0"
|
|
/* 2019 */ "beqlrl $\x02\0"
|
|
/* 2029 */ "beqlrl\0"
|
|
/* 2036 */ "beqlrl- $\x02\0"
|
|
/* 2047 */ "beqlrl-\0"
|
|
/* 2055 */ "beqlrl+ $\x02\0"
|
|
/* 2066 */ "beqlrl+\0"
|
|
/* 2074 */ "bnelrl $\x02\0"
|
|
/* 2084 */ "bnelrl\0"
|
|
/* 2091 */ "bnelrl- $\x02\0"
|
|
/* 2102 */ "bnelrl-\0"
|
|
/* 2110 */ "bnelrl+ $\x02\0"
|
|
/* 2121 */ "bnelrl+\0"
|
|
/* 2129 */ "cmpd $\x02, $\x03\0"
|
|
/* 2141 */ "cmpdi $\x02, $\xFF\x03\x01\0"
|
|
/* 2156 */ "cmpld $\x02, $\x03\0"
|
|
/* 2169 */ "cmpldi $\x02, $\xFF\x03\x04\0"
|
|
/* 2185 */ "cmplw $\x02, $\x03\0"
|
|
/* 2198 */ "cmplwi $\x02, $\xFF\x03\x04\0"
|
|
/* 2214 */ "cmpw $\x02, $\x03\0"
|
|
/* 2226 */ "cmpwi $\x02, $\xFF\x03\x01\0"
|
|
/* 2241 */ "cntlzw $\x01, $\x02\0"
|
|
/* 2255 */ "cntlzw. $\x01, $\x02\0"
|
|
/* 2270 */ "paste. $\x01, $\x02\0"
|
|
/* 2284 */ "crset $\x01\0"
|
|
/* 2293 */ "crnot $\x01, $\x02\0"
|
|
/* 2306 */ "crmove $\x01, $\x02\0"
|
|
/* 2320 */ "crclr $\x01\0"
|
|
/* 2329 */ "isellt $\x01, $\x02, $\x03\0"
|
|
/* 2347 */ "iselgt $\x01, $\x02, $\x03\0"
|
|
/* 2365 */ "iseleq $\x01, $\x02, $\x03\0"
|
|
/* 2383 */ "mbar\0"
|
|
/* 2388 */ "mfbr0 $\x01\0"
|
|
/* 2397 */ "mfbr1 $\x01\0"
|
|
/* 2406 */ "mfbr2 $\x01\0"
|
|
/* 2415 */ "mfbr3 $\x01\0"
|
|
/* 2424 */ "mfbr4 $\x01\0"
|
|
/* 2433 */ "mfbr5 $\x01\0"
|
|
/* 2442 */ "mfbr6 $\x01\0"
|
|
/* 2451 */ "mfbr7 $\x01\0"
|
|
/* 2460 */ "mfxer $\x01\0"
|
|
/* 2469 */ "mfudscr $\x01\0"
|
|
/* 2480 */ "mfrtcu $\x01\0"
|
|
/* 2490 */ "mfrtcl $\x01\0"
|
|
/* 2500 */ "mflr $\x01\0"
|
|
/* 2508 */ "mfctr $\x01\0"
|
|
/* 2517 */ "mfuamr $\x01\0"
|
|
/* 2527 */ "mfdscr $\x01\0"
|
|
/* 2537 */ "mfdsisr $\x01\0"
|
|
/* 2548 */ "mfdar $\x01\0"
|
|
/* 2557 */ "mfdec $\x01\0"
|
|
/* 2566 */ "mfsdr1 $\x01\0"
|
|
/* 2576 */ "mfsrr0 $\x01\0"
|
|
/* 2586 */ "mfsrr1 $\x01\0"
|
|
/* 2596 */ "mfcfar $\x01\0"
|
|
/* 2606 */ "mfamr $\x01\0"
|
|
/* 2615 */ "mfpid $\x01\0"
|
|
/* 2624 */ "mfasr $\x01\0"
|
|
/* 2633 */ "mfpvr $\x01\0"
|
|
/* 2642 */ "mfspefscr $\x01\0"
|
|
/* 2655 */ "mfdbatu $\x01, 0\0"
|
|
/* 2669 */ "mfdbatl $\x01, 0\0"
|
|
/* 2683 */ "mfibatu $\x01, 0\0"
|
|
/* 2697 */ "mfibatl $\x01, 0\0"
|
|
/* 2711 */ "mfdbatu $\x01, 1\0"
|
|
/* 2725 */ "mfdbatl $\x01, 1\0"
|
|
/* 2739 */ "mfibatu $\x01, 1\0"
|
|
/* 2753 */ "mfibatl $\x01, 1\0"
|
|
/* 2767 */ "mfdbatu $\x01, 2\0"
|
|
/* 2781 */ "mfdbatl $\x01, 2\0"
|
|
/* 2795 */ "mfibatu $\x01, 2\0"
|
|
/* 2809 */ "mfibatl $\x01, 2\0"
|
|
/* 2823 */ "mfdbatu $\x01, 3\0"
|
|
/* 2837 */ "mfdbatl $\x01, 3\0"
|
|
/* 2851 */ "mfibatu $\x01, 3\0"
|
|
/* 2865 */ "mfibatl $\x01, 3\0"
|
|
/* 2879 */ "mfppr $\x01\0"
|
|
/* 2888 */ "mfesr $\x01\0"
|
|
/* 2897 */ "mfdear $\x01\0"
|
|
/* 2907 */ "mftcr $\x01\0"
|
|
/* 2916 */ "mftbhi $\x01\0"
|
|
/* 2926 */ "mftblo $\x01\0"
|
|
/* 2936 */ "mfsrr2 $\x01\0"
|
|
/* 2946 */ "mfsrr3 $\x01\0"
|
|
/* 2956 */ "mfdccr $\x01\0"
|
|
/* 2966 */ "mficcr $\x01\0"
|
|
/* 2976 */ "mftbu $\x01\0"
|
|
/* 2985 */ "mfvrsave $\x01\0"
|
|
/* 2997 */ "mffprd $\x01, $\x02\0"
|
|
/* 3011 */ "mffprwz $\x01, $\x02\0"
|
|
/* 3026 */ "mtcr $\x02\0"
|
|
/* 3034 */ "mtbr0 $\x01\0"
|
|
/* 3043 */ "mtbr1 $\x01\0"
|
|
/* 3052 */ "mtbr2 $\x01\0"
|
|
/* 3061 */ "mtbr3 $\x01\0"
|
|
/* 3070 */ "mtbr4 $\x01\0"
|
|
/* 3079 */ "mtbr5 $\x01\0"
|
|
/* 3088 */ "mtbr6 $\x01\0"
|
|
/* 3097 */ "mtbr7 $\x01\0"
|
|
/* 3106 */ "mtfsf $\x01, $\x02\0"
|
|
/* 3119 */ "mtfsfi $\xFF\x01\x05, $\xFF\x02\x06\0"
|
|
/* 3137 */ "mtfsfi. $\xFF\x01\x05, $\xFF\x02\x06\0"
|
|
/* 3156 */ "mtfsf. $\x01, $\x02\0"
|
|
/* 3170 */ "mtmsr $\x01\0"
|
|
/* 3179 */ "mtmsrd $\x01\0"
|
|
/* 3189 */ "mtxer $\x02\0"
|
|
/* 3198 */ "mtudscr $\x02\0"
|
|
/* 3209 */ "mtlr $\x02\0"
|
|
/* 3217 */ "mtctr $\x02\0"
|
|
/* 3226 */ "mtuamr $\x02\0"
|
|
/* 3236 */ "mtdscr $\x02\0"
|
|
/* 3246 */ "mtdsisr $\x02\0"
|
|
/* 3257 */ "mtdar $\x02\0"
|
|
/* 3266 */ "mtdec $\x02\0"
|
|
/* 3275 */ "mtsdr1 $\x02\0"
|
|
/* 3285 */ "mtsrr0 $\x02\0"
|
|
/* 3295 */ "mtsrr1 $\x02\0"
|
|
/* 3305 */ "mtcfar $\x02\0"
|
|
/* 3315 */ "mtamr $\x02\0"
|
|
/* 3324 */ "mtpid $\x02\0"
|
|
/* 3333 */ "mtasr $\x02\0"
|
|
/* 3342 */ "mttbl $\x02\0"
|
|
/* 3351 */ "mttbu $\x02\0"
|
|
/* 3360 */ "mtspefscr $\x02\0"
|
|
/* 3373 */ "mtdbatu 0, $\x02\0"
|
|
/* 3387 */ "mtdbatl 0, $\x02\0"
|
|
/* 3401 */ "mtibatu 0, $\x02\0"
|
|
/* 3415 */ "mtibatl 0, $\x02\0"
|
|
/* 3429 */ "mtdbatu 1, $\x02\0"
|
|
/* 3443 */ "mtdbatl 1, $\x02\0"
|
|
/* 3457 */ "mtibatu 1, $\x02\0"
|
|
/* 3471 */ "mtibatl 1, $\x02\0"
|
|
/* 3485 */ "mtdbatu 2, $\x02\0"
|
|
/* 3499 */ "mtdbatl 2, $\x02\0"
|
|
/* 3513 */ "mtibatu 2, $\x02\0"
|
|
/* 3527 */ "mtibatl 2, $\x02\0"
|
|
/* 3541 */ "mtdbatu 3, $\x02\0"
|
|
/* 3555 */ "mtdbatl 3, $\x02\0"
|
|
/* 3569 */ "mtibatu 3, $\x02\0"
|
|
/* 3583 */ "mtibatl 3, $\x02\0"
|
|
/* 3597 */ "mtppr $\x02\0"
|
|
/* 3606 */ "mtesr $\x02\0"
|
|
/* 3615 */ "mtdear $\x02\0"
|
|
/* 3625 */ "mttcr $\x02\0"
|
|
/* 3634 */ "mttbhi $\x02\0"
|
|
/* 3644 */ "mttblo $\x02\0"
|
|
/* 3654 */ "mtsrr2 $\x02\0"
|
|
/* 3664 */ "mtsrr3 $\x02\0"
|
|
/* 3674 */ "mtdccr $\x02\0"
|
|
/* 3684 */ "mticcr $\x02\0"
|
|
/* 3694 */ "mtudscr $\x01\0"
|
|
/* 3705 */ "mtvrsave $\x01\0"
|
|
/* 3717 */ "mtfprd $\x01, $\x02\0"
|
|
/* 3731 */ "mtfprwa $\x01, $\x02\0"
|
|
/* 3746 */ "mtfprwz $\x01, $\x02\0"
|
|
/* 3761 */ "not $\x01, $\x02\0"
|
|
/* 3772 */ "not. $\x01, $\x02\0"
|
|
/* 3784 */ "mr $\x01, $\x02\0"
|
|
/* 3794 */ "mr. $\x01, $\x02\0"
|
|
/* 3805 */ "nop\0"
|
|
/* 3809 */ "paddi $\x01, $\x02, $\xFF\x03\x07\0"
|
|
/* 3828 */ "qvfclr $\x01\0"
|
|
/* 3838 */ "qvfand $\x01, $\x02, $\x03\0"
|
|
/* 3856 */ "qvfandc $\x01, $\x02, $\x03\0"
|
|
/* 3875 */ "qvfctfb $\x01, $\x02\0"
|
|
/* 3890 */ "qvfxor $\x01, $\x02, $\x03\0"
|
|
/* 3908 */ "qvfor $\x01, $\x02, $\x03\0"
|
|
/* 3925 */ "qvfnor $\x01, $\x02, $\x03\0"
|
|
/* 3943 */ "qvfequ $\x01, $\x02, $\x03\0"
|
|
/* 3961 */ "qvfnot $\x01, $\x02\0"
|
|
/* 3975 */ "qvforc $\x01, $\x02, $\x03\0"
|
|
/* 3993 */ "qvfnand $\x01, $\x02, $\x03\0"
|
|
/* 4012 */ "qvfset $\x01\0"
|
|
/* 4022 */ "rfebb\0"
|
|
/* 4028 */ "rotld $\x01, $\x02, $\x03\0"
|
|
/* 4045 */ "rotld. $\x01, $\x02, $\x03\0"
|
|
/* 4063 */ "rotldi $\x01, $\x02, $\xFF\x03\x08\0"
|
|
/* 4083 */ "clrldi $\x01, $\x02, $\xFF\x04\x08\0"
|
|
/* 4103 */ "rotldi. $\x01, $\x02, $\xFF\x03\x08\0"
|
|
/* 4124 */ "clrldi. $\x01, $\x02, $\xFF\x04\x08\0"
|
|
/* 4145 */ "rotlwi $\x01, $\x02, $\xFF\x03\x09\0"
|
|
/* 4165 */ "clrlwi $\x01, $\x02, $\xFF\x04\x09\0"
|
|
/* 4185 */ "rotlwi. $\x01, $\x02, $\xFF\x03\x09\0"
|
|
/* 4206 */ "clrlwi. $\x01, $\x02, $\xFF\x04\x09\0"
|
|
/* 4227 */ "rotlw $\x01, $\x02, $\x03\0"
|
|
/* 4244 */ "rotlw. $\x01, $\x02, $\x03\0"
|
|
/* 4262 */ "sc\0"
|
|
/* 4265 */ "sub $\x01, $\x03, $\x02\0"
|
|
/* 4280 */ "sub. $\x01, $\x03, $\x02\0"
|
|
/* 4296 */ "subc $\x01, $\x03, $\x02\0"
|
|
/* 4312 */ "subc. $\x01, $\x03, $\x02\0"
|
|
/* 4329 */ "sync\0"
|
|
/* 4334 */ "lwsync\0"
|
|
/* 4341 */ "ptesync\0"
|
|
/* 4349 */ "phwsync\0"
|
|
/* 4357 */ "plwsync\0"
|
|
/* 4365 */ "sync $\xFF\x01\x05\0"
|
|
/* 4375 */ "stncisync\0"
|
|
/* 4385 */ "stcisync\0"
|
|
/* 4394 */ "stsync\0"
|
|
/* 4401 */ "tdlt $\x02, $\x03\0"
|
|
/* 4413 */ "tdeq $\x02, $\x03\0"
|
|
/* 4425 */ "tdgt $\x02, $\x03\0"
|
|
/* 4437 */ "tdne $\x02, $\x03\0"
|
|
/* 4449 */ "tdllt $\x02, $\x03\0"
|
|
/* 4462 */ "tdlgt $\x02, $\x03\0"
|
|
/* 4475 */ "tdu $\x02, $\x03\0"
|
|
/* 4486 */ "tdlti $\x02, $\xFF\x03\x01\0"
|
|
/* 4501 */ "tdeqi $\x02, $\xFF\x03\x01\0"
|
|
/* 4516 */ "tdgti $\x02, $\xFF\x03\x01\0"
|
|
/* 4531 */ "tdnei $\x02, $\xFF\x03\x01\0"
|
|
/* 4546 */ "tdllti $\x02, $\xFF\x03\x01\0"
|
|
/* 4562 */ "tdlgti $\x02, $\xFF\x03\x01\0"
|
|
/* 4578 */ "tdui $\x02, $\xFF\x03\x01\0"
|
|
/* 4592 */ "tend.\0"
|
|
/* 4598 */ "tendall.\0"
|
|
/* 4607 */ "tlbie $\x02\0"
|
|
/* 4616 */ "tlbilxlpid\0"
|
|
/* 4627 */ "tlbilxpid\0"
|
|
/* 4637 */ "tlbilxva $\x02, $\x03\0"
|
|
/* 4653 */ "tlbilxva $\x03\0"
|
|
/* 4665 */ "tlbrehi $\x01, $\x02\0"
|
|
/* 4680 */ "tlbrelo $\x01, $\x02\0"
|
|
/* 4695 */ "tlbwehi $\x01, $\x02\0"
|
|
/* 4710 */ "tlbwelo $\x01, $\x02\0"
|
|
/* 4725 */ "tsuspend.\0"
|
|
/* 4735 */ "tresume.\0"
|
|
/* 4744 */ "trap\0"
|
|
/* 4749 */ "twlt $\x02, $\x03\0"
|
|
/* 4761 */ "tweq $\x02, $\x03\0"
|
|
/* 4773 */ "twgt $\x02, $\x03\0"
|
|
/* 4785 */ "twne $\x02, $\x03\0"
|
|
/* 4797 */ "twllt $\x02, $\x03\0"
|
|
/* 4810 */ "twlgt $\x02, $\x03\0"
|
|
/* 4823 */ "twu $\x02, $\x03\0"
|
|
/* 4834 */ "twlti $\x02, $\xFF\x03\x01\0"
|
|
/* 4849 */ "tweqi $\x02, $\xFF\x03\x01\0"
|
|
/* 4864 */ "twgti $\x02, $\xFF\x03\x01\0"
|
|
/* 4879 */ "twnei $\x02, $\xFF\x03\x01\0"
|
|
/* 4894 */ "twllti $\x02, $\xFF\x03\x01\0"
|
|
/* 4910 */ "twlgti $\x02, $\xFF\x03\x01\0"
|
|
/* 4926 */ "twui $\x02, $\xFF\x03\x01\0"
|
|
/* 4940 */ "vnot $\x01, $\x02\0"
|
|
/* 4952 */ "vmr $\x01, $\x02\0"
|
|
/* 4963 */ "wait\0"
|
|
/* 4968 */ "waitrsv\0"
|
|
/* 4976 */ "waitimpl\0"
|
|
/* 4985 */ "xnop\0"
|
|
/* 4990 */ "xvmovdp $\x01, $\x02\0"
|
|
/* 5005 */ "xvmovsp $\x01, $\x02\0"
|
|
/* 5020 */ "xxspltd $\x01, $\x02, 0\0"
|
|
/* 5038 */ "xxspltd $\x01, $\x02, 1\0"
|
|
/* 5056 */ "xxmrghd $\x01, $\x02, $\x03\0"
|
|
/* 5075 */ "xxmrgld $\x01, $\x02, $\x03\0"
|
|
/* 5094 */ "xxswapd $\x01, $\x02\0"
|
|
/* 5109 */ "bt $\x02, $\xFF\x03\x02\0"
|
|
/* 5121 */ "bf $\x02, $\xFF\x03\x02\0"
|
|
/* 5133 */ "bt- $\x02, $\xFF\x03\x02\0"
|
|
/* 5146 */ "bf- $\x02, $\xFF\x03\x02\0"
|
|
/* 5159 */ "bt+ $\x02, $\xFF\x03\x02\0"
|
|
/* 5172 */ "bf+ $\x02, $\xFF\x03\x02\0"
|
|
/* 5185 */ "bdnzt $\x02, $\xFF\x03\x02\0"
|
|
/* 5200 */ "bdnzf $\x02, $\xFF\x03\x02\0"
|
|
/* 5215 */ "bdzt $\x02, $\xFF\x03\x02\0"
|
|
/* 5229 */ "bdzf $\x02, $\xFF\x03\x02\0"
|
|
/* 5243 */ "b $\xFF\x03\x02\0"
|
|
/* 5250 */ "bta $\x02, $\xFF\x03\x03\0"
|
|
/* 5263 */ "bfa $\x02, $\xFF\x03\x03\0"
|
|
/* 5276 */ "bta- $\x02, $\xFF\x03\x03\0"
|
|
/* 5290 */ "bfa- $\x02, $\xFF\x03\x03\0"
|
|
/* 5304 */ "bta+ $\x02, $\xFF\x03\x03\0"
|
|
/* 5318 */ "bfa+ $\x02, $\xFF\x03\x03\0"
|
|
/* 5332 */ "bdnzta $\x02, $\xFF\x03\x03\0"
|
|
/* 5348 */ "bdnzfa $\x02, $\xFF\x03\x03\0"
|
|
/* 5364 */ "bdzta $\x02, $\xFF\x03\x03\0"
|
|
/* 5379 */ "bdzfa $\x02, $\xFF\x03\x03\0"
|
|
/* 5394 */ "ba $\xFF\x03\x03\0"
|
|
/* 5402 */ "bca+ $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 5422 */ "bca- $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 5442 */ "bdz $\xFF\x04\x03\0"
|
|
/* 5451 */ "bdnz $\xFF\x04\x03\0"
|
|
/* 5461 */ "bdz+ $\xFF\x04\x03\0"
|
|
/* 5471 */ "bdnz+ $\xFF\x04\x03\0"
|
|
/* 5482 */ "bdz- $\xFF\x04\x03\0"
|
|
/* 5492 */ "bdnz- $\xFF\x04\x03\0"
|
|
/* 5503 */ "btctr $\x02\0"
|
|
/* 5512 */ "bfctr $\x02\0"
|
|
/* 5521 */ "btctr- $\x02\0"
|
|
/* 5531 */ "bfctr- $\x02\0"
|
|
/* 5541 */ "btctr+ $\x02\0"
|
|
/* 5551 */ "bfctr+ $\x02\0"
|
|
/* 5561 */ "bctr\0"
|
|
/* 5566 */ "btctrl $\x02\0"
|
|
/* 5576 */ "bfctrl $\x02\0"
|
|
/* 5586 */ "btctrl- $\x02\0"
|
|
/* 5597 */ "bfctrl- $\x02\0"
|
|
/* 5608 */ "btctrl+ $\x02\0"
|
|
/* 5619 */ "bfctrl+ $\x02\0"
|
|
/* 5630 */ "bctrl\0"
|
|
/* 5636 */ "btl $\x02, $\xFF\x03\x02\0"
|
|
/* 5649 */ "bfl $\x02, $\xFF\x03\x02\0"
|
|
/* 5662 */ "btl- $\x02, $\xFF\x03\x02\0"
|
|
/* 5676 */ "bfl- $\x02, $\xFF\x03\x02\0"
|
|
/* 5690 */ "btl+ $\x02, $\xFF\x03\x02\0"
|
|
/* 5704 */ "bfl+ $\x02, $\xFF\x03\x02\0"
|
|
/* 5718 */ "bdnztl $\x02, $\xFF\x03\x02\0"
|
|
/* 5734 */ "bdnzfl $\x02, $\xFF\x03\x02\0"
|
|
/* 5750 */ "bdztl $\x02, $\xFF\x03\x02\0"
|
|
/* 5765 */ "bdzfl $\x02, $\xFF\x03\x02\0"
|
|
/* 5780 */ "bl $\xFF\x03\x02\0"
|
|
/* 5788 */ "btla $\x02, $\xFF\x03\x03\0"
|
|
/* 5802 */ "bfla $\x02, $\xFF\x03\x03\0"
|
|
/* 5816 */ "btla- $\x02, $\xFF\x03\x03\0"
|
|
/* 5831 */ "bfla- $\x02, $\xFF\x03\x03\0"
|
|
/* 5846 */ "btla+ $\x02, $\xFF\x03\x03\0"
|
|
/* 5861 */ "bfla+ $\x02, $\xFF\x03\x03\0"
|
|
/* 5876 */ "bdnztla $\x02, $\xFF\x03\x03\0"
|
|
/* 5893 */ "bdnzfla $\x02, $\xFF\x03\x03\0"
|
|
/* 5910 */ "bdztla $\x02, $\xFF\x03\x03\0"
|
|
/* 5926 */ "bdzfla $\x02, $\xFF\x03\x03\0"
|
|
/* 5942 */ "bla $\xFF\x03\x03\0"
|
|
/* 5951 */ "bcla+ $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 5972 */ "bcla- $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 5993 */ "bdzla $\xFF\x04\x03\0"
|
|
/* 6004 */ "bdnzla $\xFF\x04\x03\0"
|
|
/* 6016 */ "bdzla+ $\xFF\x04\x03\0"
|
|
/* 6028 */ "bdnzla+ $\xFF\x04\x03\0"
|
|
/* 6041 */ "bdzla- $\xFF\x04\x03\0"
|
|
/* 6053 */ "bdnzla- $\xFF\x04\x03\0"
|
|
/* 6066 */ "bdzlr\0"
|
|
/* 6072 */ "bdnzlr\0"
|
|
/* 6079 */ "bdzlr+\0"
|
|
/* 6086 */ "bdnzlr+\0"
|
|
/* 6094 */ "bdzlr-\0"
|
|
/* 6101 */ "bdnzlr-\0"
|
|
/* 6109 */ "btlr $\x02\0"
|
|
/* 6117 */ "bflr $\x02\0"
|
|
/* 6125 */ "btlr- $\x02\0"
|
|
/* 6134 */ "bflr- $\x02\0"
|
|
/* 6143 */ "btlr+ $\x02\0"
|
|
/* 6152 */ "bflr+ $\x02\0"
|
|
/* 6161 */ "bdnztlr $\x02\0"
|
|
/* 6172 */ "bdnzflr $\x02\0"
|
|
/* 6183 */ "bdztlr $\x02\0"
|
|
/* 6193 */ "bdzflr $\x02\0"
|
|
/* 6203 */ "blr\0"
|
|
/* 6207 */ "bdzlrl\0"
|
|
/* 6214 */ "bdnzlrl\0"
|
|
/* 6222 */ "bdzlrl+\0"
|
|
/* 6230 */ "bdnzlrl+\0"
|
|
/* 6239 */ "bdzlrl-\0"
|
|
/* 6247 */ "bdnzlrl-\0"
|
|
/* 6256 */ "btlrl $\x02\0"
|
|
/* 6265 */ "bflrl $\x02\0"
|
|
/* 6274 */ "btlrl- $\x02\0"
|
|
/* 6284 */ "bflrl- $\x02\0"
|
|
/* 6294 */ "btlrl+ $\x02\0"
|
|
/* 6304 */ "bflrl+ $\x02\0"
|
|
/* 6314 */ "bdnztlrl $\x02\0"
|
|
/* 6326 */ "bdnzflrl $\x02\0"
|
|
/* 6338 */ "bdztlrl $\x02\0"
|
|
/* 6349 */ "bdzflrl $\x02\0"
|
|
/* 6360 */ "blrl\0"
|
|
/* 6365 */ "bcl+ $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 6385 */ "bcl- $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 6405 */ "bdzl $\xFF\x04\x02\0"
|
|
/* 6415 */ "bdnzl $\xFF\x04\x02\0"
|
|
/* 6426 */ "bdzl+ $\xFF\x04\x02\0"
|
|
/* 6437 */ "bdnzl+ $\xFF\x04\x02\0"
|
|
/* 6449 */ "bdzl- $\xFF\x04\x02\0"
|
|
/* 6460 */ "bdnzl- $\xFF\x04\x02\0"
|
|
/* 6472 */ "bc+ $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 6491 */ "bc- $\xFF\x01\x09, $\x03, $\xFF\x04\x02\0"
|
|
/* 6510 */ "bdz $\xFF\x04\x02\0"
|
|
/* 6519 */ "bdnz $\xFF\x04\x02\0"
|
|
/* 6529 */ "bdz+ $\xFF\x04\x02\0"
|
|
/* 6539 */ "bdnz+ $\xFF\x04\x02\0"
|
|
/* 6550 */ "bdz- $\xFF\x04\x02\0"
|
|
/* 6560 */ "bdnz- $\xFF\x04\x02\0"
|
|
;
|
|
|
|
#ifndef NDEBUG
|
|
//static struct SortCheck {
|
|
// SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
|
|
// assert(std::is_sorted(
|
|
// OpToPatterns.begin(), OpToPatterns.end(),
|
|
// [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
|
|
// return L.Opcode < R.Opcode;
|
|
// }) &&
|
|
// "tablegen failed to sort opcode patterns");
|
|
// }
|
|
//} sortCheckVar(OpToPatterns);
|
|
#endif
|
|
|
|
AliasMatchingData M = {
|
|
OpToPatterns,
|
|
Patterns,
|
|
Conds,
|
|
AsmStrings,
|
|
NULL,
|
|
};
|
|
const char *AsmString = matchAliasPatterns(MI, &M);
|
|
if (!AsmString) return false;
|
|
|
|
unsigned I = 0;
|
|
while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
|
|
AsmString[I] != '$' && AsmString[I] != '\0')
|
|
++I;
|
|
SStream_concat1(OS, '\t');
|
|
char *substr = malloc(I+1);
|
|
memcpy(substr, AsmString, I);
|
|
substr[I] = '\0';
|
|
SStream_concat0(OS, substr);
|
|
free(substr);
|
|
if (AsmString[I] != '\0') {
|
|
if (AsmString[I] == ' ' || AsmString[I] == '\t') {
|
|
SStream_concat1(OS, '\t');
|
|
++I;
|
|
}
|
|
do {
|
|
if (AsmString[I] == '$') {
|
|
++I;
|
|
if (AsmString[I] == (char)0xff) {
|
|
++I;
|
|
int OpIdx = AsmString[I++] - 1;
|
|
int PrintMethodIdx = AsmString[I++] - 1;
|
|
printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
|
|
} else
|
|
printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
|
|
} else {
|
|
SStream_concat1(OS, AsmString[I++]);
|
|
}
|
|
} while (AsmString[I] != '\0');
|
|
}
|
|
|
|
return true;
|
|
#else
|
|
return false;
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
|
|
static void printCustomAliasOperand(
|
|
MCInst *MI, uint64_t Address, unsigned OpIdx,
|
|
unsigned PrintMethodIdx,
|
|
SStream *OS) {
|
|
#ifndef CAPSTONE_DIET
|
|
switch (PrintMethodIdx) {
|
|
default:
|
|
CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
|
|
break;
|
|
case 0:
|
|
printS16ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 1:
|
|
printBranchOperand(MI, Address, OpIdx, OS);
|
|
break;
|
|
case 2:
|
|
printAbsBranchOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 3:
|
|
printU16ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 4:
|
|
printU3ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 5:
|
|
printU4ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 6:
|
|
printS34ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 7:
|
|
printU6ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 8:
|
|
printU5ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
}
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|