343 lines
11 KiB
C
343 lines
11 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Sparc Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MCDisassembler.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "SparcDisassemblerExtension.h"
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#include "SparcLinkage.h"
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#include "SparcMapping.h"
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#include "SparcMCTargetDesc.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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#define DEBUG_TYPE "sparc-disassembler"
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static const unsigned IntRegDecoderTable[] = {
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Sparc_G0, Sparc_G1, Sparc_G2, Sparc_G3, Sparc_G4, Sparc_G5, Sparc_G6, Sparc_G7,
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Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, Sparc_O6, Sparc_O7,
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Sparc_L0, Sparc_L1, Sparc_L2, Sparc_L3, Sparc_L4, Sparc_L5, Sparc_L6, Sparc_L7,
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Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, Sparc_I6, Sparc_I7
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};
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static const unsigned FPRegDecoderTable[] = {
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Sparc_F0, Sparc_F1, Sparc_F2, Sparc_F3, Sparc_F4, Sparc_F5, Sparc_F6, Sparc_F7,
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Sparc_F8, Sparc_F9, Sparc_F10, Sparc_F11, Sparc_F12, Sparc_F13, Sparc_F14, Sparc_F15,
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Sparc_F16, Sparc_F17, Sparc_F18, Sparc_F19, Sparc_F20, Sparc_F21, Sparc_F22, Sparc_F23,
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Sparc_F24, Sparc_F25, Sparc_F26, Sparc_F27, Sparc_F28, Sparc_F29, Sparc_F30, Sparc_F31
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};
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static const unsigned DFPRegDecoderTable[] = {
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Sparc_D0, Sparc_D16, Sparc_D1, Sparc_D17, Sparc_D2, Sparc_D18, Sparc_D3, Sparc_D19,
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Sparc_D4, Sparc_D20, Sparc_D5, Sparc_D21, Sparc_D6, Sparc_D22, Sparc_D7, Sparc_D23,
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Sparc_D8, Sparc_D24, Sparc_D9, Sparc_D25, Sparc_D10, Sparc_D26, Sparc_D11, Sparc_D27,
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Sparc_D12, Sparc_D28, Sparc_D13, Sparc_D29, Sparc_D14, Sparc_D30, Sparc_D15, Sparc_D31
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};
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static const unsigned QFPRegDecoderTable[] = {
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Sparc_Q0, Sparc_Q8, ~0U, ~0U, Sparc_Q1, Sparc_Q9, ~0U, ~0U,
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Sparc_Q2, Sparc_Q10, ~0U, ~0U, Sparc_Q3, Sparc_Q11, ~0U, ~0U,
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Sparc_Q4, Sparc_Q12, ~0U, ~0U, Sparc_Q5, Sparc_Q13, ~0U, ~0U,
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Sparc_Q6, Sparc_Q14, ~0U, ~0U, Sparc_Q7, Sparc_Q15, ~0U, ~0U
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};
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static const unsigned FCCRegDecoderTable[] = { Sparc_FCC0, Sparc_FCC1, Sparc_FCC2,
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Sparc_FCC3 };
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static const unsigned ASRRegDecoderTable[] = {
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Sparc_Y, Sparc_ASR1, Sparc_ASR2, Sparc_ASR3, Sparc_ASR4, Sparc_ASR5, Sparc_ASR6,
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Sparc_ASR7, Sparc_ASR8, Sparc_ASR9, Sparc_ASR10, Sparc_ASR11, Sparc_ASR12, Sparc_ASR13,
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Sparc_ASR14, Sparc_ASR15, Sparc_ASR16, Sparc_ASR17, Sparc_ASR18, Sparc_ASR19, Sparc_ASR20,
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Sparc_ASR21, Sparc_ASR22, Sparc_ASR23, Sparc_ASR24, Sparc_ASR25, Sparc_ASR26, Sparc_ASR27,
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Sparc_ASR28, Sparc_ASR29, Sparc_ASR30, Sparc_ASR31
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};
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static const unsigned PRRegDecoderTable[] = {
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Sparc_TPC, Sparc_TNPC, Sparc_TSTATE, Sparc_TT, Sparc_TICK,
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Sparc_TBA, Sparc_PSTATE, Sparc_TL, Sparc_PIL, Sparc_CWP,
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Sparc_CANSAVE, Sparc_CANRESTORE, Sparc_CLEANWIN, Sparc_OTHERWIN, Sparc_WSTATE
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};
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static const uint16_t IntPairDecoderTable[] = {
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Sparc_G0_G1, Sparc_G2_G3, Sparc_G4_G5, Sparc_G6_G7, Sparc_O0_O1, Sparc_O2_O3,
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Sparc_O4_O5, Sparc_O6_O7, Sparc_L0_L1, Sparc_L2_L3, Sparc_L4_L5, Sparc_L6_L7,
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Sparc_I0_I1, Sparc_I2_I3, Sparc_I4_I5, Sparc_I6_I7,
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};
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static const unsigned CPRegDecoderTable[] = {
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Sparc_C0, Sparc_C1, Sparc_C2, Sparc_C3, Sparc_C4, Sparc_C5, Sparc_C6, Sparc_C7,
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Sparc_C8, Sparc_C9, Sparc_C10, Sparc_C11, Sparc_C12, Sparc_C13, Sparc_C14, Sparc_C15,
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Sparc_C16, Sparc_C17, Sparc_C18, Sparc_C19, Sparc_C20, Sparc_C21, Sparc_C22, Sparc_C23,
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Sparc_C24, Sparc_C25, Sparc_C26, Sparc_C27, Sparc_C28, Sparc_C29, Sparc_C30, Sparc_C31
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};
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static const uint16_t CPPairDecoderTable[] = {
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Sparc_C0_C1, Sparc_C2_C3, Sparc_C4_C5, Sparc_C6_C7, Sparc_C8_C9, Sparc_C10_C11,
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Sparc_C12_C13, Sparc_C14_C15, Sparc_C16_C17, Sparc_C18_C19, Sparc_C20_C21, Sparc_C22_C23,
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Sparc_C24_C25, Sparc_C26_C27, Sparc_C28_C29, Sparc_C30_C31
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};
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static DecodeStatus DecodeDisp19(MCInst *Inst, uint32_t ImmVal,
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uint64_t Address,
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const void *Decoder)
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{
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int64_t BranchTarget = Address + (SignExtend64(ImmVal, 19) * 4);
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MCOperand_CreateImm0(Inst, BranchTarget);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeDisp16(MCInst *Inst, uint32_t ImmVal,
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uint64_t Address,
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const void *Decoder)
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{
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int64_t BranchTarget = Address + (SignExtend64(ImmVal, 16) * 4);
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MCOperand_CreateImm0(Inst, BranchTarget);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeDisp22(MCInst *Inst, uint32_t ImmVal,
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uint64_t Address,
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const void *Decoder)
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{
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int64_t BranchTarget = Address + (SignExtend64(ImmVal, 22) * 4);
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MCOperand_CreateImm0(Inst, BranchTarget);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
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}
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// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
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// depending on SparcRegisterInfo::getPointerRegClass.
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static DecodeStatus DecodePointerLikeRegClass0(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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unsigned Reg = FPRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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unsigned Reg = DFPRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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unsigned Reg = QFPRegDecoderTable[RegNo];
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if (Reg == ~0U)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeCoprocRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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unsigned Reg = CPRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 3)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, (FCCRegDecoderTable[RegNo]));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeASRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, (ASRRegDecoderTable[RegNo]));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodePRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= ARR_SIZE(PRRegDecoderTable))
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, (PRRegDecoderTable[RegNo]));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeIntPairRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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DecodeStatus S = MCDisassembler_Success;
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if (RegNo > 31)
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return MCDisassembler_Fail;
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if ((RegNo & 1))
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S = MCDisassembler_SoftFail;
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unsigned RegisterPair = IntPairDecoderTable[RegNo / 2];
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MCOperand_CreateReg0(Inst, (RegisterPair));
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return S;
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}
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static DecodeStatus DecodeCoprocPairRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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unsigned RegisterPair = CPPairDecoderTable[RegNo / 2];
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MCOperand_CreateReg0(Inst, (RegisterPair));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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#include "SparcGenDisassemblerTables.inc"
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static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
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size_t BytesLen, uint64_t Address, SStream *CStream)
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{
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if (BytesLen < 4) {
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return MCDisassembler_Fail;
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}
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uint32_t Insn = readBytes32(Instr, Bytes);
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DecodeStatus Result = MCDisassembler_Fail;
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// Calling the auto-generated decoder function.
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if (Sparc_getFeatureBits(Instr->csh->mode, Sparc_FeatureV9)) {
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Result = decodeInstruction_4(DecoderTableSparcV932, Instr, Insn,
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Address, NULL);
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} else {
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Result = decodeInstruction_4(DecoderTableSparcV832, Instr, Insn,
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Address, NULL);
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}
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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Result = decodeInstruction_4(DecoderTableSparc32, Instr, Insn, Address,
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NULL);
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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return MCDisassembler_Fail;
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst *MI,
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const void *Decoder)
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{
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// Capstone doesn't support symbols.
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return false;
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}
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static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Offset = fieldFromInstruction_4(insn, 0, 30);
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int64_t CallTarget = Address + (SignExtend64(Offset, 30) * 4);
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if (!tryAddingSymbolicOperand(CallTarget, false, Address, 0, 30, MI,
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Decoder))
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MCOperand_CreateImm0(MI, CallTarget);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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CS_ASSERT(isUIntN(13, insn));
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MCOperand_CreateImm0(MI, (SignExtend64((insn), 13)));
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return MCDisassembler_Success;
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}
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DecodeStatus Sparc_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
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size_t ByteLen, MCInst *MI, uint16_t *Size,
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uint64_t Address, void *Info) {
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uint64_t s = 0;
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DecodeStatus status = getInstruction(MI, &s, Bytes, ByteLen, Address, NULL);
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*Size = (uint16_t) s;
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return status;
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}
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