495 lines
13 KiB
C
495 lines
13 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_SPARC
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../Mapping.h"
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#include "../../utils.h"
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#include "../../cs_simple_types.h"
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#include "SparcMapping.h"
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void Sparc_init_cs_detail(MCInst *MI)
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{
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if (!detail_is_set(MI)) {
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return;
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}
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memset(get_detail(MI), 0, offsetof(cs_detail, sparc) + sizeof(cs_sparc));
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Sparc_get_detail(MI)->cc = SPARC_CC_UNDEF;
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Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_NONE;
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}
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const insn_map sparc_insns[] = {
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#include "SparcGenCSMappingInsn.inc"
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};
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void Sparc_set_instr_map_data(MCInst *MI)
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{
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map_cs_id(MI, sparc_insns, ARR_SIZE(sparc_insns));
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map_implicit_reads(MI, sparc_insns);
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map_implicit_writes(MI, sparc_insns);
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map_groups(MI, sparc_insns);
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const sparc_suppl_info *suppl_info =
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map_get_suppl_info(MI, sparc_insns);
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if (suppl_info) {
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Sparc_get_detail(MI)->format = suppl_info->form;
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}
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}
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/// Adds details which are not defined consistently as LLVM operands like
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/// condition codes for alias instructions or branch hint bits.
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static void Sparc_add_bit_details(MCInst *MI, const uint8_t *Bytes,
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size_t BytesLen)
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{
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if (!Bytes || BytesLen < 4 || !detail_is_set(MI)) {
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return;
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}
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uint32_t insn = readBytes32(MI, Bytes);
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// CC field
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cs_sparc *detail = Sparc_get_detail(MI);
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switch (detail->format) {
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default:
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break;
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case SPARC_INSN_FORM_F2_2: {
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// This format is used either by B or FB instructions.
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// The op2 == 6 for the FB and 2 for B.
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// This is the only indicator we have here to determine which CC field is used
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// if we don't want big switch cases.
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//
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// See: Opcode Maps - Table 39 - Sparc V9 ISA
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size_t op2 = get_insn_field_r(insn, 22, 24);
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detail->cc_field = op2 == 6 ? SPARC_CC_FIELD_FCC0 : SPARC_CC_FIELD_ICC;
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break;
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}
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case SPARC_INSN_FORM_F2_3:
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detail->cc_field = 0x4 | get_insn_field_r(insn, 20, 21);
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break;
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case SPARC_INSN_FORM_TRAPSP:
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detail->cc_field = 0x4 | get_insn_field_r(insn, 11, 12);
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break;
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case SPARC_INSN_FORM_F4_1:
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case SPARC_INSN_FORM_F4_2:
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detail->cc_field = get_insn_field_r(insn, 11, 12);
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detail->cc_field |= get_insn_field_r(insn, 18, 18) << 2;
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break;
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case SPARC_INSN_FORM_F4_3:
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detail->cc_field = get_insn_field_r(insn, 11, 13);
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break;
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}
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// Condition codes
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switch (detail->format) {
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default:
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break;
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case SPARC_INSN_FORM_F2_1:
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case SPARC_INSN_FORM_F2_2:
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case SPARC_INSN_FORM_F2_3:
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case SPARC_INSN_FORM_TRAPSP: {
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// cond
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// Alias instructions don't define the conditions as operands.
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// We need to add them here to the details again.
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sparc_cc cc = get_insn_field_r(insn, 25, 28);
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if (MCInst_getOpcode(MI) == Sparc_CBCOND ||
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MCInst_getOpcode(MI) == Sparc_CBCONDA) {
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cc += SPARC_CC_CPCC_BEGIN;
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}
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detail->cc = cc;
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break;
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}
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case SPARC_INSN_FORM_F4_1:
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case SPARC_INSN_FORM_F4_2:
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case SPARC_INSN_FORM_F4_3: {
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sparc_cc cc = get_insn_field_r(insn, 14, 17);
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detail->cc = cc;
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break;
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}
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case SPARC_INSN_FORM_F2_4: {
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// cond
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// Alias instructions don't define the conditions as operands.
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// We need to add them here to the details again.
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sparc_cc rcc = get_insn_field_r(insn, 25, 27);
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detail->cc = rcc + SPARC_CC_REG_BEGIN;
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break;
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}
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case SPARC_INSN_FORM_F4_4R:
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case SPARC_INSN_FORM_F4_4I: {
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sparc_cc rcc = get_insn_field_r(insn, 10, 12);
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detail->cc = rcc + SPARC_CC_REG_BEGIN;
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break;
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}
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}
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switch (detail->cc_field) {
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default:
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case SPARC_CC_FIELD_ICC:
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case SPARC_CC_FIELD_XCC:
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break;
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case SPARC_CC_FIELD_FCC0:
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case SPARC_CC_FIELD_FCC1:
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case SPARC_CC_FIELD_FCC2:
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case SPARC_CC_FIELD_FCC3:
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detail->cc += SPARC_CC_FCC_BEGIN;
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break;
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}
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// Hints
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switch (detail->format) {
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default:
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break;
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case SPARC_INSN_FORM_F2_2:
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detail->hint = get_insn_field_r(insn, 29, 29);
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break;
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case SPARC_INSN_FORM_F2_3:
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case SPARC_INSN_FORM_F2_4:
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detail->hint = get_insn_field_r(insn, 29, 29);
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detail->hint |=
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get_insn_field_r(insn, 19, 19) == 0 ? SPARC_HINT_PN :
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SPARC_HINT_PT;
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break;
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}
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}
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bool Sparc_getInstruction(csh handle, const uint8_t *code, size_t code_len,
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MCInst *instr, uint16_t *size, uint64_t address,
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void *info)
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{
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Sparc_init_cs_detail(instr);
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bool Result = Sparc_LLVM_getInstruction(handle, code, code_len, instr,
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size, address,
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info) != MCDisassembler_Fail;
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Sparc_set_instr_map_data(instr);
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Sparc_add_bit_details(instr, code, code_len);
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return Result;
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}
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void Sparc_init_mri(MCRegisterInfo *MRI)
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{
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MCRegisterInfo_InitMCRegisterInfo(
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MRI, SparcRegDesc, sizeof(SparcRegDesc), 0, 0,
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SparcMCRegisterClasses, ARR_SIZE(SparcMCRegisterClasses), 0, 0,
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SparcRegDiffLists, 0, SparcSubRegIdxLists,
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ARR_SIZE(SparcSubRegIdxLists), 0);
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}
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const char *Sparc_reg_name(csh handle, unsigned int reg)
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{
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int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
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if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
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return Sparc_LLVM_getRegisterName(reg, Sparc_NoRegAltName);
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}
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return Sparc_LLVM_getRegisterName(reg, Sparc_RegNamesStateReg);
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}
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void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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// Not used by Sparc. Information is set after disassembly.
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}
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static const char *const insn_name_maps[] = {
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#include "SparcGenCSMappingInsnName.inc"
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};
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#ifndef CAPSTONE_DIET
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static const name_map insn_alias_mnem_map[] = {
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#include "SparcGenCSAliasMnemMap.inc"
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{ SPARC_INS_ALIAS_CALL, "call" },
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{ SPARC_INS_ALIAS_END, NULL },
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};
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#endif
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static void insert_op(MCInst *MI, unsigned index, cs_sparc_op op)
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{
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if (!detail_is_set(MI)) {
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return;
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}
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Sparc_check_safe_inc(MI);
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cs_sparc_op *ops = Sparc_get_detail(MI)->operands;
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int i = Sparc_get_detail(MI)->op_count;
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if (index == -1) {
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ops[i] = op;
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Sparc_inc_op_count(MI);
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return;
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}
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for (; i > 0 && i > index; --i) {
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ops[i] = ops[i - 1];
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}
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ops[index] = op;
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Sparc_inc_op_count(MI);
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}
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/// Inserts a register to the detail operands at @index.
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/// Already present operands are moved.
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/// If @index is -1 the operand is appended.
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static void Sparc_insert_detail_op_reg_at(MCInst *MI, unsigned index, sparc_reg Reg,
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cs_ac_type access)
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{
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if (!detail_is_set(MI))
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return;
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cs_sparc_op op = { 0 };
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op.type = SPARC_OP_REG;
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op.reg = Reg;
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op.access = access;
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insert_op(MI, index, op);
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}
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static void Sparc_correct_details(MCInst *MI)
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{
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if (!detail_is_set(MI)) {
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return;
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}
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switch (MCInst_getOpcode(MI)) {
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default:
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return;
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case Sparc_LDSTUBri:
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case Sparc_LDSTUBrr:
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case Sparc_LDSTUBAri:
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case Sparc_LDSTUBArr:
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// The memory gets written back with ones
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// but there is not write back memory operand defined
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// (if even possible).
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Sparc_get_detail(MI)->operands[0].access = CS_AC_READ_WRITE;
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break;
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case Sparc_RDPSR:
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Sparc_insert_detail_op_reg_at(MI, 0, SPARC_REG_PSR, CS_AC_READ);
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break;
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case Sparc_PWRPSRri:
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case Sparc_PWRPSRrr:
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case Sparc_WRPSRri:
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case Sparc_WRPSRrr:
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Sparc_insert_detail_op_reg_at(MI, -1, SPARC_REG_PSR, CS_AC_WRITE);
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break;
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case Sparc_RDWIM:
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Sparc_insert_detail_op_reg_at(MI, 0, SPARC_REG_WIM, CS_AC_READ);
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break;
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case Sparc_WRWIMri:
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case Sparc_WRWIMrr:
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Sparc_insert_detail_op_reg_at(MI, -1, SPARC_REG_WIM, CS_AC_WRITE);
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break;
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case Sparc_RDTBR:
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Sparc_insert_detail_op_reg_at(MI, 0, SPARC_REG_TBR, CS_AC_READ);
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break;
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case Sparc_WRTBRri:
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case Sparc_WRTBRrr:
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Sparc_insert_detail_op_reg_at(MI, -1, SPARC_REG_TBR, CS_AC_WRITE);
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break;
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}
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}
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void Sparc_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
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{
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MCRegisterInfo *MRI = (MCRegisterInfo *)info;
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MI->MRI = MRI;
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MI->flat_insn->usesAliasDetails = map_use_alias_details(MI);
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Sparc_LLVM_printInst(MI, MI->address, "", O);
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#ifndef CAPSTONE_DIET
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map_set_alias_id(MI, O, insn_alias_mnem_map,
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ARR_SIZE(insn_alias_mnem_map));
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Sparc_correct_details(MI);
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#endif
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}
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const char *Sparc_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id < SPARC_INS_ALIAS_END && id > SPARC_INS_ALIAS_BEGIN) {
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if (id - SPARC_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
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return NULL;
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return insn_alias_mnem_map[id - SPARC_INS_ALIAS_BEGIN - 1].name;
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}
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if (id >= SPARC_INS_ENDING)
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return NULL;
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if (id < ARR_SIZE(insn_name_maps))
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return insn_name_maps[id];
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// not found
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return NULL;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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{ SPARC_GRP_INVALID, NULL },
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{ SPARC_GRP_JUMP, "jump" },
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{ SPARC_GRP_CALL, "call" },
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{ SPARC_GRP_RET, "return" },
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{ SPARC_GRP_INT, "int" },
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{ SPARC_GRP_IRET, "iret" },
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{ SPARC_GRP_PRIVILEGE, "privilege" },
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{ SPARC_GRP_BRANCH_RELATIVE, "branch_relative" },
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// architecture-specific groups
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#include "SparcGenCSFeatureName.inc"
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};
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#endif
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const char *Sparc_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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static const map_insn_ops insn_operands[] = {
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#include "SparcGenCSMappingInsnOp.inc"
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};
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void Sparc_set_detail_op_imm(MCInst *MI, unsigned OpNum, sparc_op_type ImmType,
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int64_t Imm)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT_RET((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
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CS_ASSERT_RET(ImmType == SPARC_OP_IMM);
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Sparc_get_detail_op(MI, 0)->type = ImmType;
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Sparc_get_detail_op(MI, 0)->imm = Imm;
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Sparc_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
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Sparc_inc_op_count(MI);
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}
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void Sparc_set_detail_op_reg(MCInst *MI, unsigned OpNum, sparc_reg Reg)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT_RET((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
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switch (Reg) {
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default:
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Sparc_get_detail_op(MI, 0)->type = SPARC_OP_REG;
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Sparc_get_detail_op(MI, 0)->reg = Reg;
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Sparc_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
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Sparc_inc_op_count(MI);
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return;
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// The LLVM definition is inconsistent with the cc fields.
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// Sometimes they are encoded as register, sometimes not at all.
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// For Capstone they are always saved in the cc_field field for now.
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case SPARC_REG_ICC:
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Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_ICC;
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break;
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case SPARC_REG_FCC0:
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Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC0;
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break;
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case SPARC_REG_FCC1:
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Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC1;
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break;
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case SPARC_REG_FCC2:
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Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC2;
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break;
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case SPARC_REG_FCC3:
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Sparc_get_detail(MI)->cc_field = SPARC_CC_FIELD_FCC3;
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break;
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}
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}
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static inline bool is_single_reg_mem_case(MCInst *MI, unsigned OpNo)
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{
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if (map_get_op_type(MI, OpNo) != CS_OP_MEM_REG) {
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return false;
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}
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if (MI->size == 1) {
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return true;
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} else if (MI->size > OpNo + 1 && Sparc_get_detail(MI)->operands[0].type != SPARC_OP_MEM) {
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// Next operand is not a memory operand (disponent or index reg).
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return !(map_get_op_type(MI, OpNo + 1) & SPARC_OP_MEM);
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}
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return false;
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}
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void Sparc_add_cs_detail_0(MCInst *MI, sparc_op_group op_group, unsigned OpNo)
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{
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if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
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return;
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cs_op_type op_type = map_get_op_type(MI, OpNo);
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switch (op_group) {
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default:
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case Sparc_OP_GROUP_GetPCX:
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printf("Operand group %d not handled!\n", op_group);
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return;
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case Sparc_OP_GROUP_Operand:
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if (op_type & CS_OP_MEM) {
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if (is_single_reg_mem_case(MI, OpNo)) {
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Sparc_get_detail_op(MI, 0)->type = SPARC_OP_MEM;
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Sparc_get_detail_op(MI, 0)->mem.base =
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MCInst_getOpVal(MI, OpNo);
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Sparc_get_detail_op(MI, 0)->access =
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map_get_op_access(MI, OpNo);
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Sparc_inc_op_count(MI);
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}
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break;
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}
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if (op_type == CS_OP_IMM) {
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Sparc_set_detail_op_imm(MI, OpNo, SPARC_OP_IMM,
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MCInst_getOpVal(MI, OpNo));
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} else if (op_type == CS_OP_REG) {
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Sparc_set_detail_op_reg(MI, OpNo,
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MCInst_getOpVal(MI, OpNo));
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} else {
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CS_ASSERT_RET(0 && "Op type not handled.");
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}
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Sparc_get_detail_op(MI, 0)->access =
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map_get_op_access(MI, OpNo);
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break;
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case Sparc_OP_GROUP_CCOperand: {
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// Handled in Sparc_add_bit_details().
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break;
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}
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case Sparc_OP_GROUP_MemOperand: {
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MCOperand *Op1 = MCInst_getOperand(MI, (OpNo));
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MCOperand *Op2 = MCInst_getOperand(MI, (OpNo + 1));
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if (!MCOperand_isReg(Op1) ||
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MCOperand_getReg(Op1) == Sparc_G0) {
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// Ignored
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return;
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}
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Sparc_get_detail_op(MI, 0)->type = SPARC_OP_MEM;
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Sparc_get_detail_op(MI, 0)->access =
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|
map_get_op_access(MI, OpNo);
|
|
Sparc_get_detail_op(MI, 0)->mem.base = MCOperand_getReg(Op1);
|
|
|
|
if (MCOperand_isReg(Op2) && MCOperand_getReg(Op2) != Sparc_G0) {
|
|
Sparc_get_detail_op(MI, 0)->mem.index =
|
|
MCOperand_getReg(Op2);
|
|
} else if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) != 0) {
|
|
Sparc_get_detail_op(MI, 0)->mem.disp =
|
|
MCOperand_getImm(Op2);
|
|
}
|
|
Sparc_inc_op_count(MI);
|
|
break;
|
|
}
|
|
case Sparc_OP_GROUP_ASITag:
|
|
Sparc_get_detail_op(MI, 0)->type = SPARC_OP_ASI;
|
|
Sparc_get_detail_op(MI, 0)->access =
|
|
map_get_op_access(MI, OpNo);
|
|
Sparc_get_detail_op(MI, 0)->asi =
|
|
MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
|
Sparc_inc_op_count(MI);
|
|
break;
|
|
case Sparc_OP_GROUP_MembarTag:
|
|
Sparc_get_detail_op(MI, 0)->type = SPARC_OP_MEMBAR_TAG;
|
|
Sparc_get_detail_op(MI, 0)->access =
|
|
map_get_op_access(MI, OpNo);
|
|
Sparc_get_detail_op(MI, 0)->membar_tag =
|
|
MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
|
Sparc_inc_op_count(MI);
|
|
break;
|
|
}
|
|
}
|
|
|
|
#endif
|