1923 lines
83 KiB
YAML
1923 lines
83 KiB
YAML
test_cases:
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-
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input:
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0x0a, 0x84, 0xf9, 0x86, 0x0a, 0x84, 0xf9, 0xcf, 0x0a, 0x84, 0xf9, 0xcd, 0x0a, 0x84, 0xf9, 0xc6, 0x0a, 0x04, 0xf9, 0x0f, 0x00, 0x04, 0xf9, 0x1f, 0x00, 0x04, 0xf9, 0x2f, 0x00, 0x04, 0xf9, 0x3f, 0x00, 0x04, 0xf9, 0x0d, 0x00, 0x04, 0xf9, 0x1d, 0x00, 0x04, 0xf9, 0x2d, 0x00, 0x04, 0xf9, 0x3d, 0x00, 0x04, 0xf9, 0x06, 0x00, 0x04, 0xf9, 0x16, 0x00, 0x04, 0xf9, 0x26, 0x00, 0x04, 0xf9, 0x36, 0x00, 0x04, 0xf9, 0x0f, 0x01, 0x04, 0xf9, 0x1f, 0x01, 0x04, 0xf9, 0x2f, 0x01, 0x04, 0xf9, 0x3f, 0x01, 0x04, 0xf9, 0x0d, 0x01, 0x04, 0xf9, 0x1d, 0x01, 0x04, 0xf9, 0x2d, 0x01, 0x04, 0xf9, 0x3d, 0x01, 0x04, 0xf9, 0x06, 0x01, 0x04, 0xf9, 0x16, 0x01, 0x04, 0xf9, 0x26, 0x01, 0x04, 0xf9, 0x36, 0x01, 0x84, 0xf9, 0x2f, 0x03, 0x84, 0xf9, 0x3f, 0x03, 0x84, 0xf9, 0x2d, 0x03, 0x84, 0xf9, 0x3d, 0x03, 0x84, 0xf9, 0x26, 0x03, 0x84, 0xf9, 0x36, 0x03, 0x04, 0xf9, 0x4f, 0x00, 0x04, 0xf9, 0x5f, 0x00, 0x04, 0xf9, 0x6f, 0x00, 0x04, 0xf9, 0x7f, 0x00, 0x04, 0xf9, 0x4d, 0x00, 0x04, 0xf9, 0x5d, 0x00, 0x04, 0xf9, 0x6d, 0x00, 0x04, 0xf9, 0x7d, 0x00, 0x04, 0xf9, 0x46, 0x00, 0x04, 0xf9, 0x56, 0x00, 0x04, 0xf9, 0x66, 0x00, 0x04, 0xf9, 0x76, 0x00, 0x04, 0xf9, 0x4f, 0x01, 0x04, 0xf9, 0x5f, 0x01, 0x04, 0xf9, 0x6f, 0x01, 0x04, 0xf9, 0x7f, 0x01, 0x04, 0xf9, 0x4d, 0x01, 0x04, 0xf9, 0x5d, 0x01, 0x04, 0xf9, 0x6d, 0x01, 0x04, 0xf9, 0x7d, 0x01, 0x04, 0xf9, 0x46, 0x01, 0x04, 0xf9, 0x56, 0x01, 0x04, 0xf9, 0x66, 0x01, 0x04, 0xf9, 0x76, 0x01, 0x84, 0xf9, 0x4f, 0x07, 0x84, 0xf9, 0x5f, 0x07, 0x84, 0xf9, 0x4d, 0x07, 0x84, 0xf9, 0x5d, 0x07, 0x84, 0xf9, 0x46, 0x07, 0x84, 0xf9, 0x56, 0x07, 0x84, 0xf9, 0x6f, 0x07, 0x84, 0xf9, 0x7f, 0x07, 0x84, 0xf9, 0x6d, 0x07, 0x84, 0xf9, 0x7d, 0x07, 0x84, 0xf9, 0x66, 0x07, 0x84, 0xf9, 0x76, 0x07, 0x04, 0xf9, 0x8f, 0x00, 0x04, 0xf9, 0x9f, 0x00, 0x04, 0xf9, 0xaf, 0x00, 0x04, 0xf9, 0xbf, 0x00, 0x04, 0xf9, 0x8d, 0x00, 0x04, 0xf9, 0x9d, 0x00, 0x04, 0xf9, 0xad, 0x00, 0x04, 0xf9, 0xbd, 0x00, 0x04, 0xf9, 0x86, 0x00, 0x04, 0xf9, 0x96, 0x00, 0x04, 0xf9, 0xa6, 0x00, 0x04, 0xf9, 0xb6, 0x00, 0x04, 0xf9, 0x8f, 0x01, 0x04, 0xf9, 0x9f, 0x01, 0x04, 0xf9, 0xaf, 0x01, 0x04, 0xf9, 0xbf, 0x01, 0x04, 0xf9, 0x8d, 0x01, 0x04, 0xf9, 0x9d, 0x01, 0x04, 0xf9, 0xad, 0x01, 0x04, 0xf9, 0xbd, 0x01, 0x04, 0xf9, 0x86, 0x01, 0x04, 0xf9, 0x96, 0x01, 0x04, 0xf9, 0xa6, 0x01, 0x04, 0xf9, 0xb6, 0x01, 0x84, 0xf9, 0x8f, 0x0b, 0x84, 0xf9, 0x9f, 0x0b, 0x84, 0xf9, 0xaf, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b ]
|
|
arch: "CS_ARCH_ARM"
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options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_MODE_THUMB" ]
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|
expected:
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insns:
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|
-
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|
asm_text: "vld1.8 {d0}, [r4]"
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|
-
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|
asm_text: "vld1.8 {d0}, [r4:64]"
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|
-
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|
asm_text: "vld1.8 {d0}, [r4]!"
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|
-
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|
asm_text: "vld1.8 {d0}, [r4:64]!"
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|
-
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|
asm_text: "vld1.8 {d0}, [r4], r6"
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|
-
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|
asm_text: "vld1.8 {d0}, [r4:64], r6"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4]"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4:64]"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4:128]"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4]!"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4:64]!"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4:128]!"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4], r6"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4:64], r6"
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|
-
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|
asm_text: "vld1.8 {d0, d1}, [r4:128], r6"
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|
-
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|
asm_text: "vld1.8 {d0, d1, d2}, [r4]"
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|
-
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|
asm_text: "vld1.8 {d0, d1, d2}, [r4:64]"
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|
-
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|
asm_text: "vld1.8 {d0, d1, d2}, [r4]!"
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|
-
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|
asm_text: "vld1.8 {d0, d1, d2}, [r4:64]!"
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-
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asm_text: "vld1.8 {d0, d1, d2}, [r4], r6"
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-
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|
asm_text: "vld1.8 {d0, d1, d2}, [r4:64], r6"
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-
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asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]"
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|
-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]"
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-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]"
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-
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asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]"
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-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]!"
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-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]!"
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-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]!"
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-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]!"
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-
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asm_text: "vld1.8 {d0, d1, d2, d3}, [r4], r6"
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-
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|
asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64], r6"
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-
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asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128], r6"
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-
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asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256], r6"
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-
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|
asm_text: "vld1.8 {d0[2]}, [r4]"
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-
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|
asm_text: "vld1.8 {d0[2]}, [r4]!"
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|
-
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|
asm_text: "vld1.8 {d0[2]}, [r4], r6"
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|
-
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|
asm_text: "vld1.8 {d0[]}, [r4]"
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|
-
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|
asm_text: "vld1.8 {d0[]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.8 {d0[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.8 {d0[], d1[]}, [r4]"
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|
-
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|
asm_text: "vld1.8 {d0[], d1[]}, [r4]!"
|
|
-
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|
asm_text: "vld1.8 {d0[], d1[]}, [r4], r6"
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|
-
|
|
asm_text: "vld1.16 {d0}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0}, [r4:64]"
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|
-
|
|
asm_text: "vld1.16 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.16 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4:64]"
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|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0[2]}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0[2]}, [r4:16]"
|
|
-
|
|
asm_text: "vld1.16 {d0[2]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0[2]}, [r4:16]!"
|
|
-
|
|
asm_text: "vld1.16 {d0[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0[2]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0[]}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0[]}, [r4:16]"
|
|
-
|
|
asm_text: "vld1.16 {d0[]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0[]}, [r4:16]!"
|
|
-
|
|
asm_text: "vld1.16 {d0[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0[]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0[], d1[]}, [r4]"
|
|
-
|
|
asm_text: "vld1.16 {d0[], d1[]}, [r4:16]"
|
|
-
|
|
asm_text: "vld1.16 {d0[], d1[]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.16 {d0[], d1[]}, [r4:16]!"
|
|
-
|
|
asm_text: "vld1.16 {d0[], d1[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.16 {d0[], d1[]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.32 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.32 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4:32]"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[]}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0[]}, [r4:32]"
|
|
-
|
|
asm_text: "vld1.32 {d0[]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[], d1[]}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0[], d1[]}, [r4:32]"
|
|
-
|
|
asm_text: "vld1.32 {d0[], d1[]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[], d1[]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[], d1[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[], d1[]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4]"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4:32]"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.32 {d0[1]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0}, [r4]"
|
|
-
|
|
asm_text: "vld1.64 {d0}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.64 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vld1.64 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.64 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d2}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0[2], d1[2]}, [r4]"
|
|
-
|
|
asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]"
|
|
-
|
|
asm_text: "vld2.8 {d0[2], d1[2]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]!"
|
|
-
|
|
asm_text: "vld2.8 {d0[2], d1[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d1[]}, [r4]"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d1[]}, [r4:16]"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d1[]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d1[]}, [r4:16]!"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d1[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d1[]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d2[]}, [r4]"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d2[]}, [r4:16]"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d2[]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d2[]}, [r4:16]!"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d2[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.8 {d0[], d2[]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d2}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d1[2]}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d1[2]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d1[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d2[2]}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d2[2]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d2[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d1[]}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d1[]}, [r4:32]"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d1[]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d1[]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d1[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d1[]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d2[]}, [r4]"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d2[]}, [r4:32]"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d2[]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d2[]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d2[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.16 {d0[], d2[]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d2}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d1[1]}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d1[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d1[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d1[]}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d1[]}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d1[]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d1[]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d1[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d1[]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d2[]}, [r4]"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d2[]}, [r4:64]"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d2[]}, [r4]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d2[]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d2[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld2.32 {d0[], d2[]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vld3.8 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld3.8 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld3.8 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld3.8 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0, d2, d4}, [r4]"
|
|
-
|
|
asm_text: "vld3.8 {d0, d2, d4}, [r4:64]"
|
|
-
|
|
asm_text: "vld3.8 {d0, d2, d4}, [r4]!"
|
|
-
|
|
asm_text: "vld3.8 {d0, d2, d4}, [r4:64]!"
|
|
-
|
|
asm_text: "vld3.8 {d0, d2, d4}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0, d2, d4}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]"
|
|
-
|
|
asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]"
|
|
-
|
|
asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vld3.16 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld3.16 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld3.16 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld3.16 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0, d2, d4}, [r4]"
|
|
-
|
|
asm_text: "vld3.16 {d0, d2, d4}, [r4:64]"
|
|
-
|
|
asm_text: "vld3.16 {d0, d2, d4}, [r4]!"
|
|
-
|
|
asm_text: "vld3.16 {d0, d2, d4}, [r4:64]!"
|
|
-
|
|
asm_text: "vld3.16 {d0, d2, d4}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0, d2, d4}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]"
|
|
-
|
|
asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]"
|
|
-
|
|
asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]"
|
|
-
|
|
asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vld3.32 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vld3.32 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vld3.32 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vld3.32 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0, d2, d4}, [r4]"
|
|
-
|
|
asm_text: "vld3.32 {d0, d2, d4}, [r4:64]"
|
|
-
|
|
asm_text: "vld3.32 {d0, d2, d4}, [r4]!"
|
|
-
|
|
asm_text: "vld3.32 {d0, d2, d4}, [r4:64]!"
|
|
-
|
|
asm_text: "vld3.32 {d0, d2, d4}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0, d2, d4}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]"
|
|
-
|
|
asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]"
|
|
-
|
|
asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]"
|
|
-
|
|
asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]!"
|
|
-
|
|
asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]!"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
|
|
-
|
|
asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]"
|
|
-
|
|
asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]!"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]!"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]!"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]!"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0}, [r4]"
|
|
-
|
|
asm_text: "vst1.8 {d0}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.8 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vst1.8 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.8 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vst1.8 {d0[2]}, [r4]"
|
|
-
|
|
asm_text: "vst1.8 {d0[2]}, [r4]!"
|
|
-
|
|
asm_text: "vst1.8 {d0[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0}, [r4]"
|
|
-
|
|
asm_text: "vst1.16 {d0}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.16 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vst1.16 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.16 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0[2]}, [r4]"
|
|
-
|
|
asm_text: "vst1.16 {d0[2]}, [r4:16]"
|
|
-
|
|
asm_text: "vst1.16 {d0[2]}, [r4]!"
|
|
-
|
|
asm_text: "vst1.16 {d0[2]}, [r4:16]!"
|
|
-
|
|
asm_text: "vst1.16 {d0[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.16 {d0[2]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0}, [r4]"
|
|
-
|
|
asm_text: "vst1.32 {d0}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.32 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vst1.32 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.32 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0[1]}, [r4]"
|
|
-
|
|
asm_text: "vst1.32 {d0[1]}, [r4:32]"
|
|
-
|
|
asm_text: "vst1.32 {d0[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst1.32 {d0[1]}, [r4:32]!"
|
|
-
|
|
asm_text: "vst1.32 {d0[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.32 {d0[1]}, [r4:32], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0}, [r4]"
|
|
-
|
|
asm_text: "vst1.64 {d0}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.64 {d0}, [r4]!"
|
|
-
|
|
asm_text: "vst1.64 {d0}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.64 {d0}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4:128]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4:128]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d2}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0[2], d1[2]}, [r4]"
|
|
-
|
|
asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]"
|
|
-
|
|
asm_text: "vst2.8 {d0[2], d1[2]}, [r4]!"
|
|
-
|
|
asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]!"
|
|
-
|
|
asm_text: "vst2.8 {d0[2], d1[2]}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4:128]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4:128]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4:128]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4:128]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d2}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]!"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d1[1]}, [r4]"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d1[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d1[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]!"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.8 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst3.8 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst3.8 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst3.8 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst3.8 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.8 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.8 {d0, d2, d4}, [r4]"
|
|
-
|
|
asm_text: "vst3.8 {d0, d2, d4}, [r4:64]"
|
|
-
|
|
asm_text: "vst3.8 {d0, d2, d4}, [r4]!"
|
|
-
|
|
asm_text: "vst3.8 {d0, d2, d4}, [r4:64]!"
|
|
-
|
|
asm_text: "vst3.8 {d0, d2, d4}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.8 {d0, d2, d4}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.16 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst3.16 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst3.16 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst3.16 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst3.16 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.16 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.16 {d0, d2, d4}, [r4]"
|
|
-
|
|
asm_text: "vst3.16 {d0, d2, d4}, [r4:64]"
|
|
-
|
|
asm_text: "vst3.16 {d0, d2, d4}, [r4]!"
|
|
-
|
|
asm_text: "vst3.16 {d0, d2, d4}, [r4:64]!"
|
|
-
|
|
asm_text: "vst3.16 {d0, d2, d4}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.16 {d0, d2, d4}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]"
|
|
-
|
|
asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.32 {d0, d1, d2}, [r4]"
|
|
-
|
|
asm_text: "vst3.32 {d0, d1, d2}, [r4:64]"
|
|
-
|
|
asm_text: "vst3.32 {d0, d1, d2}, [r4]!"
|
|
-
|
|
asm_text: "vst3.32 {d0, d1, d2}, [r4:64]!"
|
|
-
|
|
asm_text: "vst3.32 {d0, d1, d2}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.32 {d0, d1, d2}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.32 {d0, d2, d4}, [r4]"
|
|
-
|
|
asm_text: "vst3.32 {d0, d2, d4}, [r4:64]"
|
|
-
|
|
asm_text: "vst3.32 {d0, d2, d4}, [r4]!"
|
|
-
|
|
asm_text: "vst3.32 {d0, d2, d4}, [r4:64]!"
|
|
-
|
|
asm_text: "vst3.32 {d0, d2, d4}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.32 {d0, d2, d4}, [r4:64], r6"
|
|
-
|
|
asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]"
|
|
-
|
|
asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]"
|
|
-
|
|
asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]!"
|
|
-
|
|
asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6"
|
|
-
|
|
asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]"
|
|
-
|
|
asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]"
|
|
-
|
|
asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]"
|
|
-
|
|
asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]"
|
|
-
|
|
asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]!"
|
|
-
|
|
asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]!"
|
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asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]!"
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asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]!"
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asm_text: "vst4.8 {d0, d1, d2, d3}, [r4], r6"
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asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64], r6"
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asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128], r6"
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asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256], r6"
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-
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]"
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]"
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]"
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-
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]"
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-
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]!"
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]!"
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-
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]!"
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-
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]!"
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4], r6"
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-
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64], r6"
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128], r6"
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asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256], r6"
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asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
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asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]"
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asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
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asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!"
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asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
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asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]"
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]!"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]!"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]!"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]!"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4], r6"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64], r6"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128], r6"
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-
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asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256], r6"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]!"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]!"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]!"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]!"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4], r6"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64], r6"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128], r6"
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-
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asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256], r6"
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-
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asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
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-
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asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
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-
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asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
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-
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asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
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-
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asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
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-
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asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
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-
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asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
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-
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asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
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-
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asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
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-
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asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
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-
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asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
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-
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asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]!"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]!"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]!"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]!"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4], r6"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128], r6"
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-
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asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256], r6"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]!"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]!"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]!"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]!"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4], r6"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128], r6"
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-
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asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256], r6"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
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-
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asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6"
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