1255 lines
34 KiB
YAML
1255 lines
34 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x09, 0xcf, 0xbc, 0xf5, 0x09, 0xf4, 0x01, 0x00, 0x89, 0xfb, 0x8f, 0x74, 0x89, 0xfe, 0x48, 0x01, 0x29, 0x00, 0x19, 0x25, 0x29, 0x03, 0x09, 0xf4, 0x85, 0xf9, 0x68, 0x0f, 0x16, 0x01 ]
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arch: "tricore"
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "ld.a a15, [+a12]#-4"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: a15
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-
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type: TRICORE_OP_MEM
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mem_base: a12
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mem_disp: -4
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-
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asm_text: "ld.b d4, [a15+]#1"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: d4
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-
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type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0x1
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-
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asm_text: "st.h [+a15]#0x1cf, d11"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0x1cf
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-
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type: TRICORE_OP_REG
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reg: d11
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-
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asm_text: "st.d [a15+]#8, e14"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0x8
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-
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type: TRICORE_OP_REG
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reg: e14
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-
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asm_text: "ld.w d0, [p0+c]#0x99"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: d0
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-
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type: TRICORE_OP_MEM
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mem_base: p0
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mem_disp: 0x99
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-
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asm_text: "ld.b d3, [p0+c]#-0x37"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: d3
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-
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type: TRICORE_OP_MEM
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mem_base: p0
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mem_disp: -0x37
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-
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asm_text: "ld.da p8, #0xf0003428"
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details:
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tricore:
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operands:
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-
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type: TRICORE_OP_REG
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reg: p8
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-
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type: TRICORE_OP_IMM
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imm: 0xf0003428
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-
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asm_text: "and d15, #1"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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-
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type: TRICORE_OP_IMM
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imm: 0x1
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- input:
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bytes: [ 0x12, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "add d0, d15, d0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_READ
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- input:
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bytes: [ 0x1a, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "add d15, d0, d0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_READ
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_READ
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- input:
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bytes: [ 0xaa, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "cmov d0, d15, #0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- type: TRICORE_OP_IMM
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imm: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x2a, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "cmov d0, d15, d0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_READ
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- input:
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bytes: [ 0xea, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "cmovn d0, d15, #0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- type: TRICORE_OP_IMM
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imm: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x6a, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "cmovn d0, d15, d0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_READ
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- input:
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bytes: [ 0xee, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "jnz d15, #0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE # fixme: should be read
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- type: TRICORE_OP_IMM
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imm: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x6e, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "jz d15, #0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE # fixme: should be read
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- type: TRICORE_OP_IMM
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imm: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0xd8, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.a a15, [sp]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: a15
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: sp
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0xc8, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.a a0, [a15]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: a0
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0xcc, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.a a15, [a0]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: a15
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x08, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.bu d0, [a15]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x0c, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.bu d15, [a0]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x88, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.h d0, [a15]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x8c, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.h d15, [a0]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x58, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.w d15, [sp]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: sp
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x48, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.w d0, [a15]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0x4c, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "ld.w d15, [a0]#0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_WRITE
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ
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- input:
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bytes: [ 0xf8, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.a [sp]#0, a15"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_MEM
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mem_base: sp
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mem_disp: 0
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access: CS_AC_READ # fixme: should be write
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- type: TRICORE_OP_REG
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reg: a15
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access: CS_AC_READ
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- input:
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bytes: [ 0xec, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.a [a0]#0, a15"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ # fixme: should be write
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- type: TRICORE_OP_REG
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reg: a15
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access: CS_AC_READ
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- input:
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bytes: [ 0xe8, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.a [a15]#0, a0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0
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access: CS_AC_READ # fixme: should be write
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- type: TRICORE_OP_REG
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reg: a0
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access: CS_AC_READ
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- input:
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bytes: [ 0x2c, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.b [a0]#0, d15"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ # fixme: should be write
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- input:
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bytes: [ 0x28, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.b [a15]#0, d0"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_MEM
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mem_base: a15
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mem_disp: 0
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access: CS_AC_READ # fixme: should be write
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- type: TRICORE_OP_REG
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reg: d0
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access: CS_AC_READ
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- input:
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bytes: [ 0xac, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.h [a0]#0, d15"
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details:
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tricore:
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operands:
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- type: TRICORE_OP_MEM
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mem_base: a0
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mem_disp: 0
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access: CS_AC_READ # fixme: should be write
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- type: TRICORE_OP_REG
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reg: d15
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access: CS_AC_READ
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- input:
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bytes: [ 0xa8, 0x0 ]
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arch: CS_ARCH_TRICORE
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options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
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expected:
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insns:
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- asm_text: "st.h [a15]#0, d0"
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details:
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tricore:
|
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operands:
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- type: TRICORE_OP_MEM
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|
mem_base: a15
|
|
mem_disp: 0
|
|
access: CS_AC_READ # fixme: should be write
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x78, 0x0 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "st.w [sp]#0, d15"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_MEM
|
|
mem_base: sp
|
|
mem_disp: 0
|
|
access: CS_AC_READ # fixme: should be write
|
|
- type: TRICORE_OP_REG
|
|
reg: d15
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x6c, 0x0 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "st.w [a0]#0, d15"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_MEM
|
|
mem_base: a0
|
|
mem_disp: 0
|
|
access: CS_AC_READ # fixme: should be write
|
|
- type: TRICORE_OP_REG
|
|
reg: d15
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x68, 0x0 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "st.w [a15]#0, d0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_MEM
|
|
mem_base: a15
|
|
mem_disp: 0
|
|
access: CS_AC_READ # fixme: should be write
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x52, 0x0 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "sub d0, d15, d0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d15
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x5a, 0x0 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "sub d15, d0, d0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d15
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
|
|
- input:
|
|
bytes: [ 0x6b, 0x04, 0x22, 0x02 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "add.df e0, e2, e4"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x6b, 0x04, 0x32, 0x02 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "sub.df e0, e2, e4"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x6b, 0x20, 0x62, 0x64 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "madd.df e6, e4, e0, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e6
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x6b, 0x20, 0x72, 0x64 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "msub.df e6, e4, e0, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e6
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x42, 0x42, 0x00 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "mul.df e0, e2, e4"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x20, 0x52, 0x40 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "div.df e4, e0, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x20, 0x02, 0x40 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "cmp.df d4, e0, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x20, 0x22, 0x43 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "max.df e4, e0, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x20, 0x32, 0x43 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "min.df e4, e0, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x20, 0x31, 0x43 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "min.f d4, d0, d2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x20, 0x21, 0x43 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "max.f d4, d0, d2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x02, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftoi d2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x32, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftoiz d2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x72, 0x23 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftoin d2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x71, 0x23 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "ftoin d2, d10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x22, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftou d2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x72, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftouz d2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0xa2, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftol e2, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0xe2, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftoul e2, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0xf2, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftoulz e2, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x01, 0x01, 0x43 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "abs.f d4, d1"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d1
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x02, 0x02, 0x43 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "abs.df e4, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0xb2, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftolz e2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x12, 0x23 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "neg.df e2, e10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x0a, 0x11, 0x23 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "neg.f d2, d10"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d10
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0x92, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "qseed.df e2, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0x42, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "itodf e2, d0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0x62, 0x21 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "utodf e2, d0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0x62, 0x22 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "ltodf e2, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x00, 0x72, 0x22 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "ultodf e2, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x02, 0x82, 0x12 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "dftof d1, e2"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: d1
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x05, 0x92, 0x22 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "ftodf e2, d5"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: d5
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x04, 0x02, 0x22 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "div64 e2, e4, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x04, 0x12, 0x22 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "div64.u e2, e4, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x04, 0x42, 0x23 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "rem64 e2, e4, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|
|
- input:
|
|
bytes: [ 0x4b, 0x04, 0x52, 0x23 ]
|
|
arch: CS_ARCH_TRICORE
|
|
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
|
|
expected:
|
|
insns:
|
|
- asm_text: "rem64.u e2, e4, e0"
|
|
details:
|
|
tricore:
|
|
operands:
|
|
- type: TRICORE_OP_REG
|
|
reg: e2
|
|
access: CS_AC_WRITE
|
|
- type: TRICORE_OP_REG
|
|
reg: e4
|
|
access: CS_AC_READ
|
|
- type: TRICORE_OP_REG
|
|
reg: e0
|
|
access: CS_AC_READ
|